CY93C04-ZXI [CYPRESS]
EEPROM, 4KX8, Serial, CMOS, PDSO8, LEAD FREE, TSSOP-8;型号: | CY93C04-ZXI |
厂家: | CYPRESS |
描述: | EEPROM, 4KX8, Serial, CMOS, PDSO8, LEAD FREE, TSSOP-8 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 时钟 光电二极管 内存集成电路 |
文件: | 总16页 (文件大小:646K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
CY93C01/02/04/08/16
1 Kbit, 2 Kbit, 4 Kbit, 8 Kbit, and 16 Kbit
(x8 or x16) MicroWire Serial EEPROM
Features
Functional Description
■ Continuous voltage operation
❐ VCC = 1.65V to 5.5V
The CY93C01/02/04/08/16 provides 1K, 2K, 4K, 8K, and 16K
bits of serial Electrically Erasable and Programmable Read Only
Memory (EEPROM). The memory is organized as x16 when the
ORG pin is connected to VCC and as x8 when it is tied to ground.
The device is optimized for use in many industrial applications,
where low power and low voltage operations are essential. The
CY93C01/02/04/08/16 is available in space saving 8-Pin SOIC,
and 8-Pin TSSOP packages. The CY93C01/02/04/08/16 is
■ Internally organized as x8 or x16
■ Industry standard three wire serial interface
■ Schmitt trigger, filtered inputs for noise suppression
■ Programming instructions that work on byte, word, or entire
enabled through the Chip Select pin (CS), and accessed through
a three wire serial interface consisting of Data Input (DI), Data
Output (DO), and Serial Clock (SK). On receiving a read
instruction at DI, the address is decoded and the data is clocked
out serially on the data output pin DO. The write cycle is
completely self timed and no separate erase cycle is required
before write. The write cycle is enabled only when the part is in
the erase or write enable state. When CS is brought high
following the initiation of a write cycle, the DO pin outputs the
Ready/Busy status of the part. The CY93C01/02/04/08/16 is
available in a 1.65V to 5.5V version.
memory
■ Sequential read operation
■ 4 MHz clock rate (5V) compatibility
■ Self timed write cycle (5 ms max)
■ Ready/Busy signal during programming
■ Industrial temperature range
■ High reliability
❐ Endurance: 1 million write cycles
❐ Data retention: 100 years
■ RoHS compliant 8-Pin SOIC and 8-Pin TSSOP packages
■ Pb-free and RoHS compliant
Logic Block Diagram
VCC
CS
DO
ORG
CY93CXX
DI
SK
VSS
Cypress Semiconductor Corporation
Document #: 001-15635 Rev. *C
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised February 05, 2009
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CY93C01/02/04/08/16
Pinouts
Figure 1. Pin Diagram: 8-Pin SOIC/TSSOP Package
CS
SK
1
2
V
8
CC
7
6
5
NC
Top View
(not to scale)
DI
ORG
GND
3
4
DO
Table 1. Pin Definition - 8-SOIC/TSSOP
8-SOIC
Pin Name
8-TSSOP
Pin Number
I/O Type
Description
Pin Number
CS
SK
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
Input
Input
Input
Output
Input
Input
NA
Chip Select
Serial Clock
DI
Serial Data Input
Serial Data Output
Ground
Internal Organization[1]
No Connect[2]
DO
GND
ORG
NC
VCC
Input
Power Supply
Notes
1. When the ORG is connected to Vcc, the x16 organization is selected. When it is connected to ground, the x8 organization is selected. If the ORG pin is left unconnected
and the application does not load the input beyond the capability of the internal 1Meg ohm pull up, then the x16 organization is selected.
2. The NC pin does not contribute to the normal operation of the device. The pin may be left unconnected or may be connected to Vcc or GND. Direct connection of NC
to GND is recommended for lowest standby power consumption.
Document #: 001-15635 Rev. *C
Page 2 of 16
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Write
Device Operating Features
The Write (WRITE) instruction contains 8 or 16 bits of data to be
written into the specified memory location. The self timed
programming cycle tWC starts after the last bit of data is received
at serial data input pin DI. The DO pin outputs the Ready/Busy
status of the part if CS is brought high after being kept low for a
minimum of 100 ns (tCE). A logic ‘0’ at DO indicates that
programming is still in progress. A logic ‘1’ indicates that the
memory location at the specified address is written with the data
pattern contained in the instruction and the part is ready for
further instructions. A Ready/Busy status is not obtained if the
CS is brought high after the end of the self timed programming
Internal Device Reset
To prevent inadvertent write operations during power up, a
Power On Reset (POR) circuit is included.
During power up and power down, the device must not be
selected (that is, the Chip Select Input (CS) must be driven low)
until the supply voltage reaches the operating voltage VCC
.
During power up (the phase during which VCC is lower than the
minimum VCC, but increases continuously), the device does not
respond to any instruction until VCC has reached the POR
threshold voltage (this threshold is lower than the minimum VCC
operating voltage defined in DC Electrical Characteristics on
page 9). After VCC has passed the POR threshold, the device is
reset.
cycle tWC
.
An internal power on data protection mechanism in the CY93C02
inhibits the device when the supply is too low.
Erase
Before selecting the memory and issuing instructions to it, a valid
and stable VCC voltage is applied. This voltage must remain
stable and valid until the end of transmission of the instruction
and, for a write instruction, until the completion of the internal
write cycle (tWC).
The Erase (ERASE) instruction programs all bits in the specified
memory location to the logical ‘1’ state. The self timed erase
cycle starts after the ERASE instruction and address are
decoded. The DO pin outputs the Ready/Busy status of the part
if CS is brought high after being kept low for a minimum of 100
ns (tCE). A logic ‘1’ at pin DO indicates that the selected memory
location is erased, and the part is ready for another instruction.
During power down (the phase during which VCC decreases
continuously), as soon as VCC drops from the normal operating
voltage below the POR threshold voltage, the device stops
responding to any instruction sent to it.
Erase/Write Enable (EWEN)
Active and Standby Power Modes
To assure data integrity, the part automatically goes into the
Erase/Write Disable (EWDS) state when power is first applied.
An Erase/Write Enable (EWEN) instruction must be executed
first before any programming instruction is carried out. Note that
in the EWEN state, programming remains enabled until an
EWDS instruction is executed or VCC power is removed from the
part.
When Chip Select (CS) is high, the device is selected and in the
active power mode. It consumes ICC, as specified in
DC Electrical Characteristics on page 9. When Chip Select (CS)
is low, the device is deselected.
If no erase or write cycle is in progress when Chip Select goes
low, the device enters the standby power mode and the power
consumption drops to ISB1
.
Erase All (ERAL)
The Erase All (ERAL) instruction programs every bit in the
memory array to the logic ‘1’ state and is primarily used for
testing purposes. The DO pin outputs the Ready/Busy status of
the part if CS is brought high after being kept low for a minimum
of 100 ns (tCE).
Device Operations
The CY93C02 is accessed through a simple and versatile three
wire serial communication interface. Device operation is
controlled by seven instructions issued by the host processor. A
valid instruction starts with a rising edge of CS and consists of a
Start Bit (logic ‘1’) followed by the appropriate op-code and the
desired memory address location.
Write All (WRAL)
The Write All (WRAL) instruction programs all memory locations
with the data patterns specified in the instruction. The DO pin
outputs the Ready/Busy status of the part if CS is brought high
after being kept low for a minimum of 100 ns (tCE).
Read
The Read (READ) instruction contains the address code for the
memory location to be read. After the instruction and address are
decoded, data from the selected memory location is available at
the serial output pin DO. Output data changes are synchronized
with the rising edges of serial clock SK. Note that a dummy bit
(logic ‘0’) precedes the 8-bit or 16-bit data output string. The
CY93C02 supports sequential read operations. The device
automatically increments the internal address pointer and clocks
out the next memory location as long as CS is held high. In this
case, the dummy bit (logic ‘0’) is not clocked out between
memory locations, therefore enabling a continuous stream of
data to be read.
Erase/Write Disable (EWDS)
To protect against accidental data disturbance, the Erase/Write
Disable (EWDS) instruction disables all programming modes
and is executed after all programming operations. The operation
of the READ instruction is independent of both the EWEN and
EWDS instructions and is executed at any time.
Document #: 001-15635 Rev. *C
Page 3 of 16
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CY93C01/02/04/08/16
Table 2. Instruction Set for CY93C01 [3]
Instruction Start Bit Opcode
Address
Data
Comments
x8
x16
x8
x16
READ
ERASE
WRITE
EWEN
EWDS
ERAL
1
1
1
1
1
1
1
10
11
01
00
00
00
00
A6–A0
A6–A0
A6–A0
A5–A0
Read Address AN–A0
Clear Address AN–A0
A5–A0
A5–A0
D7–D0
D15–D0
D15–D0
Write Address AN–A0
Write Enable
11XXXXX
00XXXXX
10XXXXX
01XXXXX
11XXXX
00XXXX
10XXXX
01XXXX
Write Disable
Clear All Address
Write All Address
WRAL
D7–D0
Table 3. Instruction Set for CY93C02 and CY93C04 [3]
Address
Data
Instruction Start Bit Opcode
x8
Comments
x16
x8
x16
READ
ERASE
WRITE
EWEN
EWDS
ERAL
1
1
1
1
1
1
1
10
11
01
00
00
00
00
A8[4]–A0
A8[4]–A0
A8[4]–A0
A7[5]–A0
A7[5]–A0
A7[5]–A0
Read Address AN–A0
Clear Address AN–A0
Write Address AN–A0
Write Enable
D7–D0
D15–D0
11XXXXXXX
00XXXXXXX
10XXXXXXX
01XXXXXXX
11XXXXXX
00XXXXXX
10XXXXXX
01XXXXXX
Write Disable
Clear All Address
Write All Address
WRAL
D7–D0
D15–D0
Table 4. Instruction Set for CY93C08 and CY93C16 [3]
Address
Data
Instruction Start Bit Opcode
Comments
x8
x16
x8
x16
READ
ERASE
WRITE
EWEN
EWDS
ERAL
1
1
1
1
1
1
1
10
11
01
00
00
00
00
A10[6]–A0
A10[6]–A0
A10[6]–A0
A9[7]–A0
A9[7]–A0
A9[7]–A0
Read Address AN–A0
Clear Address AN–A0
Write Address AN–A0
Write Enable
D7–D0
D15–D0
11XXXXXXXXX 11XXXXXXXX
00XXXXXXXXX 00XXXXXXXX
10XXXXXXXXX 10XXXXXXXX
01XXXXXXXXX 01XXXXXXXX
Write Disable
Clear All Address
Write All Address
WRAL
D7–D0
D15–D0
Notes
3. X = Do not care bit.
4. Address bit A8 is not decoded by CY93C02.
5. Address bit A7 is not decoded by CY93C02.
6. Address bit A10 is not decoded by CY93C08.
7. Address bit A9 is not decoded by CY93C08.
Document #: 001-15635 Rev. *C
Page 4 of 16
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CY93C01/02/04/08/16
circuit current from flowing when the last address bit (A0) clashes
with the first data bit on Serial Data Output (DO).
Ready/Busy Status
While the Write or Erase cycle is underway, for a WRITE,
ERASE, WRAL or ERAL instruction, the Busy signal (DO=0) is
returned whenever Chip Select input (CS) is driven high. In this
state, the CY93C02 ignores any data on the bus. When the write
cycle is completed, and Chip Select input (CS) is driven high, the
Ready signal (DO=1) indicates that the CY93C02 is ready to
receive the next instruction. Serial Data Output (DO) remains set
to 1 until the Chip Select Input (CS) is brought low or until a new
start bit is decoded.
Clock Pulse Counter
In a noisy environment, the number of pulses received on Serial
Clock (SK) may be greater than the number delivered by the
master (the microcontroller). This leads to a misalignment of the
instruction of one or more bits, as shown in Figure 8 on page 8,
and may lead to the writing of erroneous data at an erroneous
address. To combat this problem, the CY93C02 has an on-chip
counter that counts the clock pulses from the start bit until the
falling edge of the Chip Select input (CS). If the number of clock
pulses received is not the number expected, the WRITE,
ERASE, ERAL, or WRAL instruction is aborted and the contents
of the memory are not modified.
Common I/O Operation
Serial Data Output (DO) and Serial Data Input (DI) are connected
together, through a current limiting resistor, to form a common,
single wire data bus. Some precautions must be taken when
operating the memory in this way, mostly to prevent a short
Figure 2. Read Instruction Timing
Figure 3. Erase Enable/Disable Instruction Timing
Document #: 001-15635 Rev. *C
Page 5 of 16
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CY93C01/02/04/08/16
Figure 4. Write Instruction Timing
tCE
tHZCE
tLZCE
tWC
Figure 5. Write All Instruction Timing
tCE
tHZCE
tLZCE
tWC
Document #: 001-15635 Rev. *C
Page 6 of 16
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CY93C01/02/04/08/16
Figure 6. Erase Instruction Timing
tCE
tHZCE
tLZCE
tWC
Figure 7. Erase All Instruction Timing
tCE
tHZCE
tLZCE
tWC
Document #: 001-15635 Rev. *C
Page 7 of 16
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CY93C01/02/04/08/16
Figure 8. Write Sequence with One Clock Glitch
CS
SK
DI
Document #: 001-15635 Rev. *C
Page 8 of 16
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CY93C01/02/04/08/16
Package power dissipation
capability (TA = 25°C).................................................... 1.0W
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Surface mount lead soldering
Temperature (3 Seconds)..................+260°C for 10 seconds
Output short circuit current[8]....................................... 50 mA
Storage temperature .................................. –65°C to +150°C
Ambient temperature with
power applied............................................. –55°C to +125°C
Static discharge voltage........................................... > 2001V
(per MIL-STD-883, Method 3015)
Supply voltage on VCC relative to GND..........–1.0V to +6.0V
Latch up current .................................................... > 200 mA
DC voltage applied to outputs
in high-Z state........................................ –0.5V to VCC + 1.0V
Operating Range
Range
Industrial
Ambient Temperature
VCC
Input voltage.......................................... –0.5V to VCC + 0.5V
–40°C to +85°C
1.65V to 5.5V
Transient voltage (<20 ns) on
any pin to ground potential.................... –1.0V to VCC + 2.0V
DC Electrical Characteristics
Over the Operating Range (VCC = 1.65V to 5.5V)
Parameter
VCC1
Description
Supply Voltage
Test Conditions
VCC = 1.65V, CS = VCC
Min
Max
Unit
V
1.65
5.5
ISB1
ISB2
ISB3
ICC1
ICC2
ILI
Standby Current
1
μA
μA
μA
mA
mA
μA
μA
V
Standby Current
VCC = 2.7V, CS = VCC
VCC = 5.5V, CS = VCC
VCC = 5.5V at 4 MHz
VCC = 5.5V
1.1
Standby Current
1.2
Supply Current (Read)
Supply Current (Write)
Input Leakage Current
Output Leakage Current
Input LOW Voltage
2
2
VIN = VCC or VSS
1
1
ILO
VIN = VCC or VSS
VIL
1.65V < VCC < 2.7V
2.7V < VCC < 5.5V
1.65V < VCC < 5.5V
IOL = 2.1 mA, 2.7 < VCC < 5.5V
–0.6 [9]
–0.6 [9]
0.3 VCC
0.8
VCC + 0.5 [9]
VIH
Input HIGH Voltage
Output LOW Voltage
0.7 VCC
V
V
VOL
0.4
0.2
IOL = 0.15 mA, 1.65 < VCC < 2.7V
VOH
Output HIGH Voltage
IOH = -0.1 mA, 1.65 < VCC < 2.7V
IOH = -0.4 mA, 2.7 < VCC < 5.5V
VCC – 0.2
2.4
V
Capacitance
In the following table, the capacitance parameters are listed. [10]
Parameter
CIN
Description
Input Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
CC = 1.65V
Max
Unit
5
5
pF
pF
V
COUT
Output Pin Capacitance
Thermal Resistance
In the following table, the thermal resistance parameters are listed. [10]
Parameter
Description
Test Conditions
8-SOIC 8-TSSOP
Unit
ΘJA
Thermal Resistance
(Junction to Ambient)
Test conditions follow standard test methods and
procedures for measuring thermal impedance, per EIA
/ JESD51.
120.83
119.31
°C/W
ΘJC
Thermal Resistance
(Junction to Case)
90.31
82.77
°C/W
Notes
8. Outputs shorted for only one second. Only one output shorted at a time.
9. This parameter is characterized but not tested.
10. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
Document #: 001-15635 Rev. *C
Page 9 of 16
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CY93C01/02/04/08/16
Reliability Characteristics
In the following table, the reliability characteristics parameters are listed. [10]
Parameter
Description
Endurance
Test Method
JEDEC Standard A117
JEDEC Standard A103
JEDEC Standard 78
Min
1 Million
100
Unit
Cycles
Years
mA
NEND
TDR
Data Rentention
Latch Up
ILTH
100 + ICC
Figure 9. AC Test Loads and Waveforms
R1
V
CC
OUTPUT
R2
Parameters
1.65V - 2.7V
2.7V - 5.5V
1.8K
Unit
R1
R2
CL
1.8K
1.3K
30
ohm
ohm
pF
1.3K
100
Figure 10. AC Input/Output Reference Waveforms
VIHT
VILT
VHT
VLT
VHT
VLT
OUTPUT
REFERENCE POINTS
INPUT
AC test inputs are driven at VIHT (0.9VCC) for a logic ‘1’ and VILT (0.1VCC) for a logic ‘0’. Measurement reference points for inputs and
outputs are VLT (VCC/2 - 0.1V) and VHT (VCC/2 + 0.1V). Input rise and fall times (10%–90%) are <3.3 ns.
Document #: 001-15635 Rev. *C
Page 10 of 16
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CY93C01/02/04/08/16
AC Switching Characteristics
Over the Operating Range (VCC= 1.65V–5.5V)
4 MHz
3 Mhz
2 Mhz
1 Mhz
Cypress
Alt
Description
Clock Frequency
Unit
Parameter Parameter
Min Max
Min
Max
Min Max Min Max
fSK
fSK
4
100
100
100
100
60
3
2
1
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
ns
tCL
tSKLO
tSKHI
tCS
Clock Pulse Width Low
Clock Pulse Width High
Minimum CS Low Time
Output Valid
130
130
130
200
200
200
400
400
400
tCH
tCE
tLZCE
tCES
tCEH
tSD
tSV
130
200
400
tCSS
tCSH
tDIS
tDIH
tPD1
tPD0
tHZ
CS Setup Time
50
0
50
0
50
0
CS Hold Time
0
Data In Setup Time
Data In Hold Time
Output Delay to 1
Output Delay to 0
CS to Data Out in High Impedance
Write Cycle Time
60
50
50
100
100
100
100
tHD
60
tCO2
tCO1
tHZCE
tWC
tF
100
100
60
130
130
150
5
200
200
150
5
400
400
150
5
tWP
tF
5
Input Fall Time
20
28
45
95
tR
tR
Input Rise Time
20
28
45
95
Figure 11. Synchronous Data Timing
tCEH
tCL
tCH
tHD
tSD
tCES
tCO1, tCO2
tSD
tCE
Document #: 001-15635 Rev. *C
Page 11 of 16
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CY93C01/02/04/08/16
Part Numbering Nomenclature
CY93 C 01 - SX
I T
Option:
T = Tape & Reel
Blank = Std.
Temperature:
I = Industrial (–40 to 85°C)
X = Pb-Free
Package:
S = SOIC
Z = TSSOP
Density:
01 = 1 Kb
02 = 2 Kb
04 = 4 Kb
08 = 8 Kb
16 = 16 Kb
Voltage:
C = 1.65V - 5.5V
93 =MicroWire Interface
Cypress
Ordering Information
Package
Diagram
Operating
Range
Density
Ordering Code
Package Type
1 Kbit
CY93C01-SXI
CY93C01-SXIT
CY93C01-ZXI
CY93C01-ZXIT
CY93C02-SXI
CY93C02-SXIT
CY93C02-ZXI
CY93C02-ZXIT
CY93C04-SXI
CY93C04-SXIT
CY93C04-ZXI
CY93C04-ZXIT
CY93C08-SXI
CY93C08-SXIT
CY93C08-ZXI
CY93C08-ZXIT
CY93C16-SXI
CY93C16-SXIT
CY93C16-ZXI
CY93C16-ZXIT
51-85066 8-Pin SOIC
Industrial
Industrial
Industrial
Industrial
Industrial
8-Pin SOIC (Tape & Reel)
51-85093 8-Pin TSSOP
8-Pin TSSOP (Tape & Reel)
51-85066 8-Pin SOIC
8-Pin SOIC (Tape & Reel)
51-85093 8-Pin TSSOP
8-Pin TSSOP (Tape & Reel)
51-85066 8-Pin SOIC
8-Pin SOIC (Tape & Reel)
51-85093 8-Pin TSSOP
8-Pin TSSOP (Tape & Reel)
51-85066 8-Pin SOIC
8-Pin SOIC (Tape & Reel)
51-85093 8-Pin TSSOP
8-Pin TSSOP (Tape & Reel)
51-85066 8-Pin SOIC
8-Pin SOIC (Tape & Reel)
51-85093 8-Pin TSSOP
8-Pin TSSOP (Tape & Reel)
2 Kbit
4 Kbit
8 Kbit
16 Kbit
Above table contains Preliminary information. Please contact your local Cypress sales representative for availability of these parts.
Document #: 001-15635 Rev. *C
Page 12 of 16
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CY93C01/02/04/08/16
Package Diagrams
Figure 12. 8-Pin (150-Mil) SOIC, 51-85066
PIN 1 ID
4
1
1. DIMENSIONS IN INCHES[MM] MIN.
MAX.
2. PIN 1 ID IS OPTIONAL,
ROUND ON SINGLE LEADFRAME
0.150[3.810]
0.157[3.987]
RECTANGULAR ON MATRIX LEADFRAME
3. REFERENCE JEDEC MS-012
4. PACKAGE WEIGHT 0.07gms
0.230[5.842]
0.244[6.197]
PART #
S08.15 STANDARD PKG.
SZ08.15 LEAD FREE PKG.
5
8
0.189[4.800]
0.196[4.978]
0.010[0.254]
0.016[0.406]
X 45°
SEATING PLANE
0.061[1.549]
0.068[1.727]
0.004[0.102]
0.050[1.270]
BSC
0.0075[0.190]
0.0098[0.249]
0.004[0.102]
0.0098[0.249]
0°~8°
0.016[0.406]
0.035[0.889]
0.0138[0.350]
0.0192[0.487]
51-85066-*C
Document #: 001-15635 Rev. *C
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Package Diagrams (continued)
Figure 13. 8-Pin (4.4 mm) TSSOP, 51-85093
51-85093-*A
Document #: 001-15635 Rev. *C
Page 14 of 16
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CY93C01/02/04/08/16
Document History Page
Document Title: CY93C01/02/04/08/16, 1 Kbit, 2 Kbit, 4 Kbit, 8 Kbit, and 16 Kbit (x8 or x16) MicroWire Serial EEPROM
Document Number: 001-15635
Revision
ECN No.
Orig. of
Change
Submission
Date
Description of Change
**
1069220
2522135
UHA
See ECN
06/27/08
New Data Sheet
*A
GVCH/PYRS
Added Pb-Free and RoHS Compliant information in Features
Removed PDIP package
Removed Automotive Temperature range
Changed Supply voltage on VCC relative to GND max value from 5.0V to
6.0V
Corrected Typo of Vcc max value from 5.0V to 5.5V
Added AC test load values for different parameters
Table 10: Updated AC Switching Characteristics
Table 8: Added Thermal Resistance values for 8-TSSOP packages
Table 9: Changed TDR value from 20 to 100 years
Updated Part Numbering Nomenclature and Ordering Information
*B
*C
2611873
2656511
VKN/PYRS
VKN/AESA
11/24/08
02/09/09
Updated Part numbering nomenclature
Updated Ordering information table
Changed part# from CY93C46/56/66/76/86 to CY93C01/02/04/08/16
Converted from preliminary to final
Included VIL spec of 0.8V for the VCC range between 2.7V to 5.5V
Updated VIH test conditions
Added footnote #9
Updated VOL and VOH test conditions
On page 10, Specified VCC range for AC test load conditions
On page 10, corrected AC measurement reference points from VIT and
V
OT to VLT and VHT respectively
Changed VLT level from 0.3VCC to VCC/2 - 0.1V
Changed VHT level from 0.7VCC to VCC/2 + 0.1V
Document #: 001-15635 Rev. *C
Page 15 of 16
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© Cypress Semiconductor Corporation, 2007-2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used
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Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
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Document #: 001-15635 Rev. *C
Revised February 05, 2009
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