CY8C5488LTI-LP093_技术文档

PSoC^®5LP: CY8C54LP Family

Datasheet

Programmable System-on-Chip (PSoC^®)

General Description

PSoC^®5LP is a true programmable embedded system-on-chip, integrating configurable analog and digital peripherals, memory, and

a microcontroller on a single chip. The PSoC 5LP architecture boosts performance through:

■ 32-bit ARM Cortex-M3 core plus DMA controller at up to 80 MHz

■ Ultra low power with industry's widest voltage range

■ Programmable digital and analog peripherals enable custom functions

■ Flexible routing of any analog or digital peripheral function to any pin

PSoC devices employ a highly configurable system-on-chip architecture for embedded control design. They integrate configurable

analog and digital circuits, controlled by an on-chip microcontroller. A single PSoC device can integrate as many as 100 digital and

analog peripheral functions, reducing design time, board space, power consumption, and system cost while improving system quality.

Features

■ Operating characteristics

■ Analog peripherals

❐ Voltage range: 1.71 to 5.5 V, up to 6 power domains

❐ Temperature range (ambient) –40 to 85 °C^[1]

❐ DC to 80-MHz operation

❐ Power modes

• Active mode 3.1 mA at 6 MHz, and 15.4 mA at 48 MHz

• 2-µA sleep mode

❐ Configurable 8- to 12-bit delta-sigma ADC

❐ 12-bit SAR ADC

❐ Two 8-bit DACs

❐ Four comparators

❐ Two opamps

❐ Two programmable analog blocks, to create:

• Programmable gain amplifier (PGA)

• Transimpedance amplifier (TIA)

• Mixer

• 300-nA hibernate mode with RAM retention

❐ Boost regulator from 0.5-V input up to 5-V output

• Sample and hold circuit

■ Performance

❐ 32-bit ARM Cortex-M3 CPU, 32 interrupt inputs

❐ 24-channel direct memory access (DMA) controller

❐ CapSense^®support, up to 62 sensors

❐ 1.024 V ±1% internal voltage reference

■ Versatile I/O system

❐ 46 to 72 I/O pins – up to 62 general-purpose I/Os (GPIOs)

❐ Up to eight performance I/O (SIO) pins

■ Memories

❐ Up to 256 KB program flash, with cache and security features

❐ Up to 32 KB additional flash for error correcting code (ECC)

❐ Up to 64 KB RAM

• 25 mA current sink

• Programmable input threshold and output high voltages

• Can act as a general-purpose comparator

• Hot swap capability and overvoltage tolerance

❐ Two USBIO pins that can be used as GPIOs

❐ Route any digital or analog peripheral to any GPIO

❐ LCD direct drive from any GPIO, up to 46 × 16 segments

❐ CapSense support from any GPIO

❐ 2 KB EEPROM

■ Digital peripherals

❐ Four 16-bit timer, counter, and PWM (TCPWM) blocks

❐ I²C, 1 Mbps bus speed

^❐f^Ua^Sce^B(²T^.I⁰D^c#^e1^r0^ti8^fi4^e0^d0^F3^u2^l)^l-Sus^pi^en^eg^din⁽t^Fe^Srn⁾a¹l²o^Msc^bil^pla^sto^pr^e^[2^r^]^{ipheral inter-}

❐ 20 to 24 universal digital blocks (UDB), programmable to

create any number of functions:

❐ 1.2-V to 5.5-V interface voltages, up to four power domains

■ Programming, debug, and trace

• 8-, 16-, 24-, and 32-bit timers, counters, and PWMs

• I²C, UART, SPI, I2S, LIN 2.0 interfaces

• Cyclic redundancy check (CRC)

• Pseudo random sequence (PRS) generators

• Quadrature decoders

❐ JTAG (4-wire), serial wire debug (SWD) (2-wire), single wire

viewer (SWV), and Traceport (5-wire) interfaces

❐ ARM debug and trace modules embedded in the CPU core

❐ Bootloader programming through I²C, SPI, UART, USB, and

other interfaces

• Gate-level logic functions

■ Package options: 68-pin QFN,100-pin TQFP, and 99-pin CSP

■ Programmable clocking

❐ 3- to 74-MHz internal oscillator, 2% accuracy at 3 MHz

❐ 4- to 25-MHz external crystal oscillator

❐ Internal PLL clock generation up to 80 MHz

❐ Low-power internal oscillator at 1, 33, and 100 kHz

❐ 32.768-kHz external watch crystal oscillator

❐ 12 clock dividers routable to any peripheral or I/O

■ Development support with free PSoC Creator™ tool

❐ Schematic and firmware design support

❐ Over 100 PSoC Components™ integrate multiple ICs and

system interfaces into one PSoC. Components are free

embedded ICs represented by icons. Drag and drop

component icons to design systems in PSoC Creator.

❐ Includes free GCC compiler, supports Keil/ARM MDK

compiler

❐ Supports device programming and debugging

Notes

1. The maximum storage temperature is 150 °C in compliance with JEDEC Standard JESD22-A103, High Temperature Storage Life.

2. This feature on select devices only. See Ordering Information on page 116 for details.

Cypress Semiconductor Corporation

Document Number: 001-84934 Rev. *K

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised May 2, 2017

PSoC^®5LP: CY8C54LP Family

Datasheet

More Information

Cypress provides a wealth of data at www.cypress.com to help you to select the right PSoC device for your design, and to help you

to quickly and effectively integrate the device into your design. For a comprehensive list of resources, see the knowledge base article

KBA86521, How to Design with PSoC 3, PSoC 4, and PSoC 5LP. Following is an abbreviated list for PSoC 5LP:

■ Overview: PSoC Portfolio, PSoC Roadmap

■ Development Kits:

❐ CY8CKIT-059 is a low-cost platform for prototyping, with a

unique snap-away programmer and debugger on the USB

connector.

❐ CY8CKIT-050 is designed for analog performance, for devel-

oping high-precision analog, low-power, and low-voltage ap-

plications.

❐ CY8CKIT-001 provides a common development platform for

any one of the PSoC 1, PSoC 3, PSoC 4, or PSoC 5LP

families of devices.

■ Product Selectors: PSoC 1, PSoC 3, PSoC 4, PSoC 5LP

In addition, PSoC Creator includes a device selection tool.

■ Application notes: Cypress offers a large number of PSoC

application notes and code examples covering a broad range

of topics, from basic to advanced level. Recommended appli-

cation notes for getting started with PSoC 5LP are:

❐ AN77759: Getting Started With PSoC 5LP

❐ AN77835: PSoC 3 to PSoC 5LP Migration Guide

❐ AN61290: Hardware Design Considerations

❐ AN57821: Mixed Signal Circuit Board Layout

❐ AN58304: Pin Selection for Analog Designs

❐ AN81623: Digital Design Best Practices

❐ AN73854: Introduction To Bootloaders

❐ The MiniProg3 device provides an interface for flash pro-

gramming and debug.

■ Technical Reference Manuals (TRM)

❐ Architecture TRM

❐ Registers TRM

■ Programming Specification

PSoC Creator

PSoC Creator is a free Windows-based Integrated Design Environment (IDE). It enables concurrent hardware and firmware design

of PSoC 3, PSoC 4, and PSoC 5LP based systems. Create designs using classic, familiar schematic capture supported by over 100

pre-verified, production-ready PSoC Components; see the list of component datasheets. With PSoC Creator, you can:

1. Drag and drop component icons to build your hardware

system design in the main design workspace

3. Configure components using the configuration tools

4. Explore the library of 100+ components

5. Review component datasheets

2. Codesign your application firmware with the PSoC hardware,

using the PSoC Creator IDE C compiler

Figure 1. Multiple-Sensor Example Project in PSoC Creator

1

2

3

4

5

Document Number: 001-84934 Rev. *K

Page 2 of 126

PSoC^®5LP: CY8C54LP Family

Datasheet

Contents

1. Architectural Overview ..................................................... 4

2. Pinouts ............................................................................... 6

3. Pin Descriptions .............................................................. 11

8.11 Up/Down Mixer ....................................................... 59

8.12 Sample and Hold .................................................... 60

9. Programming, Debug Interfaces, Resources ................ 60

9.1 JTAG Interface ......................................................... 61

9.2 SWD Interface .......................................................... 62

9.3 Debug Features ........................................................ 63

9.4 Trace Features ......................................................... 63

9.5 SWV and TRACEPORT Interfaces .......................... 63

9.6 Programming Features ............................................. 63

9.7 Device Security ........................................................ 63

9.8 CSP Package Bootloader ......................................... 64

4. CPU ................................................................................... 12

4.1 ARM Cortex-M3 CPU ............................................... 12

4.2 Cache Controller ...................................................... 15

4.3 DMA and PHUB ....................................................... 15

4.4 Interrupt Controller ................................................... 17

5. Memory ............................................................................. 19

5.1 Static RAM ............................................................... 19

5.2 Flash Program Memory ............................................ 19

5.3 Flash Security ........................................................... 19

5.4 EEPROM .................................................................. 19

5.5 Nonvolatile Latches (NVLs) ...................................... 20

5.6 External Memory Interface ....................................... 21

5.7 Memory Map ............................................................ 22

10. Development Support ................................................... 64

10.1 Documentation ....................................................... 64

10.2 Online ..................................................................... 64

10.3 Tools ....................................................................... 64

11. Electrical Specifications ............................................... 65

11.1 Absolute Maximum Ratings .................................... 65

11.2 Device Level Specifications .................................... 66

11.3 Power Regulators ................................................... 69

11.4 Inputs and Outputs ................................................. 73

11.5 Analog Peripherals ................................................. 81

11.6 Digital Peripherals ................................................ 101

11.7 Memory ................................................................ 105

11.8 PSoC System Resources ..................................... 109

11.9 Clocking ................................................................ 112

6. System Integration .......................................................... 23

6.1 Clocking System ....................................................... 23

6.2 Power System .......................................................... 27

6.3 Reset ........................................................................ 31

6.4 I/O System and Routing ........................................... 33

7. Digital Subsystem ........................................................... 40

7.1 Example Peripherals ................................................ 40

7.2 Universal Digital Block .............................................. 42

7.3 UDB Array Description ............................................. 45

7.4 DSI Routing Interface Description ............................ 45

7.5 USB .......................................................................... 47

7.6 Timers, Counters, and PWMs .................................. 47

7.7 I²C ............................................................................ 48

12. Ordering Information ................................................... 116

12.1 Part Numbering Conventions ............................... 117

13. Packaging ..................................................................... 118

14. Acronyms ..................................................................... 121

15. Reference Documents ................................................. 122

8. Analog Subsystem .......................................................... 50

8.1 Analog Routing ......................................................... 51

8.2 Delta-sigma ADC ...................................................... 53

8.3 Successive Approximation ADC ............................... 54

8.4 Comparators ............................................................. 54

8.5 Opamps .................................................................... 56

8.6 Programmable SC/CT Blocks .................................. 56

8.7 LCD Direct Drive ...................................................... 57

8.8 CapSense ................................................................. 58

8.9 Temp Sensor ............................................................ 58

8.10 DAC ........................................................................ 58

16. Document Conventions .............................................. 123

16.1 Units of Measure .................................................. 123

Document History Page.................................................... 124

Sales, Solutions, and Legal Information ......................... 126

Worldwide Sales and Design Support.......................... 126

Products....................................................................... 126

PSoC® Solutions ......................................................... 126

Cypress Developer Community.................................... 126

Technical Support ........................................................ 126

Document Number: 001-84934 Rev. *K

Page 3 of 126

PSoC^®5LP: CY8C54LP Family

Datasheet

1. Architectural Overview

Introducing the CY8C54LP family of ultra low-power, flash Programmable System-on-Chip (PSoC^®) devices, part of a scalable 8-bit

PSoC3 and 32-bit PSoC 5LP platform. The CY8C54LP family provides configurable blocks of analog, digital, and interconnect circuitry

around a CPU subsystem. The combination of a CPU with a flexible analog subsystem, digital subsystem, routing, and I/O enables

a high level of integration in a wide variety of consumer, industrial, and medical applications.

Figure 1-1.Simplified Block Diagram

Analog Interconnect

Digital Interconnect

System Wide

Resources

Digital System

Universal Digital Block Array(24 x UDB)

I²C

8- Bit

Timer

Quadrature Decoder

16 -Bit PRS

Master /

Slave

4- 25 MHz

( Optional)

16-Bit

PWM

UDB

22 

Xtal

Osc

USB

PHY

UDB

8- Bit

FS USB

2.0

UDB

I 2C Slave

UDB

4x

Timer

8- Bit SPI

Logic

Timer

Counter

PWM

12- Bit SPI

UDB

IMO

Logic

32.768 kHz

( Optiona)l

UDB

UART

12- Bit PWM

RTC

Timer

System Bus

Program&

Debug

Memory System

CPU System

WDT

and

Wake

Interrupt

Cortex M 3CPU

EEPROM

SRAM

Program

Controller

Debug &

Trace

Cache

Controller

PHUB

DMA

Flash

EMIF

Boundary

Scan

ILO

Clocking System

Analog System

Power Management

System

LCD Direct

Drive

+

2 x

Opamp

POR and

LVD

3 per

Opamp

-

SAR

ADC

2 x SC/CT Blocks

(TIA, PGA, Mixer etc)

Sleep

Power

+

4 x

CMP

-

Del Sig

ADC

Temperature

Sensor

1.8V LDO

SMP

2 x DAC

CapSense

0. 5 to5.5V

( Optiona)l

Figure 1-1. on page 4 illustrates the major components of the

CY8C54LP family. They are:

PSoC’s digital subsystem provides half of its unique

configurability. It connects a digital signal from any peripheral to

any pin through the digital system interconnect (DSI). It also

provides functional flexibility through an array of small, fast,

low-power UDBs. PSoC Creator provides a library of pre-built

and tested standard digital peripherals (UART, SPI, LIN, PRS,

CRC, timer, counter, PWM, AND, OR, and so on) that are

mapped to the UDB array. You can also easily create a digital

circuit using boolean primitives by means of graphical design

entry. Each UDB contains programmable array logic

(PAL)/programmable logic device (PLD) functionality, together

with a small state machine engine to support a wide variety of

peripherals.

■ ARM Cortex-M3 CPU subsystem

■ Nonvolatile subsystem

■ Programming, debug, and test subsystem

■ Inputs and outputs

■ Clocking

■ Power

■ Digital subsystem

■ Analog subsystem

Document Number: 001-84934 Rev. *K

Page 4 of 126

PSoC^®5LP: CY8C54LP Family

Datasheet

In addition to the flexibility of the UDB array, PSoC also provides

configurable digital blocks targeted at specific functions. For the

CY8C54LP family these blocks can include four 16-bit timer,

counter, and PWM blocks; I²C slave, master, and multimaster;

Full-Speed USB.

See the “Analog Subsystem” section on page 50 of this

datasheet for more details.

PSoC’s CPU subsystem is built around a 32-bit three-stage

pipelined ARM Cortex-M3 processor running at up to 80 MHz.

The Cortex-M3 includes a tightly integrated nested vectored

interrupt controller (NVIC) and various debug and trace modules.

The overall CPU subsystem includes a DMA controller, flash

cache, and RAM. The NVIC provides low latency, nested

interrupts, and tail-chaining of interrupts and other features to

increase the efficiency of interrupt handling. The DMA controller

enables peripherals to exchange data without CPU involvement.

This allows the CPU to run slower (saving power) or use those

CPU cycles to improve the performance of firmware algorithms.

The flash cache also reduces system power consumption by

allowing less frequent flash access.

For more details on the peripherals see the “Example

Peripherals” section on page 40 of this datasheet. For

information on UDBs, DSI, and other digital blocks, see the

“Digital Subsystem” section on page 40 of this datasheet.

PSoC’s analog subsystem is the second half of its unique

configurability. All analog performance is based on a highly

accurate absolute voltage reference with less than 1% error over

temperature and voltage. The configurable analog subsystem

includes:

■ Analog muxes

PSoC’s nonvolatile subsystem consists of flash, byte-writeable

EEPROM, and nonvolatile configuration options. It provides up

to 256 KB of on-chip flash. The CPU can reprogram individual

blocks of flash, enabling boot loaders. You can enable an error

correcting code (ECC) for high reliability applications. A powerful

and flexible protection model secures the user's sensitive

information, allowing selective memory block locking for read

and write protection. Two KB of byte-writable EEPROM is

available on-chip to store application data. Additionally, selected

configuration options such as boot speed and pin drive mode are

stored in nonvolatile memory. This allows settings to activate

immediately after POR.

■ Comparators

■ Analog mixers

■ Voltage references

■ Analog-to-Digital Converters (ADC)

■ Digital-to-Analog Converters (DACs)

All GPIO pins can route analog signals into and out of the device

using the internal analog bus. This allows the device to interface

up to 62 discrete analog signals.

Some CY8C54LP devices offer a fast, accurate, configurable

delta-sigma ADC with these features:

The three types of PSoC I/O are extremely flexible. All I/Os have

many drive modes that are set at POR. PSoC also provides up

to four I/O voltage domains through the VDDIO pins. Every GPIO

has analog I/O, LCD drive, CapSense, flexible interrupt

generation, slew rate control, and digital I/O capability. The SIOs

on PSoC allow V_OHto be set independently of VDDIO when used

as outputs. When SIOs are in input mode they are high

impedance. This is true even when the device is not powered or

when the pin voltage goes above the supply voltage. This makes

the SIO ideally suited for use on an I²C bus where the PSoC may

not be powered when other devices on the bus are. The SIO pins

also have high current sink capability for applications such as

LED drives. The programmable input threshold feature of the

SIO can be used to make the SIO function as a general purpose

analog comparator. For devices with Full-Speed USB the USB

physical interface is also provided (USBIO). When not using

USB these pins may also be used for limited digital functionality

and device programming. All the features of the PSoC I/Os are

covered in detail in the “I/O System and Routing” section on

page 33 of this datasheet.

■ Less than 100 µV offset

■ A gain error of 0.2 percent

■ INL less than ±1 LSB

■ DNL less than ±1 LSB

■ SINAD better than 66 dB

The CY8C54LP family also offers a SAR ADC. Featuring 12-bit

conversions at up to 1 M samples per second, it also offers low

nonlinearity and offset errors and SNR better than 70 dB. It is

well suited for a variety of higher speed analog applications.

Two high speed voltage or current DACs support 8-bit output

signals at an update rate of up to 8 Msps. They can be routed

out of any GPIO pin. You can create higher resolution voltage

PWM DAC outputs using the UDB array. This can be used to

create a pulse width modulated (PWM) DAC of up to 10 bits, at

up to 48 kHz. The digital DACs in each UDB support PWM, PRS,

or delta-sigma algorithms with programmable widths.

The PSoC device incorporates flexible internal clock generators,

designed for high stability and factory trimmed for high accuracy.

The internal main oscillator (IMO) is the master clock base for

the system, and has 2% accuracy at 3 MHz. The IMO can be

configured to run from 3 MHz up to 74 MHz. Multiple clock

derivatives can be generated from the main clock frequency to

meet application needs. The device provides a PLL to generate

system clock frequencies up to 80 MHz from the IMO, external

crystal, or external reference clock. It also contains a separate,

very low-power internal low speed oscillator (ILO) for the sleep

and watchdog timers. A 32.768-kHz external watch crystal is

also supported for use in real time clock (RTC) applications. The

clocks, together with programmable clock dividers, provide the

flexibility to integrate most timing requirements.

In addition to the ADC and DACs, the analog subsystem

provides multiple:

■ Comparators

■ Uncommitted opamps

■ Configurable switched capacitor/continuous time (SC/CT)

blocks. These support:

❐ Transimpedance amplifiers

❐ Programmable gain amplifiers

❐ Mixers

❐ Other similar analog components

Document Number: 001-84934 Rev. *K

Page 5 of 126

PSoC^®5LP: CY8C54LP Family

Datasheet

The CY8C54LP family supports a wide supply operating range

from 1.71 to 5.5 V. This allows operation from regulated supplies

such as 1.8 ± 5%, 2.5 V ±10%, 3.3 V ± 10%, or 5.0 V ± 10%, or

directly from a wide range of battery types. In addition, it provides

an integrated high efficiency synchronous boost converter that

can power the device from supply voltages as low as 0.5 V. This

enables the device to be powered directly from a single battery.

In addition, you can use the boost converter to generate other

voltages required by the device, such as a 3.3 V supply for LCD

glass drive. The boost’s output is available on the V_BOOSTpin,

allowing other devices in the application to be powered from the

PSoC.

Figure 2-1.VDDIO Current Limit

I_{DDIO X}= 100 mA

V_{DDIO X}

I/O Pins

PSoC

PSoC supports a wide range of low-power modes. These include

a 300-nA hibernate mode with RAM retention and a 2-µA sleep

mode with RTC. In the second mode the optional 32.768-kHz

watch crystal runs continuously and maintains an accurate RTC.

Power to all major functional blocks, including the programmable

digital and analog peripherals, can be controlled independently

by firmware. This allows low-power background processing

when some peripherals are not in use. This, in turn, provides a

total device current of only 3.1 mA when the CPU is running at

6 MHz.

Conversely, for the 100-pin and 68-pin devices, the set of I/O

pins associated with any VDDIO may sink up to 100 mA total, as

shown in Figure 2-2..

Figure 2-2.I/O Pins Current Limit

The details of the PSoC power modes are covered in the “Power

System” section on page 27 of this datasheet.

Ipins = 100 mA

PSoC uses JTAG (4-wire) or SWD (2-wire) interfaces for

programming, debug, and test. Using these standard interfaces

you can debug or program the PSoC with a variety of hardware

solutions from Cypress or third party vendors. The Cortex-M3

debug and trace modules include FPB, DWT, ETM, and ITM.

These modules have many features to help solve difficult debug

and trace problems. Details of the programming, test, and

debugging interfaces are discussed in the “Programming, Debug

Interfaces, Resources” section on page 60 of this datasheet.

V_{DDIO X}

I/O Pins

PSoC

V_SSD

2. Pinouts

Each VDDIO pin powers a specific set of I/O pins. (The USBIOs

are powered from VDDD.) Using the VDDIO pins, a single PSoC

can support multiple voltage levels, reducing the need for

off-chip level shifters. The black lines drawn on the pinout

diagrams in Figure 2-3. and Figure 2-4., as well as Table 2-1,

show the pins that are powered by each VDDIO.

Each VDDIO may source up to 100 mA total to its associated I/O

pins, as shown in Figure 2-1..

Document Number: 001-84934 Rev. *K

Page 6 of 126

PSoC^®5LP: CY8C54LP Family

Datasheet

Figure 2-3.68-Pin QFN Part Pinout^[3]

(TRACEDATA[2], GPIO)P2[6]

(TRACEDATA[3], GPIO)P2[7]

(I2C0: SCL, SIO) P12[4]

P0[3] (GPIO, OPAMP0-/EXTREF0)

P0[2] (GPIO, OPAMP0+/SAR1 EXTREF)

P0[1] (GPIO, OPAMP0 O)UT

1

2

3

4

5

6

51

50

LINES SHOW VDDIO

TO IO SUPPLY

ASSOCIATION

49

48

47

(I2C0: SDA, SIO) P12[5]

P0[0] (GPIO, OPAMP2OUT)

VSSB

IND

P12[3] (SIO)

P12[2] (SIO)

VSSD

VDDA

VSSA

46

45

VBOOST

VBAT

7

8

9

44

43

42

QFN

(TOP VIEW)

VSSD

VCCA

10

XRES

(TMS, SWDIO, GPIO)P1[0]

(TCK, SWDCK, GPIO)P1[1]

(Configurable XRES, GPIO)P1[2]

P15[3] (GPIO, KHZ XTAL:XI)

P15[2] (GPIO, KHZ XTAL:XO)

11

12

13

41

40

39

38

37

36

P12[1] (SIO,I2C1: SDA)

P12[0] (SIO, 12C1: SCL)

(TDO, SWV, GPIO)P1[3] 14

(TDI, GPIO)P1[4]

(NTRST, GPIO)P1[5]

VDDIO1

15

16

17

P3[7] (GPIO)

P3[6] (GPIO)

VDDIO 3

35

Notes

3. The center pad on the QFN package should be connected to digital ground (VSSD) for best mechanical, thermal, and electrical performance. If not connected to

ground, it should be electrically floated and not connected to any other signal. For more information, see AN72845, Design Guidelines for QFN Devices.

4. Pins are Do Not Use (DNU) on devices without USB. The pin must be left floating.

Document Number: 001-84934 Rev. *K

Page 7 of 126

PSoC^®5LP: CY8C54LP Family

Datasheet

Figure 2-4.100-Pin TQFP Part Pinout

(TRACEDATA[1] , GPIO)P2[5]

(TRACEDATA[2] , GPIO)P2[6]

(TRACEDATA[3] , GPIO)P2[7]

VDDIO0

1

2

3

4

5

6

75

74

P0[3] ( GPIO,OPAMP0-/EXTREF0)

P0[2] ( GPIO,OPAMP0 +/SAR1 EXTREF)

P0[1] ( GPIO,OPAMP0OUT)

73

72

71

Lines show VDDIO to

I/O supply association

(I2C0 : SCL, SIO)P12[4]

(I2C0 : SDA, SIO)P12[5]

( GPIO)P6[4]

P0[0] ( GPIO,OPAMP2OUT)

P4[1] ( GPIO)

P4[0] ( GPIO)

P12[3] (SIO)

70

69

( GPIO)P6[5]

( GPIO)P6[6]

( GPIO)P6[7]

7

8

9

68

67

P12[2] (SIO)

VSSD

10

66

VSSB

IND

VBOOST

VBAT

VDDA

VSSA

11

12

13

65

64

63

VCCA

NC

TQFP

VSSD 14

62

61

60

59

58

57

56

55

XRES

( GPIO)P5[0]

( GPIO)P5[1]

15

16

17

NC

( GPIO)P5[2]

( GPIO)P5[3]

( TMS, SWDIO, GPIO)P1[0]

18

19

20

21

22

P15[3] ( GPIO, KHZ XTAL:XI)

P15[2] ( GPIO, KHZ XTAL:XO)

( TCK, SWDCK, GPIO)P1[1]

(Configurable XRES , GPIO)P1[2]

( TDO, SWV, GPIO)P1[3]

P12[1] (SIO,I2C1 : SDA)

P12[0] (SIO,I2C1 : SCL)

P3[7] ( GPIO)

54

53

23

52

51

( TDI, GPIO)P1[4]

( NTRST, GPIO)P1[5]

24

25

P3[6] ( GPIO)

Table 2-1. V_DDIOand Port Pin Associations

VDDIO

Port Pins

VDDIO0

VDDIO1

VDDIO2

VDDIO3

VDDD

P0[7:0], P4[7:0], P12[3:2]

P1[7:0], P5[7:0], P12[7:6]

P2[7:0], P6[7:0], P12[5:4], P15[5:4]

P3[7:0], P12[1:0], P15[3:0]

P15[7:6] (USB D+, D-)

Note

5. Pins are Do Not Use (DNU) on devices without USB. The pin must be left floating.

Document Number: 001-84934 Rev. *K

Page 8 of 126

PSoC^®5LP: CY8C54LP Family

Datasheet

Table 2-2 shows the pinout for the 99-pin CSP package. Since there are four V_DDIOpins, the set of I/O pins associated with any V_DDIO

may sink up to 100 mA total, same as for the 100-pin and 68-pin devices.

Table 2-2. CSP Pinout

Ball

E5

G6

G5

H6

K7

L8

J6

Name

P2[5]

P2[6]

P2[7]

P12[4]

P12[5]

P6[4]

P6[5]

P6[6]

P6[7]

VSSB

Ind

Ball

L2

Name

VIO1

Ball

B2

B3

C3

C4

E3

E4

A1

A9

L1

Name

P3[6]

P3[7]

P12[0]

P12[1]

P15[2]

P15[3]

NC

Ball

C8

D7

E7

B9

D8

D9

F8

F7

E6

E9

F9

G9

H9

G8

H8

J9

Name

VIO0

P0[4]

P0[5]

P0[6]

P0[7]

P4[4]

P4[5]

P4[6]

P4[7]

VCCD

VSSD

VDDD

P6[0]

P6[1]

P6[2]

P6[3]

P15[4]

P15[5]

P2[0]

P2[1]

P2[2]

P2[3]

P2[4]

VIO2

K2

C9

E8

K1

H2

F4

J1

P1[6]

P4[2]

P4[3]

P1[7]

P12[6]

P12[7]

P5[4]

P5[5]

P5[6]

P5[7]

P15[6]

P15[7]

VDDD

VSSD

VCCD

P15[0]

P15[1]

P3[0]

P3[1]

P3[2]

P3[3]

P3[4]

P3[5]

VIO3

H5

J5

NC

H1

F3

G1

G2

F2

E2

F1

E1

D1

D2

C1

C2

D3

D4

B4

A2

B1

NC

L7

K6

L6

K5

L5

L4

J4

L9

NC

A3

A4

B7

B8

C7

A5

A6

B5

A7

C5

D5

B6

C6

A8

D6

VCCA

VSSA

VDDA

VSSD

P12[2]

P12[3]

P4[0]

P4[1]

P0[0]

P0[1]

P0[2]

P0[3]

VBOOST

VBAT

VSSD

XRES

P5[0]

P5[1]

P5[2]

P5[3]

P1[0]

P1[1]

P1[2]

P1[3]

P1[4]

P1[5]

K4

K3

L3

H4

J3

G7

F6

F5

J7

J8

H3

J2

K9

H7

K8

G4

G3

Document Number: 001-84934 Rev. *K

Page 9 of 126

PSoC^®5LP: CY8C54LP Family

Datasheet

Figure 2-5. and Figure 2-6. show an example schematic and an

example PCB layout, for the 100-pin TQFP part, for optimal

analog performance on a 2-layer board.

■ The two pins labeled VSSD must be connected together.

For information on circuit board layout issues for mixed signals,

refer to the application note AN57821 - Mixed Signal Circuit

Board Layout Considerations for PSoC® 3 and PSoC 5.

■ The two pins labeled VDDD must be connected together.

■ The two pins labeled VCCD must be connected together, with

capacitanceadded, asshowninFigure 2-5.andPowerSystem

on page 27. The trace between the two VCCD pins should be

as short as possible.

Figure 2-5.Example Schematic for 100-Pin TQFP Part with Power Connections

VDDD

C1

1 UF

C2

0.1 UF

VDDD

VCCD

C6

0.1 UF

VSSD

VDDA

VDDD

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

P2[5]

P2[6]

P2[7]

P12[4], SIO

P12[5], SIO

P6[4]

P6[5]

P6[6]

P6[7]

VSSB

IND

VBOOST

VBAT

VSSD

XRES

P5[0]

P5[1]

VDDIO0

OA0-, REF0, P0[3]

OA0+, SAR1REF, P0[2]

OA0OUT, P0[1]

OA2OUT, P0[0]

P4[1]

C8

0.1 UF

C17

1 UF

VSSD

P4[0]

VSSA

SIO, P12[3]

SIO, P12[2]

VSSD

VDDA

VSSA

VCCA

VDDA

VSSA

VCCA

NC

VSSD

C9

1 UF

C10

0.1 UF

P5[2]

P5[3]

NC

VSSA

P1[0], SWDIO, TMS

P1[1], SWDCK, TCK

P1[2]

P1[3], SWV, TDO

P1[4], TDI

P1[5], NTRST

KHZXIN, P15[3]

KHZXOUT, P15[2]

SIO, P12[1]

SIO, P12[0]

OA3OUT, P3[7]

OA1OUT, P3[6]

VDDD

C11

0.1 UF

C12

0.1 UF

VSSD

C15

C16

VSSD

0.1 UF

1 UF

VSSD

Note The two VCCD pins must be connected together with as short a trace as possible. A trace under the device is recommended,

as shown in Figure 2-6..

For more information on pad layout, refer to http://www.cypress.com/cad-resources/psoc-5lp-cad-libraries.

Document Number: 001-84934 Rev. *K

Page 10 of 126

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Datasheet

Figure 2-6.Example PCB Layout for 100-Pin TQFP Part for Optimal Analog Performance

VSSA

VDDD

VSSD

VDDA

VSSA

Plane

VSSD

Plane

SIO. Special I/O provides interfaces to the CPU, digital

peripherals and interrupts with a programmable high threshold

voltage, analog comparator, high sink current, and high

impedance state when the device is unpowered.

3. Pin Descriptions

IDAC0, IDAC2. Low resistance output pin for high current DACs

(IDAC).

SWDCK. Serial Wire Debug Clock programming and debug port

connection.

Opamp0out, Opamp2out. High current output of uncommitted

opamp^[6]

.

SWDIO. Serial Wire Debug Input and Output programming and

debug port connection.

Extref0, Extref1. External reference input to the analog system.

SAR0 EXTREF, SAR1 EXTREF. External references for SAR

ADCs.

TCK. JTAG Test Clock programming and debug port connection.

Opamp0-, Opamp2-. Inverting input to uncommitted opamp.

TDI. JTAG Test Data In programming and debug port

connection.

Opamp0+, Opamp2+. Noninverting input to uncommitted

opamp.

TDO. JTAG Test Data Out programming and debug port

connection.

GPIO. General purpose I/O pin provides interfaces to the CPU,

digital peripherals, analog peripherals, interrupts, LCD segment

TMS. JTAG Test Mode Select programming and debug port

connection.

drive, and CapSense^[6]

.

I2C0: SCL, I2C1: SCL. I²C SCL line providing wake from sleep

on an address match. Any I/O pin can be used for I²C SCL if

wake from sleep is not required.

TRACECLK. Cortex-M3 TRACEPORT connection, clocks

TRACEDATA pins.

TRACEDATA[3:0]. Cortex-M3 TRACEPORT connections,

output data.

I2C0: SDA, I2C1: SDA. I²C SDA line providing wake from sleep

on an address match. Any I/O pin can be used for I²C SDA if

wake from sleep is not required.

SWV. Single Wire Viewer output.

USBIO, D+. Provides D+ connection directly to a USB 2.0 bus.

May be used as a digital I/O pin; it is powered from VDDD instead

of from a VDDIO. Pins are Do Not Use (DNU) on devices without

USB.

Ind. Inductor connection to boost pump.

kHz XTAL: Xo, kHz XTAL: Xi. 32.768 kHz crystal oscillator pin.

MHz XTAL: Xo, MHz XTAL: Xi. 4 to 25 MHz crystal oscillator

pin.

USBIO, D-. Provides D- connection directly to a USB 2.0 bus.

May be used as a digital I/O pin; it is powered from VDDD instead

of from a VDDIO. Pins are Do Not Use (DNU) on devices without

USB.

nTRST. Optional JTAG Test Reset programming and debug port

connection to reset the JTAG connection.

VBOOST. Power sense connection to boost pump.

Note

6. GPIOs with opamp outputs are not recommended for use with CapSense

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PSoC^®5LP: CY8C54LP Family

Datasheet

VBAT. Battery supply to boost pump.

VDDD. Supply for all digital peripherals and digital core

regulator. VDDD must be less than or equal to VDDA.

VCCA. Output of the analog core regulator or the input to

the analog core. Requires a 1uF capacitor to VSSA. The

regulator output is not designed to drive external circuits. Note

that if you use the device with an external core regulator

(externally regulated mode), the voltage applied to this pin

must not exceed the allowable range of 1.71 V to 1.89 V.

When using the internal core regulator, (internally regulated

mode, the default), do not tie any power to this pin. For details

see Power System on page 27.

VSSA. Ground for all analog peripherals.

VSSB. Ground connection for boost pump.

VSSD. Ground for all digital logic and I/O pins.

VDDIO0, VDDIO1, VDDIO2, VDDIO3. Supply for I/O pins. Each

VDDIO must be tied to a valid operating voltage (1.71 V to 5.5 V),

and must be less than or equal to VDDA.

XRES. External reset pin. Active low with internal pull-up.

VCCD. Output of the digital core regulator or the input to the

digital core. The two VCCD pins must be shorted together, with

the trace between them as short as possible, and a 1uF capacitor

to VSSD. The regulator output is not designed to drive external

circuits. Note that if you use the device with an external core

regulator (externally regulated mode), the voltage applied to

this pin must not exceed the allowable range of 1.71 V to

1.89 V. When using the internal core regulator (internally

regulated mode, the default), do not tie any power to this pin. For

details see Power System on page 27.

4. CPU

4.1 ARM Cortex-M3 CPU

The CY8C54LP family of devices has an ARM Cortex-M3 CPU

core. The Cortex-M3 is a low power 32-bit three-stage pipelined

Harvard architecture CPU that delivers 1.25 DMIPS/MHz. It is

intended for deeply embedded applications that require fast

interrupt handling features.

VDDA. Supply for all analog peripherals and analog core

regulator. VDDA must be the highest voltage present on the

device. All other supply pins must be less than or equal to

VDDA.

Document Number: 001-84934 Rev. *K

Page 12 of 126

PSoC^®5LP: CY8C54LP Family

Datasheet

Figure 4-1.ARM Cortex-M3 Block Diagram

Data

Watchpoint and

Trace (DWT)

Nested

Vectored

Interrupt

Controller

(NVIC)

Interrupt Inputs

Cortex M3 CPU Core

Embedded

Trace Module

(ETM)

Instrumentation

Trace Module

(ITM)

D-Bus

C-Bus

I-Bus

S-Bus

Trace Pins:

5 for TRACEPORT or

1 for SWV mode

Debug Block

(Serial and

JTAG)

Trace Port

Interface Unit

(TPIU)

JTAG/SWD

Flash Patch

and Breakpoint

(FPB)

Cortex M3 Wrapper

AHB

32 KB

Bus

Matrix

Bus

Matrix

256 KB

ECC

Flash

SRAM

1 KB

Cache

AHB

32 KB

SRAM

Bus

Matrix

AHB Bridge & Bus Matrix

DMA

PHUB

AHB Spokes

GPIO &

EMIF

Prog.

Digital

Prog.

Analog

Special

Functions

Peripherals

Document Number: 001-84934 Rev. *K

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PSoC^®5LP: CY8C54LP Family

Datasheet

The Cortex-M3 CPU subsystem includes these features:

■ ARM Cortex-M3 CPU

At the user level, access to certain instructions, special registers,

configuration registers, and debugging components is blocked.

Attempts to access them cause a fault exception. At the

privileged level, access to all instructions and registers is

allowed.

■ Programmable NVIC, tightly integrated with the CPU core

■ Full-featured debug and trace modules, tightly integrated with

the CPU core

The processor runs in the handler mode (always at the privileged

level) when handling an exception, and in the thread mode when

not.

■ Up to 128 KB of flash memory, 2 KB of EEPROM, and 32 KB

of SRAM

4.1.3 CPU Registers

■ Cache controller

The Cortex-M3 CPU registers are listed in Table 4-2. Registers

R0-R15 are all 32 bits wide.

■ Peripheral HUB (PHUB)

■ DMA controller

Table 4-2. Cortex M3 CPU Registers

Register

R0-R12

Description

■ External memory interface (EMIF)

General purpose registers R0-R12 have no

special architecturally defined uses. Most

instructions that specify a general purpose

register specify R0-R12.

4.1.1 Cortex-M3 Features

The Cortex-M3 CPU features include:

■ 4-GB address space. Predefined address regions for code,

data, and peripherals. Multiple buses for efficient and

simultaneous accesses of instructions, data, and peripherals.

■ Low Registers: Registers R0-R7 are acces-

sible by all instructions that specify a general

purpose register.

®

■ The Thumb -2 instruction set, which offers ARM-level

performance at Thumb-level code density. This includes 16-bit

and 32-bit instructions. Advanced instructions include:

❐ Bit-field control

❐ Hardware multiply and divide

❐ Saturation

❐ If-Then

❐ Wait for events and interrupts

❐ Exclusive access and barrier

❐ Special register access

■ High Registers: Registers R8-R12 are acces-

sible by all 32-bit instructions that specify a

general purpose register; they are not acces-

sible by all 16-bit instructions.

R13

R13 is the stack pointer register. It is a banked

register that switches between two 32-bit stack

pointers: the Main Stack Pointer (MSP) and the

Process Stack Pointer (PSP). The PSP is used

only when the CPU operates at the user level in

thread mode. The MSP is used in all other

privilege levels and modes. Bits[0:1] of the SP

are ignored and considered to be 0, so the SP is

always aligned to a word (4 byte) boundary.

The Cortex-M3 does not support ARM instructions.

■ Bit-band support for the SRAM region. Atomic bit-level write

and read operations for SRAM addresses.

R14

R15

R14 is the Link Register (LR). The LR stores the

return address when a subroutine is called.

■ Unaligned data storage and access. Contiguous storage of

data of different byte lengths.

R15 is the Program Counter (PC). Bit 0 of the PC

is ignoredand consideredto be0, so instructions

are always aligned to a half word (2 byte)

boundary.

■ Operation at two privilege levels (privileged and user) and in

two modes (thread and handler). Some instructions can only

be executed at the privileged level. There are also two stack

pointers: Main (MSP) and Process (PSP). These features

support a multitasking operating system running one or more

user-level processes.

xPSR

The Program status registers are divided into

three status registers, which are accessed either

together or separately:

■ Extensive interrupt and system exception support.

■ Application Program Status Register (APSR)

holds program execution status bits such as

zero, carry, negative, in bits[27:31].

4.1.2 Cortex-M3 Operating Modes

The Cortex-M3 operates at either the privileged level or the user

level, and in either the thread mode or the handler mode.

Because the handler mode is only enabled at the privileged level,

there are actually only three states, as shown in Table 4-1.

■ Interrupt Program Status Register (IPSR)

holds the current exception number in bits[0:8].

■ Execution Program Status Register (EPSR)

holds control bits for interrupt continuable and

IF-THEN instructions in bits[10:15] and

[25:26]. Bit 24 is always set to 1 to indicate

Thumb mode. Trying to clear it causes a fault

exception.

Table 4-1. Operational Level

Condition

Privileged

User

Running an exception Handler mode Not used

Running main program Thread mode

Document Number: 001-84934 Rev. *K

Thread mode

Page 14 of 126

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Datasheet

Table 4-2. Cortex M3 CPU Registers (continued)

Table 4-3. PHUB Spokes and Peripherals

Register

Description

PHUB Spokes

Peripherals

PRIMASK

A 1-bit interrupt mask register. When set, it

allows only the nonmaskable interrupt (NMI) and

hard fault exception. All other exceptions and

interrupts are masked.

0

1

2

SRAM

IOs, PICU, EMIF

PHUB local configuration, Power manager,

Clocks, IC, SWV, EEPROM, Flash

programming interface

FAULTMASK A 1-bit interrupt mask register. When set, it

allows only the NMI. All other exceptions and

interrupts are masked.

3

4

5

6

7

Analog interface and trim, Decimator

2

USB, I C, Timers, Counters, and PWMs

BASEPRI

A register of up to nine bits that define the

masking priority level. When set, it disables all

interrupts of the same or higher priority value. If

set to 0 then the masking function is disabled.

Reserved

UDBs group 1

UDBs group 2

CONTROL

A 2-bit register for controlling the operating

mode.

4.3.2 DMA Features

Bit 0: 0 = privileged level in thread mode,

1 = user level in thread mode.

■ 24 DMA channels

Bit 1: 0 = default stack (MSP) is used,

■ Each channel has one or more transaction descriptors (TDs)

to configure channel behavior. Up to 128 total TDs can be

defined

1 = alternate stack is used. If in thread mode or

user level then the alternate stack is the PSP.

There is no alternate stack for handler mode; the

bit must be 0 while in handler mode.

■ TDs can be dynamically updated

■ Eight levels of priority per channel

4.2 Cache Controller

■ Anydigitallyroutablesignal, theCPU, oranotherDMAchannel,

can trigger a transaction

The CY8C58LP family has a 1 KB, 4-way set-associative

instruction cache between the CPU and the flash memory. This

guarantees a faster instruction execution rate. The flash cache

also reduces system power consumption by requiring less

frequent flash access.

■ Each channel can generate up to two interrupts per transfer

■ Transactions can be stalled or canceled

■ Supports transaction size of infinite or 1 to 64k bytes

4.3 DMA and PHUB

■ Large transactions may be broken into smaller bursts of 1 to

127 bytes

The PHUB and the DMA controller are responsible for data

transfer between the CPU and peripherals, and also data

transfers between peripherals. The PHUB and DMA also control

device configuration during boot. The PHUB consists of:

■ TDs may be nested and/or chained for complex transactions

4.3.3 Priority Levels

■ A central hub that includes the DMA controller, arbiter, and

The CPU always has higher priority than the DMA controller

when their accesses require the same bus resources. Due to the

system architecture, the CPU can never starve the DMA. DMA

channels of higher priority (lower priority number) may interrupt

current DMA transfers. In the case of an interrupt, the current

transfer is allowed to complete its current transaction. To ensure

latency limits when multiple DMA accesses are requested

simultaneously, a fairness algorithm guarantees an interleaved

minimum percentage of bus bandwidth for priority levels 2

through 7. Priority levels 0 and 1 do not take part in the fairness

algorithm and may use 100% of the bus bandwidth. If a tie occurs

on two DMA requests of the same priority level, a simple round

robin method is used to evenly share the allocated bandwidth.

The round robin allocation can be disabled for each DMA

channel, allowing it to always be at the head of the line. Priority

levels 2 to 7 are guaranteed the minimum bus bandwidth shown

in Table 4-4 after the CPU and DMA priority levels 0 and 1 have

satisfied their requirements.

router

■ Multiple spokes that radiate outward from the hub to most

peripherals

There are two PHUB masters: the CPU and the DMA controller.

Both masters may initiate transactions on the bus. The DMA

channels can handle peripheral communication without CPU

intervention. The arbiter in the central hub determines which

DMA channel is the highest priority if there are multiple requests.

4.3.1 PHUB Features

■ CPU and DMA controller are both bus masters to the PHUB

■ Eight multi-layer AHB bus parallel access paths (spokes) for

peripheral access

■ Simultaneous CPU and DMA access to peripherals located on

different spokes

When the fairness algorithm is disabled, DMA access is granted

based solely on the priority level; no bus bandwidth guarantees

are made.

■ Simultaneous DMA source and destination burst transactions

on different spokes

■ Supports 8-, 16-, 24-, and 32-bit addressing and data

Document Number: 001-84934 Rev. *K

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Datasheet

Table 4-4. Priority Levels

4.3.4 Transaction Modes Supported

The flexible configuration of each DMA channel and the ability to

chain multiple channels allow the creation of both simple and

complex use cases. General use cases include, but are not

limited to:

Priority Level

% Bus Bandwidth

0

1

2

3

4

5

6

7

100.0

50.0

25.0

12.5

6.2

4.3.4.2 Simple DMA

In a simple DMA case, a single TD transfers data between a

source and sink (peripherals or memory location). The basic

timing diagrams of DMA read and write cycles are shown in

Figure 4-3.. For more description on other transfer modes, refer

to the Technical Reference Manual.

3.1

1.5

Figure 4-3.DMA Timing Diagram

ADDRESS Phase

DATA Phase

ADDRESS Phase

DATA Phase

CLK

ADDR 16/32

WRITE

ADDR 16/32

A

B

A

B

WRITE

DATA

DATA (A)

DATA

READY

Basic DMA Read Transfer without wait states

Basic DMA Write Transfer without wait states

4.3.4.4 Auto Repeat DMA

4.3.4.8 Scatter Gather DMA

In the case of scatter gather DMA, there are multiple

Auto repeat DMA is typically used when a static pattern is

repetitively read from system memory and written to a peripheral.

This is done with a single TD that chains to itself.

noncontiguous sources or destinations that are required to

effectively carry out an overall DMA transaction. For example, a

packet may need to be transmitted off of the device and the

packet elements, including the header, payload, and trailer, exist

in various noncontiguous locations in memory. Scatter gather

DMA allows the segments to be concatenated together by using

multiple TDs in a chain. The chain gathers the data from the

multiple locations. A similar concept applies for the reception of

data onto the device. Certain parts of the received data may need

to be scattered to various locations in memory for software

processing convenience. Each TD in the chain specifies the

location for each discrete element in the chain.

4.3.4.5 Ping Pong DMA

A ping pong DMA case uses double buffering to allow one buffer

to be filled by one client while another client is consuming the

data previously received in the other buffer. In its simplest form,

this is done by chaining two TDs together so that each TD calls

the opposite TD when complete.

4.3.4.6 Circular DMA

Circular DMA is similar to ping pong DMA except it contains more

than two buffers. In this case there are multiple TDs; after the last

TD is complete it chains back to the first TD.

4.3.4.9 Packet Queuing DMA

Packet queuing DMA is similar to scatter gather DMA but

specifically refers to packet protocols. With these protocols,

there may be separate configuration, data, and status phases

associated with sending or receiving a packet.

4.3.4.7 Indexed DMA

In an indexed DMA case, an external master requires access to

locations on the system bus as if those locations were shared

memory. As an example, a peripheral may be configured as an

For instance, to transmit a packet, a memory mapped

2

SPI or I C slave where an address is received by the external

configuration register can be written inside a peripheral,

specifying the overall length of the ensuing data phase. The CPU

can set up this configuration information anywhere in system

memory and copy it with a simple TD to the peripheral. After the

configuration phase, a data phase TD (or a series of data phase

TDs) can begin (potentially using scatter gather). When the data

phase TD(s) finish, a status phase TD can be invoked that reads

some memory mapped status information from the peripheral

and copies it to a location in system memory specified by the

CPU for later inspection. Multiple sets of configuration, data, and

status phase “subchains” can be strung together to create larger

master. That address becomes an index or offset into the internal

system bus memory space. This is accomplished with an initial

“address fetch” TD that reads the target address location from

the peripheral and writes that value into a subsequent TD in the

chain. This modifies the TD chain on the fly. When the “address

fetch” TD completes it moves on to the next TD, which has the

new address information embedded in it. This TD then carries

out the data transfer with the address location required by the

external master.

chains that transmit multiple packets in this way. A similar

Document Number: 001-84934 Rev. *K

concept exists in the opposite direction to receive the packets.

Page 16 of 126

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Datasheet

4.3.4.10 Nested DMA

which again updates the second TD’s configuration. This

process repeats as often as necessary.

One TD may modify another TD, as the TD configuration space

is memory mapped similar to any other peripheral. For example,

a first TD loads a second TD’s configuration and then calls the

second TD. The second TD moves data as required by the

application. When complete, the second TD calls the first TD,

4.4 Interrupt Controller

The Cortex-M3 NVIC supports 16 system exceptions and 32

interrupts from peripherals, as shown in Table 4-5.

Table 4-5. Cortex-M3 Exceptions and Interrupts

Exception

Number

Exception Table

Address Offset

Exception Type

Priority

Function

0x00

0x04

0x08

0x0C

Starting value of R13 / MSP

Reset

1

2

3

Reset

–3 (highest)

NMI

–2

–1

Non maskable interrupt

Hard fault

Allclassesoffault, whenthecorrespondingfaulthandler

cannot be activated because it is currently disabled or

masked

4

5

6

MemManage

Bus fault

Programmable

0x10

0x14

0x18

Memory management fault, for example, instruction

fetch from a nonexecutable region

Error response received from the bus system; caused

by an instruction prefetch abort or data access error

Usage fault

Typically caused by invalid instructions or trying to

switch to ARM mode

7–10

11

–

0x1C–0x28

0x2C

Reserved

SVC

Programmable

–

System service call via SVC instruction

Debug monitor

12

Debug monitor

–

0x30

13

0x34

Reserved

14

PendSV

SYSTICK

IRQ

Programmable

0x38

Deferred request for system service

System tick timer

15

0x3C

16–47

0x40–0x3FC

Peripheral interrupt request #0–#31

Bit 0 of each exception vector indicates whether the exception is

executed using ARM or Thumb instructions. Because the

Cortex-M3 only supports Thumb instructions, this bit must

always be 1. The Cortex-M3 non maskable interrupt (NMI) input

can be routed to any pin, via the DSI, or disconnected from all

pins. See “DSI Routing Interface Description” section on

page 45.

■ Support for tail-chaining, and late arrival, of interrupts. This

enables back-to-back interrupt processing without the

overhead of state saving and restoration between interrupts.

■ Processor state automatically saved on interrupt entry, and

restored on interrupt exit, with no instruction overhead.

If the same priority level is assigned to two or more interrupts,

the interrupt with the lower vector number is executed first. Each

interrupt vector may choose from three interrupt sources: Fixed

Function, DMA, and UDB. The fixed function interrupts are direct

connections to the most common interrupt sources and provide

the lowest resource cost connection. The DMA interrupt sources

provide direct connections to the two DMA interrupt sources

provided per DMA channel. The third interrupt source for vectors

is from the UDB digital routing array. This allows any digital signal

available to the UDB array to be used as an interrupt source. All

interrupt sources may be routed to any interrupt vector using the

UDB interrupt source connections.

The NVIC handles interrupts from the peripherals, and passes

the interrupt vectors to the CPU. It is closely integrated with the

CPU for low latency interrupt handling. Features include:

■ 32 interrupts. Multiple sources for each interrupt.

■ Eight priority levels, with dynamic priority control.

■ Priority grouping. This allows selection of preempting and non

preempting interrupt levels.

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Table 4-6. Interrupt Vector Table

Interrupt # Cortex-M3 Exception #

Fixed Function

Low voltage detect (LVD)

Cache/ECC

DMA

phub_termout0[0]

phub_termout0[1]

phub_termout0[2]

phub_termout0[3]

phub_termout0[4]

phub_termout0[5]

phub_termout0[6]

phub_termout0[7]

phub_termout0[8]

phub_termout0[9]

phub_termout0[10]

phub_termout0[11]

phub_termout0[12]

phub_termout0[13]

phub_termout0[14]

phub_termout0[15]

phub_termout1[0]

phub_termout1[1]

phub_termout1[2]

phub_termout1[3]

phub_termout1[4]

phub_termout1[5]

phub_termout1[6]

phub_termout1[7]

phub_termout1[8]

phub_termout1[9]

phub_termout1[10]

phub_termout1[11]

phub_termout1[12]

phub_termout1[13]

phub_termout1[14]

phub_termout1[15]

UDB

udb_intr[0]

0

1

2

3

4

5

6

7

8

9

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

udb_intr[1]

udb_intr[2]

udb_intr[3]

udb_intr[4]

udb_intr[5]

udb_intr[6]

udb_intr[7]

udb_intr[8]

udb_intr[9]

udb_intr[10]

udb_intr[11]

udb_intr[12]

udb_intr[13]

udb_intr[14]

udb_intr[15]

udb_intr[16]

udb_intr[17]

udb_intr[18]

udb_intr[19]

udb_intr[20]

udb_intr[21]

udb_intr[22]

udb_intr[23]

udb_intr[24]

udb_intr[25]

udb_intr[26]

udb_intr[27]

udb_intr[28]

udb_intr[29]

udb_intr[30]

udb_intr[31]

Reserved

Sleep (Pwr Mgr)

PICU[0]

PICU[1]

PICU[2]

PICU[3]

PICU[4]

PICU[5]

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

PICU[6]

PICU[12]

PICU[15]

Comparators Combined

Switched Caps Combined

2

I C

Reserved

Timer/Counter0

Timer/Counter1

Timer/Counter2

Timer/Counter3

USB SOF Int

USB Arb Int

USB Bus Int

USB Endpoint[0]

USB Endpoint Data

Reserved

LCD

Reserved

Decimator Int

phub_err_int

eeprom_fault_int

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Page 18 of 126

PSoC^®5LP: CY8C54LP Family

Datasheet

“Device Security” section on page 63). For more information on

how to take full advantage of the security features in PSoC, see

the PSoC 5 TRM.

5. Memory

5.1 Static RAM

CY8C54LP static RAM (SRAM) is used for temporary data

storage. Code can be executed at full speed from the portion of

SRAM that is located in the code space. This process is slower

from SRAM above 0x20000000. The device provides up to 64

KB of SRAM. The CPU or the DMA controller can access all of

SRAM. The SRAM can be accessed simultaneously by the

Cortex-M3 CPU and the DMA controller if accessing different

32-KB blocks.

Table 5-1. Flash Protection

Protection

Setting

Allowed

Not Allowed

Unprotected

External read and write

+ internal read and write

–

Factory

Upgrade

External write + internal External read

read and write

5.2 Flash Program Memory

Field Upgrade Internal read and write External read and

write

Flash memory in PSoC devices provides nonvolatile storage for

user firmware, user configuration data, bulk data storage, and

optional ECC data. The main flash memory area contains up to

256 KB of user program space.

Full Protection Internal read

External read and

write + internal write

Up to an additional 32 KB of flash space is available for Error

Correcting Codes (ECC). If ECC is not used this space can store

device configuration data and bulk user data. User code may not

be run out of the ECC flash memory section. ECC can correct

one bit error and detect two bit errors per 8 bytes of firmware

memory; an interrupt can be generated when an error is

detected. The flash output is 9 bytes wide with 8 bytes of data

and 1 byte of ECC data.

Disclaimer

Note the following details of the flash code protection features on

Cypress devices.

Cypress products meet the specifications contained in their

particular Cypress datasheets. Cypress believes that its family of

products is one of the most secure families of its kind on the

market today, regardless of how they are used. There may be

methods, unknown to Cypress, that can breach the code

protection features. Any of these methods, to our knowledge,

would be dishonest and possibly illegal. Neither Cypress nor any

other semiconductor manufacturer can guarantee the security of

their code. Code protection does not mean that we are

guaranteeing the product as “unbreakable.”

The CPU or DMA controller read both user code and bulk data

located in flash through the cache controller. This provides

higher CPU performance. If ECC is enabled, the cache controller

also performs error checking and correction.

Flash programming is performed through a special interface and

preempts code execution out of flash. Code execution may be

done out of SRAM during flash programming.

Cypress is willing to work with the customer who is concerned

about the integrity of their code. Code protection is constantly

evolving. We at Cypress are committed to continuously

improving the code protection features of our products.

The flash programming interface performs flash erasing,

programming and setting code protection levels. Flash in-system

serial programming (ISSP), typically used for production

programming, is possible through both the SWD and JTAG

interfaces. In-system programming, typically used for

5.4 EEPROM

2

bootloaders, is also possible using serial interfaces such as I C,

PSoC EEPROM memory is a byte addressable nonvolatile

memory. The CY8C54LP has 2 KB of EEPROM memory to store

user data. Reads from EEPROM are random access at the byte

level. Reads are done directly; writes are done by sending write

commands to an EEPROM programming interface. CPU code

execution can continue from flash during EEPROM writes.

EEPROM is erasable and writeable at the row level. The

EEPROM is divided into 128 rows of 16 bytes each. The factory

default values of all EEPROM bytes are 0.

USB, UART, and SPI, or any communications protocol.

5.3 Flash Security

All PSoC devices include a flexible flash protection model that

prevents access and visibility to on-chip flash memory. This

prevents duplication or reverse engineering of proprietary code.

Flash memory is organized in blocks, where each block contains

256 bytes of program or data and 32 bytes of ECC or

configuration data.

Because the EEPROM is mapped to the Cortex-M3 Peripheral

region, the CPU cannot execute out of EEPROM. There is no

ECC hardware associated with EEPROM. If ECC is required it

must be handled in firmware.

The device offers the ability to assign one of four protection

levels to each row of flash. Table 5-1 lists the protection modes

available. Flash protection levels can only be changed by

performing a complete flash erase. The Full Protection and Field

Upgrade settings disable external access (through a debugging

tool such as PSoC Creator, for example). If your application

requires code update through a boot loader, then use the Field

Upgrade setting. Use the Unprotected setting only when no

security is needed in your application. The PSoC device also

offers an advanced security feature called Device Security which

permanently disables all test, programming, and debug ports,

protecting your application from external access (see the

It can take as much as 20 milliseconds to write to EEPROM or

flash. During this time the device should not be reset, or

unexpected changes may be made to portions of EEPROM or

flash. Reset sources (see Section 6.3.1) include XRES pin,

software reset, and watchdog; care should be taken to make

sure that these are not inadvertently activated. In addition, the

low voltage detect circuits should be configured to generate an

interrupt instead of a reset.

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5.5 Nonvolatile Latches (NVLs)

PSoC has a 4-byte array of nonvolatile latches (NVLs) that are used to configure the device at reset. The NVL register map is shown

in Table 5-2.

Table 5-2. Device Configuration NVL Register Map

Register Address

7

6

5

4

3

2

1

0

0x00

0x01

0x02

0x03

PRT3RDM[1:0]

PRT12RDM[1:0]

PRT2RDM[1:0]

PRT6RDM[1:0]

PRT1RDM[1:0]

PRT5RDM[1:0]

PRT0RDM[1:0]

PRT4RDM[1:0]

PRT15RDM[1:0]

XRESMEN

DBGEN

DIG_PHS_DLY[3:0]

ECCEN

DPS[1:0]

CFGSPEED

The details for individual fields and their factory default settings are shown in Table 5-2:.

Table 5-2. Fields and Factory Default Settings

Field

Description

Settings

PRTxRDM[1:0]

Controls reset drive mode of the corresponding IO port. 00b (default) - high impedance analog

See “Reset Configuration” on page 39. All pins of the port 01b - high impedance digital

are set to the same mode.

10b - resistive pull up

11b - resistive pull down

XRESMEN

Controls whether pin P1[2] is used as a GPIO or as an

external reset. P1[2] is generally used as a GPIO, and not 1 - external reset

0 (default) - GPIO

as an external reset.

DBGEN

Debug Enable allows access to the debug system, for

third-party programmers.

0 - access disabled

1 (default) - access enabled

CFGSPEED

Controls the speed of the IMO-based clock during the

device boot process, for faster boot or low-power

operation

0 (default) - 12 MHz IMO

1 - 48 MHz IMO

DPS[1:0]

Controls the usage of various P1 pins as a debug port. 00b - 5-wire JTAG

See “Programming, Debug Interfaces, Resources” on

page 60.

01b (default) - 4-wire JTAG

10b - SWD

11b - debug ports disabled

ECCEN

Controls whether ECC flash is used for ECC or for general 0 - ECC disabled

configuration and data storage. See “Flash Program

Memory” on page 19.

1 (default) - ECC enabled

See the TRM for details.

DIG_PHS_DLY[3:0]

Selects the digital clock phase delay.

Although PSoC Creator provides support for modifying the device configuration NVLs, the number of NVL erase/write cycles is limited

– see “Nonvolatile Latches (NVL)” on page 106.

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Datasheet

External memory is located in the Cortex-M3 external RAM

space; it can use up to 24 address bits. See Table 5-3 on page

22 and Memory Map on page 22. The memory can be 8 or 16

bits wide.

5.6 External Memory Interface

CY8C54LP provides an EMIF for connecting to external memory

devices. The connection allows read and write accesses to

external memories. The EMIF operates in conjunction with

UDBs, I/O ports, and other hardware to generate external

memory address and control signals. At 33 MHz, each memory

access cycle takes four bus clock cycles.

Cortex-M3 instructions can be fetched from external memory if it

is 16-bit. Other limitations apply; for details, see application note

®

AN89610, PSoC 4 and PSoC 5LP ARM Cortex Code

Optimization.There is no provision for code security in external

memory. If code must be kept secure, then it should be placed in

internal flash. See Flash Security on page 19 and Device

Security on page 63.

Figure 5-1. is the EMIF block diagram. The EMIF supports

synchronous and asynchronous memories. The CY8C54LP only

supports one type of external memory device at a time.

Figure 5-1.EMIF Block Diagram

[23:0]

External_MEM_ ADDR

Address Signals

I/O

PORTs

Data,

,

Address

and Control

Signals

External_MEM_DATA[15:0]

Data Signals

IO IF

I/O

PORTs

Control Signals

Control

I/O

PORTs

PHUB

Data,

Address,

and Control

Signals

DSI Dynamic Output

Control

UDB

DSI to Port

Other

EM Control

Signals

Control

Signals

Data,

Address,

and Control

Signals

EMIF

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PSoC^®5LP: CY8C54LP Family

Datasheet

Table 5-4. Peripheral Data Address Map (continued)

5.7 Memory Map

The Cortex-M3 has a fixed address map, which allows

peripherals to be accessed by simple memory access

instructions.

Address Range

Purpose

0x40004F00–0x40004FFF Fixed timer/counter/PWMs

0x40005000–0x400051FF I/O ports control

5.7.1 Address Map

0x40005400–0x400054FF External Memory Interface

(EMIF) control registers

The 4-GB address space is divided into the ranges shown in

Table 5-3:

0x40005800–0x40005FFF Analog Subsystem Interface

0x40006000–0x400060FF USB Controller

Table 5-3. Address Map

0x40006400–0x40006FFF UDB Working Registers

0x40007000–0x40007FFF PHUB Configuration

0x40008000–0x400087FF EEPROM

Address Range

Size

Use

0x00000000–

0x1FFFFFFF

0.5 GB Program code. This includes

the exception vector table at

power up, which starts at

address 0.

0x4000A000–0x4000A400 Reserved

0x40010000–0x4001FFFF Digital Interconnect Configuration

0x48000000–0x48007FFF Flash ECC Bytes

0x20000000–

0x3FFFFFFF

0.5 GB Static RAM. This includes a 1

MByte bit-band region

starting at 0x20000000 and a

32 Mbyte bit-band alias

region starting at

0x60000000–0x60FFFFFF External Memory Interface

(EMIF)

0xE0000000–0xE00FFFFF Cortex-M3 PPB Registers,

including NVIC, debug, and trace

0x22000000.

0x40000000–

0x5FFFFFFF

0.5 GB Peripherals.

0x60000000–

0x9FFFFFFF

1 GB

External RAM.

The bit-band feature allows individual bits in SRAM to be read or

written as atomic operations. This is done by reading or writing

bit 0 of corresponding words in the bit-band alias region. For

example, to set bit 3 in the word at address 0x20000000, write a

1 to address 0x2200000C. To test the value of that bit, read

address 0x2200000C and the result is either 0 or 1 depending

on the value of the bit.

0xA0000000–

0xDFFFFFFF

External peripherals.

0xE0000000–

0xFFFFFFFF

0.5 GB Internalperipherals,including

the NVIC and debug and

trace modules.

Most memory accesses done by the Cortex-M3 are aligned, that

is, done on word (4-byte) boundary addresses. Unaligned

accesses of words and 16-bit half-words on nonword boundary

addresses can also be done, although they are less efficient.

Table 5-4. Peripheral Data Address Map

Address Range

Purpose

5.7.2 Address Map and Cortex-M3 Buses

0x00000000–0x0003FFFF 256K Flash

The ICode and DCode buses are used only for accesses within

the Code address range, 0–0x1FFFFFFF.

0x1FFF8000–0x1FFFFFFF 32K SRAM in Code region

0x20000000–0x20007FFF 32K SRAM in SRAM region

0x40004000–0x400042FF Clocking, PLLs, and oscillators

0x40004300–0x400043FF Power management

0x40004500–0x400045FF Ports interrupt control

0x40004700–0x400047FF Flash programming interface

0x40004800–0x400048FF Cache controller

The system bus is used for data accesses and debug accesses

within the ranges 0x20000000–0xDFFFFFFF and

0xE0100000–0xFFFFFFFF. Instruction fetches can also be

done within the range 0x20000000–0x3FFFFFFF, although

these can be slower than instruction fetches via the ICode bus.

The private peripheral bus (PPB) is used within the Cortex-M3 to

access system control registers and debug and trace module

registers.

2

0x40004900–0x400049FF I C controller

0x40004E00–0x40004EFF Decimator

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PSoC^®5LP: CY8C54LP Family

Datasheet

Key features of the clocking system include:

6. System Integration

■ Seven general purpose clock sources

❐ 3- to 74-MHz IMO, ±2% at 3 MHz

❐ 4- to 25-MHz external crystal oscillator (MHzECO)

❐ Clock doubler provides a doubled clock frequency output for

the USB block, see USB Clock Domain on page 26

❐ DSI signal from an external I/O pin or other logic

❐ 24- to 80-MHz fractional PLL sourced from IMO, MHzECO,

or DSI

6.1 Clocking System

The clocking system generates, divides, and distributes clocks

throughout the PSoC system. For the majority of systems, no

external crystal is required. The IMO and PLL together can

generate up to a 80-MHz clock, accurate to ±2% over voltage

and temperature. Additional internal and external clock sources

allow each design to optimize accuracy, power, and cost. All of

the system clock sources can be used to generate other clock

frequencies in the 16-bit clock dividers and UDBs for anything

the user wants, for example a UART baud rate generator.

❐ 1-kHz, 33-kHz, 100-kHz ILO for watchdog timer (WDT) and

sleep timer

❐ 32.768-kHz external crystal oscillator (kHzECO) for RTC

Clock generation and distribution is automatically configured

through the PSoC Creator IDE graphical interface. This is based

on the complete system’s requirements. It greatly speeds the

design process. PSoC Creator allows designers to build clocking

systems with minimal input. The designer can specify desired

clock frequencies and accuracies, and the software locates or

builds a clock that meets the required specifications. This is

possible because of the programmability inherent in PSoC.

■ IMOhasaUSBmodethatautolockstoUSBbusclockrequiring

no external crystal for USB. (USB equipped parts only)

■ Independently sourced clock in all clock dividers

■ Eight 16-bit clock dividers for the digital system

■ Four 16-bit clock dividers for the analog system

■ Dedicated 16-bit divider for the CPU bus and CPU clock

■ Automatic clock configuration in PSoC Creator

Table 6-1. Oscillator Summary

Source

IMO

Fmin

3 MHz

4 MHz

Tolerance at Fmin

±2% over voltage and temperature

Crystal dependent

Fmax

74 MHz

25 MHz

Tolerance at Fmax

±7%

Startup Time

13 µs max

MHzECO

Crystal dependent

5 ms typ, max is

crystal dependent

DSI

PLL

0 MHz

Input dependent

33 MHz

80 MHz

48 MHz

100 kHz

Input dependent

-55%, +100%

Input dependent

250 µs max

1 µs max

24 MHz Input dependent

48 MHz Input dependent

Doubler

ILO

1 kHz

–50%, +100%

15 ms max in lowest

power mode

kHzECO

32 kHz

Crystal dependent

32 kHz

Crystal dependent

500 ms typ, max is

crystal dependent

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Figure 6-1.Clocking Subsystem

External IO

or DSI

0-33 MHz

3-74 MHz

IMO

4-25 MHz

ECO

1,33,100 kHz

ILO

32 kHz ECO

CPU

Clock

48 MHz

Doubler for

USB

24-80 MHz

PLL

System

Clock Mux

Bus

Clock

Bus Clock Divider

16 bit

s

k

e

w

Digital Clock

Divider 16 bit

Digital Clock

Divider 16 bit

Analog Clock

Divider 16 bit

s

k

e

w

Digital Clock

Divider 16 bit

Digital Clock

Divider 16 bit

Analog Clock

Divider 16 bit

7

s

k

e

w

7

Analog Clock

Divider 16 bit

Digital Clock

Divider 16 bit

Digital Clock

Divider 16 bit

s

k

e

w

Analog Clock

Divider 16 bit

Digital Clock

Divider 16 bit

Digital Clock

Divider 16 bit

6.1.1 Internal Oscillators

higher clock frequency and accuracy and, higher power

consumption and increased startup time.

Figure 6-1. shows that there are two internal oscillators. They

can be routed directly or divided. The direct routes may not have

a 50% duty cycle. Divided clocks have a 50% duty cycle.

The PLL block provides a mechanism for generating clock

frequencies based upon a variety of input sources. The PLL

outputs clock frequencies in the range of 24 to 80 MHz. Its input

and feedback dividers supply 4032 discrete ratios to create

almost any desired system clock frequency. The accuracy of the

PLL output depends on the accuracy of the PLL input source.

The most common PLL use is to multiply the IMO clock at 3 MHz,

where it is most accurate, to generate the CPU and system

clocks up to the device’s maximum frequency.

6.1.1.2 Internal Main Oscillator

In most designs the IMO is the only clock source required, due

to its ±2% accuracy. The IMO operates with no external

components and outputs a stable clock. A factory trim for each

frequency range is stored in the device. With the factory trim,

tolerance varies from ±2% at 3 MHz, up to ±7% at 74 MHz. The

IMO, in conjunction with the PLL, allows generation of CPU and

system clocks up to the device's maximum frequency (see

Phase-Locked Loop)

The PLL achieves phase lock within 250 µs (verified by bit

setting). It can be configured to use a clock from the IMO,

MHzECO, or DSI (external pin). The PLL clock source can be

used until lock is complete and signaled with a lock bit. The lock

signal can be routed through the DSI to generate an interrupt.

Disable the PLL before entering low power modes.

The IMO provides clock outputs at 3-, 6-, 12-, 24-, 48-, and

74-MHz.

6.1.1.3 Clock Doubler

6.1.1.5 Internal Low Speed Oscillator

The clock doubler outputs a clock at twice the frequency of the

input clock. The doubler works at input frequency of 24 MHz,

providing 48 MHz for the USB. It can be configured to use a clock

from the IMO, MHzECO, or the DSI (external pin).

The ILO provides clock frequencies for low power consumption,

including the watchdog timer, and sleep timer. The ILO

generates up to three different clocks: 1 kHz, 33 kHz, and

100 kHz.

6.1.1.4 Phase-Locked Loop

The 1-kHz clock (CLK1K) is typically used for a background

‘heartbeat’ timer. This clock inherently lends itself to low power

supervisory operations such as the watchdog timer and long

sleep intervals using the central timewheel (CTW).

The PLL allows low frequency, high accuracy clocks to be

multiplied to higher frequencies. This is a tradeoff between

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Datasheet

The central timewheel is a 1-kHz, free-running, 13-bit counter

clocked by the ILO. The central timewheel is always enabled

except in hibernate mode and when the CPU is stopped during

debug on chip mode. It can be used to generate periodic

interrupts for timing purposes or to wake the system from a low

power mode. Firmware can reset the central timewheel.

6.1.2.3 32.768 kHz ECO

The 32.768-kHz external crystal oscillator (32kHzECO) provides

precision timing with minimal power consumption using an

external 32.768-kHz watch crystal (see Figure 6-4.). The

32kHzECO also connects directly to the sleep timer and provides

the source for the RTC. The RTC uses a 1-second interrupt to

implement the RTC functionality in firmware.

The central timewheel can be programmed to wake the system

periodically and optionally issue an interrupt. This enables

flexible, periodic wakeups from low power modes or coarse

timing applications. Systems that require accurate timing should

use the RTC capability instead of the central timewheel.

The oscillator works in two distinct power modes. This allows

users to trade off power consumption with noise immunity from

neighboring circuits. The GPIO pins connected to the external

crystal and capacitors are fixed.

The 100-kHz clock (CLK100K) can be used as a low power

system clock to run the CPU. It can also generate time intervals

using the fast timewheel.

Figure 6-4.32kHzECO Block Diagram

The fast timewheel is a 5-bit counter, clocked by the 100-kHz

clock. It features programmable settings and automatically

resets when the terminal count is reached. An optional interrupt

can be generated each time the terminal count is reached. This

enables flexible, periodic interrupts of the CPU at a higher rate

than is allowed using the central timewheel.

XCLK32K

32 kHz

Crystal Osc

The 33-kHz clock (CLK33K) comes from a divide-by-3 operation

on CLK100K. This output can be used as a reduced accuracy

version of the 32.768-kHz ECO clock with no need for a crystal.

Xo

Xi

(Pin P15[2])

(Pin P15[3])

6.1.2 External Oscillators

32 kHz

crystal

Figure 6-1. shows that there are two external oscillators. They

can be routed directly or divided. The direct routes may not have

a 50% duty cycle. Divided clocks have a 50% duty cycle.

External

Components

Capacitors

6.1.2.1 MHz External Crystal Oscillator

The MHzECO provides high frequency, high precision clocking

using an external crystal (see Figure 6-2.). It supports a wide

variety of crystal types, in the range of 4 to 25 MHz. When used

in conjunction with the PLL, it can generate CPU and system

clocks up to the device's maximum frequency (see

Phase-Locked Loop on page 24). The GPIO pins connecting to

the external crystal and capacitors are fixed. MHzECO accuracy

depends on the crystal chosen.

It is recommended that the external 32.768-kHz watch crystal

have a load capacitance (CL) of 6 pF or 12.5 pF. Check the

crystal manufacturer's datasheet. The two external capacitors,

CL1 and CL2, are typically of the same value, and their total

capacitance, CL1CL2 / (CL1 + CL2), including pin and trace

capacitance, should equal the crystal CL value. For more infor-

mation, refer to application note AN54439: PSoC 3 and PSoC 5

External Oscillators. See also pin capacitance specifications in

the “GPIO” section on page 73.

Figure 6-2.MHzECO Block Diagram

6.1.2.5 Digital System Interconnect

XCLK_MHZ

4 - 25 MHz

Crystal Osc

The DSI provides routing for clocks taken from external clock

oscillators connected to I/O. The oscillators can also be

generated within the device in the digital system and Universal

Digital Blocks.

While the primary DSI clock input provides access to all clocking

resources, up to eight other DSI clocks (internally or externally

generated) may be routed directly to the eight digital clock

dividers. This is only possible if there are multiple precision clock

sources.

Xo

Xi

(Pin P15[0])

(Pin P15[1])

4 – 25 MHz

crystal

External

Components

Capacitors

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PSoC^®5LP: CY8C54LP Family

Datasheet

6.1.3 Clock Distribution

Each clock divider consists of an 8-input multiplexer, a 16-bit

clock divider (divide by 2 and higher) that generates ~50% duty

cycle clocks, system clock resynchronization logic, and deglitch

logic. The outputs from each digital clock tree can be routed into

the digital system interconnect and then brought back into the

clock system as an input, allowing clock chaining of up to 32 bits.

All seven clock sources are inputs to the central clock distribution

system. The distribution system is designed to create multiple

high precision clocks. These clocks are customized for the

design’s requirements and eliminate the common problems

found with limited resolution prescalers attached to peripherals.

The clock distribution system generates several types of clock

trees.

6.1.4 USB Clock Domain

The USB clock domain is unique in that it operates largely

asynchronously from the main clock network. The USB logic

contains a synchronous bus interface to the chip, while running

on an asynchronous clock to process USB data. The USB logic

requires a 48 MHz frequency. This frequency can be generated

from different sources, including DSI clock at 48 MHz or doubled

value of 24 MHz from internal oscillator, DSI signal, or crystal

oscillator.

■ The system clock is used to select and supply the fastest clock

in the system for general system clock requirements and clock

synchronization of the PSoC device.

■ Bus clock 16-bit divider uses the system clock to generate the

system’s bus clock used for data transfers and the CPU. The

CPU clock is directly derived from the bus clock.

■ Eight fully programmable 16-bit clock dividers generate digital

system clocks for general use in the digital system, as

configured by the design’s requirements. Digital system clocks

can generate custom clocks derived from any of the seven

clock sources for any purpose. Examples include baud rate

generators, accurate PWM periods, and timer clocks, and

many others. If more than eight digital clock dividers are

required, theUDBsandfixedfunctiontimer/counter/PWMscan

also generate clocks.

■ Four16-bitclockdividersgenerateclocksfortheanalogsystem

components that require clocking, such as the ADC. The

analogclockdividersincludeskewcontroltoensurethatcritical

analog events do not occur simultaneously with digital

switching events. This is done to reduce analog system noise.

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Datasheet

6.2 Power System

The power system consists of separate analog, digital, and I/O supply pins, labeled VDDA, VDDD, and VDDIOX, respectively. It also

includes two internal 1.8 V regulators that provide the digital (V ) and analog (V ) supplies for the internal core logic. The output

CCD

CCA

pins of the regulators (VCCD and VCCA) and the VDDIO pins must have capacitors connected as shown in Figure 6-6.. The two

VCCD pins must be shorted together, with as short a trace as possible, and connected to a 1 µF ±10% X5R capacitor. The power

2

system also contains a sleep regulator, an I C regulator, and a hibernate regulator.

Figure 6-6.PSoC Power System

µF

1

VDDD

VDDIO2

VDDIO0

0.1 µF

I/O Supply

VDDIO0

0.1 µF

I2C

Regulator

Sleep

Regulator

Digital

VDDA

Domain

VDDA

VCCA

Analog

Regulator

0.1 µF

Digital

Regulators

VSSB

.

µF

1

VSSA

Analog

Domain

Hibernate

Regulator

I/O Supply

0.1µF

0.1 µF

VDDD

VDDIO1

VDDIO3

Notes

■ The two V

pins must be connected together with as short a trace as possible. A trace under the device is recommended, as

CCD

shown in Figure 2-6..

■ You can power the device in internally regulated mode, where the voltage applied to the V

pins is as high as 5.5 V, and the

DDx

internal regulators provide the core voltages. In this mode, do not apply power to the V_CCxpins, and do not tie the V_DDxpins

to the V_CCxpins.

■ Youcanalsopowerthedeviceinexternallyregulatedmode, thatis, bydirectlypoweringtheV

andV

pins. Inthisconfiguration,

CCA

CCD

the V

pins should be shorted to the V

pins and the V

pin should be shorted to the V

pin. The allowed supply range

DDD

CCD

DDA

CCA

in this configuration is 1.71 V to 1.89 V. After power up in this configuration, the internal regulators are on by default, and should be

disabled to reduce power consumption.

■ It is good practice to check the datasheets for your bypass capacitors, specifically the working voltage and the DC bias specifications.

With some capacitors, the actual capacitance can decrease considerably when the DC bias (V

or V

in Figure 6-6.) is a

DDX

CCX

significant percentage of the rated working voltage.

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PSoC^®5LP: CY8C54LP Family

Datasheet

6.2.1 Power Modes

Active is the main processing mode. Its functionality is

configurable. Each power controllable subsystem is enabled or

disabled by using separate power configuration template

registers. In alternate active mode, fewer subsystems are

enabled, reducing power. In sleep mode most resources are

disabled regardless of the template settings. Sleep mode is

optimized to provide timed sleep intervals and Real Time Clock

functionality. The lowest power mode is hibernate, which retains

register and SRAM state, but no clocks, and allows wakeup only

from I/O pins. Figure 6-7. illustrates the allowable transitions

between power modes. Sleep and hibernate modes should not

be entered until all VDDIO supplies are at valid voltage levels.

PSoC 5LP devices have four different power modes, as shown

in Table 6-2 and Table 6-3. The power modes allow a design to

easily provide required functionality and processing power while

simultaneously minimizing power consumption and maximizing

battery life in low power and portable devices.

PSoC 5LP power modes, in order of decreasing power

consumption are:

■ Active

■ Alternate Active

■ Sleep

■ Hibernate

Table 6-2. Power Modes

Entry

Condition

Wakeup

Source

Power Modes

Description

Active Clocks

Regulator

Active

Primary mode of operation, all periph- Wakeup,

Any interrupt

Any (program- All regulators available.

erals available (programmable)

reset,

mable)

Digital and analog

manual

register entry

regulators can be disabled if

external regulation used.

Alternate

Active

Similar to Active mode, and is typically Manual

configured to have fewer peripherals register entry

active to reduce power. One possible

Any interrupt

Any (program- All regulators available.

mable)

Digital and analog

regulators can be disabled if

external regulation used.

configuration is to use the UDBs for

processing, with the CPU turned off

Sleep

All subsystems automatically disabled Manual

Comparator,

ILO/kHzECO Both digital and analog

regulators buzzed.

2

register entry PICU, I C, RTC,

CTW, LVD

Digital and analog

regulators can be disabled if

external regulation used.

Hibernate

All subsystems automatically disabled Manual

PICU

Only hibernate regulator

active.

Lowest power consuming mode with all register entry

peripherals and internal regulators

disabled, except hibernate regulator is

enabled

Configuration and memory contents

retained

Table 6-3. Power Modes Wakeup Time and Power Consumption

Sleep

Modes

Wakeup

Time

Current

(Typ)

Code

Digital

Analog

Clock Sources

Available

Wakeup

Sources

Reset

Sources

Execution Resources Resources

[7]

Active

–

3.1 mA

–

Yes

All

–

All

Alternate

Active

User

defined

2

<25 µs

2 µA

No

I C

Comparator

ILO/kHzECO

Comparator,

PICU, I C,

XRES, LVD,

WDR

2

Sleep

RTC, CTW,

LVD

Hibernate <200 µs

300 nA

No

None

PICU

XRES

Note

7. Bus clock off. Execute from CPU instruction buffer at 6 MHz. See Table 11-2 on page 66.

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PSoC^®5LP: CY8C54LP Family

Datasheet

Figure 6-7.Power Mode Transitions

6.2.1.5 Wakeup Events

Wakeup events are configurable and can come from an interrupt

or device reset. A wakeup event restores the system to active

mode. Firmware enabled interrupt sources include internally

generated interrupts, power supervisor, central timewheel, and

I/O interrupts. Internal interrupt sources can come from a variety

of peripherals, such as analog comparators and UDBs. The

central timewheel provides periodic interrupts to allow the

system to wake up, poll peripherals, or perform real-time

functions. Reset event sources include the external reset pin

(XRES), WDT, and Precision Reset (PRES).

Active

Manual

Sleep

Hibernate

6.2.2 Boost Converter

Applications that use a supply voltage of less than 1.71 V, such

as solar panels or single cell battery supplies, may use the

on-chip boost converter to generate a minimum of 1.8 V supply

voltage. The boost converter may also be used in any system

that requires a higher operating voltage than the supply provides

such as driving 5.0 V LCD glass in a 3.3 V system. With the

addition of an inductor, Schottky diode, and capacitors, it

produces a selectable output voltage sourcing enough current to

operate the PSoC and other on-board components.

Alternate

Active

6.2.1.1 Active Mode

Active mode is the primary operating mode of the device. When

in active mode, the active configuration template bits control

which available resources are enabled or disabled. When a

resource is disabled, the digital clocks are gated, analog bias

currents are disabled, and leakage currents are reduced as

appropriate. User firmware can dynamically control subsystem

power by setting and clearing bits in the active configuration

template. The CPU can disable itself, in which case the CPU is

automatically reenabled at the next wakeup event.

The boost converter accepts an input voltage V

from 0.5 V to

BAT

3.6 V, and can start up with V

provides a user configurable output voltage of 1.8 to 5.0 V (V

as low as 0.5 V. The converter

BAT

)

OUT

in 100 mV increments. V

greater than or equal to V

; if V

is

BAT

OUT

BAT

V

due to resistive losses in the boost converter. The block can

BAT

deliver up to 50 mA (I

) depending on configuration to both

BOOST

the PSoC device and external components. The sum of all

current sinks in the design including the PSoC device, PSoC I/O

pin loads, and external component loads must be less than the

When a wakeup event occurs, the global mode is always

returned to active, and the CPU is automatically enabled,

regardless of its template settings. Active mode is the default

global power mode upon boot.

I

specified maximum current.

BOOST

Four pins are associated with the boost converter: V , V

,

BAT SSB

6.2.1.2 Alternate Active Mode

V

, and IND. The boosted output voltage is sensed at the

BOOST

Alternate Active mode is very similar to active mode. In alternate

active mode, fewer subsystems are enabled, to reduce power

consumption. One possible configuration is to turn off the CPU

and flash, and run peripherals at full speed.

pin and must be connected directly to the chip’s supply

, V , and V if used to power the PSoC

BOOST

inputs; V

DDA

DDD

DDIO

device.

The boost converter requires four components in addition to

those required in a non-boost design, as shown in Figure 6-6. on

6.2.1.3 Sleep Mode

page 30. A 22 µF capacitor (C ) is required close to the V

BAT

Sleep mode reduces power consumption when a resume time of

15 µs is acceptable. The wake time is used to ensure that the

regulator outputs are stable enough to directly enter active

mode.

pin to provide local bulk storage of the battery voltage and

provide regulator stability. A diode between the battery and V

BAT

pin should not be used for reverse polarity protection because

the diodes forward voltage drop reduces the V voltage.

BAT

Between the V

and IND pins, an inductor of 4.7 µH, 10 µH, or

BAT

6.2.1.4 Hibernate Mode

22 µH is required. The inductor value can be optimized to

increase the boost converter efficiency based on input voltage,

output voltage, temperature, and current. Inductor size is

determined by following the design guidance in this chapter and

electrical specifications. The Inductor must be placed within

In hibernate mode nearly all of the internal functions are

disabled. Internal voltages are reduced to the minimal level to

keep vital systems alive. Configuration state is preserved in

hibernate mode and SRAM memory is retained. GPIOs

configured as digital outputs maintain their previous values and

external GPIO pin interrupt settings are preserved. The device

can only return from hibernate mode in response to an external

I/O interrupt. The resume time from hibernate mode is less than

100 µs.

1 cm of the V

and IND pins and have a minimum saturation

BAT

current of 750 mA. Between the IND and V

diode must be placed within 1 cm of the pins. The Schottky diode

shall have a forward current rating of at least 1.0 A and a reverse

pins a Schottky

BOOST

voltage of at least 20 V. A 22 µF bulk capacitor (C

) must

BOOST

be connected close to V

to provide regulator output

To achieve an extremely low current, the hibernate regulator has

limited capacity. This limits the frequency of any signal present

on the input pins; no GPIO should toggle at a rate greater than

10 kHz while in hibernate mode. If pins must be toggled at a high

rate while in a low power mode, use sleep mode instead.

BOOST

stability. It is important to sum the total capacitance connected to

the V pin and ensure the maximum C specification

BOOST

is not exceeded. All capacitors must be rated for a minimum of

10 V to minimize capacitive losses due to voltage de-rating.

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PSoC^®5LP: CY8C54LP Family

Datasheet

Figure 6-6.Application of Boost Converter powering PSoC device

PSoC

VDDA

VDDD

1.0 µF

0.1 µF

External

Load

VBOOST

IND

Schottky, 1A

VDDIO0

0.1 µF

4.7 µH

10 µH

22 µH

Boost VDDIO2

Logic

VDDIO1

VBAT

VSSB

22 µF

VDDIO3

0.1 µF

0.5–3.6 V

VSSA

VSSD

22 µF

All components and values are required

The boost converter may also generate a supply that is not used

directly by the PSoC device. An example of this use case is

boosting a 1.8 V supply to 4.0 V to drive a white LED. If the boost

the PSoC device, but with a change to the bulk capacitor

requirements. A parallel arrangement 22 µF, 1.0 µF, and 0.1 µF

capacitors are all required on the Vout supply and must be

placed within 1 cm of the VBOOST pin to ensure regulator

stability.

converter is not supplying the PSoC devices V

, V

, and

DDA

DDD

V

it must comply with the same design rules as supplying

DDIO

Figure 6-7.Application of Boost Converter not powering PSoC device

V_OUT

External

Load

PSoC

VDDA

VDDD

22 µF 1.0 µF 0.1 µF

VDDA, VDDD, and

VDDIO connections

per section 6.2

VBOOST

IND

Schottky, 1A

VDDIO0

Power System.

4.7 µH

10 µH

22 µH

Boost VDDIO2

Logic

VDDIO1

VBAT

VSSB

22 µF

VDDIO3

0.5–3.6 V

VSSA

VSSD

All components and values are required

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PSoC^®5LP: CY8C54LP Family

Datasheet

The switching frequency is set to 400 kHz using an oscillator

integrated into the boost converter. The boost converter can be

operated in two different modes: active and standby. Active

mode is the normal mode of operation where the boost regulator

actively generates a regulated output voltage. In standby mode,

most boost functions are disabled, thus reducing power

consumption of the boost circuit. Only minimal power is provided,

typically < 5 µA to power the PSoC device in Sleep mode. The

boost typically draws 250 µA in active mode and 25 µA in

standby mode. The boost operating modes must be used in

conjunction with chip power modes to minimize total power

consumption. Table 6-4 lists the boost power modes available in

different chip power modes.

1. Choose desired V , V

, T , and I

operating condition

OUT

BAT OUT

A

ranges for the application.

2. Determine if V and V

ranges fit the boost operating

OUT

BAT

range based on the T_Arange over V_BATand V_OUTchart,

Figure 11-7. on page 71. If the operating ranges are not met,

modify the operating conditions or use an external boost

regulator.

3. Determine if the desired ambient temperature (T ) range fits

A

the ambient temperature operating range based on the T_A

range over V_BATand V_OUTchart, Figure 11-7. on page 71. If

the temperature range is not met, modify the operating condi-

tions and return to step 2, or use an external boost regulator.

4. Determine if the desired output current (I

) range fits the

OUT

Table 6-4. Chip and Boost Power Modes Compatibility

output current operating range based on the I_OUTrange over

V_BATand V_OUTchart, Figure 11-8. on page 71. If the output

current range is not met, modify the operating conditions and

return to step 2, or use an external boost regulator.

Chip Power Modes

Boost Power Modes

Chip-activeoralternate Boost must be operated in its active

active mode

mode.

5. Find the allowed inductor values based on the L_BOOSTvalues

over V_BATand V_OUTchart, Figure 11-9. on page 71.

Chip-sleep mode

Boost can be operated in either active

or standby mode. In boost standby

mode, the chip must wake up periodi-

cally for boost active-mode refresh.

6. Based on the allowed inductor values, inductor dimensions,

inductor cost, boost efficiency, and V

choose the

RIPPLE

optimum inductor value for the system. Boost efficiency and

typical values are provided in the Efficiency vs V_BAT

V

Chip-hibernate mode Boost can be operated in its active

mode. However, it is recommended not

to use the boost in chip hibernate mode

due to the higher current consumption

in boost active mode.

RIPPLE

and V_RIPPLEvs V_BATcharts, Figure 11-10. on page 72

through Figure 11-13. on page 72. In general, if high efficiency

and low V

are most important, then the highest allowed

RIPPLE

inductor value should be used. If low inductor cost or small

inductor size are most important, then one of the smaller

allowed inductor values should be used. If the allowed

6.2.2.1 Boost Firmware Requirements

inductor(s) efficiency, V

, cost or dimensions are not

RIPPLE

To ensure boost inrush current is within specification at startup,

the Enable Fast IMO During Startup value must be unchecked

in the PSoC Creator IDE. The Enable Fast IMO During Startup

option is found in PSoC Creator in the design wide resources

(cydwr) file System tab. Un-checking this option configures the

device to run at 12 MHz vs 48 MHz during startup while

configuring the device. The slower clock speed results in

reduced current draw through the boost circuit.

acceptable for the application than an external boost regulator

should be used.

6.3 Reset

CY8C54LP has multiple internal and external reset sources

available. The reset sources are:

■ Power source monitoring - The analog and digital power

voltages, VDDA, VDDD, VCCA, and VCCD are monitored in

several different modes during power up, active mode, and

sleep mode (buzzing). If any of the voltages goes outside

predetermined ranges then a reset is generated. The monitors

are programmable to generate an interrupt to the processor

under certain conditions before reaching the reset thresholds.

6.2.2.2 Boost Design Process

Correct operation of the boost converter requires specific

component values determined for each designs unique

operating conditions. The C

capacitor, Inductor, Schottky

BAT

diode, and C

capacitor components are required with the

BOOST

■ External - The device can be reset from an external source by

pulling the reset pin (XRES) low. The XRES pin includes an

internal pull-up to VDDIO1. VDDD, VDDA, and VDDIO1 must

all have voltage applied before the part comes out of reset.

values specified in the electrical specifications, Table 11-8 on

page 71. The only variable component value is the inductor

L

which is primarily sized for correct operation of the boost

across operating conditions and secondarily for efficiency.

BOOST

Additional operating region constraints exist for V

, V , I

,

■ Watchdog timer - A watchdog timer monitors the execution of

instructions by the processor. If the watchdog timer is not reset

by firmware within a certain period of time, the watchdog timer

generates a reset.

OUT BAT OUT

and T .

A

The following steps must be followed to determine boost

converter operating parameters and L value.

BOOST

■ Software - The device can be reset under program control.

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PSoC^®5LP: CY8C54LP Family

Datasheet

Figure 6-3.Resets

VDDD VDDA

supervisory services and to reduce wakeup time. At these

times the PRES circuit is also buzzed to allow periodic voltage

monitoring.

■ ALVI,DLVI,AHVI-Analog/DigitalLowVoltageInterrupt,Analog

High Voltage Interrupt

Power

Voltage

Level

Processor

Interrupt

Interrupt circuits are available to detect when VDDA and

VDDD go outside a voltage range. For AHVI, VDDA is

compared to a fixed trip level. For ALVI and DLVI, VDDA and

VDDD are compared to trip levels that are programmable, as

listed in Table 6-5. ALVI and DLVI can also be configured to

generate a device reset instead of an interrupt.

Monitors

Reset

External

Reset

Controller

System

Reset

Table 6-5. Analog/Digital Low Voltage Interrupt, Analog High

Voltage Interrupt

Normal Voltage

Watchdog

Timer

Interrupt Supply

Available Trip Settings

Range

DLVI

ALVI

AHVI

VDDD 1.71 V-5.5 V

VDDA 1.71 V-5.5 V

1.70V-5.45 Vin250 mV

increments

1.70V-5.45 Vin250 mV

increments

Software

Reset

Register

5.75 V

The monitors are disabled until after IPOR. During sleep

mode these circuits are periodically activated (buzzed). If an

interrupt occurs during buzzing then the system first enters its

wakeup sequence. The interrupt is then recognized and may

be serviced.

The term system reset indicates that the processor as well as

analog and digital peripherals and registers are reset.

A reset status register shows some of the resets or power voltage

monitoring interrupts. The program may examine this register to

detect and report certain exception conditions. This register is

cleared after a power-on reset. For details see the Technical

Reference Manual.

The buzz frequency is adjustable, and should be set to be less

than the minimum time that any voltage is expected to be out

of range. For details on how to adjust the buzz frequency, see

the TRM.

6.3.1 Reset Sources

6.3.1.2 Other Reset Sources

6.3.1.1 Power Voltage Level Monitors

■ XRES - External Reset

■ IPOR - Initial Power-on-Reset

PSoC 5LP has a dedicated XRES pin, which holds the part in

reset while held active (low). The response to an XRES is the

same as to an IPOR reset.

At initial power on, IPOR monitors the power voltages V

,

DDD

V

, V

and V

. The trip level is not precise. It is set to

DDA CCD

CCA

approximately 1 volt (0.75 V to 1.45 V). This is below the

lowest specified operating voltage but high enough for the

internal circuits to be reset and to hold their reset state. The

monitor generates a reset pulse that is at least 150 ns wide.

It may be much wider if one or more of the voltages ramps up

slowly.

The external reset is active low. It includes an internal pull-up

resistor. XRES is active during sleep and hibernate modes.

After XRES has been deasserted, at least 10 µs must elapse

before it can be reasserted.

■ SRES - Software Reset

After boot, the IPOR circuit is disabled and voltage

supervision is handed off to the precise low-voltage reset

(PRES) circuit.

A reset can be commanded under program control by setting

a bit in the software reset register. This is done either directly

by the program or indirectly by DMA access. The response to

a SRES is the same as after an IPOR reset.

■ PRES - Precise Low-Voltage Reset

Another register bit exists to disable this function.

This circuit monitors the outputs of the analog and digital

internal regulators after power up. The regulator outputs are

compared to a precise reference voltage. The response to a

PRES trip is identical to an IPOR reset.

■ WRES - Watchdog Timer Reset

The watchdog reset detects when the software program is no

longer being executed correctly. To indicate to the watchdog

timer that it is running correctly, the program must periodically

reset the timer. If the timer is not reset before a user-specified

amount of time, then a reset is generated.

In normal operating mode, the program cannot disable the

digital PRES circuit. The analog regulator can be disabled,

which also disables the analog portion of the PRES. The

PRES circuit is disabled automatically during sleep and

hibernate modes, with one exception: During sleep mode the

regulators are periodically activated (buzzed) to provide

Note IPOR disables the watchdog function. The program

must enable the watchdog function at an appropriate point in

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PSoC^®5LP: CY8C54LP Family

Datasheet

the code by setting a register bit. When this bit is set, it cannot

be cleared again except by an IPOR power on reset event.

❐ Slew rate controlled digital output drive mode

❐ Access port control and configuration registers on either port

basis or pin basis

❐ Separateportread(PS)andwrite(DR)dataregisterstoavoid

read modify write errors

❐ Special functionality on a pin by pin basis

6.4 I/O System and Routing

PSoC I/Os are extremely flexible. Every GPIO has analog and

digital I/O capability. All I/Os have a large number of drive modes,

which are set at POR. PSoC also provides up to four individual

I/O voltage domains through the VDDIO pins.

■ Additional features only provided on the GPIO pins:

❐ LCD segment drive on LCD equipped devices

[8]

There are two types of I/O pins on every device; those with USB

provide a third type. Both General Purpose I/O (GPIO) and

Special I/O (SIO) provide similar digital functionality. The primary

differences are their analog capability and drive strength.

Devices that include USB also provide two USBIO pins that

support specific USB functionality as well as limited GPIO

capability.

❐ CapSense

❐ Analog input and output capability

❐ Continuous 100 µA clamp current capability

❐ Standard drive strength down to 1.71 V

■ Additional features only provided on SIO pins:

❐ Higher drive strength than GPIO

❐ Hot swap capability (5 V tolerance at any operating VDD)

❐ Programmable and regulated high input and output drive

levels down to 1.2 V

❐ No analog input, CapSense, or LCD capability

❐ Over voltage tolerance up to 5.5 V

❐ SIO can act as a general purpose analog comparator

All I/O pins are available for use as digital inputs and outputs for

both the CPU and digital peripherals. In addition, all I/O pins can

generate an interrupt. The flexible and advanced capabilities of

the PSoC I/O, combined with any signal to any pin routability,

greatly simplify circuit design and board layout. All GPIO pins can

be used for analog input, CapSense , and LCD segment drive,

while SIO pins are used for voltages in excess of VDDA and for

programmable output voltages.

[8]

■ USBIO features:

❐ Full speed USB 2.0 compliant I/O

❐ Highest drive strength for general purpose use

❐ Input, output, or both for CPU and DMA

❐ Input, output, or both for digital peripherals

❐ Digital output (CMOS) drive mode

■ Features supported by both GPIO and SIO:

❐ User programmable port reset state

❐ SeparateI/OsuppliesandvoltagesforuptofourgroupsofI/O

❐ Digital peripherals use DSI to connect the pins

❐ Input or output or both for CPU and DMA

❐ Eight drive modes

❐ Each pin can be an interrupt source configured as rising

edge, falling edge, or both edges

❐ Every pin can be an interrupt source configured as rising

edge, falling edge or both edges. If required, level sensitive

interrupts are supported through the DSI

❐ Dedicated port interrupt vector for each port

Note

8. GPIOs with opamp outputs are not recommended for use with CapSense

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Figure 6-3.GPIO Block Diagram

Digital Input Path

Naming Convention

‘x’ = Port Number

‘y’ = Pin Number

PRT[x]CTL

PRT[x]DBL_SYNC_IN

PRT[x]PS

Digital System Input

PICU[x]INTTYPE[y]

PICU[x]INTSTAT

Pin Interrupt Signal

PICU[x]INTSTAT

Input Buffer Disable

Interrupt

Logic

Digital Output Path

PRT[x]SLW

PRT[x]SYNC_OUT

Vddio Vddio

PRT[x]DR

0

1

In

Digital System Output

PRT[x]BYP

Vddio

Drive

Logic

PRT[x]DM2

PRT[x]DM1

PRT[x]DM0

Slew

Cntl

Bidirectional Control

PRT[x]BIE

OE

Analog

1

0

1

0

1

Capsense Global Control

CAPS[x]CFG1

Switches

PRT[x]AG

Analog Global

PRT[x]AMUX

Analog Mux

LCD

Display

Data

Logic & MUX

PRT[x]LCD_COM_SEG

PRT[x]LCD_EN

LCD Bias Bus

5

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Figure 6-4.SIO Input/Output Block Diagram

Digital Input Path

Naming Convention

‘x’ = Port Number

‘y’ = Pin Number

PRT[x]SIO_HYST_EN

PRT[x]SIO_DIFF

Buffer

Thresholds

Reference Level

PRT[x]DBL_SYNC_IN

PRT[x]PS

Digital System Input

PICU[x]INTTYPE[y]

PICU[x]INTSTAT

Pin Interrupt Signal

PICU[x]INTSTAT

Input Buffer Disable

Interrupt

Logic

Digital Output Path

Reference Level

PRT[x]SIO_CFG

PRT[x]SLW

Driver

Vhigh

PRT[x]SYNC_OUT

PRT[x]DR

0

1

In

Digital System Output

PRT[x]BYP

Drive

Logic

PRT[x]DM2

PRT[x]DM1

PRT[x]DM0

Slew

Cntl

Bidirectional Control

PRT[x]BIE

OE

Figure 6-5.USBIO Block Diagram

Digital Input Path

Naming Convention

‘y’ = Pin Number

USB Receiver Circuitry

PRT[15]DBL_SYNC_IN

PRT[15]PS[6,7]

USBIO_CR1[0,1]

Digital System Input

PICU[15]INTTYPE[y]

PICU[15]INTSTAT

Pin Interrupt Signal

PICU[15]INTSTAT

Interrupt

Logic

Digital Output Path

PRT[15]SYNC_OUT

USBIO_CR1[5]

USB or I/O

D+ 1.5 k

D+ pin only

Vddd Vddd Vddd

USBIO_CR1[2]

Vddd

USB SIE Control for USB Mode

PRT[15]DR1[7,6]

0

1

In

Digital System Output

PRT[15]BYP

5 k

1.5 k

Drive

Logic

PRT[15]DM0[6]

PRT[15]DM0[7]

D+ Open

Drain

D- Open

Drain

PRT[15]DM1[6]

PRT[15]DM1[7]

D+ 5 k

D- 5 k

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6.4.1 Drive Modes

bypass mode is selected. Note that the actual I/O pin voltage is

determined by a combination of the selected drive mode and the

load at the pin. For example, if a GPIO pin is configured for

resistive pull-up mode and driven high while the pin is floating,

the voltage measured at the pin is a high logic state. If the same

GPIO pin is externally tied to ground then the voltage

unmeasured at the pin is a low logic state.

Each GPIO and SIO pin is individually configurable into one of

the eight drive modes listed in Table 6-6. Three configuration bits

are used for each pin (DM[2:0]) and set in the PRTxDM[2:0]

registers. Figure 6-6. depicts a simplified pin view based on each

of the eight drive modes. Table 6-6 shows the I/O pin’s drive state

based on the port data register value or digital array signal if

Figure 6-6.Drive Mode

VDD

Out

In

Out

In

Out

In

Out

In

An

0. High Impedance

Analog

1. High Impedance

Digital

2. Resistive Pull-Up

VDD

3. Resistive Pull-Down

VDD

Out

In

Out

In

Out

In

Out

In

An

4. Open Drain,

Drives Low

5. Open Drain,

Drives High

7. Resistive Pull-Up

and Pull-Down

6. Strong Drive

The ‘Out’ connection is driven from either the Digital System (when the Digital Output terminal is connected) or the Data Register

(when HW connection is disabled).

The ‘In’ connection drives the Pin State register, and the Digital System if the Digital Input terminal is enabled and connected.

The ‘An’ connection connects to the Analog System.

Table 6-6. Drive Modes

Diagram

Drive Mode

PRTxDM2

PRTxDM1

PRTxDM0

PRTxDR = 1

High-Z

PRTxDR = 0

High-Z

0

1

2

3

4

5

6

7

High impedance analog

High Impedance digital

0

1

0

1

0

1

0

1

0

1

0

1

0

1

High-Z

[9]

Resistive pull-up

Res High (5K)

Strong High

High-Z

Strong Low

Res Low (5K)

Strong Low

High-Z

[9]

Resistive pull-down

Open drain, drives low

Open drain, drive high

Strong drive

Strong High

Res High (5K)

Strong Low

Res Low (5K)

[9]

Resistive pull-up and pull-down

Note

9. Resistive pull-up and pull-down are not available with SIO in regulated output mode.

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The USBIO pins (P15[7] and P15[6]), when enabled for I/O mode, have limited drive mode control. The drive mode is set using the

PRT15.DM0[7, 6] register. A resistive pull option is also available at the USBIO pins, which can be enabled using the PRT15.DM1[7,

6] register. When enabled for USB mode, the drive mode control has no impact on the configuration of the USB pins. Unlike the GPIO

and SIO configurations, the port wide configuration registers do not configure the USB drive mode bits. Table 6-7 shows the drive

mode configuration for the USBIO pins.

Table 6-7. USBIO Drive Modes (P15[7] and P15[6])

PRT15.DM1[7,6]

Pull up enable

PRT15.DM0[7,6]

Drive Mode enable

PRT15.DR[7,6] = 1

PRT15.DR[7,6] = 0

Description

0

1

0

1

0

1

High Z

Strong Low

Open Drain, Strong Low

Strong Outputs

Strong High

Res High (5k)

Strong High

Resistive Pull Up, Strong Low

Strong Outputs

■ High impedance analog

6.4.2 Pin Registers

The default reset state with both the output driver and digital

input buffer turned off. This prevents any current from flowing

in the I/O’s digital input buffer due to a floating voltage. This

state is recommended for pins that are floating or that support

an analog voltage. High impedance analog pins do not

provide digital input functionality.

Registers to configure and interact with pins come in two forms

that may be used interchangeably.

All I/O registers are available in the standard port form, where

each bit of the register corresponds to one of the port pins. This

register form is efficient for quickly reconfiguring multiple port

pins at the same time.

To achieve the lowest chip current in sleep modes, all I/Os

must either be configured to the high impedance analog

mode, or have their pins driven to a power supply rail by the

PSoC device or by external circuitry.

I/O registers are also available in pin form, which combines the

eight most commonly used port register bits into a single register

for each pin. This enables very fast configuration changes to

individual pins with a single register write.

■ High impedance digital

6.4.3 Bidirectional Mode

The input buffer is enabled for digital signal input. This is the

standard high impedance (HiZ) state recommended for digital

inputs.

High speed bidirectional capability allows pins to provide both

the high impedance digital drive mode for input signals and a

second user selected drive mode such as strong drive (set using

PRTxDM[2:0] registers) for output signals on the same pin,

based on the state of an auxiliary control bus signal. The

bidirectional capability is useful for processor busses and

communications interfaces such as the SPI Slave MISO pin that

requires dynamic hardware control of the output buffer.

■ Resistive pull-up or resistive pull-down

Resistive pull-up or pull-down, respectively, provides a series

resistance in one of the data states and strong drive in the

other. Pins can be used for digital input and output in these

modes. Interfacing to mechanical switches is a common

application for these modes. Resistive pull-up and pull-down

are not available with SIO in regulated output mode.

The auxiliary control bus routes up to 16 UDB or digital peripheral

generated output enable signals to one or more pins.

6.4.4 Slew Rate Limited Mode

■ Open drain, drives high and open drain, drives low

GPIO and SIO pins have fast and slow output slew rate options

for strong and open drain drive modes, not resistive drive modes.

Because it results in reduced EMI, the slow edge rate option is

recommended for signals that are not speed critical, generally

less than 1 MHz. The fast slew rate is for signals between 1 MHz

and 33 MHz. The slew rate is individually configurable for each

pin, and is set by the PRTxSLW registers.

Open drain modes provide high impedance in one of the data

states and strong drive in the other. Pins can be used for

digital input and output in these modes. A common

2

application for these modes is driving the I C bus signal lines.

■ Strong drive

Provides a strong CMOS output drive in either high or low

state. This is the standard output mode for pins. Strong Drive

mode pins must not be used as inputs under normal

circumstances. This mode is often used to drive digital output

signals or external FETs.

6.4.5 Pin Interrupts

All GPIO and SIO pins are able to generate interrupts to the

system. All eight pins in each port interface to their own Port

Interrupt Control Unit (PICU) and associated interrupt vector.

Each pin of the port is independently configurable to detect rising

edge, falling edge, both edge interrupts, or to not generate an

interrupt.

■ Resistive pull-up and pull-down

Similar to the resistive pull-up and resistive pull-down modes

except the pin is always in series with a resistor. The high data

state is pull-up while the low data state is pull-down. This

mode is most often used when other signals that may cause

shorts can drive the bus. Resistive pull-up and pull-down are

not available with SIO in regulated output mode.

Depending on the configured mode for each pin, each time an

interrupt event occurs on a pin, its corresponding status bit of the

interrupt status register is set to “1” and an interrupt request is

sent to the interrupt controller. Each PICU has its own interrupt

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vector in the interrupt controller and the pin status register

providing easy determination of the interrupt source down to the

pin level.

which is based on an internally generated reference. Typically a

voltage DAC (VDAC) is used to generate the reference (see

Figure 6-7.). The “DAC” section on page 58 has more details on

VDAC use and reference routing to the SIO pins. Resistive

pull-up and pull-down drive modes are not available with SIO in

regulated output mode.

Port pin interrupts remain active in all sleep modes allowing the

PSoC device to wake from an externally generated interrupt.

While level sensitive interrupts are not directly supported;

Universal Digital Blocks (UDB) provide this functionality to the

system when needed.

6.4.12 Adjustable Input Level

This section applies only to SIO pins. SIO pins by default support

the standard CMOS and LVTTL input levels but also support a

differential mode with programmable levels. SIO pins are

grouped into pairs. Each pair shares a reference generator block

which, is used to set the digital input buffer reference level for

interface to external signals that differ in voltage from VDDIO.

The reference sets the pins voltage threshold for a high logic

level (see Figure 6-7.). Available input thresholds are:

6.4.6 Input Buffer Mode

GPIO and SIO input buffers can be configured at the port level

for the default CMOS input thresholds or the optional LVTTL

input thresholds. All input buffers incorporate Schmitt triggers for

input hysteresis. Additionally, individual pin input buffers can be

disabled in any drive mode.

6.4.7 I/O Power Supplies

■ 0.5 ×VDDIO

■ 0.4 ×VDDIO

■ 0.5 ×VREF

■ VREF

Up to four I/O pin power supplies are provided depending on the

device and package. Each I/O supply must be less than or equal

to the voltage on the chip’s analog (VDDA) pin. This feature

allows users to provide different I/O voltage levels for different

pins on the device. Refer to the specific device package pinout

to determine VDDIO capability for a given port and pin.

Typically a voltage DAC (VDAC) generates the V

“DAC” section on page 58 has more details on VDAC use and

reference routing to the SIO pins.

reference.

REF

The SIO port pins support an additional regulated high output

capability, as described in Adjustable Output Level.

Figure 6-7.SIO Reference for Input and Output

6.4.8 Analog Connections

Input Path

These connections apply only to GPIO pins. All GPIO pins may

be used as analog inputs or outputs. The analog voltage present

on the pin must not exceed the VDDIO supply voltage to which

the GPIO belongs. Each GPIO may connect to one of the analog

global busses or to one of the analog mux buses to connect any

pin to any internal analog resource such as ADC or comparators.

In addition, select pins provide direct connections to specific

analog features such as the high current DACs or uncommitted

opamps.

Digital

Input

Vinref

Reference

Generator

SIO_Ref

6.4.9 CapSense

This section applies only to GPIO pins. All GPIO pins may be

used to create CapSense buttons and sliders . See the

“CapSense” section on page 58 for more information.

[6]

Voutref

Output Path

Driver

6.4.10 LCD Segment Drive

Vhigh

This section applies only to GPIO pins. All GPIO pins may be

used to generate Segment and Common drive signals for direct

glass drive of LCD glass. See the “LCD Direct Drive” section on

page 57 for details.

Digital

Output

Drive

Logic

6.4.11 Adjustable Output Level

This section applies only to SIO pins. SIO port pins support the

ability to provide a regulated high output level for interface to

external signals that are lower in voltage than the SIO’s

respective VDDIO. SIO pins are individually configurable to

output either the standard VDDIO level or the regulated output,

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PSoC^®5LP: CY8C54LP Family

Datasheet

6.4.13 SIO as Comparator

The SIO pin must be in one of the following modes: 0 (high

impedance analog), 1 (high impedance digital), or 4 (open drain

drives low). See Figure 6-6. for details. Absolute maximum

ratings for the device must be observed for all I/O pins.

This section applies only to SIO pins. The adjustable input level

feature of the SIOs as explained in the Adjustable Input Level

section can be used to construct a comparator. The threshold for

the comparator is provided by the SIO's reference generator. The

reference generator has the option to set the analog signal

routed through the analog global line as threshold for the

comparator. Note that a pair of SIO pins share the same

threshold.

6.4.16 Reset Configuration

While reset is active all I/Os are reset to and held in the High

Impedance Analog state. After reset is released, the state can be

reprogrammed on a port-by-port basis to pull-down or pull-up. To

ensure correct reset operation, the port reset configuration data

is stored in special nonvolatile registers. The stored reset data is

automatically transferred to the port reset configuration registers

at reset release.

The digital input path in Figure 6-4. on page 35 illustrates this

functionality. In the figure, ‘Reference level’ is the analog signal

routed through the analog global. The hysteresis feature can

also be enabled for the input buffer of the SIO, which increases

noise immunity for the comparator.

6.4.17 Low Power Functionality

In all low power modes the I/O pins retain their state until the part

is awakened and changed or reset. To awaken the part, use a

pin interrupt, because the port interrupt logic continues to

function in all low power modes.

6.4.14 Hot Swap

This section applies only to SIO pins. SIO pins support ‘hot swap’

capability to plug into an application without loading the signals

that are connected to the SIO pins even when no power is

applied to the PSoC device. This allows the unpowered PSoC to

maintain a high impedance load to the external device while also

preventing the PSoC from being powered through a SIO pin’s

protection diode.

6.4.18 Special Pin Functionality

Some pins on the device include additional special functionality

in addition to their GPIO or SIO functionality. The specific special

function pins are listed in “Pinouts” on page 6. The special

features are:

Powering the device up or down while connected to an

operational I2C bus may cause transient states on the SIO pins.

The overall I2C bus design should take this into account.

■ Digital

❐ 4- to 25-MHz crystal oscillator

❐ 32.768-kHz crystal oscillator

6.4.15 Over Voltage Tolerance

2

All I/O pins provide an over voltage tolerance feature at any

operating VDD.

❐ Wake from sleep on I C address match. Any pin can be used

2

for I C if wake from sleep is not required.

❐ JTAG interface pins

❐ SWD interface pins

❐ SWV interface pins

❐ TRACEPORT interface pins

❐ External reset

■ There are no current limitations for the SIO pins as they present

a high impedance load to the external circuit.

■ TheGPIOpinsmustbelimitedto100µAusingacurrentlimiting

resistor. GPIO pins clamp the pin voltage to approximately one

diode above the VDDIO supply.

■ Analog

■ In case of a GPIO pin configured for analog input/output, the

analog voltage on the pin must not exceed the VDDIO supply

voltage to which the GPIO belongs.

❐ Opamp inputs and outputs

❐ High current IDAC outputs

❐ External reference inputs

A common application for this feature is connection to a bus such

2

6.4.19 JTAG Boundary Scan

as I C where different devices are running from different supply

2

voltages. In the I C case, the PSoC chip is configured into the

The device supports standard JTAG boundary scan chains on all

pins for board level test.

Open Drain, Drives Low mode for the SIO pin. This allows an

2

external pull-up to pull the I C bus voltage above the PSoC pin

supply. For example, the PSoC chip could operate at 1.8 V, and

an external device could run from 5 V. Note that the SIO pin’s V

IH

and V levels are determined by the associated VDDIO supply

IL

pin.

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PSoC^®5LP: CY8C54LP Family

Datasheet

7.1 Example Peripherals

7. Digital Subsystem

The flexibility of the CY8C54LP family’s UDBs and analog blocks

allow the user to create a wide range of components

(peripherals). The most common peripherals were built and

characterized by Cypress and are shown in the PSoC Creator

component catalog, however, users may also create their own

custom components using PSoC Creator. Using PSoC Creator,

users may also create their own components for reuse within

their organization, for example sensor interfaces, proprietary

algorithms, and display interfaces.

The digital programmable system creates application specific

combinations of both standard and advanced digital peripherals

and custom logic functions. These peripherals and logic are then

interconnected to each other and to any pin on the device,

providing a high level of design flexibility and IP security.

The features of the digital programmable system are outlined

here to provide an overview of capabilities and architecture. You

do not need to interact directly with the programmable digital

system at the hardware and register level. PSoC Creator

provides a high level schematic capture graphical interface to

automatically place and route resources similar to PLDs.

The number of components available through PSoC Creator is

too numerous to list in the datasheet, and the list is always

growing. An example of a component available for use in

CY8C54LP family, but, not explicitly called out in this datasheet

is the UART component.

The main components of the digital programmable system are:

■ Universal digital blocks (UDB) - These form the core

functionality of the digital programmable system. UDBs are a

collection of uncommitted logic (PLD) and structural logic

(Datapath) optimized to create all common embedded

peripherals and customized functionality that are application or

design specific.

7.1.1 Example Digital Components

The following is a sample of the digital components available in

PSoC Creator for the CY8C54LP family. The exact amount of

hardware resources (UDBs, routing, RAM, flash) used by a

component varies with the features selected in PSoC Creator for

the component.

■ Universal digital block array - UDB blocks are arrayed within a

matrix of programmable interconnect. The UDB array structure

is homogeneous and allows for flexible mapping of digital

functions onto the array. The array supports extensive and

flexible routing interconnects between UDBs and the Digital

System Interconnect.

■ Communications

2

❐ I C

❐ UART

❐ SPI

■ Functions

❐ EMIF

❐ PWMs

❐ Timers

❐ Counters

■ Digital system interconnect (DSI) - Digital signals from UDBs,

fixed function peripherals, I/O pins, interrupts, DMA, and other

system core signals are attached to the Digital System

Interconnecttoimplementfullfeatureddeviceconnectivity. The

DSI allows any digital function to any pin or other feature

routability when used with the Universal Digital Block array.

■ Logic

❐ NOT

❐ OR

Figure 7-1.CY8C54LP Digital Programmable Architecture

❐ XOR

❐ AND

Digital Core System

and Fixed Function Peripherals

7.1.2 Example Analog Components

The following is a sample of the analog components available in

PSoC Creator for the CY8C54LP family. The exact amount of

hardware resources (SC/CT blocks, routing, RAM, flash) used

by a component varies with the features selected in PSoC

Creator for the component.

DSI Routing Interface

UDB

■ Amplifiers

❐ TIA

❐ PGA

❐ opamp

■ ADC

❐ Delta-Sigma

DSI Routing Interface

❐ Successive Approximation (SAR)

■ DACs

❐ Current

❐ Voltage

❐ PWM

Digital Core System

and Fixed Function Peripherals

■ Comparators

■ Mixers

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PSoC^®5LP: CY8C54LP Family

Datasheet

7.1.3 Example System Function Components

7.1.4.3 Component Catalog

The following is a sample of the system function components

available in PSoC Creator for the CY8C54LP family. The exact

amount of hardware resources (UDBs, SC/CT blocks, routing,

RAM, flash) used by a component varies with the features

selected in PSoC Creator for the component.

The component catalog is a repository of reusable design

elements that select device functionality and customize your

PSoC device. It is populated with an impressive selection of

content; from simple primitives such as logic gates and device

registers, through the digital timers, counters and PWMs, plus

analog components such as ADC, DACs, and filters, and

■ CapSense

■ LCD Drive

■ LCD Control

■ Filters

2

communication protocols, such as I C, and USB. See “Example

Peripherals” section on page 40 for more details about available

peripherals. All content is fully characterized and carefully

documented in datasheets with code examples, AC/DC

specifications, and user code ready APIs.

7.1.4 Designing with PSoC Creator

7.1.4.2 More Than a Typical IDE

7.1.4.4 Design Reuse

The symbol editor gives you the ability to develop reusable

components that can significantly reduce future design time. Just

draw a symbol and associate that symbol with your proven

design. PSoC Creator allows for the placement of the new

symbol anywhere in the component catalog along with the

content provided by Cypress. You can then reuse your content

as many times as you want, and in any number of projects,

without ever having to revisit the details of the implementation.

A successful design tool allows for the rapid development and

deployment of both simple and complex designs. It reduces or

eliminates any learning curve. It makes the integration of a new

design into the production stream straightforward.

PSoC Creator is that design tool.

PSoC Creator is a full featured Integrated Development

Environment (IDE) for hardware and software design. It is

optimized specifically for PSoC devices and combines a modern,

powerful software development platform with a sophisticated

graphical design tool. This unique combination of tools makes

PSoC Creator the most flexible embedded design platform

available.

7.1.4.5 Software Development

Anchoring the tool is a modern, highly customizable user

interface. It includes project management and integrated editors

for C and assembler source code, as well the design entry tools.

Project build control leverages compiler technology from top

commercial vendors such as ARM® Limited, Keil™, and

CodeSourcery (GNU). Free versions of Keil C51 and GNU C

Compiler (GCC) for ARM, with no restrictions on code size or end

product distribution, are included with the tool distribution.

Upgrading to more optimizing compilers is a snap with support

for the professional Keil C51 product and ARM RealView™

compiler.

Graphical design entry simplifies the task of configuring a

particular part. You can select the required functionality from an

extensive catalog of components and place it in your design. All

components are parameterized and have an editor dialog that

allows you to tailor functionality to your needs.

PSoC Creator automatically configures clocks and routes the I/O

to the selected pins and then generates APIs to give the

application complete control over the hardware. Changing the

PSoC device configuration is as simple as adding a new

component, setting its parameters, and rebuilding the project.

7.1.4.6 Nonintrusive Debugging

With JTAG (4-wire) and SWD (2-wire) debug connectivity

available on all devices, the PSoC Creator debugger offers full

control over the target device with minimum intrusion.

Breakpoints and code execution commands are all readily

available from toolbar buttons and an impressive lineup of

windows—register, locals, watch, call stack, memory and

peripherals—make for an unparalleled level of visibility into the

system.

At any stage of development you are free to change the

hardware configuration and even the target processor. To

retarget your application (hardware and software) to new

devices, even from 8- to 32-bit families, just select the new

device and rebuild.

You also have the ability to change the C compiler and evaluate

an alternative. Components are designed for portability and are

validated against all devices, from all families, and against all

supported tool chains. Switching compilers is as easy as editing

the from the project options and rebuilding the application with

no errors from the generated APIs or boot code.

PSoC Creator contains all the tools necessary to complete a

design, and then to maintain and extend that design for years to

come. All steps of the design flow are carefully integrated and

optimized for ease-of-use and to maximize productivity.

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PSoC^®5LP: CY8C54LP Family

Datasheet

■ Status and Control Module - The primary role of this block is to

provide a way for CPU firmware to interact and synchronize

with UDB operation.

7.2 Universal Digital Block

The Universal Digital Block (UDB) represents an evolutionary

step to the next generation of PSoC embedded digital peripheral

functionality. The architecture in first generation PSoC digital

blocks provides coarse programmability in which a few fixed

functions with a small number of options are available. The new

UDB architecture is the optimal balance between configuration

granularity and efficient implementation. A cornerstone of this

approach is to provide the ability to customize the devices digital

operation to match application requirements.

■ Clock and Reset Module - This block provides the UDB clocks

and reset selection and control.

7.2.1 PLD Module

The primary purpose of the PLD blocks is to implement logic

expressions, state machines, sequencers, look up tables, and

decoders. In the simplest use model, consider the PLD blocks as

a standalone resource onto which general purpose RTL is

synthesized and mapped. The more common and efficient use

model is to create digital functions from a combination of PLD

and datapath blocks, where the PLD implements only the

random logic and state portion of the function while the datapath

(ALU) implements the more structured elements.

To achieve this, UDBs consist of a combination of uncommitted

logic (PLD), structured logic (Datapath), and a flexible routing

scheme to provide interconnect between these elements, I/O

connections, and other peripherals. UDB functionality ranges

from simple self contained functions that are implemented in one

UDB, or even a portion of a UDB (unused resources are

available for other functions), to more complex functions that

require multiple UDBs. Examples of basic functions are timers,

counters, CRC generators, PWMs, dead band generators, and

Figure 7-8.PLD 12C4 Structure

2

communications functions, such as UARTs, SPI, and I C. Also,

IN0

IN1

IN2

IN3

IN4

IN5

IN6

IN7

IN8

IN9

IN10

IN11

T C T C T C T C T C T C T C T C

the PLD blocks and connectivity provide full featured general

purpose programmable logic within the limits of the available

resources.

Figure 7-7.UDB Block Diagram

AND

Array

PLD

Chaining

PLD

12C4

(8 PTs)

PLD

12C4

(8 PTs)

Clock

and Reset

Control

Carry In

T

MC0

MC1

MC2

MC3

OUT0

OUT1

OUT2

OUT3

Status and

Control

Datapath

Chaining

Carry Out

OR

Array

Routing Channel

One 12C4 PLD block is shown in Figure 7-8.. This PLD has 12

inputs, which feed across eight product terms. Each product term

(AND function) can be from 1 to 12 inputs wide, and in a given

product term, the true (T) or complement (C) of each input can

be selected. The product terms are summed (OR function) to

create the PLD outputs. A sum can be from 1 to 8 product terms

wide. The 'C' in 12C4 indicates that the width of the OR gate (in

this case 8) is constant across all outputs (rather than variable

as in a 22V 10 device). This PLA like structure gives maximum

flexibility and insures that all inputs and outputs are permutable

for ease of allocation by the software tools. There are two 12C4

PLDs in each UDB.

The main component blocks of the UDB are:

■ PLD blocks - There are two small PLDs per UDB. These blocks

take inputs from the routing array and form registered or

combinational sum-of-products logic. PLDs are used to

implement state machines, state bits, and combinational logic

equations. PLD configuration is automatically generated from

graphical primitives.

■ Datapath Module - This 8-bit wide datapath contains structured

logic to implement a dynamically configurable ALU, a variety

ofcompare configurations andconditiongeneration. Thisblock

alsocontainsinput/outputFIFOs, whicharetheprimaryparallel

data interface between the CPU/DMA system and the UDB.

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PSoC^®5LP: CY8C54LP Family

Datasheet

7.2.2 Datapath Module

The datapath contains an 8-bit single cycle ALU, with associated compare and condition generation logic. This datapath block is

optimized to implement embedded functions, such as timers, counters, integrators, PWMs, PRS, CRC, shifters and dead band

generators and many others.

Figure 7-9.Datapath Top Level

PHUB System Bus

R/W Access to All

Registers

F1

FIFOs

Output

Muxes

Input

Muxes

F0

A0

A1

D0

D1

Input from

Programmable

Routing

Output to

Programmable

Routing

6

D1

Data Registers

D0

To/From

Chaining

A1

Accumulators

A0

PI

Parallel Input/Output

(To/From Programmable Routing)

PO

ALU

Shift

Mask

7.2.2.1 Working Registers

7.2.2.2 Dynamic Configuration RAM

Dynamic configuration is the ability to change the datapath

function and internal configuration on a cycle-by-cycle basis,

under sequencer control. This is implemented using the 8-word

x 16-bit configuration RAM, which stores eight unique 16-bit wide

configurations. The address input to this RAM controls the

sequence, and can be routed from any block connected to the

UDB routing matrix, most typically PLD logic, I/O pins, or from

the outputs of this or other datapath blocks.

The datapath contains six primary working registers, which are

accessed by CPU firmware or DMA during normal operation.

Table 7-1. Working Datapath Registers

Name

Function

Description

A0 and A1 Accumulators

These are sources and sinks for

the ALU and also sources for the

compares.

ALU

D0 and D1 Data Registers These are sources for the ALU

and sources for the compares.

The ALU performs eight general purpose functions. They are:

■ Increment

■ Decrement

■ Add

F0 and F1 FIFOs

These are the primary interface

to the system bus. They can be a

data source for the data registers

and accumulators or they can

capture data from the accumu-

lators or ALU. Each FIFO is four

bytes deep.

■ Subtract

■ Logical AND

■ Logical OR

■ Logical XOR

■ Pass, used to pass a value through the ALU to the shift register,

mask, or another UDB register

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Datasheet

Independent of the ALU operation, these functions are available:

7.2.2.8 Chaining

The datapath can be configured to chain conditions and signals

such as carries and shift data with neighboring datapaths to

create higher precision arithmetic, shift, CRC/PRS functions.

■ Shift left

■ Shift right

■ Nibble swap

■ Bitwise OR mask

7.2.2.9 Time Multiplexing

In applications that are over sampled, or do not need high clock

rates, the single ALU block in the datapath can be efficiently

shared with two sets of registers and condition generators. Carry

and shift out data from the ALU are registered and can be

selected as inputs in subsequent cycles. This provides support

for 16-bit functions in one (8-bit) datapath.

7.2.2.3 Conditionals

Each datapath has two compares, with bit masking options.

Compare operands include the two accumulators and the two

data registers in a variety of configurations. Other conditions

include zero detect, all ones detect, and overflow. These

conditions are the primary datapath outputs, a selection of which

can be driven out to the UDB routing matrix. Conditional

computation can use the built in chaining to neighboring UDBs

to operate on wider data widths without the need to use routing

resources.

7.2.2.10 Datapath I/O

There are six inputs and six outputs that connect the datapath to

the routing matrix. Inputs from the routing provide the

configuration for the datapath operation to perform in each cycle,

and the serial data inputs. Inputs can be routed from other UDB

blocks, other device peripherals, device I/O pins, and so on. The

outputs to the routing can be selected from the generated

conditions, and the serial data outputs. Outputs can be routed to

other UDB blocks, device peripherals, interrupt and DMA

controller, I/O pins, and so on.

7.2.2.4 Variable MSB

The most significant bit of an arithmetic and shift function can be

programmatically specified. This supports variable width CRC

and PRS functions, and in conjunction with ALU output masking,

can implement arbitrary width timers, counters and shift blocks.

7.2.3 Status and Control Module

7.2.2.5 Built in CRC/PRS

The primary purpose of this circuitry is to coordinate CPU

firmware interaction with internal UDB operation.

The datapath has built in support for single cycle Cyclic

Redundancy Check (CRC) computation and Pseudo Random

Sequence (PRS) generation of arbitrary width and arbitrary

polynomial. CRC/PRS functions longer than 8 bits may be

implemented in conjunction with PLD logic, or built in chaining

may be use to extend the function into neighboring UDBs.

Figure 7-11.Status and Control Registers

System Bus

7.2.2.6 Input/Output FIFOs

Each datapath contains two four-byte deep FIFOs, which can be

independently configured as an input buffer (system bus writes

to the FIFO, datapath internal reads the FIFO), or an output

buffer (datapath internal writes to the FIFO, the system bus reads

from the FIFO). The FIFOs generate status that are selectable

as datapath outputs and can therefore be driven to the routing,

to interact with sequencers, interrupts, or DMA.

8-bit Status Register

(Read Only)

8-bit Control Register

(Write/Read)

Routing Channel

Figure 7-7.Example FIFO Configurations

The bits of the control register, which may be written to by the

system bus, are used to drive into the routing matrix, and thus

provide firmware with the opportunity to control the state of UDB

processing. The status register is read-only and it allows internal

UDB state to be read out onto the system bus directly from

internal routing. This allows firmware to monitor the state of UDB

processing. Each bit of these registers has programmable

connections to the routing matrix and routing connections are

made depending on the requirements of the application.

System Bus

F0

System Bus

F0

F1

D0/D1

D0

A0

D1

A1

7.2.3.1 Usage Examples

A0/A1/ALU

F0

A0/A1/ALU

F1

As an example of control input, a bit in the control register can

be allocated as a function enable bit. There are multiple ways to

enable a function. In one method the control bit output would be

routed to the clock control block in one or more UDBs and serve

as a clock enable for the selected UDB blocks. A status example

is a case where a PLD or datapath block generated a condition,

such as a “compare true” condition that is captured and latched

by the status register and then read (and cleared) by CPU

firmware.

F1

System Bus

Dual Capture

TX/RX

Dual Buffer

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PSoC^®5LP: CY8C54LP Family

Datasheet

7.2.3.2 Clock Generation

An example of this is the 8-bit Timer in the upper left corner of

the array. This function only requires one datapath in the UDB,

and therefore the PLD resources may be allocated to another

function. A function such as a Quadrature Decoder may require

more PLD logic than one UDB can supply and in this case can

utilize the unused PLD blocks in the 8-bit Timer UDB.

Programmable resources in the UDB array are generally

homogeneous so functions can be mapped to arbitrary

boundaries in the array.

Each subcomponent block of a UDB including the two PLDs, the

datapath, and Status and Control, has a clock selection and

control block. This promotes a fine granularity with respect to

allocating clocking resources to UDB component blocks and

allows unused UDB resources to be used by other functions for

maximum system efficiency.

7.3 UDB Array Description

Figure 7-4.Function Mapping Example in a Bank of UDBs

Figure 7-3. shows an example of a 16 UDB array. In addition to

the array core, there are a DSI routing interfaces at the top and

bottom of the array. Other interfaces that are not explicitly shown

include the system interfaces for bus and clock distribution. The

UDB array includes multiple horizontal and vertical routing

channels each comprised of 96 wires. The wire connections to

UDBs, at horizontal/vertical intersection and at the DSI interface

are highly permutable providing efficient automatic routing in

PSoC Creator. Additionally the routing allows wire by wire

segmentation along the vertical and horizontal routing to further

increase routing flexibility and capability.

8-Bit

Timer

16-Bit

PWM

Quadrature Decoder

16-Bit PYRS

UDB

HV

A

HV

B

HV

A

HV

B

UDB

8-Bit

UDB

8-Bit SPI

UDB

Figure 7-3.Digital System Interface Structure

Timer

Logic

I2C Slave

UDB

12-Bit SPI

UDB

System Connections

UDB

HV

B

HV

A

HV

B

HV

A

HV

B

HV

A

HV

B

HV

A

UDB

Logic

UDB

HV

A

HV

B

HV

A

HV

B

UDB

UART

12-Bit PWM

UDB

7.4 DSI Routing Interface Description

The DSI routing interface is a continuation of the horizontal and

vertical routing channels at the top and bottom of the UDB array

core. It provides general purpose programmable routing

between device peripherals, including UDBs, I/Os, analog

peripherals, interrupts, DMA and fixed function peripherals.

HV

B

HV

A

HV

B

HV

A

UDB

Figure 7-5. illustrates the concept of the digital system

interconnect, which connects the UDB array routing matrix with

other device peripherals. Any digital core or fixed function

peripheral that needs programmable routing is connected to this

interface.

HV

A

HV

B

HV

A

HV

B

System Connections

Signals in this category include:

■ Interrupt requests from all digital peripherals in the system.

■ DMA requests from all digital peripherals in the system.

■ Digital peripheral data signals that need flexible routing to I/Os.

■ Digital peripheral data signals that need connections to UDBs.

■ Connections to the interrupt and DMA controllers.

■ Connection to I/O pins.

7.3.1 UDB Array Programmable Resources

Figure 7-4. shows an example of how functions are mapped into

a bank of 16 UDBs. The primary programmable resources of the

UDB are two PLDs, one datapath and one status/control register.

These resources are allocated independently, because they

have independently selectable clocks, and therefore unused

blocks are allocated to other unrelated functions.

■ Connection to analog system digital signals.

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PSoC^®5LP: CY8C54LP Family

Datasheet

Figure 7-5.Digital System Interconnect

7.4.1 I/O Port Routing

I/O

Port

Pins

There are a total of 20 DSI routes to a typical 8-bit I/O port, 16

for data and four for drive strength control.

Timer

Counters

Interrupt

Controller

DMA

Controller

Global

Clocks

I2C

When an I/O pin is connected to the routing, there are two

primary connections available, an input and an output. In

conjunction with drive strength control, this can implement a

bidirectional I/O pin. A data output signal has the option to be

single synchronized (pipelined) and a data input signal has the

option to be double synchronized. The synchronization clock is

the system clock (see Figure 6-1.). Normally all inputs from pins

are synchronized as this is required if the CPU interacts with the

signal or any signal derived from it. Asynchronous inputs have

rare uses. An example of this is a feed through of combinational

PLD logic from input pins to output pins.

Digital System Routing I/F

UDB ARRAY

Figure 7-7.I/O Pin Synchronization Routing

Digital System Routing I/F

DO

DI

I/O

Port

Pins

Delta-

Sigma

ADC

Global

Clocks

SAR

ADC

SC/CT

Blocks

EMIF

DACS

Comparators

Interrupt and DMA routing is very flexible in the CY8C54LP

programmable architecture. In addition to the numerous fixed

function peripherals that can generate interrupt requests, any

data signal in the UDB array routing can also be used to generate

a request. A single peripheral may generate multiple

independent interrupt requests simplifying system and firmware

design. Figure 7-6. shows the structure of the IDMUX

(Interrupt/DMA Multiplexer).

Figure 7-8.I/O Pin Output Connectivity

8 IO Data Output Connections from the

UDB Array Digital System Interface

Figure 7-6.Interrupt and DMA Processing in the IDMUX

Interrupt and DMA Processing in IDMUX

Fixed Function IRQs

0

1

Interrupt

Controller

DO

PIN 0

DO

PIN1

DO

PIN2

DO

PIN3

DO

PIN4

DO

PIN5

DO

PIN6

DO

PIN7

IRQs

2

3

UDB Array

Edge

Detect

DRQs

Port i

DMA termout (IRQs)

0

Fixed Function DRQs

DMA

Controller

1

2

There are four more DSI connections to a given I/O port to

implement dynamic output enable control of pins. This

connectivity gives a range of options, from fully ganged 8-bits

controlled by one signal, to up to four individually controlled pins.

The output enable signal is useful for creating tri-state

bidirectional pins and buses.

Edge

Detect

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Datasheet

Figure 7-9.I/O Pin Output Enable Connectivity

7.6 Timers, Counters, and PWMs

The Timer/Counter/PWM peripheral is a 16-bit dedicated

peripheral providing three of the most common embedded

peripheral features. As almost all embedded systems use some

combination of timers, counters, and PWMs. Four of them have

been included on this PSoC device family. Additional and more

advanced functionality timers, counters, and PWMs can also be

instantiated in Universal Digital Blocks (UDBs) as required.

PSoC Creator allows you to choose the timer, counter, and PWM

features that they require. The tool set utilizes the most optimal

resources available.

4 IO Control Signal Connections from

UDB Array Digital System Interface

The Timer/Counter/PWM peripheral can select from multiple

clock sources, with input and output signals connected through

the DSI routing. DSI routing allows input and output connections

to any device pin and any internal digital signal accessible

through the DSI. Each of the four instances has a compare

output, terminal count output (optional complementary compare

output), and programmable interrupt request line. The

OE

PIN 0

OE

PIN1

OE

PIN2

OE

PIN3

OE

PIN4

OE

PIN5

OE

PIN6

OE

PIN7

Port i

Timer/Counter/PWMs are configurable as free running, one shot,

or Enable input controlled. The peripheral has timer reset and

capture inputs, and a kill input for control of the comparator

outputs. The peripheral supports full 16-bit capture.

7.5 USB

PSoC includes a dedicated Full-Speed (12 Mbps) USB 2.0

transceiver supporting all four USB transfer types: control,

interrupt, bulk, and isochronous. PSoC Creator provides full

configuration support. USB interfaces to hosts through two

dedicated USBIO pins, which are detailed in the “I/O System and

Routing” section on page 33.

Timer/Counter/PWM features include:

■ 16-bit Timer/Counter/PWM (down count only)

■ Selectable clock source

USB includes the following features:

■ Eight unidirectional data endpoints

■ PWM comparator (configurable for LT, LTE, EQ, GTE, GT)

■ Period reload on start, reset, and terminal count

■ Interrupt on terminal count, compare true, or capture

■ Dynamic counter reads

■ One bidirectional control endpoint 0 (EP0)

■ Shared 512-byte buffer for the eight data endpoints

■ Dedicated 8-byte buffer for EP0

■ Three memory modes

■ Timer capture mode

❐ Manual Memory Management with No DMA Access

❐ Manual Memory Management with Manual DMA Access

❐ Automatic Memory Management with Automatic DMA

Access

■ Count while enable signal is asserted mode

■ Free run mode

■ One Shot mode (stop at end of period)

■ Complementary PWM outputs with deadband

■ PWM output kill

■ Internal 3.3 V regulator for transceiver

■ Internal 48 MHz oscillator that auto locks to USB bus clock,

requiring no external crystal for USB (USB equipped parts only)

Figure 7-11.Timer/Counter/PWM

■ Interrupts on bus and each endpoint event, with device wakeup

■ USB Reset, Suspend, and Resume operations

■ Bus powered and self powered modes

Figure 7-10.USB

Clock

IRQ

Reset

Timer / Counter /

TC / Compare!

Compare

Enable

Capture

Kill

PWM 16-bit

512 X 8

Arbiter

SRAM

External 22 

Resistors

D+

S I E

(Serial Interface

Engine)

USB

I/O

D–

Interrupts

48 MHz

IMO

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PSoC^®5LP: CY8C54LP Family

Datasheet

2

functionality is required, I C pin connections are limited to one of

7.7 I C

two specific pairs of SIO pins. See descriptions of SCL and SDA

pins in Pin Descriptions on page 11.

2

PSoC includes a single fixed-function I C peripheral. Additional

I C interfaces can be instantiated using Universal Digital Blocks

(UDBs) in PSoC Creator, as required.

2

I C features include:

2

The I C peripheral provides a synchronous two-wire interface

■ Slave and master, transmitter, and receiver operation

■ Byte processing for low CPU overhead

■ Interrupt or polling CPU interface

2

designed to interface the PSoC device with a two-wire I C serial

communication bus. It is compatible with I C Standard-mode,

Fast-mode, and Fast-mode Plus devices as defined in the NXP

I C-bus specification and user manual (UM10204). The I C bus

I/O may be implemented with GPIO or SIO in open-drain modes.

[11]

2

■ Support for bus speeds up to 1 Mbps

To eliminate the need for excessive CPU intervention and

■ 7 or 10-bit addressing (10-bit addressing requires firmware

support)

2

overhead, I C specific support is provided for status detection

2

and generation of framing bits. I C operates as a slave, a master,

[11]

or multimaster (Slave and Master) . In slave mode, the unit

■ SMBus operation (through firmware support - SMBus

always listens for a start condition to begin sending or receiving

data. Master mode supplies the ability to generate the Start and

Stop conditions and initiate transactions. Multimaster mode

provides clock synchronization and arbitration to allow multiple

masters on the same bus. If Master mode is enabled and Slave

mode is not enabled, the block does not generate interrupts on

supported in hardware in UDBs)

■ 7-bit hardware address compare

■ Wake from low power modes on address match

■ Glitch filtering (active and alternate-active modes only)

2

externally generated Start conditions. I C interfaces through the

DSI routing and allows direct connections to any GPIO or SIO

Data transfers follow the format shown in Figure 7-12.. After the

START condition (S), a slave address is sent. This address is 7

bits long followed by an eighth bit which is a data direction bit

(R/W) - a 'zero' indicates a transmission (WRITE), a 'one'

indicates a request for data (READ). A data transfer is always

terminated by a STOP condition (P) generated by the master.

pins.

2

I C provides hardware address detect of a 7-bit address without

CPU intervention. Additionally the device can wake from low

power modes on a 7-bit hardware address match. If wakeup

Figure 7-12.I²C Complete Transfer Timing

SDA

SCL

8

9

1 - 7

8

9

1 - 7

8

9

1 - 7

START

Condition

STOP

Condition

ADDRESS

R/W

ACK

DATA

ACK

DATA

ACK

7.7.1 External Electrical Connections

Figure 7-13.Connection of Devices to the I²C Bus

2

As Figure 7-13. shows, the I C bus requires external pull-up

resistors (R ). These resistors are primarily determined by the

P

supply voltage, bus speed, and bus capacitance. For detailed

information on how to calculate the optimum pull-up resistor

value for your design, we recommend using the UM10204

I2C-bus specification and user manual Rev 6, or newer, available

from the NXP website at www.nxp.com.

Notes

10. The I²C peripheral is non-compliant with the NXP I²C specification in the following areas: analog glitch filter, I/O V_OL/I_OL, I/O hysteresis. The I²C Block has a digital

glitch filter (not available in sleep mode). The Fast-mode minimum fall-time specification can be met by setting the I/Os to slow speed mode. See the I/O Electrical

Specifications in “Inputs and Outputs” section on page 73 for details.

11. Fixed-block I²C does not support undefined bus conditions, nor does it support Repeated Start in Slave mode. These conditions should be avoided, or the UDB-based

I²C component should be used instead.

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PSoC^®5LP: CY8C54LP Family

Datasheet

For most designs, the default values in Table 7-2 will provide

excellent performance without any calculations. The default

values were chosen to use standard resistor values between the

minimum and maximum limits. The values in Table 7-2 work for

Equation parameters:

2

V

I

= Nominal supply voltage for I C bus

DD

OL

= Maximum output low voltage of bus devices.

2

designs with 1.8 V to 5.0V V , less than 200-pF bus capaci-

= Low-level output current from I C specification

DD

OL

tance (C ), up to 25 µA of total input leakage (I ), up to 0.4 V

B

IL

2

T = Rise Time of bus from I C specification

R

output voltage level (V ), and a max V of 0.7 * V . Standard

OL

IH

DD

Mode and Fast Mode can use either GPIO or SIO PSoC pins.

C = Capacitance of each bus line including pins and PCB traces

B

Fast Mode Plus requires use of SIO pins to meet the V spec

OL

V

= Minimum high-level input voltage of all bus devices

IH

at 20 mA. Calculation of custom pull-up resistor values is

required; if your design does not meet the default assumptions,

you use series resistors (RS) to limit injected noise, or you need

to maximize the resistor value for low power consumption.

2

V

= Minimum high-level input noise margin from I C specifi-

NH

cation

I

= Total input leakage current of all devices on the bus

IH

Table 7-2. Recommended default Pull-up Resistor Values

The supply voltage (V ) limits the minimum pull-up resistor

DD

value due to bus devices maximum low output voltage (V

)

OL

R_P

Units

Ω

specifications. Lower pull-up resistance increases current

though the pins and can, therefore, exceed the spec conditions

of V . Equation 1 is derived using Ohm's law to determine the

Standard Mode – 100 kbps

Fast Mode – 400 kbps

4.7 k, 5%

1.74 k, 1%

620, 5%

OH

Ω

minimum resistance that will still meet the V specification at

OL

Fast Mode Plus – 1 Mbps

Ω

3 mA for standard and fast modes, and 20 mA for fast mode plus

at the given V

.

DD

Calculation of the ideal pull-up resistor value involves finding a

value between the limits set by three equations detailed in the

NXP I C specification. These equations are:

Equation 2 determines the maximum pull-up resistance due to

bus capacitance. Total bus capacitance is comprised of all pin,

wire, and trace capacitance on the bus. The higher the bus

capacitance, the lower the pull-up resistance required to meet

the specified bus speeds rise time due to RC delays. Choosing

a pull-up resistance higher than allowed can result in failing

timing requirements resulting in communication errors. Most

2

Equation 1:

R_PMIN= V_DDmax – V_OLmax  I_OLmin

2

Equation 2:

designs with five or less I C devices and up to 20 centimeters of

bus trace length have less than 100 pF of bus capacitance.

A secondary effect that limits the maximum pull-up resistor value

is total bus leakage calculated in Equation 3. The primary source

of leakage is I/O pins connected to the bus. If leakage is too high,

R_PMAX= T_Rmax  0.8473  C_Bmax

Equation 3:

the pull-ups will have difficulty maintaining an acceptable V

IH

level causing communication errors. Most designs with five or

less I C devices on the bus have less than 10 µA of total leakage

R_PMAX= V_DDmin – V_IHmin + V_NHmin  I_IHmax

2

current.

Document Number: 001-84934 Rev. *K

Page 49 of 126

PSoC^®5LP: CY8C54LP Family

Datasheet

■ Two 8-bit DACs that provide either voltage or current output

8. Analog Subsystem

■ Fourcomparatorswithoptional connectiontoconfigurableLUT

outputs

The analog programmable system creates application specific

combinations of both standard and advanced analog signal

processing blocks. These blocks are then interconnected to

each other and also to any pin on the device, providing a high

level of design flexibility and IP security. The features of the

analog subsystem are outlined here to provide an overview of

capabilities and architecture.

■ Two configurable switched capacitor/continuos time (SC/CT)

blocks for functions that include opamp, unity gain buffer,

programmable gain amplifier, transimpedance amplifier, and

mixer

■ Two opamps for internal use and connection to GPIO that can

be used as high current output buffers

■ Flexible, configurable analog routing architecture provided by

analog globals, analog mux bus, and analog local buses

■ CapSense subsystem to enable capacitive touch sensing

■ High resolution Delta-Sigma ADC

■ Precision reference for generating an accurate analog voltage

for internal analog blocks

■ Successive approximation (SAR) ADC

Figure 8-1.Analog Subsystem Block Diagram

SAR

ADC

DAC

A

N

A

L

A

N

A

L

Precision

Reference

O

G

O

G

SC/CT Block

GPIO

Port

GPIO

Port

R

O

U

T

I

R

O

U

T

I

N

G

N

G

Comparators

CMP CM P

CM P

CapSense Subsystem

Config &

Status

Registers

Analog

Interface

PHUB

CPU

DSI

Array

Clock

Distribution

Decimator

Document Number: 001-84934 Rev. *K

Page 50 of 126

PSoC^®5LP: CY8C54LP Family

Datasheet

The PSoC Creator software program provides a user friendly

interface to configure the analog connections between the GPIO

and various analog resources and also connections from one

analog resource to another. PSoC Creator also provides

component libraries that allow you to configure the various

analog blocks to perform application specific functions (PGA,

transimpedance amplifier, voltage DAC, current DAC, and so

on). The tool also generates API interface libraries that allow you

to write firmware that allows the communication between the

analog peripheral and CPU/Memory.

8.1.2 Functional Description

Analog globals (AGs) and analog mux buses (AMUXBUS)

provide analog connectivity between GPIOs and the various

analog blocks. There are 16 AGs in the PSoC 5LP family. The

analog routing architecture is divided into four quadrants as

shown in Figure 8-1.. Each quadrant has four analog globals

(AGL[0..3], AGL[4..7], AGR[0..3], AGR[4..7]). Each GPIO is

connected to the corresponding AG through an analog switch.

The analog mux bus is a shared routing resource that connects

to every GPIO through an analog switch. There are two

AMUXBUS routes in PSoC 5LP, one in the left half (AMUXBUSL)

and one in the right half (AMUXBUSR), as shown in Figure 8-1..

8.1 Analog Routing

The PSoC 5LP family of devices has a flexible analog routing

architecture that provides the capability to connect GPIOs and

different analog blocks, and also route signals between different

analog blocks. One of the strong points of this flexible routing

architecture is that it allows dynamic routing of input and output

connections to the different analog blocks.

Analog local buses (abus) are routing resources located within

the analog subsystem and are used to route signals between

different analog blocks. There are eight abus routes in

PSoC 5LP, four in the left half (abusl [0:3]) and four in the right

half (abusr [0:3]) as shown in Figure 8-1.. Using the abus saves

the analog globals and analog mux buses from being used for

interconnecting the analog blocks.

For information on how to make pin selections for optimal analog

routing, refer to the application note, AN58304 - PSoC® 3 and

PSoC® 5 - Pin Selection for Analog Designs.

Multiplexers and switches exist on the various buses to direct

signals into and out of the analog blocks. A multiplexer can have

only one connection on at a time, whereas a switch can have

multiple connections on simultaneously. In Figure 8-1.

multiplexers are indicated by grayed ovals and switches are

indicated by transparent ovals.

8.1.1 Features

■ Flexible, configurable analog routing architecture

■ 16 Analog globals (AG) and two analog mux buses

(AMUXBUS) to connect GPIOs and the analog blocks

■ Each GPIO is connected to one analog global and one analog

mux bus

■ 8 Analog local buses (abus) to route signals between the

different analog blocks

■ Multiplexers and switches for input and output selection of the

analog blocks

Document Number: 001-84934 Rev. *K

Page 51 of 126

PSoC^®5LP: CY8C54LP Family

Datasheet

Figure 8-1.CY8C54LP Analog Interconnect

*

swinp

*

swinn

*

AMUXBUSR

AMUXBUSL

AGL[4]

AGR[4]

AGR[5]

AGR[6]

AGR[7]

AGL[5]

AGL[6]

AGL[7]

ExVrefL

ExVrefL1

ExVrefL2

swinp

swinn

GPIO

P3[5]

GPIO

P3[4]

GPIO

P3[3]

GPIO

P3[2]

GPIO

P3[1]

GPIO

P3[0]

GPXT

opamp1

swfol

opamp3

swfol

opamp0

swfol

opamp2

swfol

swinp

swinn

0123

3210

01234567

76543210

GPIO

P0[4]

GPIO

P0[5]

GPIO

P0[6]

GPIO

swinp

swinn

swout

LPF

in0

in1

abuf_vref_int

(1.024V)

abuf_vref_int

(1.024V)

i0

i2

*

ExVrefR

out0

out1

swin

comp0

comp1

+

-

+

-

*

P0[7]

i3

i1

COMPARATOR

cmp0_vref

(1.024V)

cmp0_vref

(1.024V)

+

-

+

-

GPIO

P4[2]

GPIO

P4[3]

GPIO

cmp_muxvn[1:0]

vref_cmp1

_{bg_v}(_d0_a._{_}2_re5_s6_{_}V_en)

comp2

comp3

cmp1_vref

*

P15[1]

GPXT

P15[0]

bg_vda_swabusl0

Vdda

Vdda/2

out

ref

in

out

ref

in

refbuf_vref1 (1.024V)

CAPSENSE

refbufl

refbuf_vref1 (1.024V)

refbuf_vref2 (1.2V)

*

refbuf_vref2 (1.2V)

refbufr

refsel[1:0]

P4[4]

GPIO

P4[5]

GPIO

P4[6]

GPIO

P4[7]

vssa

Vssa

sc0

Vin

Vref

out

sc1

Vin

Vref

sc1_bgref

(1.024V)

sc0_bgref

(1.024V)

*

out

sc2_bgref

(1.024V)

sc3_bgref

(1.024V)

Vccd

SC/CT

Vin

Vref

out

sc2

Vin

Vref

out

sc3

*

Vssd

*

Vccd

Vddd

*

Vssd

ABUSL0

ABUSL1

ABUSL2

ABUSL3

ABUSR0

ABUSR1

ABUSR2

ABUSR3

*

Vddd

GPIO

P6[0]

GPIO

P6[1]

GPIO

P6[2]

GPIO

P6[3]

GPIO

P15[4]

GPIO

P15[5]

GPIO

P2[0]

GPIO

P2[1]

GPIO

P2[2]

GPIO

v0

i0

v1

DAC1

i1

USB IO

DAC0

*

P15[7]

VIDAC

USB IO

v2

i2

v3

DAC3

i3

*

DAC2

P15[6]

GPIO

dac_vref (0.256V)

vcmsel[1:0]

vssd

P5[7]

GPIO

P5[6]

GPIO

P5[5]

GPIO

P5[4]

SIO

P12[7]

SIO

P12[6]

GPIO

+

DSM0

DSM

refs

-

vssa

dsm0_vcm_vref1 (0.8V)

dsm0_vcm_vref2 (0.7V)

vcm

qtz_ref

vref_vss_ext

dsm0_qtz_vref2 (1.2V)

dsm0_qtz_vref1 (1.024V)

Vdda/3

Vdda/4

ExVrefL

Vp (+)

ExVrefR

refmux[2:0]

(+) Vp

SAR1

(-) Vn

Vrefhi_out

SAR0

Vn (-)

Vrefhi_out

refs

SAR_vref1 (1.024V)

SAR_vref2 (1.2V)

SAR_vref1 (1.024V)

SAR_vref2 (1.2V)

SAR ADC ^refs

Vdda

Vdda/2

en_resvda

Vdda

*

P1[7]

GPIO

Vdda/2

ExVrefL1

ExVrefL2

en_resvda

refmux[2:0]

AMUXBUSL

AMUXBUSR

76543210

0123

ANALOG

BUS

*

P1[6]

01234567

3210

ANALOG

ANALOG ANALOG

*

P2[3]

GPIO

P2[4]

GLOBALS

BUS

GLOBALS

*

VBE

TS

ADC

*

:

Vss ref

Vddio2

LPF

AGL[3]

AGL[2]

AGR[3]

AGR[2]

AGR[1]

AGL[1]

AGL[0]

AGR[0]

AMUXBUSR

AMUXBUSL

*

Mux Group

Switch Group

*

Connection

*

Switch Resistance

Notes:

Small ( ~870 Ohms )

Large ( ~200 Ohms)

* Denotes pins on all packages

LCD signals are not shown.

Rev #60

10-Feb-2012

To preserve detail of this image, this image is best viewed with a PDF display program or printed on 11” × 17” paper.

Document Number: 001-84934 Rev. *K

Page 52 of 126

PSoC^®5LP: CY8C54LP Family

Datasheet

Figure 8-1.Delta-sigma ADC Block Diagram

8.2 Delta-sigma ADC

Some CY8C36 devices offer a delta-sigma ADC. This ADC

offers differential input, high resolution and excellent linearity,

making it a good ADC choice for measurement applications. The

converter can be configured to output 12-bit resolution at data

rates of up to 192 ksps. At a fixed clock rate, resolution can be

traded for faster data rates as shown in Table 8-1 and

Figure 8-2..

Positive

Input Mux

Delta

Sigma

Modulator

Input

Buffer

12 to 20 Bit

Result

Decimator

SOC

(Analog Routing)

Negative

Input Mux

EOC

Table 8-1. Delta-sigma ADC Performance

MaximumSampleRate

Resolution and sample rate are controlled by the Decimator.

Data is pipelined in the decimator; the output is a function of the

last four samples. When the input multiplexer is switched, the

output data is not valid until after the fourth sample after the

switch.

Bits

SINAD (dB)

(sps)

192 k

384 k

12

8

66

43

8.2.2 Operational Modes

The ADC can be configured by the user to operate in one of four

modes: Single Sample, Multi Sample, Continuous, or Multi

Sample (Turbo). All four modes are started by either a write to

the start bit in a control register or an assertion of the Start of

Conversion (SoC) signal. When the conversion is complete, a

status bit is set and the output signal End of Conversion (EoC)

asserts high and remains high until the value is read by either the

DMA controller or the CPU.

Figure 8-2.Delta-sigma ADC Sample Rates, Range = ±1.024 V

1,000,000

100,000

10,000

1,000

8.2.2.1 Single Sample

In Single Sample mode, the ADC performs one sample

conversion on a trigger. In this mode, the ADC stays in standby

state waiting for the SoC signal to be asserted. When SoC is

signaled the ADC performs four successive conversions. The

first three conversions prime the decimator. The ADC result is

valid and available after the fourth conversion, at which time the

EoC signal is generated. To detect the end of conversion, the

system may poll a control register for status or configure the

external EoC signal to generate an interrupt or invoke a DMA

request. When the transfer is done the ADC reenters the standby

state where it stays until another SoC event.

Continuous

Multi-Sample

100

7

8

9

10

11

12

13

8.2.2.2 Continuous

Resolution, bits

Continuous sample mode is used to take multiple successive

samples of a single input signal. Multiplexing multiple inputs

should not be done with this mode. There is a latency of three

conversion times before the first conversion result is available.

This is the time required to prime the decimator. After the first

result, successive conversions are available at the selected

sample rate.

8.2.1 Functional Description

The ADC connects and configures three basic components,

input buffer, delta-sigma modulator, and decimator. The basic

block diagram is shown in Figure 8-1.. The signal from the input

muxes is delivered to the delta-sigma modulator either directly or

through the input buffer. The delta-sigma modulator performs the

actual analog to digital conversion. The modulator over-samples

the input and generates a serial data stream output. This high

speed data stream is not useful for most applications without

some type of post processing, and so is passed to the decimator

through the Analog Interface block. The decimator converts the

high speed serial data stream into parallel ADC results. The

8.2.2.3 Multi Sample

Multi sample mode is similar to continuous mode except that the

ADC is reset between samples. This mode is useful when the

input is switched between multiple signals. The decimator is

re-primed between each sample so that previous samples do not

affect the current conversion. Upon completion of a sample, the

next sample is automatically initiated. The results can be

transferred using either firmware polling, interrupt, or DMA.

4

modulator/decimator frequency response is [(sin x)/x] .

More information on output formats is provided in the Technical

Reference Manual.

Document Number: 001-84934 Rev. *K

Page 53 of 126

PSoC^®5LP: CY8C54LP Family

Datasheet

8.2.3 Start of Conversion Input

8.3.2 Conversion Signals

The SoC signal is used to start an ADC conversion. A digital

clock or UDB output can be used to drive this input. It can be

used when the sampling period must be longer than the ADC

conversion time or when the ADC must be synchronized to other

hardware. This signal is optional and does not need to be

connected if ADC is running in a continuous mode.

Writing a start bit or assertion of a Start of Frame (SOF) signal is

used to start a conversion. SOF can be used in applications

where the sampling period is longer than the conversion time, or

when the ADC needs to be synchronized to other hardware. This

signal is optional and does not need to be connected if the SAR

ADC is running in a continuous mode. A digital clock or UDB

output can be used to drive this input. When the SAR is first

powered up or awakened from any of the sleeping modes, there

is a power up wait time of 10 µs before it is ready to start the first

conversion.

8.2.4 End of Conversion Output

The EoC signal goes high at the end of each ADC conversion.

This signal may be used to trigger either an interrupt or DMA

request.

When the conversion is complete, a status bit is set and the

output signal End of Frame (EOF) asserts and remains asserted

until the value is read by either the DMA controller or the CPU.

The EOF signal may be used to trigger an interrupt or a DMA

request.

8.3 Successive Approximation ADC

The CY8C54LP family of devices has a Successive

Approximation (SAR) ADC. This ADC is 12-bit at up to 1 Msps,

with single-ended or differential inputs, making it useful for a wide

variety of sampling and control applications.

8.3.3 Operational Modes

A ONE_SHOT control bit is used to set the SAR ADC conversion

mode to either continuous or one conversion per SOF signal.

DMA transfer of continuous samples, without CPU intervention,

is supported.

8.3.1 Functional Description

In a SAR ADC an analog input signal is sampled and compared

with the output of a DAC. A binary search algorithm is applied to

the DAC and used to determine the output bits in succession

from MSB to LSB. A block diagram of one SAR ADC is shown in

Figure 8-1..

8.4 Comparators

The CY8C54LP family of devices contains four comparators.

Comparators have these features:

Figure 8-1.SAR ADC Block Diagram

■ Input offset factory trimmed to less than 5 mV

■ Rail-to-rail common mode input range (V

to V

)

SSA

DDA

vin

S/H

DAC

array

SAR

digital

comparator

D0:D11

■ Speed and power can be traded off by using one of three

modes: fast, slow, or ultra low power

vrefp

vrefn

■ Comparator outputs can be routed to look up tables to perform

simple logic functions and then can also be routed to digital

blocks

autozero

reset

clock

■ The positive input ofthe comparators may be optionally passed

clock

through a low pass filter. Two filters are provided

power

filtering

POWER

GROUND

vrefp

vrefn

■ Comparator inputs can be connections to GPIO, DAC outputs

and SC block outputs

8.4.1 Input and Output Interface

The positive and negative inputs to the comparators come from

the analog global buses, the analog mux line, the analog local

bus and precision reference through multiplexers. The output

from each comparator could be routed to any of the two input

LUTs. The output of that LUT is routed to the UDB Digital System

Interface.

The input is connected to the analog globals and muxes. The

frequency of the clock is 18 times the sample rate; the clock rate

ranges from 1 to 18 MHz.

Document Number: 001-84934 Rev. *K

Page 54 of 126

PSoC^®5LP: CY8C54LP Family

Datasheet

Figure 8-2.Analog Comparator

ANAIF

From

Analog

Routing

+

comp0

_

+

_

From

Analog

Routing

comp1

From

Analog

Routing

+

comp3

_

+

From

Analog

Routing

comp2

_

4

LUT0

LUT1

LUT2

LUT3

UDBs

8.4.2 LUT

Table 8-2. LUT Function vs. Program Word and Inputs

The CY8C54LP family of devices contains four LUTs. The LUT

is a two input, one output lookup table that is driven by any one

or two of the comparators in the chip. The output of any LUT is

routed to the digital system interface of the UDB array. From the

digital system interface of the UDB array, these signals can be

connected to UDBs, DMA controller, I/O, or the interrupt

controller.

Control Word

0000b

0001b

0010b

0011b

0100b

0101b

0110b

0111b

Output (A and B are LUT inputs)

FALSE (‘0’)

A AND B

A AND (NOT B)

A

(NOT A) AND B

B

The LUT control word written to a register sets the logic function

on the output. The available LUT functions and the associated

control word is shown in Table 8-2.

A XOR B

A OR B

1000b

1001b

1010b

1011b

1100b

1101b

1110b

A NOR B

A XNOR B

NOT B

A OR (NOT B)

NOT A

(NOT A) OR B

A NAND B

TRUE (‘1’)

1111b

Document Number: 001-84934 Rev. *K

Page 55 of 126

PSoC^®5LP: CY8C54LP Family

Datasheet

The opamp has three speed modes, slow, medium, and fast. The

slow mode consumes the least amount of quiescent power and

the fast mode consumes the most power. The inputs are able to

swing rail-to-rail. The output swing is capable of rail-to-rail

operation at low current output, within 50 mV of the rails. When

driving high current loads (about 25 mA) the output voltage may

only get within 500 mV of the rails.

8.5 Opamps

The CY8C54LP family of devices contain two general purpose

opamps.

Figure 8-3.Opamp

GPIO

8.6 Programmable SC/CT Blocks

Analog

Global Bus

The CY8C54LP family of devices contains two switched

capacitor/continuous time (SC/CT) blocks in a device. Each

switched capacitor/continuous time block is built around a single

rail-to-rail high bandwidth opamp.

Opamp

Analog

Global Bus

GPIO

VREF

Analog

Switched capacitor is a circuit design technique that uses

capacitors plus switches instead of resistors to create analog

functions. These circuits work by moving charge between

capacitors by opening and closing different switches.

Nonoverlapping in phase clock signals control the switches, so

that not all switches are ON simultaneously.

Internal Bus

=

Analog Switch

GPIO

The opamp is uncommitted and can be configured as a gain

stage or voltage follower on external or internal signals.

The PSoC Creator tool offers a user friendly interface, which

allows you to easily program the SC/CT blocks. Switch control

and clock phase control configuration is done by PSoC Creator

so users only need to determine the application use parameters

such as gain, amplifier polarity, V_REFconnection, and so on.

See Figure 8-4.. In any configuration, the input and output

signals can all be connected to the internal global signals and

monitored with an ADC, or comparator. The configurations are

implemented with switches between the signals and GPIO pins.

The same opamps and block interfaces are also connectable to

an array of resistors which allows the construction of a variety of

continuous time functions.

Figure 8-4.Opamp Configurations

a) Voltage Follower

The opamp and resistor array is programmable to perform

various analog functions including

■ Naked Operational Amplifier - Continuous Mode

■ Unity-Gain Buffer - Continuous Mode

Opamp

Vout to Pin

Vin

■ Programmable Gain Amplifier (PGA) - Continuous Mode

■ Transimpedance Amplifier (TIA) - Continuous Mode

■ Up/Down Mixer - Continuous Mode

b) External Uncommitted

Opamp

■ Sample and Hold Mixer (NRZ S/H) - Switched Cap Mode

■ First Order Analog to Digital Modulator - Switched Cap Mode

8.6.1 Naked Opamp

Vout to GPIO

Opamp

The Naked Opamp presents both inputs and the output for

connection to internal or external signals. The opamp has a unity

gain bandwidth greater than 6.0 MHz and output drive current up

to 650 µA. This is sufficient for buffering internal signals (such as

DAC outputs) and driving external loads greater than 7.5 kohms.

Vp to GPIO

Vn to GPIO

8.6.2 Unity Gain

c) Internal Uncommitted

Opamp

The Unity Gain buffer is a Naked Opamp with the output directly

connected to the inverting input for a gain of 1.00. It has a -3 dB

bandwidth greater than 6.0 MHz.

Vn

To Internal Signals

Vout to Pin

GPIO Pin

Opamp

Vp

Document Number: 001-84934 Rev. *K

Page 56 of 126

PSoC^®5LP: CY8C54LP Family

Datasheet

8.6.3 PGA

Table 8-4. Feedback Resistor Settings

The PGA amplifies an external or internal signal. The PGA can

be configured to operate in inverting mode or noninverting mode.

The PGA function may be configured for both positive and

negative gains as high as 50 and 49 respectively. The gain is

adjusted by changing the values of R1 and R2 as illustrated in

Figure 8-5.. The schematic in Figure 8-5. shows the

configuration and possible resistor settings for the PGA. The

gain is switched from inverting and non inverting by changing the

shared select value of the both the input muxes. The bandwidth

for each gain case is listed in Table 8-3.

Configuration Word

Nominal R_fb(K)

000b

001b

010b

011b

100b

101b

110b

111b

20

30

40

60

120

250

500

1000

Table 8-3. Bandwidth

Gain

1

Bandwidth

6.0 MHz

340 kHz

220 kHz

215 kHz

Figure 8-6.Continuous Time TIA Schematic

24

48

50

R

fb

Figure 8-5.PGA Resistor Settings

I

in

R1

R2

V_in

0

1

V

out

V

ref

V_ref

20 k or 40 k

20 k to 980 k

S

The TIA configuration is used for applications where an external

sensor's output is current as a function of some type of stimulus

such as temperature, light, magnetic flux etc. In a common

application, the voltage DAC output can be connected to the

V_REFTIA input to allow calibration of the external sensor bias

current by adjusting the voltage DAC output voltage.

V_ref

V_in

0

1

The PGA is used in applications where the input signal may not

be large enough to achieve the desired resolution in the ADC, or

dynamic range of another SC/CT block such as a mixer. The gain

is adjustable at runtime, including changing the gain of the PGA

prior to each ADC sample.

8.7 LCD Direct Drive

The PSoC Liquid Crystal Display (LCD) driver system is a highly

configurable peripheral designed to allow PSoC to directly drive

a broad range of LCD glass. All voltages are generated on chip,

eliminating the need for external components. With a high

multiplex ratio of up to 1/16, the CY8C54LP family LCD driver

system can drive a maximum of 736 segments. The PSoC LCD

driver module was also designed with the conservative power

budget of portable devices in mind, enabling different LCD drive

modes and power down modes to conserve power.

8.6.4 TIA

The Transimpedance Amplifier (TIA) converts an internal or

external current to an output voltage. The TIA uses an internal

feedback resistor in a continuous time configuration to convert

input current to output voltage. For an input current I_in, the output

voltage is V_REF- I_inx R_fb, where V_REFis the value placed on the

non inverting input. The feedback resistor Rfb is programmable

between 20 K and 1 M through a configuration register.

Table 8-4 shows the possible values of Rfb and associated

configuration settings.

PSoC Creator provides an LCD segment drive component. The

component wizard provides easy and flexible configuration of

LCD resources. You can specify pins for segments and

commons along with other options. The software configures the

device to meet the required specifications. This is possible

because of the programmability inherent to PSoC devices.

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Key features of the PSoC LCD segment system are:

■ LCD panel direct driving

the desired image. Display data resides in a memory buffer in the

system SRAM. Each time you need to change the common and

segment driver voltages, the next set of pixel data moves from

the memory buffer into the Port Data Registers via DMA.

■ Type A (standard) and Type B (low power) waveform support

8.7.3 UDB and LCD Segment Control

■ Wide operating voltage range support (2 V to 5 V) for LCD

panels

A UDB is configured to generate the global LCD control signals

and clocking. This set of signals is routed to each LCD pin driver

through a set of dedicated LCD global routing channels. In

addition to generating the global LCD control signals, the UDB

also produces a DMA request to initiate the transfer of the next

frame of LCD data.

■ Static, 1/2, 1/3, 1/4, 1/5 bias voltage levels

■ Internalbiasvoltagegenerationthroughinternalresistorladder

■ Up to 62 total common and segment outputs

■ Up to 1/16 multiplex for a maximum of 16 backplane/common

outputs

8.7.4 LCD DAC

The LCD DAC generates the contrast control and bias voltage

for the LCD system. The LCD DAC produces up to five LCD drive

voltages plus ground, based on the selected bias ratio. The bias

voltages are driven out to GPIO pins on a dedicated LCD bias

bus, as required.

■ Up to 62 front plane/segment outputs for direct drive

■ Drives up to 736 total segments (16 backplane x 46 front plane)

■ Up to 64 levels of software controlled contrast

■ Ability to move display data from memory buffer to LCD driver

through DMA (without CPU intervention)

8.8 CapSense

The CapSense system provides a versatile and efficient means

for measuring capacitance in applications such as touch sense

buttons, sliders, proximity detection, and so on. The CapSense

system uses a configuration of system resources, including a few

hardware functions primarily targeted for CapSense. Specific

resource usage is detailed in the CapSense component in PSoC

Creator.

■ Adjustable LCD refresh rate from 10 Hz to 150 Hz

■ Ability to invert LCD display for negative image

■ Three LCD driver drive modes, allowing power optimization

Figure 8-7.LCD System

A capacitive sensing method using a Delta-Sigma Modulator

(CSD) is used. It provides capacitance sensing using a switched

capacitor technique with a delta-sigma modulator to convert the

sensing current to a digital code.

LCD

Global

DAC

Clock

8.9 Temp Sensor

Die temperature is used to establish programming parameters

for writing flash. Die temperature is measured using a dedicated

sensor based on a forward biased transistor. The temperature

sensor has its own auxiliary ADC.

UDB

LCD Driver

Block

8.10 DAC

Display

DMA

RAM

The CY8C54LP parts contain two Digital to Analog Convertors

(DACs). Each DAC is 8-bit and can be configured for either

voltage or current output. The DACs support CapSense, power

supply regulation, and waveform generation. Each DAC has the

following features.

PHUB

■ Adjustable voltage or current output in 255 steps

■ Programmable step size (range selection)

■ Eight bits of calibration to correct ± 25% of gain error

■ Source and sink option for current output

■ 8 Msps conversion rate for current output

■ 1 Msps conversion rate for voltage output

■ Monotonic in nature

8.7.1 LCD Segment Pin Driver

Each GPIO pin contains an LCD driver circuit. The LCD driver

buffers the appropriate output of the LCD DAC to directly drive

the glass of the LCD. A register setting determines whether the

pin is a common or segment. The pin’s LCD driver then selects

one of the six bias voltages to drive the I/O pin, as appropriate

for the display data.

■ Data and strobe inputs can be provided by the CPU or DMA,

or routed directly from the DSI

8.7.2 Display Data Flow

■ Dedicated low-resistance output pin for high-current mode

The LCD segment driver system reads display data and

generates proper output voltages to the LCD glass to produce

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Figure 8-8.DAC Block Diagram

I _sourceRange

1x,8x, 64x

Vout

Reference

Source

Scaler

Iout

R

3R

I _sinkRange

1x,8x, 64x

8.10.1 Current DAC

Continuous time up and down mixing works for applications with

input signals and local oscillator frequencies up to 1 MHz.

The current DAC (IDAC) can be configured for the ranges 0 to

31.875 µA, 0 to 255 µA, and 0 to 2.04 mA. The IDAC can be

configured to source or sink current.

Figure 8-1.Mixer Configuration

8.10.2 Voltage DAC

C2 = 1.7 pF

C1 = 850 fF

For the voltage DAC (VDAC), the current DAC output is routed

through resistors. The two ranges available for the VDAC are 0

to 1.02 V and 0 to 4.08 V. In voltage mode any load connected

to the output of a DAC should be purely capacitive (the output of

the VDAC is not buffered).

R^mix0 20 k or 40 k

8.11 Up/Down Mixer

sc_clk

R^mix0 20 k or 40 k

Vin

In continuous time mode, the SC/CT block components are used

to build an up or down mixer. Any mixing application contains an

input signal frequency and a local oscillator frequency. The

polarity of the clock, Fclk, switches the amplifier between

inverting or noninverting gain. The output is the product of the

input and the switching function from the local oscillator, with

frequency components at the local oscillator plus and minus the

signal frequency (Fclk + Fin and Fclk - Fin) and reduced-level

frequency components at odd integer multiples of the local

oscillator frequency. The local oscillator frequency is provided by

the selected clock source for the mixer.

Vout

0

1

Vref

sc_clk

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8.12 Sample and Hold

9. Programming, Debug Interfaces,

Resources

The main application for a sample and hold, is to hold a value

stable while an ADC is performing a conversion. Some

applications require multiple signals to be sampled

simultaneously, such as for power calculations (V and I). PSoC

Creator offers a sample and hold component to support this

function.

The Cortex-M3 has internal debugging components, tightly

integrated with the CPU, providing the following features:

■ JTAG or SWD access

■ Flash Patch and Breakpoint (FPB) block for implementing

breakpoints and code patches

Figure 8-2.Sample and Hold Topology

(1 and 2 are opposite phases of a clock)

■ Data Watchpoint and Trigger (DWT) block for implementing

watchpoints, trigger resources, and system profiling

₁

 ₂

₁

C₁

C₂

V ⁱ

V_ref

n

■ Embedded Trace Macrocell (ETM) for instruction trace

V_out

 ₁

₂

■ InstrumentationTraceMacrocell(ITM)forsupportofprintf-style

debugging

²

PSoC devices include extensive support for programming,

testing, debugging, and tracing both hardware and firmware.

Four interfaces are available: JTAG, SWD, SWV, and

TRACEPORT. JTAG and SWD support all programming and

debug features of the device. JTAG also supports standard JTAG

scan chains for board level test and chaining multiple JTAG

devices to a single JTAG connection. The SWV and

TRACEPORT provide trace output from the DWT, ETM, and

ITM. TRACEPORT is faster but uses more pins. SWV is slower

but uses only one pin.

¹

₂

₁

₂

 ₁

²

V _ref

V

ref

C₃

C₄

For more information on PSoC 5 programming, refer to the

PSoC 5 Device Programming Specification.

8.12.1 Down Mixer

The S+H can be used as a mixer to down convert an input signal.

This circuit is a high bandwidth passive sample network that can

sample input signals up to 14 MHz. This sampled value is then

held using the opamp with a maximum clock rate of 4 MHz. The

output frequency is at the difference between the input frequency

and the highest integer multiple of the Local Oscillator that is less

than the input.

Cortex-M3 debug and trace functionality enables full device

debugging in the final system using the standard production

device. It does not require special interfaces, debugging pods,

simulators, or emulators. Only the standard programming

connections are required to fully support debug.

The PSoC Creator IDE software provides fully integrated

programming and debug support for PSoC devices. The low cost

MiniProg3 programmer and debugger is designed to provide full

programming and debug support of PSoC devices in conjunction

with the PSoC Creator IDE. PSoC JTAG, SWD, and SWV

interfaces are fully compatible with industry standard third party

tools.

8.12.2 First Order Modulator - SC Mode

A first order modulator is constructed by placing the switched

capacitor block in an integrator mode and using a comparator to

provide a 1-bit feedback to the input. Depending on this bit, a

reference voltage is either subtracted or added to the input

signal. The block output is the output of the comparator and not

the integrator in the modulator case. The signal is downshifted

and buffered and then processed by a decimator to make a

delta-sigma converter or a counter to make an incremental

converter. The accuracy of the sampled data from the first-order

modulator is determined from several factors.

All Cortex-M3 debug and trace modules are disabled by default

and can only be enabled in firmware. If not enabled, the only way

to reenable them is to erase the entire device, clear flash

protection, and reprogram the device with new firmware that

enables them. Disabling debug and trace features, robust flash

protection, and hiding custom analog and digital functionality

inside the PSoC device provide a level of security not possible

with multichip application solutions. Additionally, all device

interfaces can be permanently disabled (Device Security) for

applications concerned about phishing attacks due to a

maliciously reprogrammed device. Permanently disabling

interfaces is not recommended in most applications because the

designer then cannot access the device later. Because all

programming, debug, and test interfaces are disabled when

Device Security is enabled, PSoCs with Device Security enabled

may not be returned for failure analysis.

The main application for this modulator is for a low frequency

ADC with high accuracy. Applications include strain gauges,

thermocouples, precision voltage, and current measurement

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transfers, whichever is least. By default, the JTAG pins are

enabled on new devices but the JTAG interface can be disabled,

allowing these pins to be used as General Purpose I/O (GPIO)

instead. The JTAG interface is used for programming the flash

memory, debugging, I/O scan chains, and JTAG device chaining.

9.1 JTAG Interface

The IEEE 1149.1 compliant JTAG interface exists on four or five

pins (the nTRST pin is optional). The JTAG clock frequency can

be up to 12 MHz, or 1/3 of the CPU clock frequency for 8 and

16-bit transfers, or 1/5 of the CPU clock frequency for 32-bit

Figure 9-1. JTAG Interface Connections between PSoC 5LP and Programmer

V_DD

Host Programmer

PSoC 5

1, 2, 3, 4

V_DD

V_DDD, V_DDA, V_DDIO0, V_DDIO1, V_DDIO2, V_DDIO3

TCK

TCK (P1[1]

5

TMS

TMS (P1[0])

TDO

TDI

TDI (P1[4])

TDO (P1[3])

nTRST (P1[5]) ⁶

nTRST ⁶

XRES ⁴

XRES

GND

V_SSD, V_SSA

GND

¹The voltage levels of Host Programmer and the PSoC 5 voltage domains involved in Programming should be same.

The Port 1 JTAG pins and XRES pin are powered by V_DDIO1. So, V_DDIO1of PSoC 5 should be at same

voltage level as host V_DD. Rest of PSoC 5 voltage domains ( V_DDD, V_DDA, V_DDIO0, V_DDIO2, V_DDIO3) need not be at the same

voltage level as host Programmer.

2

Vdda must be greater than or equal to all other power supplies (Vddd, Vddio’s) in PSoC 5.

3

For Power cycle mode Programming, XRES pin is not required. But the Host programmer must have

the capability to toggle power (Vddd, Vdda, All Vddio’s) to PSoC 5. This may typically require external

interface circuitry to toggle power which will depend on the programming setup. The power supplies can

be brought up in any sequence, however, once stable, VDDA must be greater than or equal to all other

supplies.

4

For JTAG Programming, Device reset can also be done without connecting to the XRES pin or Power cycle mode by

using the TMS,TCK,TDI, TDO pins of PSoC 5, and writing to a specific register. But this requires that the DPS setting

in NVL is not equal to “Debug Ports Disabled”.

5

By default, PSoC 5 is configured for 4-wire JTAG mode unless user changes the DPS setting. So the TMS pin is

unidirectional. But if the DPS setting is changed to non-JTAG mode, the TMS pin in JTAG is bi-directional as the SWD

Protocol has to be used for acquiring the PSoC 5 device initially. After switching from SWD to JTAG mode, the TMS

pin will be uni-directional. In such a case, unidirectional buffer should not be used on TMS line.

6

nTRST JTAG pin (P1[5]) cannot be used to reset the JTAG TAP controlller during first time programming of PSoC 5

as the default setting is 4-wire JTAG (nTRST disabled). Use the TMS, TCK pins to do a reset of JTAG TAP controller.

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(JTAG or USB) receives a predetermined acquire sequence of

1s and 0s. If the NVL latches are set for SWD (see Section 5.5),

this sequence need not be applied to the JTAG pin pair. The

acquire sequence must always be applied to the USB pin pair.

9.2 SWD Interface

The SWD interface is the preferred alternative to the JTAG

interface. It requires only two pins instead of the four or five

needed by JTAG. SWD provides all of the programming and

debugging features of JTAG at the same speed. SWD does not

provide access to scan chains or device chaining. The SWD

clock frequency can be up to 1/3 of the CPU clock frequency.

SWD is used for debugging or for programming the flash

memory.

The SWD interface can be enabled from the JTAG interface or

disabled, allowing its pins to be used as GPIO. Unlike JTAG, the

SWD interface can always be reacquired on any device during

the key window. It can then be used to reenable the JTAG

interface, if desired. When using SWD or JTAG pins as standard

GPIO, make sure that the GPIO functionality and PCB circuits do

not interfere with SWD or JTAG use.

SWD uses two pins, either two of the JTAG pins (TMS and TCK)

or the USBIO D+ and D- pins. The USBIO pins are useful for in

system programming of USB solutions that would otherwise

require a separate programming connector. One pin is used for

the data clock and the other is used for data input and output.

SWD can be enabled on only one of the pin pairs at a time. This

only happens if, within 8 μs (key window) after reset, that pin pair

Figure 9-2. SWD Interface Connections between PSoC 5LP and Programmer

V_DD

Host Programmer

PSoC 5

1, 2, 3

V_DD

V_DDD, V_DDA, V_DDIO0, V_DDIO1, V_DDIO2, V_DDIO3

SWDCK

SWDCK (P1[1] or P15[7])

SWDIO (P1[0] or P15[6])

SWDIO

XRES

3

XRES

GND

V_SSD, V_SSA

GND

1

The voltage levels of the Host Programmer and the PSoC 5 voltage domains involved in

programming should be the same. The XRES pin is powered by V_DDIO1. The USB SWD

pins are powered by V_DDD. So for Programming using the USB SWD pins with XRES pin, the V_DDD, V_DDIO1

of PSoC 5 should be at the same voltage level as Host V_DD. Rest of PSoC 5 voltage domains

( V_DDA, V_DDIO0, V_DDIO2, V_DDIO3) need not be at the same voltage level as host Programmer. The Port 1 SWD

pins are powered by V_DDIO1. So V_DDIO1of PSoC 5 should be at same voltage level as host V_DDfor

Port 1 SWD programming. Rest of PSoC 5 voltage domains ( V_DDD, V_DDA, V_DDIO0, V_DDIO2, V_DDIO3) need not

be at the same voltage level as host Programmer.

2

Vdda must be greater than or equal to all other power supplies (Vddd, Vddio’s) in PSoC 5.

3

For Power cycle mode Programming, XRES pin is not required. But the Host programmer must have

the capability to toggle power (Vddd, Vdda, All Vddio’s) to PSoC 5. This may typically require

external interface circuitry to toggle power which will depend on the programming setup. The power

supplies can be brought up in any sequence, however, once stable, VDDA must be greater than or

equal to all other supplies.

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9.3 Debug Features

Table 9-1. Debug Configurations

The CY8C54LP supports the following debug features:

Debug and Trace Configuration

All debug and trace disabled

JTAG

GPIO Pins Used

■ Halt and single-step the CPU

0

■ View and change CPU and peripheral registers, and RAM

addresses

4 or 5

SWD

2

■ Six program address breakpoints and two literal access

breakpoints

SWV

1

TRACEPORT

5

■ Data watchpoint events to CPU

JTAG + TRACEPORT

SWD + SWV

9 or 10

■ Patch and remap instruction from flash to SRAM

■ Debugging at the full speed of the CPU

3

7

SWD + TRACEPORT

■ CompatiblewithPSoCCreatorandMiniProg3programmerand

debugger

9.6 Programming Features

■ Standard JTAG programming and debugging interfaces make

CY8C54LP compatible with other popular third-party tools (for

example, ARM / Keil)

The JTAG and SWD interfaces provide full programming

support. The entire device can be erased, programmed, and

verified. Designers can increase flash protection levels to protect

firmware IP. Flash protection can only be reset after a full device

erase. Individual flash blocks can be erased, programmed, and

verified, if block security settings permit.

9.4 Trace Features

The following trace features are supported:

■ Instruction trace

9.7 Device Security

■ Data watchpoint on access to data address, address range, or

data value

PSoC 5LP offers an advanced security feature called device

security, which permanently disables all test, programming, and

debug ports, protecting your application from external access.

The device security is activated by programming a 32-bit key

(0x50536F43) to a Write Once Latch (WOL).

■ Trace trigger on data watchpoint

■ Debug exception trigger

■ Code profiling

The Write Once Latch is a type of nonvolatile latch (NVL). The

cell itself is an NVL with additional logic wrapped around it. Each

WOL device contains four bytes (32 bits) of data. The wrapper

outputs a ‘1’ if a super-majority (28 of 32) of its bits match a

pre-determined pattern (0x50536F43); it outputs a ‘0’ if this

majority is not reached. When the output is 1, the Write Once NV

latch locks the part out of Debug and Test modes; it also

permanently gates off the ability to erase or alter the contents of

the latch. Matching all bits is intentionally not required, so that

single (or few) bit failures do not deassert the WOL output. The

state of the NVL bits after wafer processing is truly random with

no tendency toward 1 or 0.

■ Counters for measuring clock cycles, folded instructions,

load/store operations, sleep cycles, cycles per instruction,

interrupt overhead

■ Interrupt events trace

■ Software event monitoring, “printf-style” debugging

9.5 SWV and TRACEPORT Interfaces

The SWV and TRACEPORT interfaces provide trace data to a

debug host via the Cypress MiniProg3 or an external trace port

analyzer. The 5 pin TRACEPORT is used for rapid transmission

of large trace streams. The single pin SWV mode is used to

minimize the number of trace pins. SWV is shared with a JTAG

pin. If debugging and tracing are done at the same time then

SWD may be used with either SWV or TRACEPORT, or JTAG

may be used with TRACEPORT, as shown in Table 9-1.

The WOL only locks the part after the correct 32-bit key

(0x50536F43) is loaded into the NVL's volatile memory,

programmed into the NVL's nonvolatile cells, and the part is

reset. The output of the WOL is only sampled on reset and used

to disable the access. This precaution prevents anyone from

reading, erasing, or altering the contents of the internal memory.

The user can write the key into the WOL to lock out external

access only if no flash protection is set (see “Flash Security”

section on page 19). However, after setting the values in the

WOL, a user still has access to the part until it is reset. Therefore,

a user can write the key into the WOL, program the flash

protection data, and then reset the part to lock it.

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If the device is protected with a WOL setting, Cypress cannot

perform failure analysis and, therefore, cannot accept RMAs

from customers. The WOL can be read out via Serial Wire Debug

(SWD) port to electrically identify protected parts. The user can

write the key in WOL to lock out external access only if no flash

protection is set. For more information on how to take full

advantage of the security features in PSoC see the PSoC 5

TRM.

10. Development Support

The CY8C54LP family has a rich set of documentation,

development tools, and online resources to assist you during

your development process. Visit

psoc.cypress.com/getting-started to find out more.

10.1 Documentation

Disclaimer

A suite of documentation, to ensure that you can find answers to

your questions quickly, supports the CY8C54LP family. This

section contains a list of some of the key documents.

Note the following details of the flash code protection features on

Cypress devices.

Software User Guide: A step-by-step guide for using PSoC

Creator. The software user guide shows you how the PSoC

Creator build process works in detail, how to use source control

with PSoC Creator, and much more.

Cypress products meet the specifications contained in their

particular Cypress datasheets. Cypress believes that its family of

products is one of the most secure families of its kind on the

market today, regardless of how they are used. There may be

methods, unknown to Cypress, that can breach the code

protection features. Any of these methods, to our knowledge,

would be dishonest and possibly illegal. Neither Cypress nor any

other semiconductor manufacturer can guarantee the security of

their code. Code protection does not mean that we are

guaranteeing the product as “unbreakable.”

Component Datasheets: The flexibility of PSoC allows the

creation of new peripherals (components) long after the device

has gone into production. Component datasheets provide all of

the information needed to select and use a particular component,

including a functional description, API documentation, example

code, and AC/DC specifications.

Cypress is willing to work with the customer who is concerned

about the integrity of their code. Code protection is constantly

evolving. We at Cypress are committed to continuously

improving the code protection features of our products.

Application Notes: PSoC application notes discuss a particular

application of PSoC in depth; examples include brushless DC

motor control and on-chip filtering. Application notes often

include example projects in addition to the application note

document.

9.8 CSP Package Bootloader

Technical Reference Manual: PSoC Creator makes designing

with PSoC as easy as dragging a peripheral onto a schematic,

but, when low level details of the PSoC device are required, use

the technical reference manual (TRM) as your guide.

A factory-installed bootloader program is included in all devices

with CSP packages. The bootloader is compatible with PSoC

Creator 3.0 bootloadable project files, and has the following

features:

Note Visit www.arm.com for detailed documentation about the

Cortex-M3 CPU.

■ I2C-based

■ SCLK and SDAT available at P1[6] and P1[7], respectively

■ External pull-up resistors required

■ I2C slave, address 4, data rate = 100 kbps

■ Single application

10.2 Online

In addition to print documentation, the Cypress PSoC forums

connect you with fellow PSoC users and experts in PSoC from

around the world, 24 hours a day, 7 days a week.

10.3 Tools

■ Wait 2 seconds for bootload command

With industry standard cores, programming, and debugging

interfaces, the CY8C54LP family is part of a development tool

ecosystem. Visit us at www.cypress.com/go/psoccreator for the

latest information on the revolutionary, easy to use PSoC Creator

IDE, supported third party compilers, programmers, debuggers,

and development kits.

■ Other bootloader options are as set by the PSoC Creator 3.0

Bootloader Component default

■ Occupies the bottom 9 Kbytes of flash

For more information on this bootloader, see the following

Cypress application notes:

■ AN73854, PSoC 3 and PSoC 5 LP Introduction to Bootloaders

■ AN60317, PSoC 3 and PSoC 5 LP I2C Bootloader

Note that a PSoC Creator bootloadable project must be

associated with .hex and .elf files for a bootloader project that is

configured for the target device. Bootloader .hex and .elf files

can be found at www.cypress.com/go/PSoC5LPdatasheet.

The factory-installed bootloader can be overwritten using JTAG

or SWD programming.

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Datasheet

11. Electrical Specifications

Specifications are valid for –40 °C  T_A 85 °C and T_J 100 °C, except where noted. Specifications are valid for 1.71 V to 5.5 V,

except where noted. The unique flexibility of the PSoC UDBs and analog blocks enable many functions to be implemented in PSoC

Creator components, see the component datasheets for full AC/DC specifications of individual functions. See the “Example

Peripherals” section on page 40 for further explanation of PSoC Creator components.

11.1 Absolute Maximum Ratings

[12]

Table 11-1. Absolute Maximum Ratings DC Specifications

Parameter

V_DDA

Description

Conditions

Min

Typ

Max

Units

Analog supply voltage relative to

V_SSA

–0.5

–

6

V

V_DDD

Digital supply voltage relative to

V_SSD

–0.5

–

6

V

V_DDIO

V_CCA

V_CCD

V_SSA

I/O supply voltage relative to V_SSD

Direct analog core voltage input

Direct digital core voltage input

Analog ground voltage

–0.5

–

6

V

1.95

–0.5

V_SSD– 0.5

V_SSD

0.5

+

[13]

V_GPIO

V_SIO

DC input voltage on GPIO

DC input voltage on SIO

Includes signals sourced by V_DDAV_SSD– 0.5

and routed internal to the pin.

–

V_DDIO

0.5

+

V

Output disabled

Output enabled

V_SSD– 0.5

–

7

6

V

_SSD– 0.5

0.5

V_IND

V_BAT

Voltage at boost converter input

Boost converter supply

Current per V_DDIOsupply pin

GPIO current

5.5

100

41

28

59

140

–

V

V_SSD– 0.5

–

V

I_VDDIO

I_GPIO

mA

V

–30

I_SIO

SIO current

–49

I_USBIO

LU

USBIO current

–56

Latch up current^[14]

Electrostatic discharge voltage

ESD voltage

–140

2000

500

ESD_HBM

ESD_CDM

Human body model

Charge device model

–

V

Notes

12. Usage above the absolute maximum conditions listed inTable 11-1 may cause permanent damage to the device. Exposure to Absolute Maximum conditions for

extended periods of time may affect device reliability. The Maximum Storage Temperature is 150 °C in compliance with JEDEC Standard JESD22-A103, High

Temperature Storage Life. When used below Absolute Maximum conditions but above normal operating conditions, the device may not operate to specification.

13. The V_DDIOsupply voltage must be greater than the maximum voltage on the associated GPIO pins. Maximum voltage on GPIO pin V_DDIO V_DDA

.

14. Meets or exceeds JEDEC Spec EIA/JESD78 IC Latch-up Test.

Document Number: 001-84934 Rev. *K

Page 65 of 126

PSoC^®5LP: CY8C54LP Family

Datasheet

11.2 Device Level Specifications

Specifications are valid for –40 °C  T_A 85 °C and T_J 100 °C, except where noted. Specifications are valid for 1.71 V to 5.5 V,

except where noted. Unless otherwise specified, all charts and graphs show typical values.

11.2.1 Device Level Specifications

Table 11-2. DC Specifications

Parameter

Description

Conditions

Min

Typ

Max

Units

V

Analog supply voltage and input to analog Analog core regulator enabled

core regulator

1.8

–

5.5

V

DDA

V

Analog supply voltage, analog regulator Analog core regulator disabled

bypassed

1.71

1.8

1.89

V

DDA

[15]

1.8

–

V

DDA

V

Digital supply voltage relative to V

Digital core regulator enabled

Digital core regulator disabled

V

DDD

SSD

[17]

+ 0.1

DDA

Digital supply voltage, digital regulator

bypassed

1.71

1.8

1.89

DDD

[15]

1.71

–

V

DDA

[16]

V

I/O supply voltage relative to V

V

DDIO

SSIO

V

+ 0.1

DDA

Direct analog core voltage input (Analog Analog core regulator disabled

regulator bypass)

1.71

1.8

1.89

CCA

V

Direct digital core voltage input (Digital

regulator bypass)

Digital core regulator disabled

1.71

1.8

1.89

V

CCD

Active Mode

[18]

I

Sum of digital and analog IDDD + IDDA.

V

= 2.7 V to 5.5 V; T = –40 °C

–

1.9

2

3.8

5

mA

DD

DDX

CPU

[19]

= 3 MHz

IDDIOX for I/Os not included. IMO enabled, F

bus clock and CPU clock enabled. CPU

executing complex program from flash

T = 25 °C

T = 85 °C

V

F

= 2.7 V to 5.5 V; T = –40 °C

3.1

3.2

5.4

5.6

8.9

9.1

15.5

15.4

15.7

18

DDX

CPU

= 6 MHz

T = 25 °C

5

T = 85 °C

5

V

F

= 2.7 V to 5.5 V; T = –40 °C

7

DDX

CPU

[19]

= 12 MHz

T = 25 °C

7

T = 85 °C

7

V

F

= 2.7 V to 5.5 V; T = –40 °C

10.5

17

DDX

CPU

[19]

= 24 MHz

T = 25 °C

T = 85 °C

V

F

= 2.7 V to 5.5 V; T = –40 °C

DDX

CPU

[19]

= 48 MHz

T = 25 °C

17

T = 85 °C

17

V

F

= 2.7 V to 5.5 V; T = –40 °C

19.5

30

DDX

CPU

= 62 MHz

T = 25 °C

18

T = 85 °C

18.5

26.5

27

V

F

= 2.7 V to 5.5 V; T = –40 °C

DDX

CPU

= 74 MHz

T = 25 °C

30

T = 85 °C

30

V

F

= 2.7 V to 5.5 V; T = –40 °C

22

25.5

DDX

CPU

= 80 MHz, IMO

T = 25 °C

22

= 3 MHz with PLL

T = 85 °C

22.5

Notes

15. The power supplies can be brought up in any sequence however once stable V_DDAmust be greater than or equal to all other supplies.

16. The V_DDIOsupply voltage must be greater than the maximum voltage on the associated GPIO pins. Maximum voltage on GPIO pin V_DDIO V_DDA

17. Guaranteed by design, not production tested.

.

18. The current consumption of additional peripherals that are implemented only in programmed logic blocks can be found in their respective datasheets, available in

PSoC Creator, the integrated design environment. To estimate total current, find CPU current at frequency of interest and add peripheral currents for your particular

system from the device datasheet and component datasheets.

19. Based on device characterization (Not production tested).

Document Number: 001-84934 Rev. *K

Page 66 of 126

PSoC^®5LP: CY8C54LP Family

Datasheet

Table 11-2. DC Specifications (continued)

Parameter

Description

[21]

Conditions

Min

Typ

Max

Units

[20]

I

Sleep Mode

DD

V

= V

=

T = –40 °C

T = 25 °C

T = 85 °C

T = –40 °C

T = 25 °C

T = 85 °C

T = –40 °C

T = 25 °C

T = 85 °C

T = 25 °C

–

1.9

2.4

5

3.1

3.6

16

µA

DD

DDIO

CPU = OFF

4.5–5.5 V

RTC = ON (= ECO32K ON, in low-power

mode)

[22]

Sleep timer = ON (= ILO ON at 1 kHz)

V

= V

1.7

2

3.1

3.6

16

DD

DDIO

WDT = OFF

2.7–3.6 V

2

I C Wake = OFF

Comparator = OFF

POR = ON

4.2

1.6

1.9

4.2

3

V

= V

3.1

3.6

16

Boost = OFF

DD

DDIO

1.71–1.95 V

SIO pins in single ended input, unregu-

lated output mode

Comparator = ON

CPU = OFF

V

= V

4.2

µA

DD

DDIO

[23]

2.7–3.6 V

RTC = OFF

Sleep timer = OFF

WDT = OFF

I2C Wake = OFF

POR = ON

Boost = OFF

SIO pins in single ended input, unregu-

lated output mode

I2C Wake = ON

CPU = OFF

V

= V

=

T = 25 °C

–

1.7

3.6

µA

DD

DDIO

[23]

2.7–3.6 V

RTC = OFF

Sleep timer = OFF

WDT = OFF

Comparator = OFF

POR = ON

Boost = OFF

SIO pins in single ended input, unregu-

lated output mode

Hibernate Mode

V

= V

=

T = –40 °C

T = 25 °C

T = 85 °C

T = –40 °C

T = 25 °C

T = 85 °C

T = –40 °C

T = 25 °C

T = 85 °C

–

0.2

0.24

2.6

0.11

0.3

2

µA

DD

DDIO

4.5–5.5 V

Hibernate mode current

All regulators and oscillators off.

SRAM retention

GPIO interrupts are active

Boost = OFF

SIO pins in single ended input, unregu-

lated output mode

15

2

V

= V

DDIO

DD

2.7–3.6 V

2

15

2

V

= V

0.9

0.11

1.8

0.3

1.4

1.1

0.7

15

DD

DDIO

1.71–1.95 V

2

15

0.6

3.3

3.1

21

[23]

I

Analog current consumption while device V

 3.6 V

 3.6 V

 3.6 V

 3.6 V

mA

DDAR

DDA

DDD

is reset

V

Digital current consumption while device is V

reset

DDDR

V

[23]

Current consumption while device

programming. Sum of digital, analog, and

I/Os: IDDD + IDDA + IDDIOX

DD_PROG

Notes

20. The current consumption of additional peripherals that are implemented only in programmed logic blocks can be found in their respective datasheets, available in

PSoC Creator, the integrated design environment. To estimate total current, find CPU current at frequency of interest and add peripheral currents for your particular

system from the device datasheet and component datasheets.

21. If V_CCDand V_CCAare externally regulated, the voltage difference between V_CCDand V_CCAmust be less than 50 mV.

22. Sleep timer generates periodic interrupts to wake up the CPU. This specification applies only to those times that the CPU is off.

23. Based on device characterization (Not production tested).

Document Number: 001-84934 Rev. *K

Page 67 of 126

PSoC^®5LP: CY8C54LP Family

Datasheet

Figure 11-1. Active Mode Current vs F_CPU, V_DD= 3.3 V,

Temperature = 25 °C

Figure 11-2. I_DDvs Frequency at 25 °C

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

25

20

15

10

5

ꢀꢁꢂꢃꢄ<ꢂJQJRꢅꢆꢇꢂIQꢈV

0

20

40

60

80

0

20

40

60

80

Bus Clock, MHz

CPU Frequency, MHz

Figure 11-3. Active Mode Current vs Temperature and F_CPU

,

Figure 11-4. Active Mode Current vs V_DDand Temperature,

V_DD= 3.3 V

F_CPU= 24 MHz

10

8

25

20

15

10

5

105 °C

25 °C

80 MHz

24 MHz

6 MHz

6

-40 °C

4

2

0

1.5

2

2.5

3

3.5

4

4.5

5

5.5

-40

-20

0

20

40

60

80

100

V_DD, V

Temperature, °C

Table 11-3. AC Specifications

Parameter

Description

Conditions

Min

DC

–

Typ

Max

Units

F_CPU

CPU frequency

Bus frequency

V_DDramp rate

1.71 V  V_DDD 5.5 V

–

80.01 MHz

F_BUSCLK

[24]

S_VDD

0.066

10

V/µs

µs

[24]

T_{IO_INIT}

Time from V_DDD/V_DDA/V_CCD/V_CCAIPOR to

I/O ports set to their reset states

–

[24]

T_STARTUP

Time from V_DDD/V_DDA/V_CCD/V_CCA PRES to V_CCA/V_DDA= regulated from

CPU executing code at reset vector

–

33

66

µs

V_DDA/V_DDD, no PLL used, fast IMO

boot mode (48 MHz typ.)

_CCA/V_CCD= regulated from

V_DDA/V_DDD, no PLL used, slow

IMO boot mode (12 MHz typ.)

V

[24]

T_SLEEP

Wakeup from sleep mode –

25

Application of non-LVD interrupt to beginning

of execution of next CPU instruction

[24]

T_HIBERNATE

Wakeupformhibernatemode–Applicationof

external interrupt to beginning of execution of

next CPU instruction

150

Note

24. Based on device characterization (Not production tested).

Document Number: 001-84934 Rev. *K

Page 68 of 126

PSoC^®5LP: CY8C54LP Family

Datasheet

11.3 Power Regulators

Specifications are valid for –40 °C  T_A 85 °C and T_J 100 °C, except where noted. Specifications are valid for 1.71 V to 5.5 V,

except where noted.

11.3.1 Digital Core Regulator

Table 11-1. Digital Core Regulator DC Specifications

Parameter

V_DDD

V_CCD

Description

Input voltage

Conditions

Min

1.8

–

Typ

–

Max

5.5

–

Units

V

Output voltage

1.80

1

V

Regulator output capacitor

±10%, X5R ceramic or better. The two V_CCD

pins must be shorted together, with as short

a trace as possible, see Power System on

page 27

0.9

1.1

µF

Figure 11-5. Analog and Digital Regulators, V_CCvs V_DD

,

Figure 11-5.Digital Regulator PSRR vs Frequency and V_DD

10 mA Load

100

80

60

Vdd=4.5V

Vdd=3.6V

Vdd=2.7V

40

20

0

0.1

1

10

Frequency, kHz

100

1000

11.3.2 Analog Core Regulator

Table 11-6. Analog Core Regulator DC Specifications

Parameter

V_DDA

V_CCA

Description

Input voltage

Conditions

Min

1.8

–

Typ

Max

5.5

–

Units

V

–

1.80

1

Output voltage

V

Regulator output capacitor

±10%, X5R ceramic or better

0.9

1.1

µF

Figure 11-6.Analog Regulator PSRR vs Frequency and V_DD

100

80

60

40

20

0

Vdd=4.5V

Vdd=3.6V

Vdd=2.7V

0.1

1

10

Frequency, KHz

100

1000

Document Number: 001-84934 Rev. *K

Page 69 of 126

PSoC^®5LP: CY8C54LP Family

Datasheet

11.3.3 Inductive Boost Regulator

Unless otherwise specified, operating conditions are: V_BAT= 0.5 V–3.6 V, V_OUT= 1.8 V–5.0 V, I_OUT= 0 mA–50 mA,

L_BOOST= 4.7 µH–22 µH, C_BOOST= 22 µF || 3 × 1.0 µF || 3 × 0.1 µF, C_BAT= 22 µF, I_F= 1.0 A, excludes 99-pin CSP package. For

information on using boost with 99-pin CSP package please contact Cypress support. Unless otherwise specified, all charts and

graphs show typical values.

Table 11-7. Inductive Boost Regulator DC Specifications

Parameter

Description

Conditions

Min

1.71

Typ

Max

1.89

Units

Boost output voltage^[25]

V_OUT

vsel = 1.8 V in register BOOST_CR0

vsel = 1.9 V in register BOOST_CR0

vsel = 2.0 V in register BOOST_CR0

vsel = 2.4 V in register BOOST_CR0

vsel = 2.7 V in register BOOST_CR0

vsel = 3.0 V in register BOOST_CR0

vsel = 3.3 V in register BOOST_CR0

vsel = 3.6 V in register BOOST_CR0

vsel = 5.0 V in register BOOST_CR0

1.8

V

1.81

1.90

2.16

2.43

2.70

2.97

3.24

4.50

0.5

1.90

2.00

2.40

2.70

3.00

3.30

3.60

5.00

–

2.00

2.10

2.64

2.97

3.30

3.63

3.96

5.50

0.8

Input voltage to boost^[26]

V_BAT

I_OUT= 0 mA–5 mA vsel = 1.8 V–2.0 V,

T_A= 0 °C–70 °C

I_OUT= 0 mA–15 mA vsel = 1.8 V–5.0 V^[27]

T_A= –10 °C–85 °C

,

1.6

0.8

1.8

1.3

2.5

–

3.6

1.6

2.5

3.6

V

I_OUT= 0 mA–25 mA vsel = 1.8 V–2.7 V,

T_A= –10 °C–85 °C

I

_OUT= 0 mA–50 mA vsel = 1.8 V–3.3 V^[27]

T_A= –40 °C–85 °C

,

vsel = 1.8 V–3.3 V^[27]

T_A= –10 °C–85 °C

vsel = 2.5 V–5.0 V^[27]

T_A= –10 °C–85 °C

I_OUT

Output current

T_A= 0 °C–70 °C

V_BAT= 0.5 V–0.8 V

0

–

5

mA

T_A= –10 °C–85 °C V_BAT= 1.6 V–3.6 V

15

25

50

V_BAT= 0.8 V–1.6 V

V_BAT= 1.3 V–2.5 V

V_BAT= 2.5 V–3.6 V

T_A= –40 °C–85 °C V_BAT= 1.8 V–2.5 V

I_LPK

I_Q

Inductor peak current

Quiescent current

–

700

Boost active mode

–

250

25

–

µA

Boost sleep mode, I_OUT< 1 µA

Reg_LOAD

Reg_LINE

Load regulation

Line regulation

–

10

%

Notes

25. Listed vsel options are characterized. Additional vsel options are valid and guaranteed by design.

26. The boost will start at all valid V_BATconditions including down to V_BAT= 0.5 V.

27. If V_BATis greater than or equal to V_OUTboost setting, then V_OUTwill be less than V_BATdue to resistive losses in the boost circuit.

Document Number: 001-84934 Rev. *K

Page 70 of 126

PSoC^®5LP: CY8C54LP Family

Datasheet

Table 11-8. Recommended External Components for Boost Circuit

Parameter Description Conditions

L_BOOSTBoost inductor

Min

3.7

Typ

4.7

Max

5.7

Units

µH

4.7 µH nominal

10 µH nominal

22 µH nominal

8.0

10.0

22.0

26.0

12.0

27.0

31.0

µH

17.0

µH

C_BOOST

Total capacitance sum of

V_DDD, V_DDA, V_DDIO

µF

[28]

C_BAT

I_F

Battery filter capacitor

17.0

1.0

22.0

–

27.0

–

µF

A

Schottky diode average

forward current

V_R

Schottky reverse voltage

20.0

–

V

Figure 11-7.T_Arange over V_BATand V_OUT

Figure 11-8.I_OUTrange over V_BATand V_OUT

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ꢀ

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Figure 11-9.L_BOOSTvalues over V_BATand V_OUT

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Note

28. Based on device characterization (Not production tested).

Document Number: 001-84934 Rev. *K

Page 71 of 126

PSoC^®5LP: CY8C54LP Family

Datasheet

[29]

Figure 11-10.Efficiency vs V_BAT, L_BOOST= 4.7 µH

Figure 11-11.Efficiency vs V_BAT, L_BOOST= 10 µH

100%

95%

90%

85%

80%

Vout = 1.8 V

Vout = 2.4 V

Vout = 3.3 V

Vout = 5.0 V

95%

90%

85%

80%

75%

70%

65%

60%

55%

50%

Vout = 1.8 V

75%

Vout = 2.4 V

Vout = 3.3 V

Vout = 5.0 V

70%

65%

60%

55%

50%

0

0.5

1

1.5

2

2.5

3

3.5

4

0

0.5

1

1.5

2

2.5

3

3.5

4

V_BAT, V

[29]

Figure 11-12.Efficiency vs V_BAT, L_BOOST= 22 µH

Figure 11-13.V_RIPPLEvs V_BAT

100%

95%

90%

85%

80%

Vout = 1.8 V

Vout = 2.4 V

Vout = 3.3 V

75%

70%

65%

60%

55%

50%

0

0.5

1

1.5

2

2.5

3

3.5

4

V_BAT, V

Note

29. Typical example. Actual values may vary depending on external component selection, PCB layout, and other design parameters.

Document Number: 001-84934 Rev. *K

Page 72 of 126

PSoC^®5LP: CY8C54LP Family

Datasheet

11.4 Inputs and Outputs

Specifications are valid for –40 °C  T_A 85 °C and T_J 100 °C, except where noted. Specifications are valid for 1.71 V to 5.5 V,

except where noted. Unless otherwise specified, all charts and graphs show typical values.

When the power supplies ramp up, there are low-impedance connections between each GPIO pin and its V_DDIOsupply. This causes

the pin voltages to track V_DDIOuntil both V_DDIOand V_DDAreach the IPOR voltage, which can be as high as 1.45 V. At that point the

low-impedance connections no longer exist, and the pins change to their normal NVL settings.

Also, if V_DDAis less than V_DDIO, a low-impedance path may exist between a GPIO and V_DDA, causing the GPIO to track V_DDAuntil

V_DDAbecomes greater than or equal to V_DDIO.

11.4.1 GPIO

Table 11-9. GPIO DC Specifications

Parameter

V_IH

Description

Input voltage high threshold

Input voltage low threshold

Conditions

Min

0.7  V_DDIO

–

Typ

–

Max

Units

CMOS Input, PRT[x]CTL = 0

–

V

V_IL

V_IH

V_IL

V_OH

–

0.3 

V_DDIO

Input voltage high threshold

Input voltage low threshold

Output voltage high

LVTTL Input, PRT[x]CTL= 1,V_DDIO0.7 x V_DDIO

< 2.7 V

–

V

LVTTL Input, PRT[x]CTL = 1,

V_DDIO 2.7 V

2.0

LVTTL Input, PRT[x]CTL= 1,V_DDIO

< 2.7 V

–

0.3 x

V_DDIO

LVTTL Input, PRT[x]CTL = 1,

V_DDIO 2.7 V

–

0.8

I_OH= 4 mA at 3.3 V_DDIO

V_DDIO– 0.6

–

V

I

_OH= 1 mA at 1.8 V_DDIO

V_DDIO– 0.5

–

V_OL

Output voltage low

I_OL= 8 mA at 3.3 V_DDIO

I_OL= 3 mA at 3.3 V_DDIO

–

0.6

0.4

0.6

8.5

2

V

–

V

I

_OL= 4 mA at 1.8 V_DDIO

–

V

Rpullup

Rpulldown

I_IL

Pull-up resistor

3.5

–

5.6

–

k

nA

Pull-down resistor

Input leakage current (absolute

value)^[30]

25 °C, V_DDIO= 3.0 V

C_IN

Input capacitance^[30]

P0.0, P0.1, P0.2, P3.6, P3.7

P0.3, P0.4, P3.0, P3.1, P3.2

P0.6, P0.7, P15.0, P15.6, P15.7^[31]

All other GPIOs

–

17

10

7

20

15

12

9

pF

mV

5

V_H

Input voltage hysteresis

(Schmitt-Trigger)^[30]

40

–

Idiode

Current through protection diode to

V_DDIOand V_SSIO

–

100

µA

Rglobal

Rmux

Resistance pin to analog global bus 25 °C, V_DDIO= 3.0 V

Resistance pin to analog mux bus 25 °C, V_DDIO= 3.0 V

–

320

220

–



Notes

30. Based on device characterization (Not production tested).

31. For information on designing with PSoC oscillators, refer to the application note, AN54439 - PSoC^®3 and PSoC 5 External Oscillator.

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Datasheet

Figure 11-14.GPIO Output High Voltage and Current

Figure 11-15.GPIO Output Low Voltage and Current

[32]

Table 11-10. GPIO AC Specifications

Parameter

TriseF

Description

Conditions

Min

–

Typ

–

Max

6

Units

ns

Rise time in Fast Strong Mode

Fall time in Fast Strong Mode

Rise time in Slow Strong Mode

Fall time in Slow Strong Mode

GPIO output operating frequency

3.3 V V_DDIOCload = 25 pF

TfallF

TriseS

TfallS

–

6

ns

–

60

ns

–

ns

2.7 V < V_DDIO< 5.5 V, fast strong 90/10% V_DDIOinto 25 pF

drive mode

–

33

20

7

MHz

1.71 V < V_DDIO< 2.7 V, fast strong 90/10% V_DDIOinto 25 pF

drive mode

Fgpioout

Fgpioin

3.3 V < V_DDIO< 5.5 V, slow strong 90/10% V_DDIOinto 25 pF

drive mode

1.71 V < V_DDIO< 3.3 V, slow strong 90/10% V_DDIOinto 25 pF

drive mode

3.5

33

GPIO input operating frequency

90/10% V_DDIO

Note

32. Based on device characterization (Not production tested).

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Datasheet

11.4.2 SIO

Table 11-11. SIO DC Specifications

Parameter

Vinmax

Description

Conditions

Min

Typ

Max

Units

Maximum input voltage

All allowed values of V_DDIOand

V_DDD, see Section 11.1

–

5.5

V

Vinref

Input voltage reference (Differential

input mode)

0.5

–

0.52 V_DDIO

V

Output voltage reference (Regulated output mode)

V_DDIO> 3.7

Voutref

1

–

V_DDIO– 1

V

V_DDIO< 3.7

V_DDIO– 0.5

Input voltage high threshold

GPIO mode

Differential input mode^[33]

Input voltage low threshold

GPIO mode

V_IH

CMOS input

0.7  V_DDIO

SIO_ref + 0.2

–

V

Hysteresis disabled

V_IL

CMOS input

–

0.3 V_DDIO

SIO_ref – 0.2

V

Differential input mode^[33]

Output voltage high

Unregulated mode

Hysteresis disabled

I_OH= 4 mA, V_DDIO= 3.3 V

I_OH= 1 mA

V_DDIO– 0.4

–

V

V_OH

Regulated mode^[33]

SIO_ref – 0.65

SIO_ref + 0.2

I_OH= 0.1 mA

SIO_ref – 0.3

–

SIO_ref + 0.2

V

no load, I_OH= 0

SIO_ref – 0.1

–

SIO_ref + 0.1

V

Output voltage low

V_DDIO= 3.30 V, I_OL= 25 mA

V_DDIO= 3.30 V, I_OL= 20 mA

V_DDIO= 1.80 V, I_OL= 4 mA

–

0.8

0.4

8.5

V

V_OL

–

V

–

V

Rpullup

Rpulldown

I_IL

Pull-up resistor

3.5

5.6

k

Pull-down resistor

Input leakage current (absolute

value)^[34]

V_IH< V_DDSIO

25 °C, V_DDSIO= 3.0 V, V_IH= 3.0 V

25 °C, V_DDSIO= 0 V, V_IH= 3.0 V

–

14

10

9

nA

µA

pF

V_IH> V_DDSIO

Input capacitance^[34]

C_IN

V_H

–

Input voltage hysteresis

(Schmitt-Trigger)^[34]

Single ended mode (GPIO mode)

Differential mode

115

50

–

mV

µA

–

Current through protection diode to

V_SSIO

100

Idiode

Notes

33. See Figure 6-4. on page 35 and Figure 6-7. on page 38 for more information on SIO reference.

34. Based on device characterization (Not production tested).

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Datasheet

Figure 11-16.SIO Output High Voltage and Current,

Unregulated Mode

Figure 11-17.SIO Output Low Voltage and Current,

Unregulated Mode

Figure 11-18.SIO Output High Voltage and Current, Regulat-

ed Mode

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Datasheet

[35]

Table 11-12. SIO AC Specifications

Parameter

TriseF

Description

Conditions

Min

Typ

Max

Units

Rise time in Fast Strong Mode

(90/10%)

Cload = 25 pF, V_DDIO= 3.3 V

–

12

ns

TfallF

TriseS

TfallS

Fall time in Fast Strong Mode

(90/10%)

Cload = 25 pF, V_DDIO= 3.3 V

Cload = 25 pF, V_DDIO= 3.0 V

–

12

75

60

ns

Rise time in Slow Strong Mode

(90/10%)

Fall time in Slow Strong Mode

(90/10%)

SIO output operating frequency

2.7 V < V_DDIO< 5.5 V, Unregulated 90/10% V_DDIOinto 25 pF

output (GPIO) mode, fast strong

drive mode

–

33

16

5

MHz

1.71 V < V_DDIO< 2.7 V, Unregu-

lated output (GPIO) mode, fast

strong drive mode

90/10% V_DDIOinto 25 pF

3.3 V < V_DDIO< 5.5 V, Unregulated 90/10% V_DDIOinto 25 pF

output (GPIO) mode, slow strong

drive mode

Fsioout

1.71 V < V_DDIO< 3.3 V, Unregu-

lated output (GPIO) mode, slow

strong drive mode

90/10% V_DDIOinto 25 pF

4

2.7 V < V_DDIO< 5.5 V, Regulated Output continuously switching

output mode, fast strong drive mode into 25 pF

–

20

10

MHz

1.71 V < V_DDIO< 2.7 V, Regulated Output continuously switching

output mode, fast strong drive mode into 25 pF

1.71 V < V_DDIO< 5.5 V, Regulated Output continuously switching

2.5

output mode, slow strong drive

mode

into 25 pF

SIO input operating frequency

1.71 V < V_DDIO< 5.5 V

Fsioin

90/10% V_DDIO

–

33

MHz

Figure 11-19.SIO Output Rise and Fall Times, Fast Strong

Mode, V_DDIO= 3.3 V, 25 pF Load

Figure 11-20.SIO Output Rise and Fall Times, Slow Strong

Mode, V_DDIO= 3.3 V, 25 pF Load

Note

35. Based on device characterization (Not production tested).

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Datasheet

[36]

Table 11-13. SIO Comparator Specifications

Parameter

Description

Offset voltage

Conditions

Min

Typ

Max

Units

Vos

V_DDIO= 2 V

–

68

72

mV

V_DDIO= 2.7 V

V_DDIO= 5.5 V

82

TCVos

CMRR

Offset voltage drift with temp

Common mode rejection ratio

250

μV/°C

V

_DDIO= 2 V

_DDIO= 2.7 V

_DDIO= 5.5 V

30

35

40

–

dB

V

–

Tresp

Response time

30

ns

11.4.3 USBIO

For operation in GPIO mode, the standard range for V_DDDapplies, see Device Level Specifications on page 66.

Table 11-14. USBIO DC Specifications

Parameter

Rusbi

Description

USB D+ pull-up resistance^[36]

Static output high^[36]

Static output low^[36]

Input voltage high, GPIO mode^[36]

Conditions

Min

0.900

1.425

2.8

–

Typ

–

Max Units

With idle bus

1.575

3.090

3.6

0.3

–

k

V

Rusba

While receiving traffic

15 k ±5% to Vss, internal pull-up enabled

V_DDD= 1.8 V

–

Vohusb

Volusb

–

V

Vihgpio

1.5

2

–

V

V_DDD= 3.3 V

–

V

V_DDD= 5.0 V

2

–

V

Vilgpio

Input voltage low, GPIO mode^[36]

Output voltage high, GPIO mode^[36]

Output voltage low, GPIO mode^[36]

V_DDD= 1.8 V

–

0.8

–

V

V_DDD= 3.3 V

–

V

V_DDD= 5.0 V

–

V

Vohgpio

Volgpio

I_OH= 4 mA, V_DDD= 1.8 V

I_OH= 4 mA, V_DDD= 3.3 V

I_OH= 4 mA, V_DDD= 5.0 V

I_OL= 4 mA, V_DDD= 1.8 V

I_OL= 4 mA, V_DDD= 3.3 V

I_OL= 4 mA, V_DDD= 5.0 V

|(D+)–(D–)|

1.6

3.1

4.2

–

V

–

V

–

V

–

0.3

0.2

2.5

2

V

–

V

–

V

Vdi

Differential input sensitivity

–

V

Vcm

Vse

Differential input common mode range

Single ended receiver threshold

PS/2 pull-up resistance^[36]

0.8

3

–

V

–

V

Rps2

Rext

In PS/2 mode, with PS/2 pull-up enabled

In series with each USB pin

–

7

k



External USB series resistor ^[36]

21.78

(–1%)

22

22.22

(+1%)

Zo

USB driver output impedance^[36]

USB transceiver input capacitance

Including Rext

28

–

44

20

2



C_IN

pF

nA

Input leakage current (absolute

value)^[36]

25 °C, V_DDD= 3.0 V

–

[36]

I_IL

Note

36. Based on device characterization (Not production tested).

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Datasheet

Figure 11-21.USBIO Output High Voltage and Current, GPIO

Mode

Figure 11-22.USBIO Output Low Voltage and Current, GPIO

Mode

[37]

Table 11-15. USBIO AC Specifications

Parameter

Description

Conditions

Min

Typ

Max

Units

Tdrate

Full-speed data rate average bit rate

12 – 0.25%

12

12 +

0.25%

MHz

Tjr1

Tjr2

Receiver data jitter tolerance to next

transition

–8

–5

–

8

5

ns

Receiver data jitter tolerance to pair

transition

Tdj1

Driver differential jitter to next transition

Driver differential jitter to pair transition

–3.5

–4

–

3.5

4

ns

Tdj2

Tfdeop

Source jitter for differential transition to

SE0 transition

–2

5

Tfeopt

Tfeopr

Tfst

Source SE0 interval of EOP

Receiver SE0 interval of EOP

160

82

–

175

–

ns

Width of SE0 interval during differential

transition

14

Fgpio_out GPIO mode output operating frequency 3 V  V_DDD 5.5 V

_DDD= 1.71 V

–

20

6

MHz

ns

V

Tr_gpio

Rise time, GPIO mode, 10%/90% V_DDDV_DDD> 3 V, 25 pF load

V_DDD= 1.71 V, 25 pF load

12

40

12

40

ns

Tf_gpio

Fall time, GPIO mode, 90%/10% V_DDDV_DDD> 3 V, 25 pF load

ns

V_DDD= 1.71 V, 25 pF load

ns

Note

37. Based on device characterization (Not production tested).

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Datasheet

Figure 11-23.USBIO Output Rise and Fall Times, GPIO Mode,

V_DDD= 3.3 V, 25 pF Load

[38]

Table 11-16. USB Driver AC Specifications

Parameter

Tr

Description

Transition rise time

Conditions

Min

–

Typ

–

Max

20

Units

ns

Tf

Transition fall time

–

20

ns

TR

Rise/fall time matching

V_{USB_5}, V_{USB_3.3}, see USB DC

Specifications on page 103

90%

–

111%

Vcrs

Output signal crossover voltage

1.3

–

2

V

11.4.4 XRES

Table 11-17. XRES DC Specifications

Parameter

Description

Input voltage high threshold

Input voltage low threshold

Conditions

Min

0.7  V_DDIO

–

Typ

–

Max

Units

V_IH

V_IL

–

V

–

0.3 

V_DDIO

Rpullup

C_IN

Pull-up resistor

Input capacitance^[38]

3.5

–

5.6

3

8.5

–

k

pF

V_H

Input voltage hysteresis

(Schmitt-Trigger)^[38]

–

100

–

mV

Idiode

Current through protection diode to

V_DDIOand V_SSIO

–

100

µA

[38]

Table 11-18. XRES AC Specifications

Parameter

Description

Reset pulse width

Conditions

Min

Typ

Max

Units

T_RESET

1

–

µs

Note

38. Based on device characterization (Not production tested).

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Datasheet

11.5 Analog Peripherals

Specifications are valid for –40 °C  T_A 85 °C and T_J 100 °C, except where noted. Specifications are valid for 1.71 V to 5.5 V,

except where noted.

11.5.1 Opamp

Table 11-19. Opamp DC Specifications

Parameter

Description

Input voltage range

Input offset voltage

Conditions

Min

V_SSA

–

Typ

–

Max

V_DDA

2.5

Units

mV

V_I

Vos

–

mV

Operating temperature –40 °C to

70 °C

–

2

mV

TCVos

Ge1

Cin

Input offset voltage drift with temperature Power mode = high

–

±30

±0.1

18

µV / °C

Gain error, unity gain buffer mode

Input capacitance

Rload = 1 k

%

pF

V

Routing from pin

Vo

Output voltage range

1 mA, source or sink, power mode V_SSA+ 0.05

= high

V_DDA

0.05

–

Iout

Output current capability, source or sink V_SSA+ 500 mV V_OUT V_DDA

25

–

mA

–500 mV, V_DDA> 2.7 V

V_SSA+ 500 mV  V_OUT V_DDA

–500 mV, 1.7 V = V_DDA 2.7 V

16

–

Idd

Quiescent current^[39]

Power mode = min

Power mode = low

Power mode = med

Power mode = high

–

250

330

1000

–

400

950

2500

–

uA

dB

pA

–

CMRR

PSRR

Common mode rejection ratio^[39]

Power supply rejection ratio^[39]

80

85

70

–

V_DDA 2.7 V

V_DDA< 2.7 V

25 °C

–

I_IB

Input bias current^[39]

10

–

Figure11-1.OpampVosHistogram,7020samples/1755parts,

30 °C, VDDA = 3.3 V

Figure 11-2.Opamp Vos vs Temperature, V_DDA= 5V

0.2

20

18

16

14

12

10

8

0.1

0

6

-0.1

-0.2

4

2

0

-40

-20

0

20

40

60

80

Temperature, °C

Vos, mV

Note

39. Based on device characterization (Not production tested).

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Figure 11-3.Opamp Vos vs Vcommon and V_DDA, 25 °C

Figure 11-4.Opamp Output Voltage vs Load Current and Tem-

perature, High Power Mode, 25 °C, V_DDA= 2.7 V

0.3

0.25

0.2

3

2.5

2

Vdda = 5.5 V

0.15

0.1

0.05

0

Vin = 2.7 V

Vin = 0 V

Vdda = 2.7 V

Vdda = 1.7 V

1.5

1

0.5

0

1

2

3

4

5

6

Vcommon, V

0

5

10

15

20

25

Iload, Source / Sink, mA

Figure 11-5.Opamp Operating Current vs V_DDAand Power

Mode

1

0.8

0.6

0.4

0.2

0

1

2

3

V_DDA, V

4

5

High Power Mode

Medium

Low, Minimum

[40]

Table 11-20. Opamp AC Specifications

Parameter

Description

Conditions

Min

1

Typ

–

Max

–

Units

MHz

V/µs

GBW

Gain-bandwidth product

Power mode = minimum, 15 pF load

Power mode = low, 15 pF load

2

–

Power mode = medium, 200 pF load

Power mode = high, 200 pF load

Power mode = minimum, 15 pF load

Power mode = low, 15 pF load

1

–

3

–

SR

e_n

Slew rate, 20% - 80%

Input noise density

1.1

0.9

3

–

Power mode = medium, 200 pF load

Power mode = high, 200 pF load

–

Power mode = high, V_DDA= 5 V, at

100 kHz

–

45

–

nV/sqrtHz

Note

40. Based on device characterization (Not production tested).

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Datasheet

Figure 11-6.Opamp Noise vs Frequency, Power Mode = High,

V_DDA= 5 V

Figure 11-7.Opamp Step Response, Rising

1.2

1

1000

100

10

0.8

0.6

0.4

0.2

0

Input

Output

-1

-0.5

0

0.5

1

0.01

0.1

1

10

100

1000

Time, μs

Frequency, kHz

Figure 11-8.Opamp Step Response, Falling

1.2

1

0.8

0.6

0.4

0.2

0

Input

Output

-1

-0.5

0

0.5

1

Time, μs

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Datasheet

11.5.2 Delta-Sigma ADC

Unless otherwise specified, operating conditions are:

■ Operation in continuous sample mode

■ fclk = 6.144 MHz

■ Reference = 1.024 V internal reference bypassed on P3.2 or P0.3

■ Unless otherwise specified, all charts and graphs show typical values

Table 11-21. 12-bit Delta-sigma ADC DC Specifications

Parameter

Description

Conditions

Min

Typ

Max

Units

Resolution

8

–

12

bits

No. of

GPIO

Number of channels, single ended

–

Differential pair is formed using a

pair of GPIOs.

No. of

GPIO/2

Number of channels, differential

Monotonic

–

Yes

–

Buffered, buffer gain = 1,

Range = ±1.024 V, 25 °C

Ge

Gd

Gain error

±0.4

%

Buffered, buffer gain = 1,

Range = ±1.024 V

ppm/°

C

Gain drift

–

50

Buffered, 16-bit mode, full voltage

range

±0.2

±0.1

mV

Vos

Input offset voltage

Buffered, 16-bit mode,

V_DDA= 1.8 V ±5%, 25 °C

Temperature coefficient, input offset

voltage

Input voltage range, single ended^[41]

Buffer gain = 1, 12-bit,

Range = ±1.024 V

TCVos

–

1

µV/°C

V_SSA

V_DDA

V

Input voltage range, differential unbuf-

fered^[41]

Input voltage range, differential,

V_SSA

–

V_DDA– 1

V

buffered^[41]

INL12

DNL12

INL8

Integral non linearity^[41]

Differential non linearity^[41]

Integral non linearity^[41]

Differential non linearity^[41]

ADC input resistance

Range = ±1.024 V, unbuffered

Input buffer used

–

±1

–

LSB

M

–

DNL8

–

Rin_Buff

10

Inputbufferbypassed, 12bit, Range

= ±1.024 V

Rin_ADC12 ADC input resistance

–

148^[42]

–

k

Rin_ExtRef ADC external reference input resistance

ADCexternalreferenceinputvoltage, see

70^{[42, 43]}

Vextref

also internal reference in Voltage

Reference on page 86

Pins P0[3], P3[2]

0.9

–

1.3

V

Current Consumption

I_{DD_12}

Current consumption, 12 bit^[41]

I_BUFF

Buffer current consumption^[41]

192 ksps, unbuffered

–

1.4

2.5

mA

Notes

41. Based on device characterization (not production tested).

42. By using switched capacitors at the ADC input an effective input resistance is created. Holding the gain and number of bits constant, the resistance is proportional to

the inverse of the clock frequency. This value is calculated, not measured. For more information see the Technical Reference Manual.

43. Recommend an external reference device with an output impedance <100 ꢀ, for example, the LM185/285/385 family. A 1 µF capacitor is recommended. For more

information, see AN61290 - PSoC® 3 and PSoC 5LP Hardware Design Considerations.

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Datasheet

Table 11-22. Delta-sigma ADC AC Specifications

Parameter

Description

Conditions

Min

–

Typ

–

Max

4

Units

Samples

%

Startup time

Total harmonic distortion^[44]

THD

Buffer gain = 1, 12-bit,

Range = ±1.024 V

–

0.0032

12-Bit Resolution Mode

SR12

BW12

Sample rate, continuous, high power^[44]

Input bandwidth at max sample rate^[44]

Range = ±1.024 V, unbuffered

4

–

44

–

192

–

ksps

kHz

dB

SINAD12int Signal to noise ratio, 12-bit, internal reference^[44]

Range = ±1.024 V, unbuffered 66

–

8-Bit Resolution Mode

SR8

Sample rate, continuous, high power^[44]

Input bandwidth at max sample rate^[44]

Range = ±1.024 V, unbuffered

8

–

88

–

384

–

ksps

kHz

dB

BW8

SINAD8int Signal to noise ratio, 8-bit, internal reference^[44]

Range = ±1.024 V, unbuffered 43

–

Table 11-23. Delta-sigma ADC Sample Rates, Range = ±1.024 V

Continuous

Multi-Sample

Resolution,

Bits

Min

Max

Min

1911

1543

1348

1154

978

Max

8

8000

6400

5566

4741

4000

384000

307200

267130

227555

192000

91701

74024

64673

55351

46900

9

10

11

12

Figure 11-9.Delta-sigma ADC IDD vs sps, Range = ±1.024 V,

Continuous Sample Mode, Input Buffer Bypassed

2

1.5

1

0.5

0

1

10

100

Sample Rate, Ksps

Note

44. Based on device characterization (Not production tested).

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Datasheet

11.5.3 Voltage Reference

Table 11-24. Voltage Reference Specifications

Parameter

Description

Conditions

Min

Typ

Max

Units

V_REF

Precision reference voltage

Initial trimming, 25 °C

1.013

(–1%)

1.024

1.035

(+1%)

V

11.5.3 SAR ADC

Table 11-25. SAR ADC DC Specifications

Parameter

Description

Conditions

Min

Typ

Max

Units

Resolution

–

12

bits

Number of channels – single-ended

No of

GPIO

Number of channels – differential

Differential pair is formed using a

pair of neighboring GPIO.

–

No of

GPIO/2

Monotonicity^[45]

Gain error^[46]

Yes

–

±0.1

±2

Ge

External reference

%

mV

mA

V

V_OS

I_DD

Input offset voltage

–

Current consumption^[45]

Input voltage range – single-ended^[45]

Input voltage range – differential^[45]

Power supply rejection ratio^[45]

Common mode rejection ratio

Integral non linearity^[46]

–

1

V_SSA

70

–

V_DDA

–

V

PSRR

CMRR

INL

dB

LSB

–

V_DDA1.71 to 5.5 V, 1 Msps, V_REF

to 5.5 V, bypassed at ExtRef pin

1

+2/–1.5

V_DDA2.0 to 3.6 V, 1 Msps, V_REF

to V_DDA, bypassed at ExtRef pin

2

–

±1.2

±1.3

LSB

V_DDA1.71 to 5.5 V, 500 ksps, V_REF

1 to 5.5 V, bypassed at ExtRef pin

DNL

Differential non linearity^[46]

V_DDA1.71 to 5.5 V, 1 Msps, V_REF

to 5.5 V, bypassed at ExtRef pin

1

+2/–1

V_DDA2.0 to 3.6 V, 1 Msps, V_REF

to V_DDA, bypassed at ExtRef pin

No missing codes

2

1.7/–0.99

V_DDA1.71 to 5.5 V, 500 ksps, V_REF

1 to 5.5 V, bypassed at ExtRef pin

No missing codes

–

+2/–0.99

–

LSB

R_IN

Input resistance^[46]

180

kꢀ

Notes

45. Based on device characterization (Not production tested).

46. For total analog system Idd < 5 mA, depending on package used. With higher total analog system currents it is recommended that the SAR ADC be used in differential

mode.

Document Number: 001-84934 Rev. *K

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Datasheet

Figure 11-10.SAR ADC DNL vs Output Code,

Bypassed Internal Reference Mode

Figure 11-11.SAR ADC INL vs Output Code,

Bypassed Internal Reference Mode

1

0.5

0

0.5

0

-0.5

-1

-2048

0

2048

-2048

0

2048

Code (12 bit)

Figure 11-12.SAR ADC I_DDvs sps, V_DDA= 5 V, Continuous

Sample Mode, External Reference Mode

0.5

0.4

0.3

0.2

0.1

0

250

500

750

1000

Sample Rate, ksps

[47]

Table 11-26. SAR ADC AC Specifications

Parameter

Description

Conditions

Min

Typ

Max

Units

A_SAMP_1

Sample rate with external reference

bypass cap

–

1

Msps

A_SAMP_2

A_SAMP_3

Sample rate with no bypass cap.

Reference = V_DD

–

500

100

Ksps

Sample rate with no bypass cap.

Internal reference

Startup time

–

68

–

10

–

µs

dB

%

SINAD

THD

Signal-to-noise ratio

Total harmonic distortion

0.02

Note

47. Based on device characterization (Not production tested).

Document Number: 001-84934 Rev. *K

Page 87 of 126

PSoC^®5LP: CY8C54LP Family

Datasheet

Figure 11-13.SAR ADC Noise Histogram, 100 ksps, Internal

Reference No Bypass

Figure 11-14.SAR ADC Noise Histogram, 1 msps, Internal

Reference Bypassed

100

80

60

40

20

0

100

80

60

40

20

0

Counts, 12 bit

Figure 11-15.SAR ADC Noise Histogram, 1 msps, External

Reference

100

80

60

40

20

0

Counts, 12 bit

Document Number: 001-84934 Rev. *K

Page 88 of 126

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Datasheet

11.5.4 Analog Globals

Table 11-27. Analog Globals DC Specifications

Parameter

Rppag

Description

Conditions

Min

–

Typ

1500

1200

700

Max

2200

1700

1100

900

Units



Resistance pin-to-pin through P2[4], AGL0, V_DDA= 3.0 V

DSM INP, AGL1, P2[5]^{[48, 49]}

V_DDA= 1.71 V

–

Rppmuxbus

Resistance pin-to-pin through P2[3],

amuxbusL, P2[4]^{[48, 49]}

V_DDA= 3.0 V

V_DDA= 1.71 V

–

600

Table 11-28. Analog Globals AC Specifications

Parameter

Description

Conditions

Min

106

–

Typ

–

Max

–

Units

dB

Inter-pair crosstalk for analog routes^[50]

Analog globals 3 db bandwidth^[50]

BWag

V_DDA= 3.0 V, 25 °C

26

–

MHz

11.5.5 Comparator

[51]

Table 11-29. Comparator DC Specifications

Parameter

Description

Conditions

Min

Typ

Max

Units

Input offset voltage in fast mode

Factory trim, V_DDA> 2.7 V,

Vin  0.5 V

–

10

mV

V_OS

Input offset voltage in slow mode

Factory trim, V_IN 0.5 V

Custom trim

–

9

4

mV

Input offset voltage in fast mode^[48]

Input offset voltage in slow mode^[48]

Input offset voltage in ultra low power mode

–

V_OS

Custom trim

4

mV

V_OS

–

±12

63

15

10

–

mV

TCVos

Temperature coefficient, input offset

voltage

V_CM= V_DDA/ 2, fast mode

–

85

µV/°C

V_CM= V_DDA/ 2, slow mode

–

20

V_HYST

V_ICM

Hysteresis

Hysteresis enable mode

High current / fast mode

Low current / slow mode

Ultra low power mode

–

32

mV

V

Input common mode voltage

V_SSA

V_DDA

–

V

–

V_DDA

1.15

–

V

CMRR

I_CMP

Common mode rejection ratio

High current mode/fast mode^[48]

Low current mode/slow mode^[48]

Ultra low power mode^[48]

–

50

–

dB

µA

400

100

–

6

[51]

Table 11-30. Comparator AC Specifications

Parameter

Description

Response time, high current mode^[48]

Conditions

Min

Typ

Max

Units

50 mV overdrive, measured

pin-to-pin

–

75

110

ns

Response time, low current mode^[48]

50 mV overdrive, measured

pin-to-pin

–

155

55

200

–

ns

µs

T_RESP

Response time, ultra low power mode^[48]50 mV overdrive, measured

pin-to-pin

Notes

48. Based on device characterization (Not production tested).

49. The resistance of the analog global and analog mux bus is high if V_DDA 2.7 V, and the chip is in either sleep or hibernate mode. Use of analog global and analog

mux bus under these conditions is not recommended.

50. Pin P6[4] to del-sig ADC input; calculated, not measured.

51. The recommended procedure for using a custom trim value for the on-chip comparators are found in the TRM.

Document Number: 001-84934 Rev. *K

Page 89 of 126

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Datasheet

11.5.6 Current Digital-to-analog Converter (IDAC)

All specifications are based on use of the low-resistance IDAC output pins (see Pin Descriptions on page 11 for details). See the IDAC

component data sheet in PSoC Creator for full electrical specifications and APIs.

Unless otherwise specified, all charts and graphs show typical values.

Table 11-31. IDAC DC Specifications

Parameter

Description

Conditions

Min

–

Typ

–

Max

8

Units

bits

Resolution

I_OUT

Output current at code = 255

Range = 2.04 mA, code = 255,

V_DDA 2.7 V, Rload = 600 

–

2.04

–

mA

Range = 2.04 mA, High mode,

code = 255, V_DDA 2.7 V, Rload =

300 

–

2.04

–

mA

Range=255µA, code=255, Rload

= 600 

–

255

–

µA

Range = 31.875 µA, code = 255,

31.875

Rload = 600 

Monotonicity

Zero scale error

Gain error

–

0

Yes

±1

Ezs

Eg

LSB

%

Range = 2.04 mA

Range = 255 µA

Range = 31.875 µA

Range = 2.04 mA

Range = 255 µA

Range = 31.875 µA

–

±2.5

±3.5

0.045

0.05

±1

–

%

–

%

TC_Eg

INL

Temperature coefficient of gain

error

–

% / °C

LSB

–

Integral nonlinearity

Sink mode, range = 255 µA, Codes

8–255, Rload = 2.4 k,

Cload = 15 pF

±0.9

Source mode, range = 255 µA,

Codes 8–255, Rload = 2.4 k,

Cload = 15 pF

–

±1.2

±0.9

±0.6

±1.6

±2

LSB

Source mode, range = 31.875 µA,

Codes 8–255, Rload = 20 kꢀ,

Cload = 15 pF^[52]

Sink mode, range = 31.875 µA,

Codes 8–255, Rload = 20 kꢀ,

Cload = 15 pF^[52]

±2

Source mode, range = 2.04 mA,

Codes 8–255, Rload = 600 ꢀ,

Cload = 15 pF^[52]

±2

Sink mode, range = 2.04 mA,

Codes 8–255, Rload = 600 ꢀ,

Cload = 15 pF^[52]

±1

Note

52. Based on device characterization (Not production tested).

Document Number: 001-84934 Rev. *K

Page 90 of 126

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Datasheet

Table 11-31. IDAC DC Specifications (continued)

Parameter

DNL

Description

Conditions

Min

Typ

Max

Units

Differential nonlinearity

Sink mode, range = 255 µA,

Rload = 2.4 k, Cload = 15 pF

–

±0.3

±1

LSB

Source mode, range = 255 µA,

Rload = 2.4 k, Cload = 15 pF

–

1

±0.3

±0.2

–

±1

–

LSB

V

Source mode, range = 31.875 µA,

Rload = 20 kꢀ, Cload = 15 pF^[53]

Sink mode, range = 31.875 µA,

Rload = 20 kꢀ, Cload = 15 pF^[53]

Source mode, range = 2.0 4 mA,

Rload = 600 ꢀ, Cload = 15 pF^[53]

Sink mode, range = 2.0 4 mA,

Rload = 600 ꢀ, Cload = 15 pF^[53]

Vcompliance

I_DD

Dropout voltage, source or sink

mode

Voltage headroom at max current,

Rload to V_DDAor Rload to V_SSA

,

V_DIFFfrom V_DDA

Operating current, code = 0

Slow mode, source mode, range =

31.875 µA

–

44

33

100

500

µA

Slow mode, source mode, range =

255 µA,

Slow mode, source mode, range =

2.04 mA

33

Slow mode, sink mode, range =

31.875 µA

36

Slow mode, sink mode, range =

255 µA

33

Slow mode, sink mode, range =

2.04 mA

33

Fast mode, source mode, range =

31.875 µA

310

305

310

300

Fast mode, source mode, range =

255 µA

Fast mode, source mode, range =

2.04 mA

Fast mode, sink mode, range =

31.875 µA

Fast mode, sink mode, range =

255 µA

Fast mode, sink mode, range =

2.04 mA

Note

53. Based on device characterization (Not production tested).

Document Number: 001-84934 Rev. *K

Page 91 of 126

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Datasheet

Figure 11-1.IDAC INL vs Input Code, Range = 255 µA, Source

Mode

Figure 11-2.IDAC INL vs Input Code, Range = 255 µA, Sink

Mode

1

0.5

0

1

0.5

0

-0.5

-1

-0.5

-1

0

32

64

96

128

160

192

224

256

0

32

64

96

128

160

192

224

256

Code, 8-bit

Figure11-3.IDACDNLvsInputCode, Range=255µA,Source

Mode

Figure 11-4.IDAC DNL vs Input Code, Range = 255 µA, Sink

Mode

0.5

0.25

0

0.5

0.25

0

-0.25

-0.5

-0.25

-0.5

0

32

64

96

128

160

192

224

256

0

32

64

96

128

160

192

224

256

Code, 8-bit

Figure 11-5.IDAC INL vs Temperature, Range = 255 µA, Fast

Mode

Figure 11-6.IDAC DNL vs Temperature, Range = 255 µA, Fast

Mode

0.5

1

Source mode

0.4

Source mode

0.75

Sink mode

0.3

0.5

0.25

0

0.2

0.1

0

-40

-20

0

20

40

60

80

-40

-20

0

20

40

60

80

Temperature, °C

Document Number: 001-84934 Rev. *K

Page 92 of 126

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Datasheet

Figure 11-7.IDAC Full Scale Error vs Temperature,

Range = 255 µA, Source Mode

Figure 11-8.IDAC Full Scale Error vs Temperature,

Range = 255 µA, Sink Mode

1

0.5

0

1

0.5

0

-0.5

-1

-0.5

-1

-40

-20

0

20

40

60

80

-40

-20

0

20

40

60

80

Temperature, °C

Figure 11-9.IDAC Operating Current vs Temperature, Range

= 255 µA, Code = 0, Source Mode

Figure11-10.IDACOperatingCurrentvsTemperature,Range

= 255 µA, Code = 0, Sink Mode

350

300

250

350

300

250

Fast Mode

Slow Mode

Fast Mode

Slow Mode

200

150

200

150

100

50

0

100

50

0

-40

-20

0

20

40

60

80

-40

-20

0

20

40

60

80

Temperature, °C

[54]

Table 11-32. IDAC AC Specifications

Parameter

F_DAC

Description

Update rate

Settling time to 0.5 LSB

Conditions

Range = 31.875 µA, full scale

Min

Typ

–

Max

8

Units

Msps

ns

–

T_SETTLE

–

125

transition, fast mode, 600  15-pF

load

Range = 255 µA, full scale

transition, fast mode, 600  15-pF

load

–

125

–

ns

Current noise

Range=255 µA,sourcemode,fast

mode, V_DDA= 5 V, 10 kHz

340

pA/sqrtHz

Note

54. Based on device characterization (Not production tested).

Document Number: 001-84934 Rev. *K

Page 93 of 126

PSoC^®5LP: CY8C54LP Family

Datasheet

Figure 11-11.IDAC Step Response, Codes 0x40 - 0xC0,

255 µA Mode, Source Mode, Fast Mode, V_DDA= 5 V

Figure 11-12.IDAC Glitch Response, Codes 0x7F - 0x80,

255 µA Mode, Source Mode, Fast Mode, V_DDA= 5 V

134

132

130

128

126

124

122

120

250

200

150

100

50

0

0.5

1

1.5

2

0

0.5

1

1.5

2

Time, μs

Figure 11-13.IDAC PSRR vs Frequency

Figure 11-14.IDAC Current Noise, 255 µA Mode,

Source Mode, Fast Mode, V_DDA= 5 V

10000

1000

100

10

60

50

40

30

20

10

0

0.1

1

10

100

1000

10000

1

Frequency, kHz

0.01

0.1

1

10

100

Frequency, kHz

255 )A, code 0x7F

255 )A, code 0xFF

11.5.7 Voltage Digital to Analog Converter (VDAC)

See the VDAC component datasheet in PSoC Creator for full electrical specifications and APIs.

Unless otherwise specified, all charts and graphs show typical values.

Table 11-33. VDAC DC Specifications

Parameter

Description

Conditions

Min

–

Typ

8

Max

Units

bits

Resolution

–

±2.5

±1

–

INL1

Integral nonlinearity

1 V scale

4 V scale

1 V scale

4 V scale

1 V scale

4 V scale

–

±2.1

±0.3

4

LSB

k

INL4

Integral nonlinearity^[55]

Differential nonlinearity

Differential nonlinearity^[55]

Output resistance

–

DNL1

DNL4

Rout

–

16

–

k

Note

55. Based on device characterization (Not production tested).

Document Number: 001-84934 Rev. *K

Page 94 of 126

PSoC^®5LP: CY8C54LP Family

Datasheet

Table 11-33. VDAC DC Specifications (continued)

Parameter

V_OUT

Description

Conditions

Min

–

Typ

Max

–

Units

Output voltage range, code = 255 1 V scale

1.02

V

4 V scale, V_DDA= 5 V

–

4.08

–

V

Monotonicity

Zero scale error

Gain error

–

Yes

±0.9

±2.5

0.03

100

500

–

V_OS

Eg

–

0

LSB

1 V scale

4 V scale

–

%

–

TC_Eg

I_DD

Temperature coefficient, gain error 1 V scale

4 V scale

–

%FSR / °C

µA

–

Operating current^[56]

Slow mode

Fast mode

–

µA

Figure 11-1.VDAC INL vs Input Code, 1 V Mode

Figure 11-2.VDAC DNL vs Input Code, 1 V Mode

1

0.5

0

0.25

0

-0.5

-1

-0.25

-0.5

0

32

64

96

128

160

192

224

256

0

32

64

96

128

160

192

224

256

Code, 8-bit

Figure 11-3.VDAC INL vs Temperature, 1 V Mode

Figure 11-4.VDAC DNL vs Temperature, 1 V Mode

1

0.5

0.4

0.3

0.2

0.1

0

0.75

0.5

0.25

0

-40

-20

0

20

40

60

80

100

-40

-20

0

20

40

60

80

100

Temperature, °C

Note

56. Based on device characterization (Not production tested).

Document Number: 001-84934 Rev. *K

Page 95 of 126

PSoC^®5LP: CY8C54LP Family

Datasheet

Figure 11-5.VDAC Full Scale Error vs Temperature, 1 V Mode

Figure 11-6.VDAC Full Scale Error vs Temperature, 4 V Mode

2

1

1.5

1

0.75

0.5

0.25

0

0.5

0

-40

-20

0

20

40

60

80

100

-40

-20

0

20

40

60

80

100

Temperature, °C

Figure 11-7.VDAC Operating Current vs Temperature, 1V

Mode, Slow Mode

Figure 11-8.VDAC Operating Current vs Temperature, 1 V

Mode, Fast Mode

400

300

200

100

0

50

40

30

20

10

0

-40

-20

0

20

40

60

80

100

-40

-20

0

20

40

60

80

100

Temperature, °C

[57]

Table 11-34. VDAC AC Specifications

Parameter Description

F_DAC

Conditions

Min

–

Typ

–

Max

1000

250

1

Units

ksps

µs

Update rate

1 V scale

4 V scale

–

TsettleP

TsettleN

Settling time to 0.1%, step 25% to 75% 1 V scale, Cload = 15 pF

4 V scale, Cload = 15 pF

–

0.45

0.8

0.45

0.7

750

–

3.2

1

µs

Settling time to 0.1%, step 75% to 25% 1 V scale, Cload = 15 pF

4 V scale, Cload = 15 pF

–

µs

–

3

µs

Voltage noise

Range = 1 V, fast mode,

V_DDA= 5 V, 10 kHz

–

nV/sqrtHz

Note

57. Based on device characterization (Not production tested).

Document Number: 001-84934 Rev. *K

Page 96 of 126

PSoC^®5LP: CY8C54LP Family

Datasheet

Figure 11-9.VDAC Step Response, Codes 0x40 - 0xC0, 1 V

Mode, Fast Mode, V_DDA= 5 V

Figure 11-10.VDAC Glitch Response, Codes 0x7F - 0x80, 1 V

Mode, Fast Mode, V_DDA= 5 V

0.54

0.52

0.5

1

0.75

0.5

0.25

0

0.48

0

0.5

1

1.5

2

0

0.5

1

1.5

2

Time, μs

Figure 11-11.VDAC PSRR vs Frequency

Figure 11-12.VDAC Voltage Noise, 1 V Mode, Fast Mode,

V_DDA= 5 V

100000

10000

1000

100

50

40

30

20

10

0

0.1

1

10

100

1000

10

Frequency, kHz

0.01

0.1

1

10

100

4 V, code 0x7F

4 V, code 0xFF

Frequency, kHz

Document Number: 001-84934 Rev. *K

Page 97 of 126

PSoC^®5LP: CY8C54LP Family

Datasheet

11.5.8 Mixer

The mixer is created using a SC/CT analog block; see the Mixer component datasheet in PSoC Creator for full electrical specifications

and APIs.

Table 11-35. Mixer DC Specifications

Parameter

V_OS

Description

Input offset voltage

Conditions

Min

Typ

Max

Units

High power mode, V_IN= 1.024 V,

V_REF= 1.024 V

–

15

mV

Quiescent current

Gain

–

0.9

0

2

–

mA

dB

G

[58]

Table 11-36. Mixer AC Specifications

Parameter Description

f_LO

Conditions

Down mixer mode

Up mixer mode

Min

–

Typ

–

Max

4

Units

MHz

V/µs

Local oscillator frequency

Input signal frequency

Local oscillator frequency

Input signal frequency

Slew rate

f_in

f_LO

f_in

–

14

1

–

Up mixer mode

–

1

SR

3

–

11.5.9 Transimpedance Amplifier

The TIA is created using a SC/CT analog block; see the TIA component datasheet in PSoC Creator for full electrical specifications

and APIs.

Table 11-37. Transimpedance Amplifier (TIA) DC Specifications

Parameter

V_IOFF

Description

Input offset voltage

Conditions

Min

Typ

Max

Units

–

10

mV

Conversion resistance^[59]

R = 20K

40 pF load

–25

–

+35

2

%

R = 30K

R = 40K

–

%

Rconv

R = 80K

–

%

R = 120K

–

%

R = 250K

–

%

R= 500K

–

%

R = 1M

Quiescent current^[58]

–

%

1.1

mA

[58]

Table 11-38. Transimpedance Amplifier (TIA) AC Specifications

Parameter

BW

Description

Conditions

Min

Typ

Max

Units

Input bandwidth (–3 dB)

R = 20K; –40 pF load

1200

–

kHz

R = 120K; –40 pF load

R = 1M; –40 pF load

240

25

–

kHz

Notes

58. Based on device characterization (Not production tested).

59. Conversion resistance values are not calibrated. Calibratedvalues and details about calibration are provided inPSoC Creator component datasheets. External precision

resistors can also be used.

Document Number: 001-84934 Rev. *K

Page 98 of 126

PSoC^®5LP: CY8C54LP Family

Datasheet

11.5.10 Programmable Gain Amplifier

The PGA is created using a SC/CT analog block; see the PGA component datasheet in PSoC Creator for full electrical specifications

and APIs.

Unless otherwise specified, operating conditions are:

■ Operating temperature = 25 °C for typical values

■ Unless otherwise specified, all charts and graphs show typical values

Table 11-39. PGA DC Specifications

Parameter

Vin

Description

Input voltage range

Input offset voltage

Conditions

Min

Vssa

–

Typ

–

Max

V_DDA

10

Units

V

Power mode = minimum

Vos

Power mode = high,

gain = 1

–

mV

TCVos

Input offset voltage drift

with temperature

Power mode = high,

gain = 1

–

±30

µV/°C

Ge1

Gain error, gain = 1

Gain error, gain = 16

Gain error, gain = 50

DC output nonlinearity

–

±0.15

±2.5

±5

%

Ge16

Ge50

Vonl

Gain = 1

±0.01

% of

FSR

Cin

Input capacitance

–

7

–

pF

V

Voh

Output voltage swing

Power mode = high,

gain = 1, Rload = 100 k

to V_DDA/ 2

V

_DDA– 0.15

Vol

Output voltage swing

Power mode = high,

gain = 1, Rload = 100 k

to V_DDA/ 2

–

V_SSA+ 0.15

300

V

Vsrc

Output voltage under load

Operating current^[60]

Iload = 250 µA, V_DDA

2.7V, power mode = high



mV

IDD

Power mode = high

–

1.5

–

1.65

–

mA

dB

PSRR

Power supply rejection

ratio

48

Figure 11-1.PGA Voffset Histogram, 4096 samples/

1024 parts

Note

60. Based on device characterization (Not production tested).

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Datasheet

[61]

Table 11-40. PGA AC Specifications

Parameter

BW1

Description

–3 dB bandwidth

Conditions

Min

6.7

Typ

8

Max

–

Units

MHz

Power mode = high,

gain = 1, input = 100 mV

peak-to-peak

SR1

e_n

Slew rate

Power mode = high,

gain = 1, 20% to 80%

Power mode = high,

3

–

V/µs

Input noise density

43

nV/sqrtHz

V_DDA= 5 V, at 100 kHz

Figure 11-2.Bandwidth vs. Temperature, at Different Gain

Settings, Power Mode = High

Figure 11-3.Noise vs. Frequency, Vdda = 5 V,

Power Mode = High

10

1000

100

10

1

0.1

-40

-20

0

20

40

60

80

Temperature, °C

Gain = 24

0.01

0.1

1

10

100

1000

Gain = 1

Gain = 48

Frequency, kHz

11.5.11 Temperature Sensor

Table 11-41. Temperature Sensor Specifications

Parameter

Description

Conditions

Range: –40 °C to +85 °C

Min

Typ

Max

Units

Temp sensor accuracy

–

±5

–

°C

11.5.12 LCD Direct Drive

[61]

Table 11-42. LCD Direct Drive DC Specifications

Parameter

I_CC

Description

LCD Block (no glass)

Conditions

Min

–

Typ

81

Max

–

Units

A

Device sleep mode with wakeup at

400Hz rate to refresh LCD, bus, clock

= 3MHz, Vddio = Vdda = 3V, 8

commons, 16segments, 1/5dutycycle,

40 Hz frame rate, no glass connected

I_{CC_SEG}

V_BIAS

Current per segment driver

LCD bias range (V_BIASrefers to the

main output voltage(V0) of LCD DAC)

Strong drive mode

V_DDA 3 V and V_DDA V_BIAS

–

2

260

–

5

µA

V

LCD bias step size

V_DDA 3 V and V_DDA V_BIAS

Drivers may be combined

Vdda 3V and Vdda  Vbias

–

9.1 ×

V_DDA

500

–

mV

pF

LCD capacitance per segment/

common driver

Maximum segment DC offset

5000

–

355

–

20

710

mV

µA

I_OUT

Output drive current per segment driver) V_DDIO= 5.5V, strong drive mode

[61]

Table 11-43. LCD Direct Drive AC Specifications

Parameter

f_LCD

Description

LCD frame rate

Conditions

Min

10

Typ

50

Max

150

Units

Hz

Note

61. Based on device characterization (Not production tested).

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Datasheet

11.6 Digital Peripherals

Specifications are valid for –40 °C  T_A 85 °C and T_J 100 °C, except where noted. Specifications are valid for 1.71 V to 5.5 V,

except where noted.

11.6.1 Timer

The following specifications apply to the Timer/Counter/PWM peripheral in timer mode. Timers can also be implemented in UDBs; for

more information, see the Timer component datasheet in PSoC Creator.

[62]

Table 11-44. Timer DC Specifications

Parameter

Description

Conditions

Min

Typ

Max

Units

Block current consumption

16-bit timer, at listed input clock

frequency

–

µA

3 MHz

–

15

60

260

360

–

µA

12 MHz

48 MHz

80 MHz

[62]

Table 11-45. Timer AC Specifications

Parameter Description

Operating frequency

Conditions

Min

DC

15

30

15

30

15

30

Typ

–

Max

Units

MHz

ns

80.01

Capture pulse width (Internal)^[63]

Capture pulse width (external)

Timer resolution^[63]

–

ns

–

ns

Enable pulse width^[63]

–

ns

Enable pulse width (external)

Reset pulse width^[63]

–

ns

–

ns

Reset pulse width (external)

–

ns

11.6.2 Counter

The following specifications apply to the Timer/Counter/PWM peripheral, in counter mode. Counters can also be implemented in

UDBs; for more information, see the Counter component datasheet in PSoC Creator.

[62]

Table 11-46. Counter DC Specifications

Parameter

Description

Conditions

Min

Typ

Max

Units

Block current consumption

16-bit counter, at listed input clock

frequency

–

µA

3 MHz

–

15

60

–

µA

12 MHz

48 MHz

80 MHz

260

360

Notes

62. Based on device characterization (Not production tested).

63. For correct operation, the minimum Timer/Counter/PWM input pulse width is the period of bus clock.

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Datasheet

[64]

Table 11-47. Counter AC Specifications

Parameter Description

Operating frequency

Conditions

Min

DC

15

30

15

30

15

30

Typ

–

Max

Units

MHz

ns

80.01

Capture pulse^[65]

Resolution^[65]

Pulse width^[65]

–

ns

–

ns

Pulse width (external)

Enable pulse width^[65]

–

ns

–

ns

Enable pulse width (external)

Reset pulse width^[65]

–

ns

–

ns

Reset pulse width (external)

–

ns

11.6.3 Pulse Width Modulation

The following specifications apply to the Timer/Counter/PWM peripheral, in PWM mode. PWM components can also be implemented

in UDBs; for more information, see the PWM component datasheet in PSoC Creator.

[64]

Table 11-48. PWM DC Specifications

Parameter

Description

Conditions

Min

Typ

Max

Units

Block current consumption

16-bit PWM, at listed input clock

frequency

–

µA

3 MHz

–

15

60

–

µA

12 MHz

48 MHz

80 MHz

260

360

[64]

Table 11-49. PWM AC Specifications

Parameter

Description

Operating frequency

Pulse width^[65]

Conditions

Min

DC

15

30

15

30

15

30

15

30

Typ

–

Max

Units

MHz

ns

80.01

–

Pulse width (external)

Kill pulse width^[65]

–

ns

–

ns

Kill pulse width (external)

Enable pulse width^[65]

–

ns

–

ns

Enable pulse width (external)

Reset pulse width^[65]

–

ns

–

ns

Reset pulse width (external)

–

ns

Notes

64. Based on device characterization (Not production tested).

65. For correct operation, the minimum Timer/Counter/PWM input pulse width is the period of bus clock.

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11.6.4 I²C

[66]

Table 11-50. Fixed I²C DC Specifications

Parameter

Description

Conditions

Min

–

Typ

–

Max

250

260

Units

µA

Block current consumption

Enabled, configured for 100 kbps

Enabled, configured for 400 kbps

–

µA

Table 11-51. Fixed I²C AC Specifications

Parameter

Description

Conditions

Min

Typ

Max

Units

Bit rate

–

1

Mbps

11.6.5 USB

Table 11-52. USB DC Specifications

Parameter Description

V_{USB_5}

Conditions

Min

Typ

Max

Units

Device supply (V_DDD) for USB

operation

USB configured, USB regulator

enabled

4.35

3.15

2.85

–

5.25

V

V_{USB_3.3}

V_{USB_3}

USB configured, USB regulator

bypassed

–

3.6

V

USB configured, USB regulator

bypassed^[67]

3.6

I_{USB_Configured}Device supply current in device active V_DDD= 5 V, F_CPU= 1.5 MHz

–

10

8

–

mA

mode, bus clock and IMO = 24 MHz

V_DDD= 3.3 V, F_CPU= 1.5 MHz

I_{USB_Suspended}Device supply current in device sleep V_DDD= 5 V, connected to USB

0.5

mode

host, PICU configured to wake on

USB resume signal

V_DDD= 5 V, disconnected from

USB host

–

0.3

0.5

–

mA

V_DDD= 3.3 V, connected to USB

host, PICU configured to wake on

USB resume signal

V_DDD= 3.3 V, disconnected from

–

0.3

–

mA

USB host

Notes

66. Based on device characterization (Not production tested).

67. Rise/fall time matching (TR) not guaranteed, see Table 11-16 on page 80.

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11.6.6 Universal Digital Blocks (UDBs)

PSoC Creator provides a library of pre-built and tested standard digital peripherals (UART, SPI, LIN, PRS, CRC, timer, counter, PWM,

AND, OR, and so on) that are mapped to the UDB array. See the component datasheets in PSoC Creator for full AC/DC specifications,

APIs, and example code.

[68]

Table 11-53. UDB AC Specifications

Parameter

Description

Conditions

Min

Typ

Max

Units

Datapath Performance

F_{MAX_TIMER}Maximum frequency of 16-bit timer in

a UDB pair

–

67.01

MHz

F_{MAX_ADDER}Maximum frequency of 16-bit adder in

a UDB pair

F_{MAX_CRC}

Maximum frequency of 16-bit

CRC/PRS in a UDB pair

PLD Performance

F_{MAX_PLD}Maximum frequency of a two-pass

PLD function in a UDB pair

Clock to Output Performance

t_{CLK_OUT}Propagation delay for clock in to data 25 °C, V_DDD 2.7 V

out, see Figure 11-1..

Propagation delay for clock in to data Worst-case placement, routing,

–

67.01

MHz

–

20

–

25

55

ns

t_{CLK_OUT}

out, see Figure 11-1..

and pin selection

Figure 11-1.Clock to Output Performance

Note

68. Based on device characterization (Not production tested).

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Datasheet

11.7 Memory

Specifications are valid for –40 °C  T_A 85 °C and T_J 100 °C, except where noted. Specifications are valid for 1.71 V to 5.5 V,

except where noted.

11.7.1 Flash

Table 11-54. Flash DC Specifications

Parameter

Description

Conditions

Min

Typ

Max

Units

Erase and program voltage

V_DDDpin

1.71

–

5.5

V

Table 11-55. Flash AC Specifications

Parameter

T_WRITE

Description

Row write time (erase + program)

Row erase time

Min

–

Typ

15

10

5

Max

20

13

7

Units

ms

T_ERASE

–

ms

Row program time

–

ms

T_BULK

T_PROG

Bulk erase time (256 KB)

Sector erase time (16 KB)

Total device programming time

Flash data retention time, retention

–

140

15

7.5

–

ms

–

ms

No overhead^[69]

–

5

Seconds

Years

Average ambient temp.

20

–

period measured from last erase cycle T_A 55 °C, 100 K erase/program

cycles

Average ambient temp.

T_A 85 °C, 10 K erase/program

cycles

10

–

11.7.2 EEPROM

Table 11-56. EEPROM DC Specifications

Parameter

Description

Conditions

Min

Typ

Max

Units

Erase and program voltage

1.71

–

5.5

V

Table 11-57. EEPROM AC Specifications

Parameter

Description

Min

–

Typ

10

–

Max

20

–

Units

ms

T_WRITE

Single row erase/write cycle time

EEPROM data retention time, retention Average ambient temp, T_A 25 °C,

period measured from last erase cycle 1M erase/program cycles

20

years

Average ambient temp, T_A 55 °C,

20

10

–

100 K erase/program cycles

Average ambient temp. T_A85 °C,

10 K erase/program cycles

Note

69. See PSoC 5 Device Programming Specifications for a description of a low-overhead method of programming PSoC 5 flash.

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Datasheet

11.7.3 Nonvolatile Latches (NVL)

Table 11-58. NVL DC Specifications

Parameter

Description

Conditions

Min

Typ

Max

Units

Erase and program voltage

V_DDDpin

1.71

–

5.5

V

Table 11-59. NVL AC Specifications

Parameter Description

NVL endurance

Min

Typ

Max

Units

Programmed at 25 °C

1 K

–

Program/

erase

cycles

Programmed at 0 °C to 70 °C

100

–

Program/

erase

cycles

NVL data retention time

Average ambient temp. T_A≤ 55 °C

Average ambient temp. T_A≤ 85 °C

20

10

–

Years

11.7.4 SRAM

Table 11-60. SRAM DC Specifications

Parameter

Description

SRAM retention voltage^[70]

Conditions

Min

Typ

Max

Units

V_SRAM

1.2

–

V

Table 11-61. SRAM AC Specifications

Parameter

Description

Min

Typ

Max

Units

F_SRAM

SRAM operating frequency

DC

–

80.01

MHz

Note

70. Based on device characterization (Not production tested).

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11.7.5 External Memory Interface

Figure 11-1.Asynchronous Write and Read Cycle Timing, No Wait States

Tbus_clock

Bus Clock

EM_Addr

EM_CE

EM_WE

EM_OE

Twr_setup

Trd_hold

Trd_setup

EM_Data

Write Cycle

Read Cycle

Minimum of 4 bus clock cycles between successive EMIF accesses

Table 11-62. Asynchronous Write and Read Timing Specifications^[71]

Parameter Description Conditions

Fbus_clock Bus clock frequency^[72]

Tbus_clock Bus clock period^[73]

Min

Typ

–

Max

33

–

Units

–

MHz

ns

30.3

–

Twr_Setup Time from EM_data valid to rising edge of

EM_WE and EM_CE

Tbus_clock – 10

–

ns

Trd_setup

Time that EM_data must be valid before rising

edge of EM_OE

5

–

ns

Trd_hold

Time that EM_data must be valid after rising

edge of EM_OE

Notes

71. Based on device characterization (Not production tested).

72. EMIF signal timings are limited by GPIO frequency limitations. See “GPIO” section on page 73.

73. EMIF output signals are generally synchronized to bus clock, so EMIF signal timings are dependent on bus clock frequency.

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Figure 11-2.Synchronous Write and Read Cycle Timing, No Wait States

Tbus_clock

Bus Clock

EM_Clock

EM_Addr

EM_CE

EM_ADSC

EM_WE

EM_OE

Twr_setup

Trd_hold

Trd_setup

EM_Data

Write Cycle

Read Cycle

Minimum of 4 bus clock cycles between successive EMIF accesses

Table 11-63. Synchronous Write and Read Timing Specifications^[74]

Parameter Description Conditions

Fbus_clock Bus clock frequency^[75]

Tbus_clock Bus clock period^[76]

Min

Typ

–

Max

33

–

Units

–

MHz

ns

30.3

–

Twr_Setup Time from EM_data valid to rising edge of

EM_Clock

Tbus_clock – 10

–

ns

Trd_setup

Time that EM_data must be valid before rising

edge of EM_OE

5

–

ns

Trd_hold

Time that EM_data must be valid after rising

edge of EM_OE

Notes

74. Based on device characterization (Not production tested).

75. EMIF signal timings are limited by GPIO frequency limitations. See “GPIO” section on page 73.

76. EMIF output signals are generally synchronized to bus clock, so EMIF signal timings are dependent on bus clock frequency.

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11.8 PSoC System Resources

Specifications are valid for –40 °C  T_A 85 °C and T_J 100 °C, except where noted. Specifications are valid for 1.71 V to 5.5 V,

except where noted.

11.8.1 POR with Brown Out

For brown out detect in regulated mode, V_DDDand V_DDAmust be  2.0 V. Brown out detect is not available in externally regulated

mode.

Table 11-64. Precise Low-Voltage Reset (PRES) with Brown Out DC Specifications

Parameter

PRESR

Description

Rising trip voltage

Falling trip voltage

Conditions

Factory trim

Min

1.64

1.62

Typ

–

Max

1.68

1.66

Units

V

PRESF

–

[77]

Table 11-65. Power-On-Reset (POR) with Brown Out AC Specifications

Parameter Description Conditions

PRES_TR^[78]Response time

V_DDD/V_DDAdroop rate

Min

–

Typ

–

Max

0.5

–

Units

µs

Sleep mode

–

5

V/sec

11.8.2 Voltage Monitors

Table 11-66. Voltage Monitors DC Specifications

Parameter

Description

Conditions

Min

–

Typ

–

Max

–

Units

LVI

Trip voltage

LVI_A/D_SEL[3:0] = 0000b

LVI_A/D_SEL[3:0] = 0001b

LVI_A/D_SEL[3:0] = 0010b

LVI_A/D_SEL[3:0] = 0011b

LVI_A/D_SEL[3:0] = 0100b

LVI_A/D_SEL[3:0] = 0101b

LVI_A/D_SEL[3:0] = 0110b

LVI_A/D_SEL[3:0] = 0111b

LVI_A/D_SEL[3:0] = 1000b

LVI_A/D_SEL[3:0] = 1001b

LVI_A/D_SEL[3:0] = 1010b

LVI_A/D_SEL[3:0] = 1011b

LVI_A/D_SEL[3:0] = 1100b

LVI_A/D_SEL[3:0] = 1101b

LVI_A/D_SEL[3:0] = 1110b

LVI_A/D_SEL[3:0] = 1111b

Trip voltage

1.68

1.89

2.14

2.38

2.62

2.87

3.11

3.35

3.59

3.84

4.08

4.32

4.56

4.83

5.05

5.30

5.57

1.73

1.95

2.20

2.45

2.71

2.95

3.21

3.46

3.70

3.95

4.20

4.45

4.70

4.98

5.21

5.47

5.75

1.77

2.01

2.27

2.53

2.79

3.04

3.31

3.56

3.81

4.07

4.33

4.59

4.84

5.13

5.37

5.63

5.92

V

HVI

Table 11-67. Voltage Monitors AC Specifications

Parameter

LVI_tr^[78]

Description

Response time

Conditions

Min

Typ

Max

Units

–

1

µs

Notes

77. Based on device characterization (Not production tested).

78. This value is calculated, not measured.

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11.8.3 Interrupt Controller

Table 11-68. Interrupt Controller AC Specifications

Parameter

Description

Conditions

Min

Typ

Max

Units

Delay from interrupt signal input to ISR

code execution from main line code^[79]

–

12

Tcy CPU

Delay from interrupt signal input to ISR

code execution from ISR code

(tail-chaining)^[79]

–

6

Tcy CPU

11.8.4 JTAG Interface

Figure 11-1.JTAG Interface Timing

(1/f_TCK)

TCK

TDI

T_TDI_setup

T_TDI_hold

T_TDO_hold

T_TDO_valid

TDO

TMS

T_TMS_setup

T_TMS_hold

[80]

Table 11-69. JTAG Interface AC Specifications

Parameter Description

f_TCK TCK frequency

Conditions

3.3 V  V_DDD 5 V

Min

Typ

Max

12^[81]

7^[81]

Units

MHz

ns

–

1.71 V  V_DDD< 3.3 V

–

T_TDI_setup

T_TMS_setup

T_TDI_hold

T_TDO_valid

T_TDO_hold

T_nTRST

TDI setup before TCK high

TMS setup before TCK high

TDI, TMS hold after TCK high

TCK low to TDO valid

(T/10) – 5

–

T/4

–

T = 1/f_TCK max

f_TCK = 2 MHz

–

2T/5

–

TDO hold after TCK high

Minimum nTRST pulse width

T/4

8

–

ns

Notes

79. ARM Cortex-M3 NVIC spec. Visit www.arm.com for detailed documentation about the Cortex-M3 CPU.

80. Based on device characterization (Not production tested).

81. f_TCK must also be no more than 1/3 CPU clock frequency.

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Datasheet

11.8.5 SWD Interface

Figure 11-1.SWD Interface Timing

(1/f_SWDCK)

SWDCK

T_SWDI_setup

T_SWDI_hold

SWDIO

(PSoC input)

T_SWDO_valid

T_SWDO_hold

SWDIO

(PSoC output)

[82]

Table 11-70. SWD Interface AC Specifications

Parameter

Description

SWDCLK frequency

Conditions

Min

–

Typ

Max

12^[83]

7^[83]

Units

MHz

f_SWDCK

3.3 V  V_DDD 5 V

–

1.71 V  V_DDD< 3.3 V

–

1.71 V  V_DDD< 3.3 V, SWD over

USBIO pins

–

5.5^[83]

T_SWDI_setup SWDIO input setup before SWDCK high T = 1/f_SWDCK max

T/4

–

T_SWDI_hold SWDIO input hold after SWDCK high

T_SWDO_valid SWDCK high to SWDIO output

T = 1/f_SWDCK max

T/2

–

T_SWDO_hold SWDIO output hold after SWDCK high T = 1/f_SWDCK max

1

ns

11.8.6 TPIU Interface

[82]

Table 11-71. TPIU Interface AC Specifications

Parameter

Description

TRACEPORT (TRACECLK) frequency

SWV bit rate

Conditions

Min

–

Typ

–

Max

33^[84]

Units

MHz

Mbit

–

Notes

82. Based on device characterization (Not production tested).

83. f_SWDCK must also be no more than 1/3 CPU clock frequency.

84. TRACEPORT signal frequency and bit rate are limited by GPIO output frequency, see Table 11-10 on page 74.

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11.9 Clocking

Specifications are valid for –40 °C T_A 85 °C and T_J 100 °C, except where noted. Specifications are valid for 1.71 V to 5.5 V,

except where noted. Unless otherwise specified, all charts and graphs show typical values.

11.9.1 Internal Main Oscillator

Table 11-72. IMO DC Specifications^[85]

Parameter

Description

Supply current

Conditions

Min

Typ

Max

Units

74.7 MHz

–

730

600

500

300

200

180

150

µA

62.6 MHz

48 MHz

Icc_imo

24 MHz – USB mode

24 MHz – non USB mode

12 MHz

With oscillator locking to USB bus

6 MHz

3 MHz

Figure 11-2.IMO Current vs. Frequency

700

600

500

400

300

200

100

0

10

20

30

40

50

60

70

80

Frequency, MHz

)

Table 11-73. IMO AC Specifications

Parameter Description

Conditions

Min

Typ

Max

Units

IMO frequency stability (with factory trim)

74.7 MHz

–7

–

7

%

µs

62.6 MHz

48 MHz

–5

5

F

24 MHz – Non USB mode

24 MHz – USB mode

12 MHz

–4

4

IMO

With oscillator locking to USB bus

–0.25

–3

0.25

3

6 MHz

–2

2

3 MHz

–2

2

[85]

Tstart_imo Startup time

From enable (during normal system

operation)

–

13

Note

85. Based on device characterization (Not production tested).

Document Number: 001-84934 Rev. *K

Page 112 of 126

PSoC^®5LP: CY8C54LP Family

Datasheet

Table 11-73. IMO AC Specifications (continued)

Parameter

Description

Conditions

Min

Typ

Max

Units

[86]

Jitter (peak to peak)

Jp-p

F = 24 MHz

F = 3 MHz

–

0.9

1.6

–

ns

[86]

Jitter (long term)

F = 24 MHz

F = 3 MHz

Jperiod

–

0.9

12

–

ns

Figure 11-3.IMO Frequency Variation vs. Temperature

Figure 11-4.IMO Frequency Variation vs. V_CC

0.5

62.6 MHz

24 MHz

3 MHz

0.25

0

-0.25

-0.5

-40

-20

0

20

40

60

80

100

Temperature, °C

Note

86. Based on device characterization (Not production tested).

Document Number: 001-84934 Rev. *K

Page 113 of 126

PSoC^®5LP: CY8C54LP Family

Datasheet

11.9.2 Internal Low-Speed Oscillator

Table 11-74. ILO DC Specifications

Parameter

Description

Operating current^[87]

Conditions

F_OUT= 1 kHz

Min

–

Typ

–

Max

1.7

2.6

15

Units

µA

I_CC

F_OUT= 33 kHz

–

µA

F_OUT= 100 kHz

Power down mode

–

µA

Leakage current^[87]

–

nA

Table 11-75. ILO AC Specifications^[88]

Parameter Description

Conditions

Turbo mode

Min

Typ

Max

Units

Tstart_ilo Startup time, all frequencies

ILO frequencies

–

2

ms

F_ILO

100 kHz

1 kHz

45

100

1

200

2

kHz

0.5

Figure 11-5.ILO Frequency Variation vs. Temperature

Figure 11-6.ILO Frequency Variation vs. V_DD

50

20

25

10

0

100 kHz

1 kHz

-25

-10

-20

1 kHz

-50

-40

-20

0

20

40

60

80

100

1.5

2.5

3.5

4.5

5.5

Temperature, °C

V_DDD, V

Notes

87. This value is calculated, not measured.

88. Based on device characterization (Not production tested).

Document Number: 001-84934 Rev. *K

Page 114 of 126

PSoC^®5LP: CY8C54LP Family

Datasheet

11.9.3 MHz External Crystal Oscillator

For more information on crystal or ceramic resonator selection for the MHzECO, refer to application note AN54439: PSoC 3 and

PSoC 5 External Oscillators.

Table 11-76. MHzECO DC Specifications

Parameter

Description

Operating current^[89]

Conditions

13.56 MHz crystal

Min

Typ

Max

Units

I_CC

–

3.8

–

mA

Table 11-77. MHzECO AC Specifications

Parameter

Description

Conditions

Min

Typ

Max

Units

F

Crystal frequency range

4

–

25

MHz

11.9.4 kHz External Crystal Oscillator

[89]

Table 11-78. kHzECO DC Specifications

Parameter

Description

Operating current

Drive level

Conditions

Min

–

Typ

0.25

–

Max

1.0

1

Units

µA

I_CC

DL

Low power mode; CL = 6 pF

–

µW

Table 11-79. kHzECO AC Specifications

Parameter

Description

Conditions

Min

–

Typ

32.768

1

Max

–

Units

kHz

s

F

Frequency

T_ON

Startup time

High power mode

–

11.9.5 External Clock Reference

Table 11-80. External Clock Reference AC Specifications

[89]

Parameter

Description

External frequency range

Input duty cycle range

Input edge rate

Conditions

Min

0

Typ

–

Max

33

70

–

Units

MHz

%

Measured at V_DDIO/2

V_ILto V_IH

30

0.5

50

–

V/ns

11.9.6 Phase-Locked Loop

Table 11-81. PLL DC Specifications

Parameter

I_DD

Description

PLL operating current

Conditions

In = 3 MHz, Out = 80 MHz

In = 3 MHz, Out = 67 MHz

In = 3 MHz, Out = 24 MHz

Min

–

Typ

650

400

200

Max

Units

µA

–

µA

–

µA

Table 11-82. PLL AC Specifications

Parameter

Description

PLL input frequency^[90]

PLL intermediate frequency^[91]

PLL output frequency^[90]

Lock time at startup

Conditions

Min

1

Typ

–

Max

48

Units

MHz

µs

Fpllin

Output of prescaler

1

–

3

Fpllout

24

–

80

–

250

Jperiod-rms Jitter (rms)^[89]

–

ps

Notes

89. Based on device characterization (Not production tested).

90. This specification is guaranteed by testing the PLL across the specified range using the IMO as the source for the PLL.

91. PLL input divider, Q, must be set so that the input frequency is divided down to the intermediate frequency range. Value for Q ranges from 1 to 16.

Document Number: 001-84934 Rev. *K

Page 115 of 126

PSoC^®5LP: CY8C54LP Family

Datasheet

12. Ordering Information

In addition to the features listed in Table 12-1, every CY8C54LP device includes: up to 256 KB flash, 64 KB SRAM, 2 KB EEPROM,

a precision on-chip voltage reference, precision oscillators, flash, ECC, DMA, a fixed function I²C, JTAG/SWD programming and

debug, external memory interface, boost, and more. In addition to these features, the flexible UDBs and analog subsection support

a wide range of peripherals. To assist you in selecting the ideal part, PSoC Creator makes a part recommendation after you choose

the components required by your application. All CY8C54LP derivatives incorporate device and flash security in user-selectable

security levels; see the TRM for details.

Table 12-1. CY8C54LP Family with ARM Cortex-M3 CPU

[94]

MCU Core

Analog

Digital

I/O

[95]

JTAG ID

Part Number

Package

CY8C5468LTI-LP026

CY8C5468AXI-LP106

CY8C5468AXI-LP042

CY8C5467LTI-LP003

CY8C5467AXI-LP108

CY8C5466AXI-LP002

CY8C5466LTI-LP072

CY8C5466LTI-LP085

CY8C5466AXI-LP107

CY8C5465AXI-LP043

CY8C5465LTI-LP104

CY8C5488AXI-LP120

CY8C5488LTI-LP093

CY8C5488FNI-LP212

67 256 64

67 128 32

67 64 16

2

✔ 1x12-bit SAR

2

4

2

–

✔

24

4

✔

48 38

72 62

48 38

72 62

46 38

48 38

70 62

72 62

48 38

72 62

48 38

72 62

8

2

0

2

0

2

68-QFN

100-TQFP

68-QFN

0x2E11A069

0x2E16A069

0x2E12A069

0x2E103069

0x2E16C069

0x2E102069

0x2E148069

0x2E155069

0x2E16B069

0x2E12B069

0x2E168069

0x2E178069

0x2E15D069

0x2E1D4069

✔ 1x12-bit SAR

✔ 12-bit Del-Sig

✔ 1x12-bit SAR

4

24

20

24

✔

–

100-TQFP

68-QFN

✔

–

68-QFN

100-TQFP

68-QFN

67 32

8

✔

80 256 64

100-TQFP

68-QFN

99-WLCSP

Notes

92. Analog blocks support a wide variety of functionality including TIA, PGA, and mixers. See Example Peripherals on page 40 for more information on how analog blocks

can be used.

93. UDBs support a wide variety of functionality including SPI, LIN, UART, timer, counter, PWM, PRS, and others. Individual functions may use a fraction of a UDB or

multiple UDBs. Multiple functions can share a single UDB. See Example Peripherals on page 40 for more information on how UDBs can be used.

94. The I/O Count includes all types of digital I/O: GPIO, SIO, and the two USB I/O. See I/O System and Routing on page 33 for details on the functionality of each of

these types of I/O.

95. The JTAG ID has three major fields. The most significant nibble (left digit) is the version, followed by a 2 byte part number and a 3 nibble manufacturer ID.

Document Number: 001-84934 Rev. *K

Page 116 of 126

PSoC^®5LP: CY8C54LP Family

Datasheet

12.1 Part Numbering Conventions

PSoC 5LP devices follow the part numbering convention described here. All fields are single character alphanumeric (0, 1, 2, …, 9,

A, B, …, Z) unless stated otherwise.

CY8Cabcdefg-LPxxx

■ a: Architecture

❐ 3: PSoC 3

❐ 5: PSoC 5

■ ef: Package code

❐ Two character alphanumeric

❐ AX: TQFP

❐ LT: QFN

❐ FN: CSP

■ b: Family group within architecture

❐ 2: CY8C52LP family

■ g: Temperature range

❐ C: commercial

❐ I: industrial

❐ 4: CY8C54LP family

❐ 6: CY8C56LP family

❐ 8: CY8C58LP family

❐ A: automotive

■ c: Speed grade

❐ 6: 67 MHz

■ xxx: Peripheral set

❐ 8: 80 MHz

❐ Three character numeric

❐ No meaning is associated with these three characters

■ d: Flash capacity

❐ 5: 32 KB

❐ 6: 64 KB

❐ 7: 128 KB

❐ 8: 256 KB

CY8C 5 4 8 8 AX/PV I - LPx x x

Examples

Cypress Prefix

5: PSoC 5

Architecture

Family Group within Architecture

Speed Grade

4: CY8C54 Family

8: 80 MHz

8: 256 KB

Flash Capacity

AX: TQFP, PV: SSOP

I: Industrial

Package Code

Temperature Range

Peripheral Set

Tape and reel versions of these devices are available and are marked with a "T" at the end of the part number.

All devices in the PSoC 5LP CY8C54LP family comply to RoHS-6 specifications, demonstrating the commitment by Cypress to

lead-free products. Lead (Pb) is an alloying element in solders that has resulted in environmental concerns due to potential toxicity.

Cypress uses nickel-palladium-gold (NiPdAu) technology for the majority of leadframe-based packages.

A high level review of the Cypress Pb-free position is available on our website. Specific package information is also available. Package

Material Declaration Datasheets (PMDDs) identify all substances contained within Cypress packages. PMDDs also confirm the

absence of many banned substances. The information in the PMDDs will help Cypress customers plan for recycling or other “end of

life” requirements.

Document Number: 001-84934 Rev. *K

Page 117 of 126

PSoC^®5LP: CY8C54LP Family

Datasheet

13. Packaging

Table 13-1. Package Characteristics

Parameter

T_A

Description

Conditions

Min

–40

–

Typ

25

–

Max

85

100

–

Units

°C

Operating ambient temperature

Operating junction temperature

Package _JA(68-pin QFN)

Package _JA(100-pin TQFP)

Package _JC(68-pin QFN)

Package _JC(100-pin TQFP)

Operating ambient temperature

Operating junction temperature

Package _JA(99-ball CSP)

Package _JC(99-ball CSP)

T_J

°C

T_JA

T_JC

T_A

15

34

13

10

25

–

°C/Watt

°C

–

For CSP parts

–40

85

100

T_J

For CSP parts

°C

T_JA

T_Jc

16.5

0.1

°C/Watt

–

Table 13-2. Solder Reflow Peak Temperature

Maximum Peak

Package

Maximum Time at

Peak Temperature

Temperature

68-pin QFN

100-pin TQFP

99-pin CSP

260 °C

255 °C

30 seconds

Table 13-2. Package Moisture Sensitivity Level (MSL), IPC/JEDEC J-STD-2

Package

68-pin QFN

100-pin TQFP

99-pin CSP

MSL

MSL 3

MSL 1

Document Number: 001-84934 Rev. *K

Page 118 of 126

PSoC^®5LP: CY8C54LP Family

Datasheet

Figure 13-1.68-Pin QFN 8 × 8 with 0.4 mm Pitch Package Outline (Sawn Version)

001-09618 *E

Figure 13-2.100-Pin TQFP (14 × 14 × 1.4 mm) Package Outline

51-85048 *J

Document Number: 001-84934 Rev. *K

Page 119 of 126

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Datasheet

Figure 13-3.WLCSP Package (5.192 × 5.940 × 0.6 mm)

001-88034 *B

Document Number: 001-84934 Rev. *K

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PSoC^®5LP: CY8C54LP Family

Datasheet

Table 14-1. Acronyms Used in this Document (continued)

14. Acronyms

Acronym

FS

Description

Table 14-1. Acronyms Used in this Document

full-speed

Acronym

abus

Description

GPIO

general-purpose input/output, applies to a PSoC

analog local bus

ADC

AG

analog-to-digital converter

analog global

HVI

high-voltage interrupt, see also LVI, LVD

integrated circuit

IC

AHB

AMBA (advanced microcontroller bus archi-

tecture) high-performance bus, an ARM data

transfer bus

IDAC

IDE

current DAC, see also DAC, VDAC

integrated development environment

ALU

arithmetic logic unit

I²C, or IIC

Inter-Integrated Circuit, a communications

protocol

AMUXBUS analog multiplexer bus

IIR

infinite impulse response, see also FIR

internal low-speed oscillator, see also IMO

internal main oscillator, see also ILO

integral nonlinearity, see also DNL

input/output, see also GPIO, DIO, SIO, USBIO

initial power-on reset

API

application programming interface

ILO

IMO

INL

APSR

ARM^®

ATM

application program status register

advanced RISC machine, a CPU architecture

automatic thump mode

I/O

BW

bandwidth

IPOR

IPSR

IRQ

ITM

LCD

LIN

CMRR

CPU

CRC

common-mode rejection ratio

central processing unit

interrupt program status register

interrupt request

cyclic redundancy check, an error-checking

protocol

instrumentation trace macrocell

liquid crystal display

DAC

DFB

DIO

digital-to-analog converter, see also IDAC, VDAC

digital filter block

Local Interconnect Network, a communications

protocol.

digital input/output, GPIO with only digital

capabilities, no analog. See GPIO.

LR

link register

DMA

DNL

direct memory access, see also TD

differential nonlinearity, see also INL

do not use

LUT

LVD

lookup table

low-voltage detect, see also LVI

low-voltage interrupt, see also HVI

low-voltage transistor-transistor logic

multiply-accumulate

DNU

DR

LVI

port write data registers

digital system interconnect

data watchpoint and trace

error correcting code

LVTTL

MAC

MCU

MISO

NC

DSI

DWT

ECC

ECO

EEPROM

microcontroller unit

master-in slave-out

external crystal oscillator

no connect

electrically erasable programmable read-only

memory

NMI

nonmaskable interrupt

non-return-to-zero

NRZ

NVIC

NVL

opamp

PAL

EMI

electromagnetic interference

external memory interface

end of conversion

nested vectored interrupt controller

nonvolatile latch, see also WOL

operational amplifier

EMIF

EOC

EOF

EPSR

ESD

ETM

FIR

end of frame

programmable array logic, see also PLD

program counter

execution program status register

electrostatic discharge

PC

PCB

PGA

PHUB

PHY

printed circuit board

embedded trace macrocell

finite impulse response, see also IIR

flash patch and breakpoint

programmable gain amplifier

peripheral hub

FPB

physical layer

Document Number: 001-84934 Rev. *K

Page 121 of 126

PSoC^®5LP: CY8C54LP Family

Datasheet

Table 14-1. Acronyms Used in this Document (continued)

Acronym Description

PICU port interrupt control unit

Table 14-1. Acronyms Used in this Document (continued)

Acronym

TTL

Description

transistor-transistor logic

PLA

programmable logic array

programmable logic device, see also PAL

phase-locked loop

TX

transmit

PLD

UART

Universal Asynchronous Transmitter Receiver, a

communications protocol

PLL

UDB

universal digital block

Universal Serial Bus

PMDD

POR

PRES

PRS

PS

package material declaration datasheet

power-on reset

USB

USBIO

USB input/output, PSoC pins used to connect to

a USB port

precise low-voltage reset

pseudo random sequence

port read data register

VDAC

WDT

voltage DAC, see also DAC, IDAC

watchdog timer

PSoC^®

PSRR

PWM

RAM

RISC

RMS

RTC

RTL

Programmable System-on-Chip™

power supply rejection ratio

pulse-width modulator

WOL

write once latch, see also NVL

watchdog timer reset

external reset pin

WRES

XRES

XTAL

random-access memory

reduced-instruction-set computing

root-mean-square

crystal

real-time clock

register transfer language

remote transmission request

receive

RTR

RX

SAR

SC/CT

SCL

successive approximation register

switched capacitor/continuous time

I²C serial clock

SDA

S/H

I²C serial data

sample and hold

SIO

special input/output, GPIO with advanced

features. See GPIO.

SNR

SOC

SOF

SPI

signal-to-noise ratio

start of conversion

start of frame

Serial Peripheral Interface, a communications

protocol

SR

slew rate

SRAM

SRES

SWD

SWV

TD

static random access memory

software reset

serial wire debug, a test protocol

single-wire viewer

transaction descriptor, see also DMA

total harmonic distortion

transimpedance amplifier

technical reference manual

THD

TIA

TRM

Document Number: 001-84934 Rev. *K

Page 122 of 126

PSoC^®5LP: CY8C54LP Family

Datasheet

15. Document Conventions

15.1 Units of Measure

Table 15-1. Units of Measure

Symbol

°C

Unit of Measure

degrees Celsius

decibels

dB

fF

femtofarads

hertz

Hz

KB

kbps

Khr

kHz

k

1024 bytes

kilobits per second

kilohours

kilohertz

kilohms

ksps

LSB

Mbps

MHz

M

Msps

µA

kilosamples per second

least significant bit

megabits per second

megahertz

megaohms

megasamples per second

microamperes

microfarads

microhenrys

microseconds

microvolts

µF

µH

µs

µV

µW

mA

ms

mV

nA

microwatts

milliamperes

milliseconds

millivolts

nanoamperes

nanoseconds

nanovolts

ns

nV



ohms

pF

picofarads

ppm

ps

parts per million

picoseconds

seconds

s

sps

sqrtHz

V

samples per second

square root of hertz

volts

Document Number: 001-84934 Rev. *K

Page 123 of 126

PSoC^®5LP: CY8C54LP Family

Datasheet

Document History Page

Description Title: PSoC^®5LP: CY8C54LP Family Datasheet Programmable System-on-Chip (PSoC^®)

Document Number: 001-84934

Orig. of

Change

Submission

Date

Revision

ECN

Description of Change

**

3825653

3897878

MKEA

12/07/2012 Datasheet for new CY8C54LP family

02/07/2013 Removed Preliminary status.

*A

Updated characterization footnotes in Electrical Specifications.

Updated conditions for SAR ADC INL and DNL specifications in Table 11-25

Updated Table 11-75 (ILO AC specifications).

Changed “UDB Configuration" to "UDB Working Registers” in Table 5-4.

Removed references to CAN.

Updated INL VIDAC spec.

Updated VREF accuracy.

Removed drift specs from Voltage Reference Specifications.

*B

*C

3902085

4114902

MKEA

02/12/2013 Changed Hibernate wakeup time from 125 µs to 200 µs in Table 6-3 and

Table 11-3.

09/30/2013 Added information about 1 KB cache in Features.

Updated SAR ADC graphs.

Added warning on reset devices in the EEPROM section.

Updated C_INspecs in GPIO DC Specifications and SIO DC Specifications.

Added min and max values for the Regulator Output Capacitor parameter.

Added I_IBparameter in Opamp DC Specifications

*D

*E

*F

4225729

4386988

4587100

MKEA

12/20/2013 Added SIO Comparator Specifications.

Changed T_HIBERNATEmax value from 200 to 150.

Updated CSP package and ordering information.

Added 80 MHz parts in Table 12-1.

05/22/2014 Updated General Description and Features.

Added More Information and PSoC Creator sections.

Updated JTAG IDs in Ordering Information.

Updated 100-TQFP package diagram.

12/08/2014 Added link to AN72845 in Note 4.

Updated interrupt priority numbers in Section 4.4.

Updated Section 5.4 to clarify the factory default values of EEPROM.

Corrected ECCEN settings in Table 5-3.

Updated Section 6.1.1 and Section 6.1.2.

Added a note below Figure 6-6..

Updated Figure 6-6..

Changed ‘Control Store RAM’ to ‘Dynamic Configuration RAM’ in Figure 7-9.

and changed Section 7.2.2.2 heading to ‘Dynamic Configuration RAM’.

Updated Section 7.7.

Document Number: 001-84934 Rev. *K

Page 124 of 126

PSoC^®5LP: CY8C54LP Family

Datasheet

Document History Page (continued)

Description Title: PSoC^®5LP: CY8C54LP Family Datasheet Programmable System-on-Chip (PSoC^®)

Document Number: 001-84934

Orig. of

Change

Submission

Date

Revision

ECN

Description of Change

*G

4698847

MKEA /

GJV

03/24/2015 Updated System Integration

Updated Power System

Updated Boost Converter

Updated Electrical Specifications:

Updated Power Regulators

Updated Inductive Boost Regulator

Updated Table 11-7

Updated details of V_BAT, I_OUT, V_OUT, Reg_LOAD, Reg_LINEparameters.

Removed V_OUT: V_BATparameter and its details.

Removed Table “Inductive Boost Regulator AC Specifications”.

Updated Table 11-8:

Updated details of L_BOOST, C_BOOSTparameters.

Added C_BATparameter and its details.

Added Figure 11-7., Figure 11-8., Figure 11-9., Figure 11-10., Figure 11-11.,

Figure 11-12., Figure 11-13..

Removed Figure “Efficiency vs I_OUTV_BOOST= 3.3 V, L_BOOST= 10 μH”.

Removed Figure “Efficiency vs I_OUTV_BOOST= 3.3 V, L_BOOST= 22 μH”

Updated Appendix: CSP Package Summary:

Updated :

spec 001-88034 – Changed revision from ** to *A

*H

4839323

5030641

MKEA

07/15/2015 Added reference to code examples in More Information.

Updated typ value of T_WRITEfrom 2 to 10 in EEPROM AC specs table.

Changed “Device supply for USB operation" to "Device supply (V_DDD) for USB

operation" in USB DC Specifications.

Clarified power supply sequencing and margin for V_DDAand V_DDD

.

Updated Serial Wire Debug Interface with limitations of debugging on Port 15.

Added a part number with a delta-sigma ADC. Added supporting content

throughout the document.

*I

11/30/2015 Added Table 2-1.

Removed the configurable XRES information.

Updated Section 5.6

Updated Section 6.3.1.1.

Updated values for DSI Fmax, Fgpioin max, and Fsioin max.

Corrected the web link for the PSoC 5 Device Programming Specifications in

Section 9.

Updated CSP Package Bootloader section.

Added MHzECO DC Specifications.

Updated 99-WLCSP and 100-pin TQFP package drawings.

Added a footnote reference for the "CY8C5287AXI-LP095" part in Table 12-1

clarifying that it has 256 KB flash.

Added the CY8C5667AXQ-LP040 part in Table 12-1.

*J

5478402

5688089

MKEA

RUPA

10/25/2016 Updated More Information.

Add Links to CAD Libraries in Section 2.

Corrected typos in External Electrical Connections.

Updated Cypress logo.

Updated Copyright information.

*K

05/02/2017

Document Number: 001-84934 Rev. *K

Page 125 of 126

PSoC^®5LP: CY8C54LP Family

Datasheet

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office

closest to you, visit us at Cypress Locations.

®

Products

PSoC Solutions

ARM^®Cortex^®Microcontrollers

cypress.com/arm

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cypress.com/iot

PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6

Automotive

Cypress Developer Community

Clocks & Buffers

Interface

Training | Components

Internet of Things

Memory

Technical Support

cypress.com/memory

cypress.com/mcu

cypress.com/support

Microcontrollers

PSoC

cypress.com/psoc

Power Management ICs

Touch Sensing

USB Controllers

Wireless Connectivity

cypress.com/pmic

cypress.com/touch

cypress.com/usb

cypress.com/wireless

including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries

worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other

intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress

hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to

modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users

(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as

provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation

of the Software is prohibited.

TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE

OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent

permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any

product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is

the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products

are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or

systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the

device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably

expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim,

damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other

liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.

Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in

the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.

Document Number: 001-84934 Rev. *K

Revised May 2, 2017

Page 126 of 126


型号：	CY8C5488LTI-LP093
厂家：	CYPRESS
描述：	Multifunction Peripheral, CMOS, QFN-68 时钟
文件：	总126页 (文件大小：4536K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CY8C5488LTI-LP093 [CYPRESS]

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