CY8C5486AXI-064 [CYPRESS]
Programmable System-on-Chip (PSoC); 可编程系统级芯片（的PSoC ）
| 型号： | CY8C5486AXI-064 |
| 厂家： | 
CYPRESS |
| 描述： | Programmable System-on-Chip (PSoC) |
| 文件： | 总93页 (文件大小：2957K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
PSoC®5: CY8C54 Family Data Sheet
Programmable System-on-Chip (PSoC®)
General Description
With its unique array of configurable blocks, PSoC®5 is a true system level solution providing MCU, memory, analog, and digital
peripheral functions in a single chip. The CY8C54 family offers a modern method of signal acquisition, signal processing, and control
with high accuracy, high bandwidth, and high flexibility. Analog capability spans the range from thermocouples (near DC voltages) to
ultrasonic signals. The CY8C54 family can handle dozens of data acquisition channels and analog inputs on every GPIO pin. The
CY8C54 family is also a high performance configurable digital system with some part numbers including interfaces such as USB,
multi-master I2C, and CAN. In addition to communication interfaces, the CY8C54 family has an easy to configure logic array, flexible
routing to all I/O pins, and a high performance 32-bit ARM® Cortex™-M3 microprocessor core. Designers can easily create system
level designs using a rich library of prebuilt components and boolean primitives using PSoC® Creator™, a hierarchical schematic
design entry tool. The CY8C54 family provides unparalleled opportunities for analog and digital bill of materials integration while easily
accommodating last minute design changes through simple firmware updates.
Library of advanced peripherals
• Cyclic Redundancy Check (CRC)
• Pseudo Random Sequence (PRS) generator
• LIN Bus 2.0
Features
32-bit ARM Cortex-M3 CPU core
DC to 80 MHz operation
Flash program memory, up to 256 KB, 100,000 write cycles,
20 year retention, multiple security features
• Quadrature decoder
Analog peripherals (1.71V ≤ Vdda ≤ 5.5V)
Up to 64 KB SRAM memory
1.024V±0.1% internal voltage reference across -40°C to
+85°C (14 ppm/°C)
2 KB EEPROM memory, 1 million cycles, 20 years retention
24 channel DMA with multilayer AHB bus access
• Programmable chained descriptors and priorities
• High bandwidth 32-bit transfer support
Two SAR ADCs, each 12-bit at 1 Msps[1]
80 MHz, 24-bit fixed point digital filter block (DFB) to
implement FIR and IIR filters[1]
Four 8-bit 8 Msps IDACs or 1 Msps VDACs
Four comparators with 75 ns response time
Four uncommitted opamps with 25 mA drive capability
Four configurable multifunction analog blocks. Example con-
figurations are PGA, TIA. Mixer and Sample and hold
Low voltage, ultra low power
Wide operating voltage range: 0.5V to 5.5V
Highefficiencyboostregulatorfrom0.5Vinputto1.8Vto5.0V
output
2 mA at 6 MHz
Low power modes including:
Programming, debug, and trace
• 300 nA hibernate mode with RAM retention and LVD
• 2 µA sleep mode with real time clock and low voltage reset
JTAG(4wire), SerialWireDebug(SWD)(2wire), SingleWire
Viewer (SWV), and TRACEPORT interfaces
Cortex-M3 Flash Patch and Breakpoint (FPB) block
Cortex-M3 Embedded Trace Macrocell™ (ETM™) gener-
ates an instruction trace stream.
Cortex-M3 Data Watchpoint and Trace (DWT) generates
data trace information
Cortex-M3 Instrumentation Trace Macrocell (ITM) can be
used for printf-style debugging
Versatile I/O system
28 to 72 I/O (62 GPIO, 8 SIO, 2 USBIO[1]
)
Any GPIO to any digital or analog peripheral routability
LCD direct drive from any GPIO, up to 46x16 segments[1]
1.2V to 5.5V I/O interface voltages, up to 4 domains
Maskable, independent IRQ on any pin or port
Schmitt trigger TTL inputs
DWT, ETM, andITMblockscommunicatewithoff-chipdebug
and trace systems via the SWV or TRACEPORT
All GPIO configurable as open drain high/low, pull up/down,
High-Z, or strong output
Bootloader programming supportable through I2C, SPI,
UART, USB, and other interfaces
Configurable GPIO pin state at power on reset (POR)
25 mA sink on SIO
Precision, programmable clocking
Digital peripherals
1 to 72 MHz internal ±1% oscillator (over full temperature and
voltage range) with PLL
4 to 33 MHz crystal oscillator for crystal PPM accuracy
Internal PLL clock generation up to 80 MHz
32.768 kHz watch crystal oscillator
20 to 24 programmable PLD based Universal Digital Blocks
Full CAN 2.0b 16 RX, 8 TX buffers[1]
Full-Speed (FS) USB 2.0 12 Mbps using internal oscillator[1]
Four 16-bit configurable timer, counter, and PWM blocks
Library of standard peripherals
Low power internal oscillator at 1 kHz, 100 kHz
• 8, 16, 24, and 32-bit timers, counters, and PWMs
Temperature and packaging
• SPI, UART, I2C
-40°C to +85°C degrees industrial temperature
48-pin SSOP, 68-pin QFN, and 100-pin TQFP package
options
• Many others available in catalog
Note
1. This feature on select devices only. See Ordering Information on page 88 for details.
Cypress Semiconductor Corporation
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Document Number: 001-55036 Rev. *A
Revised December 03, 2009
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PRELIMINARY
PSoC®5:CY8C54FamilyData Sheet
Content Overview
1. ARCHITECTURAL OVERVIEW ......................................... 3
2. PINOUTS ............................................................................. 5
3. PIN DESCRIPTIONS ........................................................... 9
8.5 Programmable SC/CT Blocks .................................. 50
8.6 LCD Direct Drive ...................................................... 51
8.7 CapSense ................................................................. 52
8.8 Temp Sensor ............................................................ 52
8.9 DAC .......................................................................... 52
8.10 Up/Down Mixer ....................................................... 53
8.11 Sample and Hold .................................................... 53
4. CPU ................................................................................... 10
4.1 ARM Cortex-M3 CPU ............................................... 10
4.2 Cache Controller ...................................................... 12
4.3 DMA and PHUB ....................................................... 12
4.4 Interrupt Controller ................................................... 14
9. PROGRAMMING, DEBUG INTERFACES,
RESOURCES ........................................................................ 54
9.1 JTAG Interface ......................................................... 54
9.2 SWD Interface .......................................................... 54
9.3 Debug Features ........................................................ 55
9.4 Trace Features ......................................................... 55
9.5 SWV and TRACEPORT Interfaces .......................... 55
9.6 Programming Features ............................................. 55
9.7 Device Security ........................................................ 55
5. MEMORY .......................................................................... 15
5.1 Static RAM ............................................................... 15
5.2 Flash Program Memory ............................................ 15
5.3 Flash Security ........................................................... 15
5.4 EEPROM .................................................................. 16
5.5 External Memory Interface ....................................... 16
5.6 Memory Map ............................................................ 18
6. SYSTEM INTEGRATION .................................................. 19
6.1 Clocking System ....................................................... 19
6.2 Power System .......................................................... 22
6.3 Reset ........................................................................ 25
6.4 I/O System and Routing ........................................... 26
10. DEVELOPMENT SUPPORT ........................................... 56
10.1 Documentation ....................................................... 56
10.2 Online ..................................................................... 56
10.3 Tools ....................................................................... 56
11. ELECTRICAL SPECIFICATIONS ................................... 57
11.1 Absolute Maximum Ratings .................................... 57
11.2 Device Level Specifications .................................... 58
11.3 Power Regulators ................................................... 60
11.4 Inputs and Outputs ................................................. 61
11.5 Analog Peripherals ................................................. 66
11.6 Digital Peripherals .................................................. 75
11.7 Memory .................................................................. 78
11.8 PSoC System Resources ....................................... 83
11.9 Clocking .................................................................. 85
7. DIGITAL SUBSYSTEM ..................................................... 31
7.1 Example Peripherals ................................................ 32
7.2 Universal Digital Block .............................................. 36
7.3 UDB Array Description ............................................. 39
7.4 DSI Routing Interface Description ............................ 40
7.5 CAN .......................................................................... 41
7.6 USB .......................................................................... 43
7.7 Timers, Counters, and PWMs .................................. 44
7.8 I2C ............................................................................ 44
7.9 Digital Filter Block ..................................................... 45
12. ORDERING INFORMATION ........................................... 88
8. ANALOG SUBSYSTEM .................................................... 45
8.1 Analog Routing ......................................................... 46
8.2 Successive Approximation ADCs ............................. 48
8.3 Comparators ............................................................. 48
8.4 Opamps .................................................................... 50
12.1 Part Numbering Conventions ................................. 89
13. PACKAGING ................................................................... 90
14. REVISION HISTORY ...................................................... 92
15. SALES, SOLUTIONS, AND LEGAL INFORMATION .... 93
Document Number: 001-55036 Rev. *A
Page 2 of 93
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PRELIMINARY
PSoC®5:CY8C54FamilyData Sheet
1. Architectural Overview
Introducing the CY8C54 family of ultra low power, Flash Programmable System-on-Chip (PSoC®) devices, part of a scalable 8-bit
PSoC®3 and 32-bit PSoC 5 platform. The CY8C54 family provides configurable blocks of analog, digital, and interconnect circuitry
around a CPU subsystem. The combination of a CPU with a very flexible analog subsystem, digital subsystem, routing, and I/O
enables a high level of integration in a wide variety of consumer, industrial, and medical applications.
Figure 1-1. Simplified Block Diagram
Analog Interconnect
Digital Interconnect
SYSTEM WIDE
RESOURCES
DIGITAL SYSTEM
I2C
Master/
Slave
Universal Digital Block Array(24 x UDB)
CAN
2.0
8- Bit
Timer
Quadrature Decoder
16- Bit PRS
4- 33 MHz
( Optional)
16- Bit
PWM
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
Xtal
Osc
D+
D-
USB
PHY
UDB
8- Bit
FS USB
2.0
UDB
UDB
UDB
I 2C Slave
UDB
4x
Timer
8- Bit SPI
Logic
Timer
Counter
PWM
12- Bit SPI
UDB
UDB
UDB
UDB
UDB
IMO
Logic
32.768 KHz
( Optiona)l
UDB
UDB
UART
12- Bit PWM
RTC
Timer
SYSTEM BUS
Program&
Debug
MEMORY SYSTEM
CPU SYSTEM
WDT
and
Wake
8051or
Interrupt
EEPROM
SRAM
Program
Cortex M3 CPU
Controller
Debug&
Trace
Cache
Controller
PHUB
DMA
FLASH
EMIF
Boundary
Scan
ILO
Clocking System
ANALOG SYSTEM
Digital
Filter
Block
Power Management
System
LCD Direct
Drive
+
4 x
ADCs
2 x
Opamp
POR and
LVD
3 per
Opamp
-
SAR
ADC
4 x SC/ CT Blocks
(TIA, PGA, Mixer etc)
Sleep
Power
+
4 x
CMP
-
Temperature
Sensor
1.8V LDO
SMP
4 x DAC
CapSense
0. 5 to5.5V
( Optional)
Document Number: 001-55036 Rev. *A
Page 3 of 93
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PRELIMINARY
PSoC®5:CY8C54FamilyData Sheet
Figure 1-1 illustrates the major components of the CY8C54
family. They are:
errors and SNR better than 70 dB. They are well suited for a
variety of higher speed analog applications.
The output of either ADC can optionally feed the programmable
DFB via Direct Memory Access (DMA) without CPU intervention.
The designer can configure the DFB to perform IIR and FIR
digital filters and several user defined custom functions. The
DFB can implement filters with up to 64 taps. It can perform a
48-bit multiply-accumulate (MAC) operation in one clock cycle.
ARM Cortex-M3 CPU Subsystem
Nonvolatile Subsystem
Programming, Debug, and Test Subsystem
Inputs and Outputs
Four high speed voltage or current DACs support 8-bit output
signals at waveform frequencies of up to 8 MHz. They can be
routed out of any GPIO pin. You can create higher resolution
voltage DAC outputs using the UDB array. This can be used to
create a pulse width modulated (PWM) DAC of up to 10 bits, at
up to 48 kHz. The digital DACs in each UDB support PWM, PRS,
or delta-sigma algorithms with programmable widths.
Clocking
Power
Digital Subsystem
Analog Subsystem
PSoC’s digital subsystem provides half of its unique config-
urability. It connects a digital signal from any peripheral to any
pin through the Digital System Interconnect (DSI). It also
provides functional flexibility through an array of small, fast, low
power Universal Digital Blocks (UDBs). PSoC Creator provides
a library of pre-built and tested standard digital peripherals
(UART, SPI, LIN, PRS, CRC, timer, counter, PWM, AND, OR,
and so on) that are mapped to the UDB array. The designer can
also easily create a digital circuit using boolean primitives by
means of graphical design entry. Each UDB contains Program-
mable Array Logic (PAL)/Programmable Logic Device (PLD)
functionality, together with a small state machine engine to
support a wide variety of peripherals.
In addition to the ADCs, DACs, and DFB, the analog subsystem
provides multiple:
Comparators
Uncommitted opamps
Configurable Switched Capacitor/Continuous Time (SC/CT)
blocks. These support:
Transimpedance amplifiers
Programmable gain amplifiers
Mixers
Other similar analog components
In addition to the flexibility of the UDB array, PSoC also provides
configurable digital blocks targeted at specific functions. For the
CY8C54 family these blocks can include four 16-bit timer,
counter, and PWM blocks; I2C slave, master, and multi-master;
Full-Speed USB; and Full CAN 2.0b.
See the “Analog Subsystem” section on page 45 of this data
sheet for more details.
PSoC’s CPU subsystem is built around a 32-bit three-stage
pipelined ARM Cortex-M3 processor running at up to 80 MHz.
The Cortex-M3 includes a tightly integrated nested vectored
interrupt controller (NVIC) and various debug and trace modules.
The overall CPU subsystem includes a DMA controller, Flash
cache, and RAM. The NVIC provides low latency, nested inter-
rupts, and tail-chaining of interrupts and other features to
increase the efficiency of interrupt handling. The DMA controller
enables peripherals to exchange data without CPU involvement.
This allows the CPU to run slower (saving power) or use those
CPU cycles to improve the performance of firmware algorithms.
The Flash cache also reduces system power consumption by
allowing less frequent Flash access.
For more details on the peripherals see the “Example Periph-
erals” section on page 32 of this data sheet. For information on
UDBs, DSI, and other digital blocks, see the “Digital Subsystem”
section on page 32 of this data sheet.
PSoC’s analog subsystem is the second half of its unique config-
urability. All analog performance is based on a highly accurate
absolute voltage reference with less than 0.1% error over
temperature and voltage. The configurable analog subsystem
includes:
Analog muxes
PSoC’s nonvolatile subsystem consists of Flash, byte-writeable
EEPROM, and nonvolatile configuration options. It provides up
to 256 KB of on-chip Flash. The CPU can reprogram individual
blocks of Flash, enabling boot loaders. The designer can enable
an Error Correcting Code (ECC) for high reliability applications.
A powerful and flexible protection model secures the user's
sensitive information, allowing selective memory block locking
for read and write protection. Two KB of byte-writable EEPROM
is available on-chip to store application data. Additionally,
selected configuration options such as boot speed and pin drive
mode are stored in nonvolatile memory. This allows settings to
activate immediately after power on reset (POR).
Comparators
Analog mixers
Voltage references
Analog-to-Digital Converters (ADCs)
Digital-to-Analog Converters (DACs)
Digital Filter Block (DFB)
All GPIO pins can route analog signals into and out of the device
using the internal analog bus. This allows the device to interface
up to 62 discrete analog signals.
The three types of PSoC I/O are extremely flexible. All I/Os have
many drive modes that are set at POR. PSoC also provides up
to four I/O voltage domains through the Vddio pins. Every GPIO
has analog I/O, LCD drive, flexible interrupt generation, slew rate
control, and digital I/O capability. The SIOs on PSoC allow Voh
to be set independently of Vddio when used as outputs. When
The CY8C54 family offers two Successive Approximation
Register (SAR) ADCs. Featuring 12-bit conversions at up to 1M
samples per second, they also offer low nonlinearity and offset
Document Number: 001-55036 Rev. *A
Page 4 of 93
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PRELIMINARY
PSoC®5:CY8C54FamilyData Sheet
SIOs are in input mode they are high impedance. This is true
even when the device is not powered or when the pin voltage
goes above the supply voltage. This makes the SIO ideally suited
for use on an I2C bus where the PSoC may not be powered when
other devices on the bus are. The SIO pins also have high
current sink capability for applications such as LED drives. The
programmable input threshold feature of the SIO can be used to
make the SIO function as a general purpose analog comparator.
For devices with Full-Speed USB the USB physical interface is
also provided (USBIO). When not using USB these pins may
also be used for limited digital functionality and device
programming. All the features of the PSoC I/Os are covered in
detail in the “I/O System and Routing” section on page 26 of this
data sheet.
Vboost pin, allowing other devices in the application to be
powered from the PSoC.
PSoC supports a wide range of low power modes. These include
a 300 nA hibernate mode with RAM retention and a 2 µA sleep
mode with real time clock (RTC). In the second mode the
optional 32.768 kHz watch crystal runs continuously and
maintains an accurate RTC.
Power to all major functional blocks, including the programmable
digital and analog peripherals, can be controlled independently
by firmware. This allows low power background processing
when some peripherals are not in use. This, in turn, provides a
total device current of only 2 mA when the CPU is running at
6 MHz.
The details of the PSoC power modes are covered in the “Power
System” section on page 22 of this data sheet.
The PSoC device incorporates flexible internal clock generators,
designed for high stability, and factory trimmed for absolute
accuracy. The Internal Main Oscillator (IMO) is the master clock
base for the system with 1% absolute accuracy at 3 MHz. The
IMO can be configured to run from 3 MHz up to 72 MHz. Multiple
clock derivatives can be generated from the main clock
frequency to meet application needs. The device provides a PLL
to generate system clock frequencies up to 79 MHz (80 MHz
including +1% tolerance) from the IMO, external crystal, or
external reference clock. It also contains a separate, very low
power Internal Low Speed Oscillator (ILO) for the sleep and
watchdog timers. A 32.768 kHz external watch crystal is also
supported for use in Real Time Clock (RTC) applications. The
clocks, together with programmable clock dividers, provide the
flexibility to integrate most timing requirements.
PSoC uses JTAG (4 wire) or Serial Wire Debug (SWD) (2 wire)
interfaces for programming, debug, and test. Using these
standard interfaces enables the designer to debug or program
the PSoC with a variety of hardware solutions from Cypress or
third party vendors. The Cortex-M3 debug and trace modules
include Flash Patch and Breakpoint (FPB), Data Watchpoint and
Trace (DWT), Embedded Trace Macrocell (ETM), and Instru-
mentation Trace Macrocell (ITM). These modules have many
features to help solve difficult debug and trace problems. Details
of the programming, test, and debugging interfaces are
discussed in the “Programming, Debug Interfaces, Resources”
section on page 54 of this data sheet.
2. Pinouts
The CY8C54 family supports a wide supply operating range from
1.71 to 5.5V. This allows operation from regulated supplies such
as 1.8 ± 5%, 2.5V ±10%, 3.3V ± 10%, or 5.0V ± 10%, or directly
from a wide range of battery types. In addition, it provides an
integrated high efficiency synchronous boost converter that can
power the device from supply voltages as low as 0.5V. This
enables the device to be powered directly from a single battery
or solar cell. In addition, the designer can use the boost converter
to generate other voltages required by the device, such as a 3.3V
supply for LCD glass drive. The boost’s output is available on the
The Vddio pin that supplies a particular set of pins is indicated
by the black lines drawn on the pinout diagrams in Figure 2-1
through Figure 2-3. Using the Vddio pins, a single PSoC can
support multiple interface voltage levels, eliminating the need for
off-chip level shifters. Each Vddio may sink up to 100 mA total to
its associated I/O pins and opamps. On the 68 pin and 100 pin
devices each set of Vddio associated pins may sink up to 100
mA. The 48 pin device may sink up to 100 mA total for all Vddio0
plus Vddio2 associated I/O pins and 100 mA total for all Vddio1
plus Vddio3 associated I/O pins.
Document Number: 001-55036 Rev. *A
Page 5 of 93
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PRELIMINARY
PSoC®5:CY8C54FamilyData Sheet
[2]
Figure 2-1. 48-Pin SSOP Part Pinout
(SIO) P12[2]
(SIO) P12[3]
Vdda
Vssa
1
2
3
4
5
6
7
8
9
48
47
Lines show
Vddio to I/O
supply
(OpAmp2out, GPIO) P0[0]
(OpAmp0out, GPIO) P0[1]
(OpAmp0+, GPIO) P0[2]
(OpAmp0-/Extref0, GPIO) P0[3]
Vddio0
46 Vcca
45 P15[3] (GPIO, kHz XTAL: Xi)
44 P15[2] (GPIO, kHz XTAL: Xo)
association
P12[1] (SIO, I2C1: SDA)
43
42 P12[0] (SIO, I2C1: SCL)
41 Vddio3
(OpAmp2+, GPIO) P0[4]
(OpAmp2-, GPIO) P0[5]
40 P15[1] (GPIO, MHz XTAL: Xi)
39 P15[0] (GPIO, MHz XTAL: Xo)
(IDAC0, GPIO) P0[6] 10
(IDAC2, GPIO) P0[7]
Vccd 12
Vssd
Vddd 14
Vccd
37 Vssd
Vddd
35 P15[7] (USBIO, D-, SWDCK)
11
38
SSOP
13
36
[2]
[2]
(TRACECLK, GPIO) P2[3]
P15[6] (USBIO, D+, SWDIO)
P1[7] (GPIO)
15
16
17
18
34
33
32
31
(TRACEDATA[0], GPIO) P2[4]
Vddio2
P1[6] (GPIO)
(TRACEDATA[1], GPIO) P2[5]
Vddio1
(TRACEDATA[2], GPIO) P2[6] 19
30 P1[5] (GPIO, nTRST)
(TRACEDATA[3], GPIO) P2[7]
P1[4] (GPIO, TDI)
20
21
22
29
28
27
Vssb
Ind
P1[3] (GPIO, TDO, SWV)
P1[2] (GPIO, configurable XRES)
Vboost 23
Vbat 24
26 P1[1] (GPIO, TCK, SWDCK)
25 P1[0] (GPIO, TMS, SWDIO)
Figure 2-2. 68-Pin QFN Part Pinout[3]
(TRACEDATA[2], GPIO) P2[6]
(TRACEDATA[3], GPIO) P2[7]
(I2C0: SCL, SIO) P12[4]
P0[3] (GPIO, OpAmp0-/Extref0)
P0[2] (GPIO, OpAmp0+)
1
2
3
51
50
P0[1] (GPIO, OpAmp0out)
P0[0] (GPIO, OpAmp2out)
49
48
47
Lines show Vddio
to IO supply
association
(I2C0: SDA, SIO) P12[5]
4
Vssb
Ind
5
P12[3] (SIO)
P12[2] (SIO)
Vssd
Vdda
Vssa
46
45
6
Vboost
Vbat
7
8
9
44
43
42
41
QFN
(Top View)
Vssd
Vcca
10
XRES
(TMS, SWDIO, GPIO) P1[0]
(TCK, SWDCK, GPIO) P1[1]
(configurable XRES, GPIO) P1[2]
P15[3] (GPIO, kHz XTAL: Xi)
P15[2] (GPIO, kHz XTAL: Xo)
11
12
13
40
39
P12[1] (SIO, I2C1: SDA)
P12[0] (SIO, 12C1: SCL)
(TDO, SWV, GPIO) P1[3] 14
38
37
36
35
(TDI, GPIO) P1[4]
(nTRST, GPIO) P1[5]
Vddio1
15
16
17
P3[7] (GPIO, OpAmp3out)
P3[6] (GPIO, OpAmp1out)
Vddio3
Notes
2. Pins are No Connect (NC) on devices without USB. NC means that the pin has no electrical connection. The pin can be left floating or tied to a supply voltage or ground.
3. The center pad on the QFN package should be connected to digital ground (Vssd) for best mechanical, thermal, and electrical performance. If not connected to
ground, it should be electrically floated and not connected to any other signal.
Document Number: 001-55036 Rev. *A
Page 6 of 93
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PRELIMINARY
PSoC®5:CY8C54FamilyData Sheet
Figure 2-3. 100-Pin TQFP Part Pinout
(TRACEDATA[1], GPIO) P2[5]
(TRACEDATA[2], GPIO) P2[6]
(TRACEDATA[3], GPIO) P2[7]
Vddio0
1
2
3
4
75
74
P0[3] (GPIO, OpAmp0-/Extref0)
P0[2] (GPIO, OpAmp0+)
P0[1] (GPIO, OpAmp0out)
73
72
71
Lines show Vddio
to IO supply
association
(I2C0: SCL, SIO) P12[4]
(I2C0: SDA, SIO) P12[5]
(GPIO) P6[4]
5
6
P0[0] (GPIO, OpAmp2out)
P4[1] (GPIO)
P4[0] (GPIO)
P12[3] (SIO)
P12[2] (SIO)
Vssd
70
69
(GPIO) P6[5]
(GPIO) P6[6]
(GPIO) P6[7]
7
8
9
10
68
67
66
Vssb
Ind
Vboost
Vbat
Vdda
Vssa
11
12
13
14
15
16
17
65
64
63
Vcca
NC
TQFP
Vssd
XRES
(GPIO) P5[0]
(GPIO) P5[1]
62
61
60
NC
NC
NC
NC
59
58
57
56
55
(GPIO) P5[2]
(GPIO) P5[3]
(TMS, SWDIO, GPIO) P1[0]
18
19
20
21
22
NC
P15[3] (GPIO, kHz XTAL: Xi)
P15[2] (GPIO, kHz XTAL: Xo)
(TCK, SWDCK, GPIO) P1[1]
(configurable XRES, GPIO) P1[2]
(TDO, SWV, GPIO) P1[3]
P12[1] (SIO, I2C1: SDA)
P12[0] (SIO, I2C1: SCL)
P3[7] (GPIO, OpAmp3out)
54
53
23
52
51
(TDI, GPIO) P1[4]
(nTRST, GPIO) P1[5]
24
25
P3[6] (GPIO, OpAmp1out)
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Figure 2-4 and Figure 2-5 show an example schematic and an
example PCB layout, for the 100-pin TQFP part, for optimal
analog performance on a 2-layer board.
Figure 2-4 and Power System on page 22. The trace between
the two Vccd pins should be as short as possible.
The two pins labeled Vssd must be connected together.
The two pins labeled Vddd must be connected together.
The two pins labeled Vccd must be connected together, and
have capacitors connected between them as shown in
Figure 2-4. Example Schematic for 100-Pin TQFP Part with Power Connections
Vddd
Vddd
Vccd
C1
C2
C3
0.1uF
Vddd
Vssd
1uF
0.1uF
C6
0.1uF
Vssd
Vssd
Vssd
U2
CY8C55xx
Vdda
Vddd
Vssd
1
2
3
4
5
6
7
8
9
75
P2[5]
P2[6]
P2[7]
P12[4], SIO
P12[5], SIO
P6[4]
P6[5]
P6[6]
P6[7]
Vssb
Ind
Vboost
Vbat
Vssd
XRES
P5[0]
P5[1]
P5[2]
P5[3]
P1[0], SWIO, TMS
P1[1], SWDIO, TCK
P1[2]
P1[3], SWV, TDO
P1[4], TDI
P1[5], nTRST
Vddio0
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
OA0-, REF0, P0[3]
OA0+, P0[2]
OA0out, P0[1]
OA2out, P0[0]
P4[1]
C8
0.1uF
C13
1uF
P4[0]
Vssa
SIO, P12[3]
SIO, P12[2]
Vssd
Vssd
Vssd
Vdda
Vssa
Vcca
Vdda
10
Vddd
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
Vdda
Vssa
Vcca
NC
NC
NC
NC
NC
Vssd
Vssd
C9
C10
0.1uF
1uF
NC
Vssa
kHzXin, P15[3]
kHzXout, P15[2]
SIO, P12[1]
SIO, P12[0]
OA3out, P3[7]
OA1out, P3[6]
Vddd
Vddd
C11
C12
0.1uF
0.1uF
Vssd
C15
1uF
C16
0.1uF
Vssd
Vssd
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Figure 2-5. Example PCB Layout for 100-Pin TQFP Part for Optimal Analog Performance
VSSA
VSSD
VDDD
VDDA
VSSA
Plane
VSSD
Plane
analog comparator, high sink current, and high impedance state
when the device is unpowered.
3. Pin Descriptions
IDAC0, IDAC1, IDAC2, IDAC3. Low resistance output pin for
high current DACs (IDAC).
SWDCK. Serial Wire Debug Clock programming and debug port
connection.
OpAmp0out, OpAmp1out, OpAmp2out, OpAmp3out. High
SWDIO. Serial Wire Debug Input and Output programming and
debug port connection.
current output of uncommitted opamp[4]
.
Extref0, Extref1. External reference input to the analog system.
TCK. JTAG Test Clock programming and debug port connection.
OpAmp0-, OpAmp1-, OpAmp2-, OpAmp3-. Inverting input to
uncommitted opamp.
TDI. JTAG Test Data In programming and debug port
connection.
OpAmp0+, OpAmp1+, OpAmp2+, OpAmp3+. Noninverting
input to uncommitted opamp.
TDO. JTAG Test Data Out programming and debug port
connection.
GPIO. General purpose I/O pin provides interfaces to the CPU,
TMS. JTAG Test Mode Select programming and debug port
connection.
digital peripherals, analog peripherals, interrupts, LCD segment
drive, and CapSense®[4]
.
TRACECLK. Cortex-M3 TRACEPORT connection, clocks
TRACEDATA pins.
I2C0: SCL, I2C1: SCL. I2C SCL line providing wake from sleep
on an address match. Any I/O pin can be used for I2C SCL if
wake from sleep is not required.
TRACEDATA[3:0]. Cortex-M3 TRACEPORT connections,
output data.
I2C0: SDA, I2C1: SDA. I2C SDA line providing wake from sleep
on an address match. Any I/O pin can be used for I2C SDA if
wake from sleep is not required.
SWV. Single Wire Viewer output.
USBIO, D+. Provides D+ connection directly to a USB 2.0 bus.
May be used as a digital I/O pin; it is powered from Vddd instead
of from a Vddio. Pins are No Connect (NC) on devices without
USB.[2]
Ind. Inductor connection to boost pump.
kHz XTAL: Xo, kHz XTAL: Xi. 32.768 kHz crystal oscillator pin.
MHz XTAL: Xo, MHz XTAL: Xi. 4 to 33 MHz crystal oscillator
pin.
USBIO, D-. Provides D- connection directly to a USB 2.0 bus.
May be used as a digital I/O pin; it is powered from Vddd instead
of from a Vddio. Pins are No Connect (NC) on devices without
USB.[2]
nTRST. Optional JTAG Test Reset programming and debug port
connection to reset the JTAG connection.
SIO. Special I/O provides interfaces to the CPU, digital periph-
erals and interrupts with a programmable high threshold voltage,
Vboost. Power sense connection to boost pump.
Vbat. Battery supply to boost pump.
Note
4. GPIOs with OpAmp outputs are not recommended for use with CapSense.
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Vcca. Output of analog core regulator and input to analog core.
Requires a 1 µF capacitor to Vssa. Regulator output not for
external use.
Vssd. Ground for all digital logic and I/O pins.
Vddio0, Vddio1, Vddio2, Vddio3. Supply for I/O pins. See
pinouts for specific I/O pin to Vddio mapping. Vddio must be less
than or equal to Vdda.
Vccd. Output of digital core regulator and input to digital core.
Requires a capacitor from each Vccd pin to Vssd; see Power
System on page 22. Regulator output not for external use.
XRES (and configurable XRES). External reset pin. Active low
with internal pullup. In 48-pin SSOP parts, P1[2] is configured as
XRES. In all other parts the pin is configured as a GPIO.
Vdda. Supply for all analog peripherals and analog core
regulator. Vdda must be the highest voltage present on the
device. All other supply pins must be less than or equal to
Vdda.
4. CPU
Vddd. Supply for all digital peripherals and digital core regulator.
Vddd must be less than or equal to Vdda.
4.1 ARM Cortex-M3 CPU
The CY8C54 family of devices has an ARM Cortex-M3 CPU
core. The Cortex-M3 is a low power 32-bit three-stage pipelined
Harvard architecture CPU that delivers 1.25 DMIPS/MHz. It is
intended for deeply embedded applications that require fast
interrupt handling features.
Vssa. Ground for all analog peripherals.
Vssb. Ground connection for boost pump.
Figure 4-1. ARM Cortex-M3 Block Diagram
Data
Watchpoint and
Trace (DWT)
Nested
Interrupt Inputs
Cortex M3 CPU Core
Vectored
Interrupt
Controller
(NVIC)
Embedded
Trace Module
(ETM)
Instrumentation
Trace Module
(ITM)
D-Bus
C-Bus
I-Bus
S-Bus
Trace Pins:
5 for TRACEPORT or
1 for SWV mode
Debug Block
(Serial and
JTAG)
Trace Port
Interface Unit
(TPIU)
JTAG/SWD
Flash Patch
and Breakpoint
(FPB)
Cortex M3 Wrapper
AHB
AHB
32 KB
SRAM
Bus
Matrix
Bus
Matrix
256 KB
ECC
Cache
Flash
AHB
32 KB
SRAM
Bus
Matrix
AHB Bridge & Bus Matrix
DMA
PHUB
AHB Spokes
GPIO &
EMIF
Prog.
Digital
Prog.
Analog
Special
Functions
Peripherals
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The Cortex-M3 CPU subsystem includes these features:
At the user level, access to certain instructions, special registers,
configuration registers, and debugging components is blocked.
Attempts to access them cause a fault exception. At the privi-
leged level, access to all instructions and registers is allowed.
ARM Cortex-M3 CPU
Programmable Nested Vectored Interrupt Controller (NVIC),
tightly integrated with the CPU core
The processor runs in the handler mode (always at the privileged
level) when handling an exception, and in the thread mode when
not.
Full featured debug and trace modules, tightly integrated with
the CPU core
4.1.3 CPU Registers
Up to 256 KB of Flash memory, 2 KB of EEPROM, and 64 KB
of SRAM
The Cortex-M3 CPU registers are listed in Table 4-2. Registers
R0-R15 are all 32 bits wide.
Cache controller
Table 4-2. Cortex M3 CPU Registers
Peripheral HUB (PHUB)
DMA controller
Register
R0-R12
Description
General purpose registers R0-R12 have no
special architecturally defined uses. Most
instructions that specify a general purpose
register specify R0-R12.
External Memory Interface (EMIF)
4.1.1 Cortex-M3 Features
The Cortex-M3 CPU features include:
Low Registers: Registers R0-R7 are acces-
sible by all instructions that specify a general
purpose register.
4 GB address space. Predefined address regions for code,
data, and peripherals. Multiple buses for efficient and simulta-
neous accesses of instructions, data, and peripherals.
High Registers: Registers R8-R12 are acces-
sible by all 32-bit instructions that specify a
general purpose register; they are not acces-
sible by all 16-bit instructions.
The Thumb®-2 instruction set, which offers ARM-level perfor-
mance at Thumb-level code density. This includes 16-bit and
32-bit instructions. Advanced instructions include:
Bit-field control
Hardware multiply and divide
Saturation
R13
R13 is the stack pointer register. It is a banked
register that switches between two 32-bit stack
pointers: the Main Stack Pointer (MSP) and the
Process Stack Pointer (PSP). The PSP is used
only when the CPU operates at the user level in
thread mode. The MSP is used in all other
privilege levels and modes. Bits[0:1] of the SP
are ignored and considered to be 0, so the SP is
always aligned to a word (4 byte) boundary.
If-Then
Wait for events and interrupts
Exclusive access and barrier
Special register access
The Cortex-M3 does not support ARM instructions.
R14
R15
R14 is the Link Register (LR). The LR stores the
return address when a subroutine is called.
Bit-band support. Atomic bit-level write and read operations.
Unaligned data storage and access. Contiguous storage of
data of different byte lengths.
R15 is the Program Counter (PC). Bit 0 of the PC
is ignoredand consideredto be0, so instructions
are always aligned to a half word (2 byte)
boundary.
Operation at two privilege levels (privileged and user) and in
two modes (thread and handler). Some instructions can only
be executed at the privileged level. There are also two stack
pointers: Main (MSP) and Process (PSP). These features
support a multitasking operating system running one or more
user-level processes.
xPSR
The Program status registers are divided into
three status registers, which are accessed either
together or separately:
Application Program Status Register (APSR)
holds program execution status bits such as
zero, carry, negative, in bits[27:31].
Extensive interrupt and system exception support.
4.1.2 Cortex-M3 Operating Modes
Interrupt Program Status Register (IPSR)
holds the current exception number in bits[0:8].
The Cortex-M3 operates at either the privileged level or the user
level, and in either the thread mode or the handler mode.
Because the handler mode is only enabled at the privileged level,
there are actually only three states, as shown in Table 4-1.
Execution Program Status Register (EPSR)
holds control bits for interrupt continuable and
IF-THEN instructions in bits[10:15] and
[25:26]. Bit 24 is always set to 1 to indicate
Thumb mode. Trying to clear it causes a fault
exception.
Table 4-1. Operational Level
Condition
Privileged
User
Running an exception Handler mode Not used
Running main program Thread mode
Thread mode
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Table 4-2. Cortex M3 CPU Registers (continued)
Table 4-3. PHUB Spokes and Peripherals
Register
Description
PHUB Spokes
Peripherals
PRIMASK
A 1-bit interrupt mask register. When set, it
allows only the nonmaskable interrupt (NMI) and
hard fault exception. All other exceptions and
interrupts are masked.
0
1
2
SRAM
IOs, PICU, EMIF
PHUB local configuration, Power manager,
Clocks, IC, SWV, EEPROM, Flash
programming interface
FAULTMASK A 1-bit interrupt mask register. When set, it
allows only the NMI. All other exceptions and
interrupts are masked.
3
4
5
6
7
Analog interface and trim, Decimator
USB, CAN, I2C, Timers, Counters, and PWMs
BASEPRI
A register of up to nine bits that define the
masking priority level. When set, it disables all
interrupts of the same or higher priority value. If
set to 0 then the masking function is disabled.
DFB
UDBs group 1
UDBs group 2
CONTROL
A 2-bit register for controlling the operating
mode.
Bit 0: 0 = privileged level in thread mode, 1 = user
level in thread mode.
4.3.2 DMA Features
24 DMA channels
Bit 1: 0 = default stack (MSP) is used, 1 =
alternate stack is used. If in thread mode or user
level then the alternate stack is the PSP. There
is no alternate stack for handler mode; the bit
must be 0 while in handler mode.
Each channel has one or more Transaction Descriptors (TDs)
to configure channel behavior. Up to 128 total TDs can be
defined
TDs can be dynamically updated
Eight levels of priority per channel
4.2 Cache Controller
The CY8C54 family adds an instruction cache between the CPU
and the Flash memory. This guarantees a faster instruction
execution rate. The Flash cache also reduces system power
consumption by requiring less frequent Flash access.
Anydigitallyroutablesignal, theCPU, oranotherDMAchannel,
can trigger a transaction
Each channel can generate up to two interrupts per transfer
Transactions can be stalled or canceled
4.3 DMA and PHUB
Supports transaction size of infinite or 1 to 64k bytes
The PHUB and the DMA controller are responsible for data
transfer between the CPU and peripherals, and also data
transfers between peripherals. The PHUB and DMA also control
device configuration during boot. The PHUB consists of:
Large transactions may be broken into smaller bursts of 1 to
127 bytes
TDs may be nested and/or chained for complex transactions
A central hub that includes the DMA controller, arbiter, and
router
4.3.3 Priority Levels
The CPU always has higher priority than the DMA controller
when their accesses require the same bus resources. Due to the
system architecture, the CPU can never starve the DMA. DMA
channels of higher priority (lower priority number) may interrupt
current DMA transfers. In the case of an interrupt, the current
transfer is allowed to complete its current transaction. To ensure
latency limits when multiple DMA accesses are requested simul-
taneously, a fairness algorithm guarantees an interleaved
minimum percentage of bus bandwidth for priority levels 2
through 7. Priority levels 0 and 1 do not take part in the fairness
algorithm and may use 100% of the bus bandwidth. If a tie occurs
on two DMA requests of the same priority level, a simple round
robin method is used to evenly share the allocated bandwidth.
The round robin allocation can be disabled for each DMA
channel, allowing it to always be at the head of the line. Priority
levels 2 to 7 are guaranteed the minimum bus bandwidth shown
in Table 4-4 after the CPU and DMA priority levels 0 and 1 have
satisfied their requirements.
Multiple spokes that radiate outward from the hub to most
peripherals
There are two PHUB masters: the CPU and the DMA controller.
Both masters may initiate transactions on the bus. The DMA
channels can handle peripheral communication without CPU
intervention. The arbiter in the central hub determines which
DMA channel is the highest priority if there are multiple requests.
4.3.1 PHUB Features
CPU and DMA controller are both bus masters to the PHUB
Eight Multi-layer AHB Bus parallel access paths (spokes) for
peripheral access
Simultaneous CPU and DMA access to peripherals located on
different spokes
Simultaneous DMA source and destination burst transactions
on different spokes
When the fairness algorithm is disabled, DMA access is granted
based solely on the priority level; no bus bandwidth guarantees
are made.
Supports 8, 16, 24, and 32-bit addressing and data
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Table 4-4. Priority Levels
the peripheral and writes that value into a subsequent TD in the
chain. This modifies the TD chain on the fly. When the “address
fetch” TD completes it moves on to the next TD, which has the
new address information embedded in it. This TD then carries
out the data transfer with the address location required by the
external master.
Priority Level
% Bus Bandwidth
0
1
2
3
4
5
6
7
100.0
100.0
50.0
25.0
12.5
6.2
4.3.4.6 Scatter Gather DMA
In the case of scatter gather DMA, there are multiple noncon-
tiguous sources or destinations that are required to effectively
carry out an overall DMA transaction. For example, a packet may
need to be transmitted off of the device and the packet elements,
including the header, payload, and trailer, exist in various
noncontiguous locations in memory. Scatter gather DMA allows
the segments to be concatenated together by using multiple TDs
in a chain. The chain gathers the data from the multiple locations.
A similar concept applies for the reception of data onto the
device. Certain parts of the received data may need to be
scattered to various locations in memory for software processing
convenience. Each TD in the chain specifies the location for
each discrete element in the chain.
3.1
1.5
4.3.4 Transaction Modes Supported
The flexible configuration of each DMA channel and the ability to
chain multiple channels allow the creation of both simple and
complex use cases. General use cases include, but are not
limited to:
4.3.4.1 Simple DMA
4.3.4.7 Packet Queuing DMA
In a simple DMA case, a single TD transfers data between a
source and sink (peripherals or memory location).
Packet queuing DMA is similar to scatter gather DMA but specif-
ically refers to packet protocols. With these protocols, there may
be separate configuration, data, and status phases associated
with sending or receiving a packet.
4.3.4.2 Auto Repeat DMA
Auto repeat DMA is typically used when a static pattern is repet-
itively read from system memory and written to a peripheral. This
is done with a single TD that chains to itself.
For instance, to transmit a packet, a memory mapped configu-
ration register can be written inside a peripheral, specifying the
overall length of the ensuing data phase. The CPU can set up
this configuration information anywhere in system memory and
copy it with a simple TD to the peripheral. After the configuration
phase, a data phase TD (or a series of data phase TDs) can
begin (potentially using scatter gather). When the data phase
TD(s) finish, a status phase TD can be invoked that reads some
memory mapped status information from the peripheral and
copies it to a location in system memory specified by the CPU
for later inspection. Multiple sets of configuration, data, and
status phase “subchains” can be strung together to create larger
chains that transmit multiple packets in this way. A similar
concept exists in the opposite direction to receive the packets.
4.3.4.3 Ping Pong DMA
A ping pong DMA case uses double buffering to allow one buffer
to be filled by one client while another client is consuming the
data previously received in the other buffer. In its simplest form,
this is done by chaining two TDs together so that each TD calls
the opposite TD when complete.
4.3.4.4 Circular DMA
Circular DMA is similar to ping pong DMA except it contains more
than two buffers. In this case there are multiple TDs; after the last
TD is complete it chains back to the first TD.
4.3.4.8 Nested DMA
4.3.4.5 Indexed DMA
One TD may modify another TD, as the TD configuration space
is memory mapped similar to any other peripheral. For example,
a first TD loads a second TD’s configuration and then calls the
second TD. The second TD moves data as required by the appli-
cation. When complete, the second TD calls the first TD, which
again updates the second TD’s configuration. This process
repeats as often as necessary.
In an indexed DMA case, an external master requires access to
locations on the system bus as if those locations were shared
memory. As an example, a peripheral may be configured as an
SPI or I2C slave where an address is received by the external
master. That address becomes an index or offset into the internal
system bus memory space. This is accomplished with an initial
“address fetch” TD that reads the target address location from
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4.4 Interrupt Controller
The Cortex-M3 NVIC supports 16 system exceptions and 32
interrupts from peripherals, as shown in Table 4-5.
Table 4-5. Cortex-M3 Exceptions and Interrupts
Exception
Number
Exception Table
Address Offset
Exception Type
Priority
Function
0x00
0x04
0x08
0x0C
Starting value of R13 / MSP
Reset
1
2
3
Reset
-3 (highest)
NMI
-2
-1
Non maskable interrupt
Hard fault
All classesoffault, whenthecorrespondingfaulthandler
cannot be activated because it is currently disabled or
masked
4
5
6
MemManage
Bus fault
Programmable
Programmable
Programmable
0x10
0x14
0x18
Memory management fault, for example, instruction
fetch from a nonexecutable region
Error response received from the bus system; caused
by an instruction prefetch abort or data access error
Usage fault
Typically caused by invalid instructions or trying to
switch to ARM mode
7 – 10
11
-
-
0x1C – 0x28
0x2C
Reserved
SVC
Programmable
Programmable
-
System service call via SVC instruction
Debug monitor
12
Debug monitor
-
0x30
13
0x34
Reserved
14
PendSV
SYSTICK
IRQ
Programmable
Programmable
Programmable
0x38
Deferred request for system service
System tick timer
15
0x3C
16 – 47
0x40 – 0x3FC
Peripheral interrupt request #0 - #31
Bit 0 of each exception vector indicates whether the exception is
executed using ARM or Thumb instructions. Because the
Cortex-M3 only supports Thumb instructions, this bit must
always be 1. The Cortex-M3 non maskable interrupt (NMI) input
can be routed to any pin, via the DSI, or disconnected from all
pins. See “DSI Routing Interface Description” section on
page 40.
Support for tail-chaining, and late arrival, of interrupts. This
enables back-to-back interrupt processing without the
overhead of state saving and restoration between interrupts.
Processor state automatically saved on interrupt entry, and
restored on interrupt exit, with no instruction overhead.
If the same priority level is assigned to two or more interrupts,
the interrupt with the lower vector number is executed first. Each
interrupt vector may choose from three interrupt sources: Fixed
Function, DMA, and UDB. The fixed function interrupts are direct
connections to the most common interrupt sources and provide
the lowest resource cost connection. The DMA interrupt sources
provide direct connections to the two DMA interrupt sources
provided per DMA channel. The third interrupt source for vectors
is from the UDB digital routing array. This allows any digital signal
available to the UDB array to be used as an interrupt source. All
interrupt sources may be routed to any interrupt vector using the
UDB interrupt source connections.
The Nested Vectored Interrupt Controller (NVIC) handles inter-
rupts from the peripherals, and passes the interrupt vectors to
the CPU. It is closely integrated with the CPU for low latency
interrupt handling. Features include:
32 interrupts. Multiple sources for each interrupt.
Configurable number of priority levels: from 3 to 8.
Dynamic reprioritization of interrupts.
Priority Grouping. This allows selection of preempting and non
preempting interrupt levels.
Table 4-6. Interrupt Vector Table
Interrupt # Cortex-M3 Exception #
Fixed Function
Low voltage detect (LVD) phub_termout0[0]
DMA
UDB
udb_intr[0]
udb_intr[1]
udb_intr[2]
udb_intr[3]
udb_intr[4]
udb_intr[5]
0
1
2
3
4
5
16
17
18
19
20
21
Cache/ECC
Reserved
Sleep (Pwr Mgr)
PICU[0]
phub_termout0[1]
phub_termout0[2]
phub_termout0[3]
phub_termout0[4]
phub_termout0[5]
PICU[1]
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Table 4-6. Interrupt Vector Table (continued)
Interrupt # Cortex-M3 Exception # Fixed Function
PICU[2]
DMA
UDB
udb_intr[6]
udb_intr[7]
udb_intr[8]
udb_intr[9]
udb_intr[10]
udb_intr[11]
udb_intr[12]
udb_intr[13]
udb_intr[14]
udb_intr[15]
udb_intr[16]
udb_intr[17]
udb_intr[18]
udb_intr[19]
udb_intr[20]
udb_intr[21]
udb_intr[22]
udb_intr[23]
udb_intr[24]
udb_intr[25]
udb_intr[26]
udb_intr[27]
udb_intr[28]
udb_intr[29]
udb_intr[30]
udb_intr[31]
6
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
phub_termout0[6]
phub_termout0[7]
phub_termout0[8]
phub_termout0[9]
phub_termout0[10]
phub_termout0[11]
phub_termout0[12]
phub_termout0[13]
phub_termout0[14]
phub_termout0[15]
phub_termout1[0]
phub_termout1[1]
phub_termout1[2]
phub_termout1[3]
phub_termout1[4]
phub_termout1[5]
phub_termout1[6]
phub_termout1[7]
phub_termout1[8]
phub_termout1[9]
phub_termout1[10]
phub_termout1[11]
phub_termout1[12]
phub_termout1[13]
phub_termout1[14]
phub_termout1[15]
7
8
9
PICU[3]
PICU[4]
PICU[5]
PICU[6]
PICU[12]
PICU[15]
Comparator Int
Switched Cap Int
I2C
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
CAN
Timer/Counter0
Timer/Counter1
Timer/Counter2
Timer/Counter3
USB SOF Int
USB Arb Int
USB Bus Int
USB Endpoint[0]
USB Endpoint Data
Reserved
Reserved
DFB Int
Decimator Int
phub_err_int
eeprom_fault_int
higher CPU performance. If ECC is enabled, the cache controller
also performs error checking and correction. Flash programming
is performed through a special interface and preempts code
execution out of Flash. Code execution out of cache may
continue during Flash programming as long as that code is
contained inside the cache.
5. Memory
5.1 Static RAM
CY8C54 Static RAM (SRAM) is used for temporary data storage.
Code can be executed at full speed from the portion of SRAM
that is located in the code space. This process is slower from
SRAM above 0x20000000. The device provides up to 64 KB of
SRAM. The CPU or the DMA controller can access all of SRAM.
The SRAM can be accessed simultaneously by the Cortex-M3
CPU and the DMA controller if accessing different 32 KB blocks.
The Flash programming interface performs Flash erasing,
programming and setting code protection levels. Flash In
System Serial Programming (ISSP), typically used for production
programming, is possible through both the SWD and JTAG inter-
faces. In-system programming, typically used for bootloaders, is
also possible using serial interfaces such as I2C, USB, UART,
and SPI, or any communications protocol.
5.2 Flash Program Memory
Flash memory in PSoC devices provides nonvolatile storage for
user firmware, user configuration data, bulk data storage, and
optional ECC data. The main Flash memory area contains up to
256 KB of user program space.
5.3 Flash Security
All PSoC devices include a flexible Flash protection model that
prevents access and visibility to on-chip Flash memory. This
prevents duplication or reverse engineering of proprietary code.
Flash memory is organized in blocks, where each block contains
256 bytes of program or data and 32 bytes of ECC or configu-
ration data.
Up to an additional 32 KB of Flash space is available for Error
Correcting Codes (ECC). If ECC is not used this space can store
device configuration data and bulk user data. User code may not
be run out of the ECC Flash memory section. ECC can correct
one bit error and detect two bit errors per 8 bytes of firmware
memory; an interrupt can be generated when an error is
detected. The Flash output is 9 bytes wide with 8 bytes of data
and 1 byte of ECC data.
The device offers the ability to assign one of four protection
levels to each row of Flash. Table 5-1 lists the protection modes
available. Flash protection levels can only be changed by
performing a complete Flash erase. The Full Protection and Field
Upgrade settings disable external access (through a debugging
The CPU or DMA controller read both user code and bulk data
located in Flash through the cache controller. This provides
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tool such as PSoC Creator, for example). If your application
requires code update through a boot loader, then use the Field
Upgrade setting. Use the Unprotected setting only when no
security is needed in your application. The PSoC device also
offers an advanced security feature called Device Security which
permanently disables all test, programming, and debug ports,
protecting your application from external access (see the
“Device Security” section on page 55). For more information on
how to take full advantage of the security features in PSoC, see
the PSoC 5 TRM.
their code. Code protection does not mean that we are guaran-
teeing the product as “unbreakable.”
Cypress is willing to work with the customer who is concerned
about the integrity of their code. Code protection is constantly
evolving. We at Cypress are committed to continuously
improving the code protection features of our products.
5.4 EEPROM
PSoC EEPROM memory is a byte addressable nonvolatile
memory. The CY8C54 has 2 KB of EEPROM memory to store
user data. Reads from EEPROM are random access at the byte
level. Reads are done directly; writes are done by sending write
commands to an EEPROM programming interface. CPU code
execution can continue from Flash during EEPROM writes.
EEPROM is erasable and writeable at the row level. The
EEPROM is divided into two sections, each containing 64 rows
of 16 bytes each.
Table 5-1. Flash Protection
Protection
Setting
Allowed
Not Allowed
Unprotected
External read and write
+ internal read and write
-
Factory
Upgrade
External write + internal External read
read and write
The CPU can not execute out of EEPROM. There is no ECC
hardware associated with EEPROM. If ECC is required it must
be handled in firmware.
Field Upgrade Internal read and write External read and
write
5.5 External Memory Interface
Full Protection Internal read
External read and
write + internal write
CY8C54 provides an External Memory Interface (EMIF) for
connecting to external memory devices. The connection allows
read and write accesses to external memories. The EMIF
operates in conjunction with UDBs, I/O ports, and other
hardware to generate external memory address and control
signals.
Disclaimer
Note the following details of the Flash code protection features
on Cypress devices.
Figure 5-1 is the EMIF block diagram. The EMIF supports
synchronous and asynchronous memories. The CY8C54 only
supports one type of external memory device at a time.
Cypress products meet the specifications contained in their
particular Cypress data sheets. Cypress believes that its family
of products is one of the most secure families of its kind on the
market today, regardless of how they are used. There may be
methods, unknown to Cypress, that can breach the code
protection features. Any of these methods, to our knowledge,
would be dishonest and possibly illegal. Neither Cypress nor any
other semiconductor manufacturer can guarantee the security of
External memory is located in the Cortex-M3 external RAM
space; it can use up to 24 address bits. See “Memory Map”
section on page 18. The memory can be 8 or 16 bits wide.
Cortex-M3 instructions can be fetched/executed from external
memory, although at a slower rate than from Flash.
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Figure 5-1. EMIF Block Diagram
Externa_l MEM_ ADDR[23:0]
Externa_l MEM_DATA[15:0]
Address Signals
IO
PORTs
Data,
Address,
and Control
Signals
Data Signals
IO IF
IO
PORTs
Control Signals
Control
IO
PORTs
PHUB
Data,
Address,
and Control
Signals
DSI Dynamic Output
Control
UDB
DSI to Port
Other
EM Control
Signals
Control
Signals
Data,
Address,
and Control
Signals
EMIF
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Table 5-3. Peripheral Data Address Map (continued)
5.6 Memory Map
The Cortex-M3 has a fixed address map, which allows periph-
erals to be accessed by simple memory access instructions.
Address Range
Purpose
0x40004F00 – 0x40004FFF Fixed Timer, Counter, PWMs
0x40005000 – 0x400051FF General Purpose I/Os
0x40005300 – 0x4000530F Output Port Select Register
5.6.1 Address Map
The 4 GB address space is divided into the ranges shown in
Table 5-2:
0x40005400 – 0x400054FF External Memory Interface
(EMIF) Control Registers
Table 5-2. Address Map
0x40005800 – 0x40005FFF Analog Subsystem Interface
0x40006000 – 0x400060FF USB Controller
0x40006400 – 0x40006FFF UDB Configuration
0x40007000 – 0x40007FFF PHUB Configuration
0x40008000 – 0x400087FF EEPROM
Address Range
Size
Use
0x00000000 –
0x1FFFFFFF
0.5 GB Program code. This includes
the exception vector table at
power up, which starts at
address 0.
0x20000000 –
0x3FFFFFFF
0.5 GB Static RAM. This includes a 1
MByte bit-band region
starting at 0x20000000 and a
32 Mbyte bit-band alias
region starting at
0x4000A000 – 0x4000A400 CAN
0x4000C000 – 0x4000C800 Digital Filter Block
0x40010000 – 0x4001FFFF Digital Interconnect Configuration
0x60000000 – 0x60FFFFFF External Memory Interface
(EMIF)
0x22000000.
0x40000000 –
0x5FFFFFFF
0.5 GB Peripherals. This includes a 1
MByte bit-band region
starting at 0x40000000 and a
32 Mbyte bit-band alias
region starting at
0x80000000 – 0x800007FFF Flash ECC Bytes
0xE0000000 – 0xE00FFFFF Cortex-M3 PPB Registers,
including NVIC, debug, and trace
0x42000000.
0x60000000 –
0x9FFFFFFF
1 GB
1 GB
External RAM.
The bit-band feature allows individual bits in words in the
bit-band region to be read or written as atomic operations. This
is done by reading or writing bit 0 of corresponding words in the
bit-band alias region. For example, to set bit 3 in the word at
address 0x20000000, write a 1 to address 0x2200000C. To test
the value of that bit, read address 0x2200000C and the result is
either 0 or 1 depending on the value of the bit.
0xA0000000 –
0xDFFFFFFF
External peripherals.
0xE0000000 –
0xFFFFFFFF
0.5 GB Internalperipherals,including
the NVIC and debug and
trace modules.
Most memory accesses done by the Cortex-M3 are aligned, that
is, done on word (4-byte) boundary addresses. Unaligned
accesses of words and 16-bit half-words on nonword boundary
addresses can also be done, although they are less efficient.
Table 5-3. Peripheral Data Address Map
Address Range
Purpose
5.6.2 Address Map and Cortex-M3 Buses
0x00000000 – 0x0003FFFF 256K Flash
The ICode and DCode buses are used only for accesses within
the Code address range, 0 - 0x1FFFFFFF.
0x1FFF8000 – 0x1FFFFFFF 32K SRAM in Code region
0x20000000 – 0x20007FFF 32K SRAM in SRAM region
0x40004000 – 0x400042FF Clocking, PLLs, and oscillators
0x40004300 – 0x400043FF Power management
0x40004500 – 0x400045FF Ports interrupt control
0x40004700 – 0x400047FF System performance controller
0x40004800 – 0x400048FF Cache controller
0x40004900 – 0x400049FF I2C controller
The System bus is used for data accesses and debug accesses
within the ranges 0x20000000 - 0xDFFFFFFF and 0xE0100000
- 0xFFFFFFFF. Instruction fetches can also be done within the
range 0x20000000 - 0x3FFFFFFF, although these can be slower
than instruction fetches via the ICode bus.
The Private Peripheral Bus (PPB) is used within the Cortex-M3
to access system control registers and debug and trace module
registers.
0x40004E00 – 0x40004EFF Decimator
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Key features of the clocking system include:
6. System Integration
Seven general purpose clock sources
6.1 Clocking System
3 to 80 MHz IMO ±1% at 3 MHz
4 to 33 MHz External Crystal Oscillator (MHzECO)
DSI signal from an external I/O pin or other logic
24 to 80 MHz fractional Phase-Locked Loop (PLL) sourced
from IMO, MHzECO, or DSI
The clocking system generates, divides, and distributes clocks
throughout the PSoC system. For the majority of systems, no
external crystal is required. The IMO and PLL can generate up
to a 80 MHz clock, accurate to ±1% over voltage and temper-
ature. Additional internal and external clock sources allow each
design to optimize accuracy, power, and cost. All of the system
clock sources can be used to generate other clock frequencies
in the 16-bit clock dividers and throughout the device for anything
the user wants, for example a UART baud rate generator.
Clock Doubler
1 kHz, 33 kHz, 100 kHz ILO for Watch Dog Timer (WDT) and
Sleep Timer
32.768 kHz External Crystal Oscillator (kHzECO) for Real
Time Clock (RTC)
36 MHz fixed clock (available only during test mode)
Clock generation and distribution is automatically configured
through the PSoC Creator IDE graphical interface. This is based
on the complete system’s requirements. It greatly speeds the
design process. PSoC Creator allows designers to build clocking
systems with minimal input. The designer can specify desired
clock frequencies and accuracies, and the software locates or
builds a clock that meets the required specifications. This is
possible because of the programmability inherent PSoC.
Dedicated 48 MHz Internal Oscillator for USB that auto locks
to USB bus clock requiring no external crystal for USB. (USB
equipped parts only)
Independently sourced clock dividers in all clocks
Eight 16-bit clock dividers for the digital system
Four 16-bit clock dividers for the analog system
Dedicated 16-bit divider for the CPU bus and CPU clock
Automatic clock configuration in PSoC Creator
Table 6-1. Oscillator Summary
Source
IMO
Fmin
3 MHz
4 MHz
Tolerance at Fmin
±1% over voltage and temperature
Crystal dependent
Fmax
80 MHz
33 MHz
Tolerance at Fmax
±5%
Startup Time
10 µs max
MHzECO
Crystal dependent
5 ms typ, max is
crystal dependent
DSI
PLL
0 MHz
Input dependent
33 MHz
80 MHz
48 MHz
100 kHz
32 kHz
Input dependent
Input dependent
Input dependent
-20%, +30%
Input dependent
250 µs max
1 µs max
24 MHz Input dependent
12 MHz Input dependent
Doubler
ILO
1 kHz
-30%, +65%
1000 µs max
kHzECO
32 kHz
Crystal dependent
Crystal dependent
500 ms typ, max is
crystal dependent
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Figure 6-1. Clocking Subsystem
External IO
or DSI
0-33 MHz
3-72 MHz
IMO
4-33 MHz
ECO
1,33,100 kHz
ILO
32 kHz ECO
12-72 MHz
Doubler
24-67 MHz
PLL
System
Clock Mux
Bus/CPU Clock
Divider 16 bit
s
k
e
w
Digital Clock
Divider 16 bit
Digital Clock
Divider 16 bit
Analog Clock
Divider 16 bit
s
k
e
w
Digital Clock
Divider 16 bit
Digital Clock
Divider 16 bit
Analog Clock
Divider 16 bit
7
s
k
e
w
7
Analog Clock
Divider 16 bit
Digital Clock
Divider 16 bit
Digital Clock
Divider 16 bit
s
k
e
w
Analog Clock
Divider 16 bit
Digital Clock
Divider 16 bit
Digital Clock
Divider 16 bit
6.1.1 Internal Oscillators
and feedback dividers supply 4032 discrete ratios to create
almost any desired system clock frequency. The most common
PLL use is to multiply the IMO clock at 3 MHz, where it is most
accurate to generate the CPU and system clocks up to the
device’s maximum frequency.
6.1.1.1 Internal Main Oscillator
In most designs the IMO is the only clock source required, due
to its ±1% accuracy. The IMO operates with no external compo-
nents and outputs a stable clock. A factory trim for each
frequency range is stored in the device. With the factory trim,
tolerance varies from ±1% at 3 MHz, up to ±10% at 72 MHz. The
IMO, in conjunction with the PLL, allows generation of up to a 66
MHz clock with ±1% accuracy.
The PLL achieves phase lock within 250 µs (verified by bit
setting). It can be configured to use a clock from the IMO,
MHzECO, DSI (external pin), or doubler. The PLL clock source
can be used until lock is complete and signaled with a lock bit.
Disable the PLL before entering low power modes.
The IMO provides clock outputs at 3, 6, 12, 24, 48, and 72 MHz.
6.1.1.4 Internal Low Speed Oscillator
6.1.1.2 Clock Doubler
The ILO provides clock frequencies for low power consumption,
including the watchdog timer, and sleep timer. The ILO
generates up to three different clocks: 1 kHz, 33 kHz, and
100 kHz.
The clock doubler outputs a clock at twice the frequency of the
input clock. The doubler works for input frequency ranges of 6 to
24 MHz (providing 12 to 72 MHz at the output). It can be
configured to use a clock from the IMO, MHzECO, or the DSI
(external pin).
The 1 kHz clock (CLK1K) is typically used for a background
‘heartbeat’ timer. This clock inherently lends itself to low power
supervisory operations such as the watchdog timer and long
sleep intervals using the central timewheel (CTW).
6.1.1.3 Phase-Locked Loop
The PLL allows low frequency, high accuracy clocks to be multi-
plied to higher frequencies. This is a tradeoff between higher
clock frequency and accuracy and, higher power consumption
and increased startup time.
The central timewheel is a 1 kHz, free running, 13-bit counter
clocked by the ILO. The central timewheel is always enabled
except in hibernate mode and when the CPU is stopped during
debug on chip mode. It can be used to generate periodic inter-
rupts for timing purposes or to wake the system from a low power
mode. Firmware can reset the central timewheel.
The PLL block provides a mechanism for generating clock
frequencies based upon a variety of input sources. The PLL
outputs clock frequencies in the range of 24 to 80 MHz. Its input
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The central timewheel can be programmed to wake the system
periodically and optionally issue an interrupt. This enables
flexible, periodic wakeups from low power modes or coarse
timing applications. Systems that require accurate timing should
use the Real Time Clock capability instead of the central
timewheel.
neighboring circuits. The GPIO pins connected to the external
crystal and capacitors are fixed.
6.1.3 Clock Distribution
All seven clock sources are inputs to the central clock distribution
system. The distribution system is designed to create multiple
high precision clocks. These clocks are customized for the
design’s requirements and eliminate the common problems
found with limited resolution prescalers attached to peripherals.
The clock distribution system generates several types of clock
trees.
The 100 kHz clock (CLK100K) works as a low power system
clock to run the CPU. It can also generate time intervals such as
fast sleep intervals using the fast timewheel.
The fast timewheel is a 100 kHz, 5-bit counter clocked by the ILO
that can also be used to wake the system. The fast timewheel
settings are programmable, and the counter automatically resets
when the terminal count is reached. This enables flexible,
periodic wakeups of the CPU at a higher rate than is allowed
using the central timewheel. The fast timewheel can generate an
optional interrupt each time the terminal count is reached.
The system clock is used to select and supply the fastest clock
in the system for general system clock requirements and clock
synchronization of the PSoC device.
Bus Clock 16-bit divider uses the system clock to generate the
system’s bus clock used for data transfers and the CPU. The
CPU clock is directly derived from the bus clock.
The 33 kHz clock (CLK33K) comes from a divide-by-3 operation
on CLK100K. This output can be used as a reduced accuracy
version of the 32.768 kHz ECO clock with no need for a crystal.
Eight fully programmable 16-bit clock dividers generate digital
system clocks for general use in the digital system, as
configured by the design’s requirements. Digital system clocks
can generate custom clocks derived from any of the seven
clock sources for any purpose. Examples include baud rate
generators, accurate PWM periods, and timer clocks, and
many others. If more than eight digital clock dividers are
required, theUniversalDigitalBlocks(UDBs)andfixedfunction
Timer/Counter/PWMs can also generate clocks.
6.1.2 External Oscillators
6.1.2.5 MHz External Crystal Oscillator
The MHzECO provides high frequency, high precision clocking
using an external crystal. It supports a wide variety of crystal
types, in the range of 4 to 33 MHz. When used in conjunction
with the PLL, it can synthesize a wide range of precise clock
frequencies up to 80 MHz. The GPIO pins connecting to the
external crystal and capacitors are fixed. MHzECO accuracy
depends on the crystal chosen.
Four16-bitclockdividersgenerateclocksfortheanalogsystem
components that require clocking, such as ADCs and mixers.
The analog clock dividers include skew control to ensure that
critical analog events do not occur simultaneously with digital
switching events. This is done to reduce analog system noise.
6.1.2.6 Digital System Interconnect
The DSI provides routing for clocks taken from external clock
oscillators connected to I/O. The oscillators can also be
generated within the device in the digital system and Universal
Digital Blocks.
Each clock divider consists of an 8-input multiplexer, a 16-bit
clock divider (divide by 2 and higher) that generates ~50% duty
cycle clocks, system clock resynchronization logic, and deglitch
logic. The outputs from each digital clock tree can be routed into
the digital system interconnect and then brought back into the
clock system as an input, allowing clock chaining of up to 32 bits.
While the primary DSI clock input provides access to all clocking
resources, up to eight other DSI clocks (internally or externally
generated) may be routed directly to the eight digital clock
dividers. This is only possible if there are multiple precision clock
sources.
6.1.4 USB Clock Domain
The USB clock domain is unique in that it operates largely
asynchronously from the main clock network. The USB logic
contains a synchronous bus interface to the chip, while running
on an asynchronous clock to process USB data. The USB logic
requires a 48 MHz frequency. This frequency can be generated
from different sources, including DSI clock at 48 MHz or doubled
value of 24 MHz from internal oscillator, DSI signal, or crystal
oscillator.
6.1.2.7 32.768 kHz ECO
The 32.768 kHz External Crystal Oscillator (32kHzECO)
provides precision timing with minimal power consumption using
an external 32.768 kHz watch crystal. The 32kHzECO also
connects directly to the sleep timer and provides the source for
the Real Time Clock (RTC). The RTC uses a 1 second interrupt
to implement the RTC functionality in firmware.
The oscillator works in two distinct power modes. This allows
users to trade off power consumption with noise immunity from
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6.2 Power System
The power system consists of separate analog, digital, and I/O supply pins, labeled Vdda, Vddd, and Vddiox, respectively. It also
includes two internal 1.8V regulators that provide the digital (Vccd) and analog (Vcca) supplies for the internal core logic. The output
pins of the regulators (Vccd and Vcca) and the Vddio pins must have capacitors connected as shown in Figure 6-2. One of the Vccd
pins must have a 1 µF ±10% X5R capacitor connected to Vssd. The other Vccd pin should have a 0.1 µF ±10% X5R capacitor
connected to Vssd. Also, a trace that is as short as possible must run between the two Vccd pins. The power system also contains a
sleep regulator, an I2C regulator, and a hibernate regulator.
Figure 6-2. PSoC Power System
µF
1
Vddio2
Vddd
Vddio0
0.1µF
I/ O Supply
I/ O Supply
Vddio0
0.1µF
I2C
Regulator
Sleep
Regulator
Digital
Domain
Vdda
Vcca
Vdda
Analog
Regulator
Digital
Regulators
Vssd
.
µF
1
Vssa
Analog
Domain
Hibernate
Regulator
I/O Supply
I/O Supply
0.1µF
0.1µF
0.1µF
Vddd
Vddio1
Vddio3
6.2.1 Power Modes
Active is the main processing mode. Its functionality is config-
urable. Each power controllable subsystem is enabled or
disabled by using separate power configuration template
registers. In alternate active mode, fewer subsystems are
enabled, reducing power. In sleep mode most resources are
disabled regardless of the template settings. Sleep mode is
optimized to provide timed sleep intervals and Real Time Clock
functionality. The lowest power mode is hibernate, which retains
register and SRAM state, but no clocks, and allows wakeup only
from I/O pins. Figure 6-3 illustrates the allowable transitions
between power modes.
PSoC 5 devices have four different power modes. The power
modes allow a design to easily provide required functionality and
processing power while simultaneously minimizing power
consumption and maximizing battery life in low power and
portable devices.
PSoC
5 power modes, in order of decreasing power
consumption are:
Active
Alternate Active
Sleep
Hibernate
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Table 6-2. Power Modes
Power Modes
Description
EntryCondition WakeupSource Active Clocks
Regulator
Active
Primary mode of operation, all Wakeup, reset, Any interrupt
peripherals available (program- manual register
Any (program-
mable)
All regulators available.
Digital and analog
mable)
entry
regulators can be disabled
if external regulation used.
Alternate
Active
Similar to Active mode, and is
typically configured to have
fewer peripherals active to
reduce power. One possible
configuration is to turn off the
CPU and Flash, and run periph-
erals at full speed
Manual register Any interrupt
entry
Any (program-
mable)
All regulators available.
Digital and analog
regulators can be disabled
if external regulation used.
Sleep
All subsystems automatically
disabled
Manual register PICU,
entry
ILO/ECO32K
Both digital and analog
regulators buzzed.
Digital and analog
comparator, I2C,
RTC, CTW,
XRES_N, WDR,
PPOR, HBR
regulators can be disabled
if external regulation used.
Hibernate
All subsystems automatically
disabled
Manual register PICU, XRES_N,
entry HBR
Only hibernate regulator
active.
Lowest power consuming mode
with all peripherals and internal
regulators disabled, except
hibernate regulator is enabled
Configuration and memory
contents retained
Table 6-3. Power Modes Wakeup Time and Power Consumption
Sleep
Modes
Wakeup Power
Time (Typ)
Code
Digital
Analog
Clock Sources
Available
Wakeup Sources Reset Sources
Execution Resources Resources
Active
-
-
2 mA[5] Yes
All
All
All
All
All
All
-
-
All
All
Alternate
Active
User
20 µA
defined
<12 µs
No
I2C
Comparator ILO/kHzECO
None None
PICU,comparator, XRES, LVD,
Sleep
2 µA
I2C, RTC, CTW
PICU
WDR
Hibernate <100 µs 300 nA No
None
XRES, HRES
Figure 6-3. Power Mode Transitions
Active mode is the primary operating mode of the device. When
in active mode, the active configuration template bits control
which available resources are enabled or disabled. When a
resource is disabled, the digital clocks are gated, analog bias
currents are disabled, and leakage currents are reduced as
appropriate. User firmware can dynamically control subsystem
power by setting and clearing bits in the active configuration
template. The CPU can disable itself, in which case the CPU is
automatically reenabled at the next wakeup event.
Active
Alternate
Sleep
Hibernate
Active
When a wakeup event occurs, the global mode is always
returned to active, and the CPU is automatically enabled,
regardless of its template settings. Active mode is the default
global power mode upon boot.
6.2.1.1 Active Mode
Note
5. IMO 6 MHz, CPU 6 MHz, all peripherals disabled.
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6.2.1.2 Alternate Active Mode
Figure 6-4. Application for Boost Converter
Alternate Active mode is very similar to Active mode. In alternate
active mode, fewer subsystems are enabled, to reduce power
consumption. One possible configuration is to turn off the CPU
and Flash, and run peripherals at full speed.
Vdda Vddd Vddio
Vboost
Ind
Optional
Schottky Diode
Only required
Vboost>3.6V
6.2.1.3 Sleep Mode
Sleep mode reduces power consumption when a resume time of
12 µs is acceptable. The wake time is used to ensure that the
regulator outputs are stable enough to directly enter active
mode.
22µF 0. 1µF
PSoC
10µH
22µF
SMP
6.2.1.4 Hibernate Mode
Vbat
Vssb
In hibernate mode nearly all of the internal functions are
disabled. Internal voltages are reduced to the minimal level to
keep vital systems alive. Configuration state is preserved in
hibernate mode and SRAM memory is retained. GPIOs
configured as digital outputs maintain their previous values and
external GPIO pin interrupt settings are preserved. The
hibernate reset (HRES) occurs if the internal voltage falls below
the minimum level required for state retention. The device can
only return from hibernate mode in response to an external I/O
interrupt. The resume time from hibernate mode is less than
100 µs.
Vssa
Vssd
The boost converter can be operated in two different modes:
active and standby. Active mode is the normal mode of operation
where the boost regulator actively generates a regulated output
voltage. In standby mode, most boost functions are disabled,
thus reducing power consumption of the boost circuit. The
converter can be configured to provide low power, low current
regulation in the standby mode. The external 32 kHz crystal can
be used to generate inductor boost pulses on the rising and
falling edge of the clock when the output voltage is less than the
programmed value. This is called automatic thump mode (ATM).
6.2.1.5 Wakeup Events
Wakeup events are configurable and can come from an interrupt
or device reset. A wakeup event restores the system to active
mode. Interrupt sources include internally generated interrupts,
power supervisor, central timewheel, and I/O interrupts. Internal
interrupt sources can come from a variety of peripherals, such
as analog comparators and UDBs. The central timewheel
provides periodic interrupts to allow the system to wake up, poll
peripherals, or perform real-time functions. Reset event sources
include the external reset I/O pin (XRES), WDT, and Precision
Reset (PRES).
The boost typically draws 200 µA in active mode and 12 µA in
standby mode. The boost operating modes must be used in
conjunction with chip power modes to minimize the total chip
power consumption. Table 6-4 lists the boost power modes
available in different chip power modes.
Table 6-4. Chip and Boost Power Modes Compatibility
Chip Power Modes
Boost Power Modes
6.2.2 Boost Converter
Chip -Active mode
Boost can be operated in either active
or standby mode.
Applications that use a supply voltage of less than 1.71V, such
as solar or single cell battery supplies, may use the on-chip boost
converter. The boost converter may also be used in any system
that requires a higher operating voltage than the supply provides.
For instance, this includes driving 5.0V LCD glass in a 3.3V
system. The boost converter accepts an input voltage as low as
0.5V. With one low cost inductor it produces a selectable output
voltage sourcing enough current to operate the PSoC and other
on-board components.
Chip -Sleep mode
Boost can be operated in either active
or standby mode. However, it is recom-
mended to operate boost in standby
mode for low power consumption
Chip-Hibernate mode Boost can only be operated in active
mode. However, it is recommended not
to use boost in chip hibernate mode
due to high current consumption in
boost active mode
The boost converter accepts an input voltage from 0.5V to 5.5V
(Vbat). The converter provides a user configurable output
voltage of 1.8 to 5.0V (Vboost); Vbat must be less than Vboost.
The block can deliver up to 50 mA (Iboost) depending on config-
uration.
The switching frequency can be set to 100 kHz, 400 kHz, 2 MHz,
or 32 kHz to optimize efficiency and component cost. The 100
kHz, 400 kHz, and 2 MHz switching frequencies are generated
using oscillators internal to the boost converter block. When the
32 kHz switching frequency is selected, the clock is derived from
a 32 kHz external crystal oscillator. The 32 kHz external clock is
primarily intended for boost standby mode.
Four pins are associated with the boost converter: Vbat, Vssb,
Vboost, and Ind. The boosted output voltage is sensed at the
Vboost pin and must be connected directly to the chip’s supply
inputs. An inductor is connected between the Vbat and Ind pins.
The designer can optimize the inductor value to increase the
boost converter efficiency based on input voltage, output
voltage, current and switching frequency. The External Schottky
diode shown in Figure 6-4 is required only in cases when
Vboost>3.6V.
If the boost converter is not used in a given application, tie the
Vbat, Vssb, and Vboost pins to ground and leave the Ind pin
unconnected.
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corresponding internal regulators. The trip level is not precise.
It is set to a voltage below the lowest specified operating volt-
age but high enough for the internal circuits to be reset and to
hold their reset state. The monitor generates a reset pulse that
is at least 100 ns wide. It may be much wider if one or more of
the voltages ramps up slowly.
6.3 Reset
CY8C54 has multiple internal and external reset sources
available. The reset sources are:
Power source monitoring - The analog and digital power
voltages, Vdda, Vddd, Vcca, and Vccd are monitored in several
different modes during power up, normal operation, and sleep
and hibernate states. If any of the voltages goes outside prede-
termined ranges then a reset is generated. The monitors are
programmable to generate an interrupt to the processor under
certain conditions before reaching the reset thresholds.
To save power the IPOR circuit is disabled when the internal
digital supply is stable. Voltage supervision is then handed off
to the precise low voltage reset (PRES) circuit. When the volt-
age is high enough for PRES to release, the IMO starts.
PRES - Precise Low Voltage Reset
External - The device can be reset from an external source by
pulling the reset pin (XRES) low. The XRES pin includes an
internal pull up to Vddio1. Vddd, Vdda, and Vddio1 must all
have voltage applied before the part comes out of reset.
This circuit monitors the outputs of the analog and digital inter-
nal regulators after power up. The regulator outputs are com-
pared to a precise reference voltage of 1.6V ±0.02V. The re-
sponse to a PRES trip is identical to an IPOR reset.
Watchdog timer - A watchdog timer monitors the execution of
instructions by the processor. If the watchdog timer is not reset
by firmware within a certain period of time, the watchdog timer
generates a reset.
In normal operating mode, the program cannot disable the dig-
ital PRES circuit. The analog regulator can be disabled, which
also disables the analog portion of the PRES. The PRES cir-
cuit is disabled automatically during sleep and hibernate
modes, with one exception: During sleep mode the regulators
are periodically activated (buzzed) to provide supervisory ser-
vices and to reduce wakeup time. At these times the PRES
circuit is also buzzed to allow periodic voltage monitoring.
Software - The device can be reset under program control.
Figure 6-5. Resets
Vddd Vdda
HRES - Hibernate/Sleep Low Voltage Reset
This circuit monitors internal voltage and issues a reset if the
voltage drops below a point where state information may be
lost. The response to a HRES trip is identical to an IPOR reset.
Power
Voltage
Level
Processor
Interrupt
Monitors
This circuit is ultra low power. It is enabled at all times but its
output only causes a reset when the device is in hibernate or
sleep mode.
Reset
Pin
External
ALVI,DLVI,AHVI-Analog/DigitalLowVoltageInterrupt,Analog
High Voltage Interrupt
Reset
Controller
System
Reset
Reset
Interrupt circuits are available to detect when Vdda and Vddd
go outside a voltage range. For AHVI, Vdda is compared to a
fixed trip level. For ALVI and DLVI, Vdda and Vddd are com-
pared to trip levels that are programmable, as listed in
Table 6-5.
Watchdog
Timer
Table 6-5. Analog/Digital Low Voltage Interrupt, Analog High
Voltage Interrupt
Software
Reset
Register
Normal
Available Trip
Interrupt Supply
Voltage
Range
Accuracy
Settings
DLVI
ALVI
AHVI
Vddd 1.71V-5.5V 1.70V-5.45V in
±2%
250 mV
increments
The term system reset indicates that the processor as well as
analog and digital peripherals and registers are reset.
Vdda 1.71V-5.5V 1.70V-5.45V in
±2%
±2%
250 mV
increments
A reset status register holds the source of the most recent reset
or power voltage monitoring interrupt. The program may
examine this register to detect and report exception conditions.
This register is cleared after a power on reset.
Vdda 1.71V-5.5V 5.75V
The monitors are disabled until after IPOR. During sleep mode
these circuits are periodically activated (buzzed). If an interrupt
occurs during buzzing then the system first enters its wakeup
sequence. The interrupt is then recognized and may be ser-
viced.
6.3.1 Reset Sources
6.3.1.1 Power Voltage Level Monitors
IPOR - Initial Power on Reset
At initial power on, IPOR monitors the power voltages Vddd
and Vdda, both directly at the pins and at the outputs of the
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6.3.1.2 Other Reset Sources
be used for analog input, CapSense[4], and LCD segment drive,
while SIO pins are used for voltages in excess of Vdda and for
programmable output voltages.
XRES - External Reset
CY8C54 has either a single GPIO pin that is configured as an
external reset or a dedicated XRES pin. Either the dedicated
XRES pin or the GPIO pin, if configured, holds the part in reset
while held active (low). The response to an XRES is the same
as to an IPOR reset.
Features supported by both GPIO and SIO:
User programmable port reset state
SeparateI/OsuppliesandvoltagesforuptofourgroupsofI/O
Digital peripherals use DSI to connect the pins
Input or output or both for CPU and DMA
Eight drive modes
Every pin can be an interrupt source configured as rising
edge, falling edge or both edges. If required, level sensitive
interrupts are supported through the DSI
The external reset is active low. It includes an internal pull up
resistor. XRES is active during sleep and hibernate modes.
SRES - Software Reset
A reset can be commanded under program control by setting
a bit in the software reset register. This is done either directly
by the program or indirectly by DMA access. The response to
a SRES is the same as after an IPOR reset.
Dedicated port interrupt vector for each port
Slew rate controlled digital output drive mode
Access port control and configuration registers on either port
basis or pin basis
Another register bit exists to disable this function.
WRES - Watchdog Timer Reset
Separateportread(PS)andwrite(DR)dataregisterstoavoid
read modify write errors
Special functionality on a pin by pin basis
The watchdog reset detects when the software program is no
longer being executed correctly. To indicate to the watchdog
timer that it is running correctly, the program must periodically
reset the timer. If the timer is not reset before a user-specified
amount of time, then a reset is generated.
Additional features only provided on the GPIO pins:
LCD segment drive on LCD equipped devices
CapSense on CapSense equipped devices[4]
Analog input and output capability
Continuous 100 µA clamp current capability
Standard drive strength down to 1.71V
Note IPOR disables the watchdog function. The program must
enable the watchdog function at an appropriate point in the
code by setting a register bit. When this bit is set, it cannot be
cleared again except by an IPOR power on reset event.
Additional features only provided on SIO pins:
Higher drive strength than GPIO
Hot swap capability (5V tolerance at any operating Vdd)
Programmable and regulated high input and output drive
levels down to 1.2V
No analog input or LCD capability
6.4 I/O System and Routing
PSoC I/Os are extremely flexible. Every GPIO has analog and
digital I/O capability. All I/Os have a large number of drive modes,
which are set at POR. PSoC also provides up to four individual
I/O voltage domains through the Vddio pins.
Over voltage tolerance up to 5.5V
SIO can act as a general purpose analog comparator
There are two types of I/O pins on every device; those with USB
provide a third type. Both General Purpose I/O (GPIO) and
Special I/O (SIO) provide similar digital functionality. The primary
differences are their analog capability and drive strength.
Devices that include USB also provide two USBIO pins that
support specific USB functionality as well as limited GPIO
capability.
USBIO features:
Full speed USB 2.0 compliant I/O
Highest drive strength for general purpose use
Input, output, or both for CPU and DMA
Input, output, or both for digital peripherals
Digital output (CMOS) drive mode
Each pin can be an interrupt source configured as rising
edge, falling edge, or both edges
All I/O pins are available for use as digital inputs and outputs for
both the CPU and digital peripherals. In addition, all I/O pins can
generate an interrupt. The flexible and advanced capabilities of
the PSoC I/O, combined with any signal to any pin routability,
greatly simplify circuit design and board layout. All GPIO pins can
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Figure 6-6. GPIO Block Diagram
Digital Input Path
Naming Convention
‘x’ = Port Number
‘y’ = Pin Number
PRT[x]CTL
PRT[x]DBL_SYNC_IN
PRT[x]PS
Digital System Input
PICU[x]INTTYPE[y]
PICU[x]INTSTAT
Pin Interrupt Signal
PICU[x]INTSTAT
Input Buffer Disable
Interrupt
Logic
Digital Output Path
PRT[x]SLW
PRT[x]SYNC_OUT
Vio Vio
PRT[x]DR
0
In
Digital System Output
PRT[x]BYP
1
Vio
Drive
Slew
PRT[x]DM2
PRT[x]DM1
PRT[x]DM0
Logic
Cntl
PIN
Bidirectional Control
PRT[x]BIE
OE
Analog
1
0
1
0
1
Capsense Global Control
CAPS[x]CFG1
Switches
PRT[x]AG
Analog Global Enable
PRT[x]AMUX
Analog Mux Enable
LCD
Display
Data
PRT[x]LCD_COM_SEG
PRT[x]LCD_EN
Logic & MUX
LCD Bias Bus
5
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Figure 6-7. SIO Input/Output Block Diagram
Digital Input Path
Naming Convention
‘x’ = Port Number
‘y’ = Pin Number
PRT[x]SIO_HYST_EN
PRT[x]SIO_DIFF
Buffer
Thresholds
Reference Level
PRT[x]DBL_SYNC_IN
PRT[x]PS
Digital System Input
PICU[x]INTTYPE[y]
PICU[x]INTSTAT
Pin Interrupt Signal
PICU[x]INTSTAT
Input Buffer Disable
Interrupt
Logic
Digital Output Path
Reference Level
PRT[x]SIO_CFG
PRT[x]SLW
Driver
Vhigh
PRT[x]SYNC_OUT
PRT[x]DR
0
1
In
Digital System Output
PRT[x]BYP
Drive
Logic
PRT[x]DM2
PRT[x]DM1
PRT[x]DM0
Slew
Cntl
PIN
Bidirectional Control
PRT[x]BIE
OE
Figure 6-8. USBIO Block Diagram
Digital Input Path
Naming Convention
‘x’ = Port Number
‘y’ = Pin Number
USB Receiver Circuitry
PRT[x]DBL_SYNC_IN
USBIO_CR1[0,1]
Digital System Input
PICU[x]INTTYPE[y]
PICU[x]INTSTAT
Pin Interrupt Signal
PICU[x]INTSTAT
Interrupt
Logic
Digital Output Path
PRT[x]SYNC_OUT
USBIO_CR1[7]
D+ pin only
USB or I/O
Vio Vio 3.3V Vio
USB SIE Control for USB Mode
USBIO_CR1[4,5]
Digital System Output
PRT[x]BYP
0
1
In
Drive
Logic
5k
1.5k
PIN
USBIO_CR1[2]
USBIO_CR1[3]
USBIO_CR1[6]
D+ 1.5k
D+D- 5k
Open Drain
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6.4.1 Drive Modes
bypass mode is selected. Note that the actual I/O pin voltage is
determined by a combination of the selected drive mode and the
load at the pin. For example, if a GPIO pin is configured for
resistive pull up mode and driven high while the pin is floating,
the voltage measured at the pin is a high logic state. If the same
GPIO pin is externally tied to ground then the voltage unmea-
sured at the pin is a low logic state.
Each GPIO and SIO pin is individually configurable into one of
the eight drive modes listed in Table 6-6. Three configuration bits
are used for each pin (DM[2:0]) and set in the PRTxDM[2:0]
registers. Figure 6-9 depicts a simplified pin view based on each
of the eight drive modes. Table 6-6 shows the I/O pin’s drive state
based on the port data register value or digital array signal if
Figure 6-9. Drive Mode
Vio
Vio
DR
PS
DR
PS
DR
PS
DR
PS
Pin
Pin
Pin
Pin
0. High Impedance
Analog
1. High Impedance
Digital
2. Resistive
Pull Up
3. Resistive
Pull Down
Vio
Vio
Vio
DR
Pin
PS
DR
Pin
PS
DR
PS
DR
PS
Pin
Pin
4. Open Drain,
Drives Low
5. Open Drain,
Drives High
6. Strong Drive
7. Resistive
Pull Up and Down
Table 6-6. Drive Modes
Diagram
Drive Mode
PRTxDM2
PRTxDM1
PRTxDM0
PRTxDR = 1
High-Z
PRTxDR = 0
High-Z
0
1
2
3
4
5
6
7
High impedence analog
High Impedance digital
Resistive pull up
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
High-Z
High-Z
Res High (5K)
Strong High
High-Z
Strong Low
Res Low (5K)
Strong Low
High-Z
Resistive pull down
Open drain, drives low
Open drain, drive high
Strong drive
Strong High
Strong High
Res High (5K)
Strong Low
Res Low (5K)
Resistive pull up and pull down
High Impedance Analog
or have their pins driven to a power supply rail by the PSoC
device or by external circuitry.
The default reset state with both the output driver and digital
input buffer turned off. This prevents any current from flowing
in the I/O’s digital input buffer due to a floating voltage. This
state is recommended for pins that are floating or that support
an analog voltage. High impedance analog pins do not provide
digital input functionality.
High Impedance Digital
The input buffer is enabled for digital signal input. This is the
standard high impedance (HiZ) state recommended for digital
inputs.
Resistive Pull Up or Resistive Pull Down
To achieve the lowest chip current in sleep modes, all I/Os
must either be configured to the high impedance analog mode,
Resistive pull up or pull down, respectively, provides a series
resistance in one of the data states and strong drive in the
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other. Pins can be used for digital input and output in these
modes. Interfacing to mechanical switches is a common appli-
cation for these modes.
Each pin of the port is independently configurable to detect rising
edge, falling edge, both edge interrupts, or to not generate an
interrupt.
Depending on the configured mode for each pin, each time an
interrupt event occurs on a pin, its corresponding status bit of the
interrupt status register is set to “1” and an interrupt request is
sent to the interrupt controller. Each PICU has its own interrupt
vector in the interrupt controller and the pin status register
providing easy determination of the interrupt source down to the
pin level.
Open Drain, Drives High and Open Drain, Drives Low
Open drain modes provide high impedance in one of the data
states and strong drive in the other. Pins can be used for digital
input and output in these modes. A common application for
these modes is driving the I2C bus signal lines.
Strong Drive
Port pin interrupts remain active in all sleep modes allowing the
PSoC device to wake from an externally generated interrupt.
Provides a strong CMOS output drive in either high or low
state. This is the standard output mode for pins. Strong Drive
mode pins must not be used as inputs under normal circum-
stances. This mode is often used to drive digital output signals
or external FETs.
While level sensitive interrupts are not directly supported;
Universal Digital Blocks (UDB) provide this functionality to the
system when needed.
Resistive Pull Up and Pull Down
6.4.6 Input Buffer Mode
Similar to the resistive pull up and resistive pull down modes
except the pin is always in series with a resistor. The high data
state is pull up while the low data state is pull down. This mode
is most often used when other signals that may cause shorts
can drive the bus.
GPIO and SIO input buffers can be configured at the port level
for the default CMOS input thresholds or the optional LVTTL
input thresholds. All input buffers incorporate Schmitt triggers for
input hysteresis. Additionally, individual pin input buffers can be
disabled in any drive mode.
6.4.2 Pin Registers
6.4.7 I/O Power Supplies
Registers to configure and interact with pins come in two forms
that may be used interchangeably.
Up to four I/O pin power supplies are provided depending on the
device and package. Each I/O supply must be less than or equal
to the voltage on the chip’s analog (Vdda) pin. This feature allows
users to provide different I/O voltage levels for different pins on
the device. Refer to the specific device package pinout to
determine Vddio capability for a given port and pin.
All I/O registers are available in the standard port form, where
each bit of the register corresponds to one of the port pins. This
register form is efficient for quickly reconfiguring multiple port
pins at the same time.
I/O registers are also available in pin form, which combines the
eight most commonly used port register bits into a single register
for each pin. This enables very fast configuration changes to
individual pins with a single register write.
The SIO port pins support an additional regulated high output
capability, as described in Adjustable Output Level.
6.4.8 Analog Connections
These connections apply only to GPIO pins. All GPIO pins may
be used as analog inputs or outputs. The analog voltage present
on the pin must not exceed the Vddio supply voltage to which the
GPIO belongs. Each GPIO may connect to one of the analog
global busses or to one of the analog mux buses to connect any
pin to any internal analog resource such as ADC or comparators.
In addition, select pins provide direct connections to specific
analog features such as the high current DACs or uncommitted
opamps.
6.4.3 Bidirectional Mode
High speed bidirectional capability allows pins to provide both
the high impedance digital drive mode for input signals and a
second user selected drive mode such as strong drive (set using
PRTxDM[2:0] registers) for output signals on the same pin,
based on the state of an auxiliary control bus signal. The bidirec-
tional capability is useful for processor busses and communica-
tions interfaces such as the SPI Slave MISO pin that requires
dynamic hardware control of the output buffer.
6.4.9 CapSense
The auxiliary control bus routes up to 16 UDB or digital peripheral
generated output enable signals to one or more pins.
This section applies only to GPIO pins. All GPIO pins may be
used to create CapSense buttons and sliders[4]. See the
“CapSense” section on page 52 for more information.
6.4.4 Slew Rate Limited Mode
GPIO and SIO pins have fast and slow output slew rate options
for strong and open drain drive modes, not resistive drive modes.
Because it results in reduced EMI, the slow edge rate option is
recommended for signals that are not speed critical, generally
less than 1 MHz. The fast slew rate is for signals between 1 MHz
and 33 MHz. The slew rate is individually configurable for each
pin, and is set by the PRTxSLW registers.
6.4.10 LCD Segment Drive
This section applies only to GPIO pins. All GPIO pins may be
used to generate Segment and Common drive signals for direct
glass drive of LCD glass. See the “LCD Direct Drive” section on
page 51 for details.
6.4.11 Adjustable Output Level
6.4.5 Pin Interrupts
This section applies only to SIO pins. SIO port pins support the
ability to provide a regulated high output level for interface to
external signals that are lower in voltage than the SIO’s
respective Vddio. SIO pins are individually configurable to output
All GPIO and SIO pins are able to generate interrupts to the
system. All eight pins in each port interface to their own Port
Interrupt Control Unit (PICU) and associated interrupt vector.
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either the standard Vddio level or the regulated output, which is
based on an internally generated reference. Typically a voltage
DAC (VDAC) is used to generate the reference. The “DAC”
section on page 52 has more details on VDAC use and reference
routing to the SIO pins.
In case of a GPIO pin configured for analog input/output, the
analog voltage on the pin must not exceed the Vddio supply
voltage to which the GPIO belongs.
A common application for this feature is connection to a bus such
as I2C where different devices are running from different supply
voltages. In the I2C case, the PSoC chip is configured into the
Open Drain, Drives Low mode for the SIO pin. This allows an
external pull up to pull the I2C bus voltage above the PSoC pin
supply. For example, the PSoC chip could operate at 1.8V, and
an external device could run from 5V. Note that the SIO pin’s VIH
and VIL levels are determined by the associated Vddio supply
pin.
6.4.12 Adjustable Input Level
This section applies only to SIO pins. SIO pins by default support
the standard CMOS and LVTTL input levels but also support a
differential mode with programmable levels. SIO pins are
grouped into pairs. Each pair shares a reference generator block
which, is used to set the digital input buffer reference level for
interface to external signals that differ in voltage from Vddio. The
reference sets the pins voltage threshold for a high logic level.
Available input thresholds are:
The I/O pin must be configured into a high impedance drive
mode, open drain low drive mode, or pull down drive mode, for
over voltage tolerance to work properly. Absolute maximum
ratings for the device must be observed for all I/O pins.
0.5 × Vddio
0.4 × Vddio
0.5 × Vref
Vref
6.4.16 Reset Configuration
By default all I/Os reset to the High Impedance Analog state but
are reprogrammable on a port-by-port basis. They can be reset
as High Impedance Analog, Pull Down, or Pull Up, based on the
application’s requirements. To ensure correct reset operation,
the port reset configuration data is stored in special nonvolatile
registers. The stored reset data is automatically transferred to
the port reset configuration registers at PPOR release.
Typically a voltage DAC (VDAC) generates the Vref reference.
“DAC” section on page 52 has more details on VDAC use and
reference routing to the SIO pins.
6.4.13 SIO as Comparator
6.4.17 Low Power Functionality
This section applies only to SIO pins. The adjustable input level
feature of the SIOs as explained in the Adjustable Input Level
section can be used to construct a comparator. The threshold for
the comparator is provided by the SIO's reference generator. The
reference generator has the option to set the analog signal
routed through the analog global line as threshold for the
comparator. Note that a pair of SIO pins share the same
threshold.
In all low power modes the I/O pins retain their state until the part
is awakened and changed or reset. To awaken the part, use a
pin interrupt, because the port interrupt logic continues to
function in all low power modes.
6.4.18 Special Pin Functionality
Some pins on the device include additional special functionality
in addition to their GPIO or SIO functionality. The specific special
function pins are listed in “Pinouts” on page 5. The special
features are:
The digital input path in Figure 6-7 on page 28 illustrates this
functionality. In the figure, ‘Reference level’ is the analog signal
routed through the analog global. The hysteresis feature can
also be enabled for the input buffer of the SIO, which increases
noise immunity for the comparator.
Digital
4 to 33 MHz crystal oscillator
32.768 kHz crystal oscillator
6.4.14 Hot Swap
Wake from sleep on I2C address match. Any pin can be used
This section applies only to SIO pins. SIO pins support ‘hot swap’
capability to plug into an application without loading the signals
that are connected to the SIO pins even when no power is
applied to the PSoC device. This allows the unpowered PSoC to
maintain a high impedance load to the external device while also
preventing the PSoC from being powered through a GPIO pin’s
protection diode.
for I2C if wake from sleep is not required.
JTAG interface pins
SWD interface pins
SWV interface pins
External reset
Analog
Opamp inputs and outputs
High current IDAC outputs
External reference inputs
6.4.15 Over Voltage Tolerance
All I/O pins provide an over voltage (Vddio < Vin < Vdda)
tolerance feature at any operating Vdd.
6.4.19 JTAG Boundary Scan
There are no current limitations for the SIO pins as they present
a high impedance load to the external circuit.
The device supports standard JTAG boundary scan chains on all
pins for board level test.
TheGPIOpinsmustbelimitedto100µAusingacurrentlimiting
resistor. GPIO pins clamp the pin voltage to approximately one
diode above the Vddio supply.
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Figure 7-1. CY8C54 Digital Programmable Architecture
7. Digital Subsystem
The digital programmable system creates application specific
combinations of both standard and advanced digital peripherals
and custom logic functions. These peripherals and logic are then
interconnected to each other and to any pin on the device,
providing a high level of design flexibility and IP security.
Digital Core System
and Fixed Function Peripherals
The features of the digital programmable system are outlined
here to provide an overview of capabilities and architecture.
Designers do not need to interact directly with the programmable
digital system at the hardware and register level. PSoC Creator
provides a high level schematic capture graphical interface to
automatically place and route resources similar to PLDs.
DSI Routing Interface
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
The main components of the digital programmable system are:
Universal Digital Blocks (UDB) - These form the core function-
ality of the digital programmable system. UDBs are a collection
of uncommitted logic (PLD) and structural logic (Datapath)
optimized to create all common embedded peripherals and
customized functionality that are application or design specific.
DSI Routing Interface
Universal Digital Block Array - UDB blocks are arrayed within
a matrix of programmable interconnect. The UDB array
structure is homogeneous and allows for flexible mapping of
digital functions onto the array. The array supports extensive
and flexible routing interconnects between UDBs and the
Digital System Interconnect.
Digital Core System
and Fixed Function Peripherals
Digital System Interconnect (DSI) - Digital signals from
Universal Digital Blocks (UDBs), fixed function peripherals, I/O
pins, interrupts, DMA, and other system core signals are
attached to the Digital System Interconnect to implement full
featureddeviceconnectivity.TheDSIallowsanydigitalfunction
to any pin or other feature routability when used with the
Universal Digital Block Array.
7.1 Example Peripherals
The flexibility of the CY8C54 family’s Universal Digital Blocks
(UDBs) and Analog Blocks allow the user to create a wide range
of components (peripherals). The most common peripherals
were built and characterized by Cypress and are shown in the
PSoC Creator component catalog, however, users may also
create their own custom components using PSoC Creator. Using
PSoC Creator, users may also create their own components for
reuse within their organization, for example sensor interfaces,
proprietary algorithms, and display interfaces.
The number of components available through PSoC Creator is
too numerous to list in the data sheet, and the list is always
growing. An example of a component available for use in
CY8C54 family, but, not explicitly called out in this data sheet is
the UART component.
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7.1.1 Example Digital Components
Comparators
Mixers
The following is a sample of the digital components available in
PSoC Creator for the CY8C54 family. The exact amount of
hardware resources (UDBs, routing, RAM, Flash) used by a
component varies with the features selected in PSoC Creator for
the component.
7.1.3 Example System Function Components
The following is a sample of the system function components
available in PSoC Creator for the CY8C54 family. The exact
amount of hardware resources (UDBs, DFB taps, SC/CT blocks,
routing, RAM, Flash) used by a component varies with the
features selected in PSoC Creator for the component.
Communications
I2C (1 to 3 UDBs)
UART (1 to 3 UDBs)
CapSense
LCD Drive
LCD Control
Filters
Functions
EMIF (External Memory Interface, 1 UDB)
Logic (x CPLD product terms per logic function)
NOT
OR
XOR
AND
7.1.4 Designing with PSoC Creator
7.1.4.1 More Than a Typical IDE
7.1.2 Example Analog Components
A successful design tool allows for the rapid development and
deployment of both simple and complex designs. It reduces or
eliminates any learning curve. It makes the integration of a new
design into the production stream straightforward.
The following is a sample of the analog components available in
PSoC Creator for the CY8C54 family. The exact amount of
hardware resources (SC/CT blocks, routing, RAM, Flash) used
by a component varies with the features selected in PSoC
Creator for the component.
PSoC Creator is that design tool.
PSoC Creator is a full featured Integrated Development
Environment (IDE) for hardware and software design. It is
optimized specifically for PSoC devices and combines a modern,
powerful software development platform with a sophisticated
graphical design tool. This unique combination of tools makes
PSoC Creator the most flexible embedded design platform
available.
Amplifiers
TIA
PGA
opamp
ADCs
Successive Approximation (SAR)
Graphical design entry simplifies the task of configuring a
particular part. You can select the required functionality from an
extensive catalog of components and place it in your design. All
components are parameterized and have an editor dialog that
allows you to tailor functionality to your needs.
DACs
Current
Voltage
PWM
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PSoC Creator automatically configures clocks and routes the I/O
to the selected pins and then generates APIs to give the appli-
cation complete control over the hardware. Changing the PSoC
device configuration is as simple as adding a new component,
setting its parameters, and rebuilding the project.
devices, even from 8- to 32-bit families, just select the new
device and rebuild.
You also have the ability to change the C compiler and evaluate
an alternative. Components are designed for portability and are
validated against all devices, from all families, and against all
supported tool chains. Switching compilers is as easy as editing
the from the project options and rebuilding the application with
no errors from the generated APIs or boot code.
At any stage of development you are free to change the
hardware configuration and even the target processor. To
retarget your application (hardware and software) to new
Figure 7-2. PSoC Creator Framework
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7.1.4.2 Component Catalog
7.1.4.4 Software Development
Figure 7-3. Component Catalog
Figure 7-4. Code Editor
Anchoring the tool is a modern, highly customizable user
interface. It includes project management and integrated editors
for C and assembler source code, as well the design entry tools.
Project build control leverages compiler technology from top
commercial vendors such as ARM® Limited, Keil™, and
CodeSourcery (GNU). Free versions of Keil C51 and GNU C
Compiler (GCC) for ARM, with no restrictions on code size or end
product distribution, are included with the tool distribution.
Upgrading to more optimizing compilers is a snap with support
for the professional Keil C51 product and ARM RealView™
compiler.
The component catalog is a repository of reusable design
elements that select device functionality and customize your
PSoC device. It is populated with an impressive selection of
content; from simple primitives such as logic gates and device
registers, through the digital timers, counters and PWMs, plus
analog components such as ADCs, DACs, and filters, and
communication protocols, such as I2C, USB and CAN. See
“Example Peripherals” section on page 32 for more details about
available peripherals. All content is fully characterized and
carefully documented in datasheets with code examples, AC/DC
specifications, and user code ready APIs.
7.1.4.5 Nonintrusive Debugging
Figure 7-5. PSoC Creator Debugger
7.1.4.3 Design Reuse
The symbol editor gives you the ability to develop reusable
components that can significantly reduce future design time. Just
draw a symbol and associate that symbol with your proven
design. PSoC Creator allows for the placement of the new
symbol anywhere in the component catalog along with the
content provided by Cypress. You can then reuse your content
as many times as you want, and in any number of projects,
without ever having to revisit the details of the implementation.
With JTAG (4-wire) and SWD (2-wire) debug connectivity
available on all devices, the PSoC Creator debugger offers full
control over the target device with minimum intrusion. Break-
points and code execution commands are all readily available
from toolbar buttons and an impressive lineup of
windows—register, locals, watch, call stack, memory and periph-
erals—make for an unparalleled level of visibility into the system.
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PSoC Creator contains all the tools necessary to complete a
design, and then to maintain and extend that design for years to
come. All steps of the design flow are carefully integrated and
optimized for ease-of-use and to maximize productivity.
ofcompare configurations andcondition generation. Thisblock
alsocontainsinput/outputFIFOs, whicharetheprimaryparallel
data interface between the CPU/DMA system and the UDB.
Status and Control Module - The primary role of this block is to
provide a way for CPU firmware to interact and synchronize
with UDB operation.
7.2 Universal Digital Block
The Universal Digital Block (UDB) represents an evolutionary
step to the next generation of PSoC embedded digital peripheral
functionality. The architecture in first generation PSoC digital
blocks provides coarse programmability in which a few fixed
functions with a small number of options are available. The new
UDB architecture is the optimal balance between configuration
granularity and efficient implementation. A cornerstone of this
approach is to provide the ability to customize the devices digital
operation to match application requirements.
Clock and Reset Module - This block provides the UDB clocks
and reset selection and control.
7.2.1 PLD Module
The primary purpose of the PLD blocks is to implement logic
expressions, state machines, sequencers, look up tables, and
decoders. In the simplest use model, consider the PLD blocks as
a standalone resource onto which general purpose RTL is
synthesized and mapped. The more common and efficient use
model is to create digital functions from a combination of PLD
and datapath blocks, where the PLD implements only the
random logic and state portion of the function while the datapath
(ALU) implements the more structured elements.
To achieve this, UDBs consist of a combination of uncommitted
logic (PLD), structured logic (Datapath), and a flexible routing
scheme to provide interconnect between these elements, I/O
connections, and other peripherals. UDB functionality ranges
from simple self contained functions that are implemented in one
UDB, or even a portion of a UDB (unused resources are
available for other functions), to more complex functions that
require multiple UDBs. Examples of basic functions are timers,
counters, CRC generators, PWMs, dead band generators, and
communications functions, such as UARTs, SPI, and I2C. Also,
the PLD blocks and connectivity provide full featured general
purpose programmable logic within the limits of the available
resources.
Figure 7-7. PLD 12C4 Structure
IN0
IN1
IN2
IN3
IN4
IN5
IN6
IN7
IN8
IN9
IN10
IN11
T C T C T C T C T C T C T C T C
T C T C T C T C T C T C T C T C
T C T C T C T C T C T C T C T C
T C T C T C T C T C T C T C T C
T C T C T C T C T C T C T C T C
T C T C T C T C T C T C T C T C
T C T C T C T C T C T C T C T C
T C T C T C T C T C T C T C T C
T C T C T C T C T C T C T C T C
T C T C T C T C T C T C T C T C
T C T C T C T C T C T C T C T C
T C T C T C T C T C T C T C T C
Figure 7-6. UDB Block Diagram
AND
Array
PLD
Chaining
PLD
12C4
(8 PTs)
PLD
12C4
(8 PTs)
Clock
and Reset
Control
SELIN
(carry in)
OUT0
OUT1
OUT2
OUT3
MC0
MC1
MC2
MC3
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
Status and
Control
Datapath
Datapath
Chaining
SELOUT
(carry out)
OR
Array
Routing Channel
One 12C4 PLD block is shown in Figure 7-7. This PLD has 12
inputs, which feed across eight product terms. Each product term
(AND function) can be from 1 to 12 inputs wide, and in a given
product term, the true (T) or complement (C) of each input can
be selected. The product terms are summed (OR function) to
create the PLD outputs. A sum can be from 1 to 8 product terms
wide. The 'C' in 12C4 indicates that the width of the OR gate (in
this case 8) is constant across all outputs (rather than variable
as in a 22V10 device). This PLA like structure gives maximum
flexibility and insures that all inputs and outputs are permutable
for ease of allocation by the software tools. There are two 12C4
PLDs in each UDB.
The main component blocks of the UDB are:
PLD blocks - There are two small PLDs per UDB. These blocks
take inputs from the routing array and form registered or combi-
national sum-of-products logic. PLDs are used to implement
state machines, state bits, and combinational logic equations.
PLD configuration is automatically generated from graphical
primitives.
Datapath Module - This 8-bit wide datapath contains structured
logic to implement a dynamically configurable ALU, a variety
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7.2.2 Datapath Module
optimized to implement embedded functions, such as timers,
counters, integrators, PWMs, PRS, CRC, shifters and dead band
generators and many others.
The datapath contains an 8-bit single cycle ALU, with associated
compare and condition generation logic. This datapath block is
Figure 7-8. Datapath Top Level
PHUB System Bus
R/W Access to All
Registers
F1
FIFOs
F0
Output
Muxes
Input
Muxes
A0
A1
D0
D1
Input from
Programmable
Routing
Output to
Programmable
Routing
6
6
D1
Data Registers
D0
To/From
Previous
Datapath
To/From
Next
Datapath
Chaining
A1
Accumulators
A0
PI
Parallel Input/Output
(to/from Programmable Routing)
PO
ALU
Shift
Mask
7.2.2.6 Working Registers
7.2.2.7 Dynamic Datapath Configuration RAM
The datapath contains six primary working registers, which are
accessed by CPU firmware or DMA during normal operation.
Dynamic configuration is the ability to change the datapath
function and internal configuration on a cycle-by-cycle basis,
under sequencer control. This is implemented using the 8-word
x 16-bit configuration RAM, which stores eight unique 16-bit wide
configurations. The address input to this RAM controls the
sequence, and can be routed from any block connected to the
UDB routing matrix, most typically PLD logic, I/O pins, or from
the outputs of this or other datapath blocks.
Table 7-1. Working Datapath Registers
Name
Function
Description
A0 and A1 Accumulators
These are sources and sinks for
the ALU and also sources for the
compares.
ALU
D0 and D1 Data Registers These are sources for the ALU
and sources for the compares.
The ALU performs eight general purpose functions. They are:
F0 and F1 FIFOs
These are the primary interface
to the system bus. They can be a
data source for the data registers
and accumulators or they can
capture data from the accumu-
lators or ALU. Each FIFO is four
bytes deep.
Increment
Decrement
Add
Subtract
Logical AND
Logical OR
Logical XOR
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Independent of the ALU operation, these functions are available:
Figure 7-9. Example FIFO Configurations
Shift left
System Bus
System Bus
Shift right
Nibble swap
Bitwise OR mask
F0
F0
F1
7.2.2.8 Conditionals
D0/D1
D0
A0
D1
A1
Each datapath has two compares, with bit masking options.
Compare operands include the two accumulators and the two
data registers in a variety of configurations. Other conditions
include zero detect, all ones detect, and overflow. These condi-
tions are the primary datapath outputs, a selection of which can
be driven out to the UDB routing matrix. Conditional computation
can use the built in chaining to neighboring UDBs to operate on
wider data widths without the need to use routing resources.
A0/A1/ALU
A0/A1/ALU
F0
A0/A1/ALU
F1
F1
System Bus
System Bus
Dual Capture
7.2.2.9 Variable MSB
TX/RX
Dual Buffer
The most significant bit of an arithmetic and shift function can be
programmatically specified. This supports variable width CRC
and PRS functions, and in conjunction with ALU output masking,
can implement arbitrary width timers, counters and shift blocks.
7.2.2.12 Chaining
The datapath can be configured to chain conditions and signals
such as carries and shift data with neighboring datapaths to
create higher precision arithmetic, shift, CRC/PRS functions.
7.2.2.10 Built in CRC/PRS
The datapath has built in support for single cycle Cyclic Redun-
dancy Check (CRC) computation and Pseudo Random
Sequence (PRS) generation of arbitrary width and arbitrary
polynomial. CRC/PRS functions longer than 8 bits may be imple-
mented in conjunction with PLD logic, or built in chaining may be
use to extend the function into neighboring UDBs.
7.2.2.13 Time Multiplexing
In applications that are over sampled, or do not need high clock
rates, the single ALU block in the datapath can be efficiently
shared with two sets of registers and condition generators. Carry
and shift out data from the ALU are registered and can be
selected as inputs in subsequent cycles. This provides support
for 16-bit functions in one (8-bit) datapath.
7.2.2.11 Input/Output FIFOs
Each datapath contains two four-byte deep FIFOs, which can be
independently configured as an input buffer (system bus writes
to the FIFO, datapath internal reads the FIFO), or an output
buffer (datapath internal writes to the FIFO, the system bus reads
from the FIFO). The FIFOs generate status that are selectable
as datapath outputs and can therefore be driven to the routing,
to interact with sequencers, interrupts, or DMA.
7.2.2.14 Datapath I/O
There are six inputs and six outputs that connect the datapath to
the routing matrix. Inputs from the routing provide the configu-
ration for the datapath operation to perform in each cycle, and
the serial data inputs. Inputs can be routed from other UDB
blocks, other device peripherals, device I/O pins, and so on. The
outputs to the routing can be selected from the generated condi-
tions, and the serial data outputs. Outputs can be routed to other
UDB blocks, device peripherals, interrupt and DMA controller,
I/O pins, and so on.
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7.2.3 Status and Control Module
7.3 UDB Array Description
The primary purpose of this circuitry is to coordinate CPU
firmware interaction with internal UDB operation.
Figure 7-11 shows an example of a 16 UDB array. In addition to
the array core, there are a DSI routing interfaces at the top and
bottom of the array. Other interfaces that are not explicitly shown
include the system interfaces for bus and clock distribution. The
UDB array includes multiple horizontal and vertical routing
channels each comprised of 96 wires. The wire connections to
UDBs, at horizontal/vertical intersection and at the DSI interface
are highly permutable providing efficient automatic routing in
PSoC Creator. Additionally the routing allows wire by wire
segmentation along the vertical and horizontal routing to further
increase routing flexibility and capability.
Figure 7-10. Status and Control Registers
System Bus
8-bit Status Register
(Read Only)
8-bit Control Register
(Write/Read)
Figure 7-11. Digital System Interface Structure
System Connections
Routing Channel
HV
B
HV
A
HV
B
HV
A
The bits of the control register, which may be written to by the
system bus, are used to drive into the routing matrix, and thus
provide firmware with the opportunity to control the state of UDB
processing. The status register is read-only and it allows internal
UDB state to be read out onto the system bus directly from
internal routing. This allows firmware to monitor the state of UDB
processing. Each bit of these registers has programmable
connections to the routing matrix and routing connections are
made depending on the requirements of the application.
UDB
UDB
UDB
UDB
HV
A
HV
B
HV
A
HV
B
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
7.2.3.15 Usage Examples
As an example of control input, a bit in the control register can
be allocated as a function enable bit. There are multiple ways to
enable a function. In one method the control bit output would be
routed to the clock control block in one or more UDBs and serve
as a clock enable for the selected UDB blocks. A status example
is a case where a PLD or datapath block generated a condition,
such as a “compare true” condition that is captured and latched
by the status register and then read (and cleared) by CPU
firmware.
HV
B
HV
A
HV
B
HV
A
UDB
UDB
UDB
UDB
HV
A
HV
B
HV
A
HV
B
7.2.3.16 Clock Generation
System Connections
Each subcomponent block of a UDB including the two PLDs, the
datapath, and Status and Control, has a clock selection and
control block. This promotes a fine granularity with respect to
allocating clocking resources to UDB component blocks and
allows unused UDB resources to be used by other functions for
maximum system efficiency.
7.3.1 UDB Array Programmable Resources
Figure 7-12 shows an example of how functions are mapped into
a bank of 16 UDBs. The primary programmable resources of the
UDB are two PLDs, one datapath and one status/control register.
These resources are allocated independently, because they
have independently selectable clocks, and therefore unused
blocks are allocated to other unrelated functions.
An example of this is the 8-bit Timer in the upper left corner of
the array. This function only requires one datapath in the UDB,
and therefore the PLD resources may be allocated to another
function. A function such as a Quadrature Decoder may require
more PLD logic than one UDB can supply and in this case can
utilize the unused PLD blocks in the 8-bit Timer UDB. Program-
mable resources in the UDB array are generally homogeneous
so functions can be mapped to arbitrary boundaries in the array.
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Figure 7-12. Function Mapping Example in a Bank of UDBs
Figure 7-13. Digital System Interconnect
8-Bit
Timer
16-Bit
PWM
Quadrature Decoder
16-Bit PYRS
UDB
Timer
Counters
Interrupt
Controller
DMA
Controller
IO Port
Pins
IO Port
Pins
CAN
I2C
UDB
UDB
UDB
HV
A
HV
B
HV
A
HV
B
Digital System Routing I/F
UDB ARRAY
UDB
8-Bit
UDB
8-Bit SPI
UDB
UDB
Timer
Logic
I2C Slave
UDB
12-Bit SPI
UDB
UDB
UDB
Digital System Routing I/F
HV
B
HV
A
HV
B
HV
A
Logic
UDB
UDB
UDB
UDB
UART
12-Bit PWM
Global
Clocks
Global
Clocks
SAR
ADC
SC
Blocks
EMIF
DACS
Comparators
7.4 DSI Routing Interface Description
Interrupt and DMA routing is very flexible in the CY8C54
programmable architecture. In addition to the numerous fixed
function peripherals that can generate interrupt requests, any
data signal in the UDB array routing can also be used to generate
The DSI routing interface is a continuation of the horizontal and
vertical routing channels at the top and bottom of the UDB array
core. It provides general purpose programmable routing
between device peripherals, including UDBs, I/Os, analog
peripherals, interrupts, DMA and fixed function peripherals.
a
request. A single peripheral may generate multiple
independent interrupt requests simplifying system and firmware
design. Figure 7-14 shows the structure of the IDMUX
(Interrupt/DMA Multiplexer).
Figure 7-13 illustrates the concept of the digital system inter-
connect, which connects the UDB array routing matrix with other
device peripherals. Any digital core or fixed function peripheral
that needs programmable routing is connected to this interface.
Figure 7-14. Interrupt and DMA Processing in the IDMUX
Signals in this category include:
Interrupt and DMA Processing in IDMUX
Interrupt requests from all digital peripherals in the system.
DMA requests from all digital peripherals in the system.
Digital peripheral data signals that need flexible routing to I/Os.
Digital peripheral data signals that need connections to UDBs.
Connections to the interrupt and DMA controllers.
Connection to I/O pins.
Fixed Function IRQs
0
1
Interrupt
Controller
IRQs
2
3
UDB Array
Edge
Detect
DRQs
DMA termout (IRQs)
Connection to analog system digital signals.
0
Fixed Function DRQs
DMA
Controller
1
2
Edge
Detect
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7.4.1 I/O Port Routing
There are four more DSI connections to a given I/O port to
implement dynamic output enable control of pins. This connec-
tivity gives a range of options, from fully ganged 8-bits controlled
by one signal, to up to four individually controlled pins. The
output enable signal is useful for creating tri-state bidirectional
pins and buses.
There are a total of 20 DSI routes to a typical 8-bit I/O port, 16
for data and four for drive strength control.
When an I/O pin is connected to the routing, there are two
primary connections available, an input and an output. In
conjunction with drive strength control, this can implement a
bidirectional I/O pin. A data output signal has the option to be
single synchronized (pipelined) and a data input signal has the
option to be double synchronized. The synchronization clock is
the system clock (see Figure 6-1). Normally all inputs from pins
are synchronized as this is required if the CPU interacts with the
signal or any signal derived from it. Asynchronous inputs have
rare uses. An example of this is a feed through of combinational
PLD logic from input pins to output pins.
Figure 7-17. I/O Pin Output Enable Connectivity
4 IO Control Signal Connections from
UDB Array Digital System Interface
Figure 7-15. I/O Pin Synchronization Routing
DO
DI
OE
PIN 0
OE
PIN1
OE
PIN2
OE
PIN3
OE
PIN4
OE
PIN5
OE
PIN6
OE
PIN7
Port i
Figure 7-16. I/O Pin Output Connectivity
7.5 CAN
The CAN peripheral is a fully functional Controller Area Network
(CAN) supporting communication baud rates up to 1 Mbps. The
CAN controller implements the CAN2.0A and CAN2.0B specifi-
cations as defined in the Bosch specification and conforms to the
ISO-11898-1 standard. The CAN protocol was originally
designed for automotive applications with a focus on a high level
of fault detection. This ensures high communication reliability at
a low cost. Because of its success in automotive applications,
CAN is used as a standard communication protocol for motion
oriented machine control networks (CANOpen) and factory
automation applications (DeviceNet). The CAN controller
features allow the efficient implementation of higher level
protocols without affecting the performance of the microcon-
troller CPU. Full configuration support is provided in PSoC
Creator.
8 IO Data Output Connections from the
UDB Array Digital System Interface
DO
DO
PIN1
DO
PIN2
DO
PIN3
DO
PIN4
DO
PIN5
DO
PIN6
DO
PIN7
PIN 0
Port i
Document Number: 001-55036 Rev. *A
Page 41 of 93
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PRELIMINARY
PSoC®5:CY8C54FamilyData Sheet
Figure 7-18. CAN Bus System Implementation
CAN Node 1
PSoC
CAN Node 2
CAN Node n
CAN
Drivers
CAN Controller
En
Tx Rx
CAN Transceiver
CAN_H
CAN_H
CAN_L
CAN_H
CAN_L
CAN_L
CAN Bus
7.5.1 CAN Features
Receive path
16 receive buffers each with its own message filter
Enhanced hardware message filter implementation that cov-
ers the ID, IDE and RTR
DeviceNet addressing support
Multiple receive buffers linkable to build a larger receive mes-
sage array
CAN2.0A/B protocol implementation - ISO 11898 compliant
Standard and extended frames with up to 8 bytes of data per
frame
Message filter capabilities
Remote Transmission Request (RTR) support
Programmable bit rate up to 1 Mbps
Automatic transmission request (RTR) response handler
Lost received message notification
Listen Only mode
Transmit path
SW readable error counter and indicator
Eight transmit buffers
Programmable transmit priority
Round robin
Fixed priority
Message transmissions abort capability
Sleep mode: Wake the device from sleep with activity on the
Rx pin
Supports two or three wire interface to external transceiver (Tx,
Rx, and Enable). The three-wire interface is compatible with
the Philips PHY; the PHY is not included on-chip. The three
wires can be routed to any I/O
7.5.2 Software Tools Support
Enhanced interrupt controller
CAN Controller configuration integrated into PSoC Creator:
CAN receive and transmit buffers status
CAN controller error status including BusOff
CAN Configuration walkthrough with bit timing analyzer
Receive filter setup
Document Number: 001-55036 Rev. *A
Page 42 of 93
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PRELIMINARY
PSoC®5:CY8C54FamilyData Sheet
Figure 7-19. CAN Controller Block Diagram
TxMessage0
TxReq
TxAbort
TxMessage1
TxReq
TxAbort
Tx Buffer
Status
TxReq
Bit Timing
Pending
Priority
Arbiter
Tx
TxMessage6
TxReq
Tx
CAN
Framer
CRC
Generator
TxInterrupt
Request
TxAbort
(if enabled)
TxMessage7
TxReq
TxAbort
Error Status
Error Active
Error Passive
Bus Off
Tx Error Counter
Rx Error Counter
RTR RxMessages
0-15
Acceptance Code 0
RxMessage0
RxMessage1
Acceptance Mask 0
Acceptance Mask 1
Rx Buffer
Status
RxMessage
Available
Acceptance Code 1
Rx
Rx
RxMessage
Handler
CAN
Framer
CRC Check
RxMessage14
RxMessage15
Acceptance Mask 14
Acceptance Mask 15
Acceptance Code 14
Acceptance Code 15
RxInterrupt
Request
(if enabled)
WakeUp
Request
Error Detection
CRC
Form
ACK
ErrInterrupt
Request
Bit Stuffing
Bit Error
Overload
Arbitration
(if enabled)
Internal 48 MHz oscillator that auto locks to USB bus clock,
requiring no external crystal for USB (USB equipped parts only)
7.6 USB
PSoC includes a dedicated Full-Speed (12 Mbps) USB 2.0 trans-
ceiver supporting all four USB transfer types: control, interrupt,
bulk, and isochronous. The maximum data payload size is 64
bytes for control, interrupt, and bulk endpoints and 1023 bytes
for isochronous. PSoC Creator provides full configuration
support. USB interfaces to hosts through two dedicated USBIO
pins, which are detailed in the “I/O System and Routing” section
on page 26.
Interrupts on bus and each endpoint event, with device wakeup
USB Reset, Suspend, and Resume operations
Bus powered and self powered modes
Figure 7-20. USB
USB includes the following features:
512 X 8
SRAM
Arbiter
Eight unidirectional data endpoints
One bidirectional control endpoint 0 (EP0)
Shared 512-byte buffer for the eight data endpoints
Dedicated 8-byte buffer for EP0
S I E
(Serial Interface
Engine)
D+
D-
USB
IO
Three memory modes
Interrupts
Manual Memory Management with No DMA Access
Manual Memory Management with Manual DMA Access
Automatic Memory Management with Automatic DMA Ac-
cess
48 MHz
IMO
Internal 3.3V regulator for transceiver
Document Number: 001-55036 Rev. *A
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PRELIMINARY
PSoC®5:CY8C54FamilyData Sheet
2
7.7 Timers, Counters, and PWMs
7.8 I C
2
The Timer/Counter/PWM peripheral is a 16-bit dedicated
peripheral providing three of the most common embedded
peripheral features. As almost all embedded systems use some
combination of timers, counters, and PWMs. Four of them have
been included on this PSoC device family. Additional and more
advanced functionality timers, counters, and PWMs can also be
instantiated in Universal Digital Blocks (UDBs) as required.
PSoC Creator allows designers to choose the timer, counter, and
PWM features that they require. The tool set utilizes the most
optimal resources available.
The I C peripheral provides a synchronous two wire interface
2
designed to interface the PSoC device with a two wire I C serial
communication bus. The bus is compliant with Philips ‘The I C
Specification’ version 2.1. Additional I C interfaces can be
instantiated using Universal Digital Blocks (UDBs) in PSoC
2
2
Creator, as required.
To eliminate the need for excessive CPU intervention and
overhead, I C specific support is provided for status detection
and generation of framing bits. I C operates as a slave, a master,
2
2
or multimaster (Slave and Master). In slave mode, the unit
always listens for a start condition to begin sending or receiving
data. Master mode supplies the ability to generate the Start and
Stop conditions and initiate transactions. Multimaster mode
provides clock synchronization and arbitration to allow multiple
masters on the same bus. If Master mode is enabled and Slave
mode is not enabled, the block does not generate interrupts on
externally generated Start conditions. I C interfaces through the
DSI routing and allows direct connections to any GPIO or SIO
pins.
The Timer/Counter/PWM peripheral can select from multiple
clock sources, with input and output signals connected through
the DSI routing. DSI routing allows input and output connections
to any device pin and any internal digital signal accessible
through the DSI. Each of the four instances has a compare
output, terminal count output (optional complementary compare
output), and programmable interrupt request line. The
Timer/Counter/PWMs are configurable as free running, one shot,
or Enable input controlled. The peripheral has timer reset and
capture inputs, and a kill input for control of the comparator
outputs. The peripheral supports full 16-bit capture.
2
2
I C provides hardware address detect of a 7-bit address without
CPU intervention. Additionally the device can wake from low
power modes on a 7-bit hardware address match. If wakeup
functionality is required, I C pin connections are limited to the
Timer/Counter/PWM features include:
2
16-bit Timer/Counter/PWM (down count only)
Selectable clock source
two special sets of SIO pins.
2
I C features include:
PWM comparator (configurable for LT, LTE, EQ, GTE, GT)
Period reload on start, reset, and terminal count
Interrupt on terminal count, compare true, or capture
Dynamic counter reads
Slave and Master, Transmitter, and Receiver operation
Byte processing for low CPU overhead
Interrupt or polling CPU interface
Support for bus speeds up to 1 Mbps (3.4 Mbps in UDBs)
Timer capture mode
7 or 10-bit addressing (10-bit addressing requires firmware
support)
Count while enable signal is asserted mode
Free run mode
SMBus operation (through firmware support - SMBus
supported in hardware in UDBs)
One Shot mode (stop at end of period)
Complementary PWM outputs with deadband
PWM output kill
7-bit hardware address compare
Wake from low power modes on address match
Figure 7-21. Timer/Counter/PWM
Clock
IRQ
Reset
Timer / Counter /
Enable
TC / Compare!
Compare
PWM 16-bit
Capture
Kill
Document Number: 001-55036 Rev. *A
Page 44 of 93
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PRELIMINARY
PSoC®5:CY8C54FamilyData Sheet
7.9 Digital Filter Block
8. Analog Subsystem
Some devices in the CY8C54 family of devices have a dedicated
HW accelerator block used for digital filtering. The DFB has a
dedicated multiplier and accumulator that calculates a 24-bit by
24-bit multiply accumulate in one system clock cycle. This
enables the mapping of a direct form FIR filter that approaches
a computation rate of one FIR tap for each clock cycle. The MCU
can implement any of the functions performed by this block, but
at a slower rate that consumes significant MCU bandwidth.
The analog programmable system creates application specific
combinations of both standard and advanced analog signal
processing blocks. These blocks are then interconnected to
each other and also to any pin on the device, providing a high
level of design flexibility and IP security. The features of the
analog subsystem are outlined here to provide an overview of
capabilities and architecture.
Flexible, configurable analog routing architecture provided by
analog globals, analog mux bus, and analog local buses
The PSoC Creator interface provides a wizard to implement FIR
and IIR digital filters with coefficients for LPF, BPF, HPF, Notch
and arbitrary shape filters. 64 pairs of data and coefficients are
stored. This enables a 64 tap FIR filter or up to 4 16 tap filters of
either FIR or IIR formulation.
Two successive approximation (SAR) ADCs
Four 8-bit DACs that provide either voltage or current output
Figure 7-22. DFB Application Diagram (pwr/gnd not shown)
FourcomparatorswithoptionalconnectiontoconfigurableLUT
outputs
Four configurable switched capacitor/continuos time (SC/CT)
blocks for functions that include opamp, unity gain buffer,
programmable gain amplifier, transimpedance amplifier, and
mixer
BUSCLK
read_data
write_data
Data
Source
(PHUB)
System
Bus
addr
Four opamps for internal use and connection to GPIO that can
be used as high current output buffers
Digital
Routing
Digital Filter
Block
Data
Dest
(PHUB)
CapSense subsystem to enable capacitive touch sensing
DMA
Request
Precision reference for generating an accurate analog voltage
for internal analog blocks
DMA
CTRL
The typical use model is for data to be supplied to the DFB over
the system bus from another on-chip system data source such
as an ADC. The data typically passes through main memory or
is directly transferred from another chip resource through DMA.
The DFB processes this data and passes the result to another
on chip resource such as a DAC or main memory through DMA
on the system bus.
Data movement in or out of the DFB is typically controlled by the
system DMA controller but can be moved directly by the MCU.
Document Number: 001-55036 Rev. *A
Page 45 of 93
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PRELIMINARY
PSoC®5:CY8C54FamilyData Sheet
Figure 8-1. Analog Subsystem Block Diagram
SAR
SAR
DAC
DAC
DAC
DAC
Precision
Reference
A
N
A
L
O
G
A
N
A
L
O
G
SC/CT Block
SC/CT Block
SC/CT Block
SC/CT Block
GPIO
Port
GPIO
Port
R
O
U
T
I
R
O
U
T
I
Comparators
CMP CMP
N
G
N
G
CMP
CMP
CapSense Subsystem
Config &
Status
Registers
Analog
Interface
AHB
PHUB
CPU
DSI
Array
Clock
Distribution
The PSoC Creator software program provides a user friendly
interface to configure the analog connections between the GPIO
and various analog resources and also connections from one
analog resource to another. PSoC Creator also provides
component libraries that allow you to configure the various
analog blocks to perform application specific functions (PGA,
transimpedance amplifier, voltage DAC, current DAC, and so
on). The tool also generates API interface libraries that allow you
to write firmware that allows the communication between the
analog peripheral and CPU/Memory.
Each GPIO is connected to one analog global and one analog
mux bus
8 Analog local buses (abus) to route signals between the
different analog blocks
Multiplexers and switches for input and output selection of the
analog blocks
8.1.2 Functional Description
Analog globals (AGs) and analog mux buses (AMUXBUS)
provide analog connectivity between GPIOs and the various
analog blocks. There are 16 AGs in the CY8C38 family. The
analog routing architecture is divided into four quadrants as
shown in Figure 8-2. Each quadrant has four analog globals
(AGL[0..3], AGL[4..7], AGR[0..3], AGR[4..7]). Each GPIO is
connected to the corresponding AG through an analog switch.
The analog mux bus is a shared routing resource that connects
to every GPIO through an analog switch. There are two
AMUXBUS routes in CY8C38, one in the left half (AMUXBUSL)
and one in the right half (AMUXBUSR), as shown in Figure 8-2.
8.1 Analog Routing
The CY8C38 family of devices has a flexible analog routing
architecture that provides the capability to connect GPIOs and
different analog blocks, and also route signals between different
analog blocks. One of the strong points of this flexible routing
architecture is that it allows dynamic routing of input and output
connections to the different analog blocks.
8.1.1 Features
Flexible, configurable analog routing architecture
16 Analog globals (AG) and two analog mux buses
(AMUXBUS) to connect GPIOs and the analog blocks
Document Number: 001-55036 Rev. *A
Page 46 of 93
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PRELIMINARY
PSoC®5:CY8C54FamilyData Sheet
Figure 8-2. CY8C54 Analog Interconnect
*
*
*
*
*
*
*
*
*
*
*
*
*
*
AMUXBUSR
AMUXBUSL
AGL[4]
AGL[5]
AGL[6]
AGL[7]
AGR[4]
AGR[5]
AGR[6]
AGR[7]
ExVrefL
ExVrefL1
ExVrefL2
44
GPIO
P3[5]
GPIO
opamp1
opamp3
opamp0
opamp2
0123
3210
76543210
01234567
GPIO
P0[4]
GPIO
P0[5]
GPIO
P0[6]
GPIO
P0[7]
P3[4]
GPIO
P3[3]
GPIO
P3[2]
GPIO
P3[1]
GPIO
P3[0]
GPXT
P15[1]
GPXT
P15[0]
LPF
in0
out0
in1
out1
1.024V
1.024V
i0
i2
*
*
5
ExVrefR
+
+
comp1
comp0
i3
i1
-
-
COMPARATOR
1.024V
1.024V
+
-
+
-
comp2
GPIO
P4[2]
GPIO
P4[3]
GPIO
P4[4]
GPIO
P4[5]
GPIO
P4[6]
GPIO
comp3
0.256V
90
*
*
vda, vda/2
1.024V
1.024V
1.2V
out
ref
in
out
ref
CAPSENSE
refbufl
1.2V
refbufr
in
Vssa
Vssa
sc0
Vin
Vref
out
sc1
Vin
Vref
*
Vccd
1.024V
out
1.024V
Vssio
SC/CT
Vin
Vref
out
sc2
Vin
Vref
out
sc3
*
P4[7]
Vssd
*
104
*
Vccd
Vddd
*
Vssd
ABUSL0
ABUSL1
ABUSL2
ABUSL3
ABUSR0
ABUSR1
ABUSR2
Vusb
Vssio
ABUSR3
*
Vddd
GPIO
P6[0]
GPIO
P6[1]
GPIO
P6[2]
GPIO
P6[3]
GPIO
P15[4]
GPIO
P15[5]
GPIO
P2[0]
GPIO
P2[1]
GPIO
P2[2]
GPIO
P2[3]
GPIO
P2[4]
v0
i0
USB IO
P15[7]
USB IO
v1
*
VIDAC i1
v2
i2
36
v3
i3
*
P15[6]
GPIO
P5[7]
GPIO
P5[6]
GPIO
P5[5]
GPIO
P5[4]
SIO
P12[7]
SIO
P12[6]
GPIO
0.256V
vpwra,
vpwra/2
Vssa
0.8V
0.7V
1.2V
vda,
vda/4
1.024V
CY8C55 only
Vp (+)
Vn (-)
Vrefhi_out
refs
(+) Vp
(-) Vn
Vrefhi_out
SAR0
SAR1
SAR ADC refs
1.2V
1.2V
vda,
vda/2
vda,
vda/2
1.024V
1.024V
*
P1[7]
GPIO
ExVrefL1
ExVrefL2
AMUXBUSL
AMUXBUSR
76543210
0123
ANALOG
BUS
*
P1[6]
01234567
3210
ANALOG
ANALOG ANALOG
BUS GLOBALS
*
GLOBALS
*
VBE
AUX
ADC
*
:
VSS ref
Vio2
LPF
AGR[3]
AGL[3]
AGL[2]
AGL[1]
AGL[0]
AGR[2]
AGR[1]
AGR[0]
AMUXBUSR
AMUXBUSL
*
*
*
*
*
13
Mux Group
*
*
*
Switch Group
Connection
*
*
*
*
*
#
Size
Notes:
Other:
DFT 24 Small
LCD 15 Small
266 Small (higher z)
93/122 Large (lower z)
* Denotes pins on all packages
LCD signals are not shown.
Rev #43
22-Apr-2009
Document Number: 001-55036 Rev. *A
Page 47 of 93
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PRELIMINARY
PSoC®5:CY8C54FamilyData Sheet
Analog local buses (abus) are routing resources located within
the analog subsystem and are used to route signals between
different analog blocks. There are eight abus routes in CY8C38,
four in the left half (abusl [0:3]) and four in the right half (abusr
[0:3]) as shown in Figure 8-2. Using the abus saves the analog
globals and analog mux buses from being used for intercon-
necting the analog blocks.
8.2.2 Conversion Signals
Writing a start bit or assertion of a Start of Frame (SOF) signal is
used to start a conversion. SOF can be used in applications
where the sampling period is longer than the conversion time, or
when the ADC needs to be synchronized to other hardware. This
signal is optional and does not need to be connected if the SAR
ADC is running in a continuous mode. A digital clock or UDB
output can be used to drive this input. When the SAR is first
powered up or awakened from any of the sleeping modes, there
is a power up wait time of 10 µs before it is ready to start the first
conversion.
Multiplexers and switches exist on the various buses to direct
signals into and out of the analog blocks. A multiplexer can have
only one connection on at a time, whereas a switch can have
multiple connections on simultaneously. In Figure 8-2, multi-
plexers are indicated by grayed ovals and switches are indicated
by transparent ovals.
When the conversion is complete, a status bit is set and the
output signal End of Frame (EOF) asserts and remains asserted
until the value is read by either the DMA controller or the CPU.
The EOF signal may be used to trigger an interrupt or a DMA
request.
8.2 Successive Approximation ADCs
The CY8C54 family of devices has two Successive Approxi-
mation (SAR) ADCs. These ADCs are 12-bit at up to 1 Msps, with
single-ended or differential inputs, making them useful for a wide
variety of sampling and control applications.
8.2.3 Operational Modes
A ONE_SHOT control bit is used to set the SAR ADC conversion
mode to either continuous or one conversion per SOF signal.
DMA transfer of continuous samples, without CPU intervention,
is supported.
8.2.1 Functional Description
In a SAR ADC an analog input signal is sampled and compared
with the output of a DAC. A binary search algorithm is applied to
the DAC and used to determine the output bits in succession
from MSB to LSB. A block diagram of one SAR ADC is shown in
Figure 8-3.
8.3 Comparators
The CY8C54 family of devices contains four comparators.
Comparators have these features:
Figure 8-3. SAR ADC Block Diagram
Input offset factory trimmed to less than 5 mV
Rail-to-rail common mode input range (Vssa to Vcca)
vin
S/H
DAC
array
Speed and power can be traded off by using one of three
modes: fast, slow, or ultra low power
SAR
digital
comparator
D0:D11
vrefp
vrefn
Comparator outputs can be routed to look up tables to perform
simple logic functions and then can also be routed to digital
blocks
autozero
reset
clock
The positive input ofthe comparators may be optionally passed
through a low pass filter. Two filters are provided
clock
power
filtering
POWER
GROUND
vrefp
vrefn
Comparator inputs can be connections to GPIO, DAC outputs
and SC block outputs
8.3.1 Input and Output Interface
The positive and negative inputs to the comparators come from
the analog global buses, the analog mux line, the analog local
bus and precision reference through multiplexers. The output
from each comparator could be routed to any of the two input
LUTs. The output of that LUT is routed to the UDB Digital System
Interface.
The input is connected to the analog globals and muxes. The
frequency of the clock is 16 times the sample rate; the maximum
clock rate is 16 MHz.
Document Number: 001-55036 Rev. *A
Page 48 of 93
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PRELIMINARY
PSoC®5:CY8C54FamilyData Sheet
Figure 8-4. Analog Comparator
ANAIF
From
Analog
Routing
+
+
_
comp0
_
From
Analog
Routing
comp1
From
Analog
Routing
+
comp3
_
+
From
Analog
Routing
comp2
_
4
4
4
4
4
4
4
4
LUT0
LUT1
LUT2
LUT3
UDBs
8.3.2 LUT
Table 8-1. LUT Function vs. Program Word and Inputs (con-
The CY8C54 family of devices contains four LUTs. The LUT is a
two input, one output lookup table that is driven by any one or
two of the comparators in the chip. The output of any LUT is
routed to the digital system interface of the UDB array. From the
digital system interface of the UDB array, these signals can be
connected to UDBs, DMA controller, I/O, or the interrupt
controller.
Control Word
0100b
0101b
0110b
Output (A and B are LUT inputs)
(NOT
A) AND B
B
A
A
A
XOR
B
B
0111b
OR
B
1000b
1001b
1010b
1011b
NOR
The LUT control word written to a register sets the logic function
on the output. The available LUT functions and the associated
A
XNOR
NOT
OR (NOT
B
control word is shown in Table 8-1
Table 8-1. LUT Function vs. Program Word and Inputs
.
B
A
B
)
Control Word
0000b
Output (A and B are LUT inputs)
1100b
NOT
A
FALSE (‘0’)
1101b
(NOT
A
) OR
B
0001b
A AND B
1110b
A
NAND
B
0010b
A
AND (NOT
A
B)
1111b
TRUE (‘1’)
0011b
Document Number: 001-55036 Rev. *A
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PRELIMINARY
PSoC®5:CY8C54FamilyData Sheet
The opamp has three speed modes, slow, medium, and fast. The
slow mode consumes the least amount of quiescent power and
the fast mode consumes the most power. The inputs are able to
swing rail-to-rail. The output swing is capable of rail-to-rail
operation at low current output, within 50 mV of the rails. When
driving high current loads (about 25 mA) the output voltage may
only get within 500 mV of the rails.
8.4 Opamps
The CY8C54 family of devices contain four general purpose
opamps.
Figure 8-5. Opamp
GPIO
8.5 Programmable SC/CT Blocks
Analog
Global Bus
The CY8C54 family of devices contains four switched
capacitor/continuous time (SC/CT) blocks. Each switched
capacitor/continuous time block is built around a single rail-to-rail
high bandwidth opamp.
Opamp
Analog
Global Bus
GPIO
VREF
Analog
Switched capacitor is a circuit design technique that uses capac-
itors plus switches instead of resistors to create analog functions.
These circuits work by moving charge between capacitors by
opening and closing different switches. Nonoverlapping in phase
clock signals control the switches, so that not all switches are ON
simultaneously.
Internal Bus
=
Analog Switch
GPIO
The opamp is uncommitted and can be configured as a gain
stage or voltage follower on external or internal signals.
The PSoC Creator tool offers a user friendly interface, which
allows you to easily program the SC/CT blocks. Switch control
and clock phase control configuration is done by PSoC Creator
so users only need to determine the application use parameters
such as gain, amplifier polarity, vref connection, and so on.
See Figure 8-6. In any configuration, the input and output signals
can all be connected to the internal global signals and monitored
with an ADC, or comparator. The configurations are imple-
mented with switches between the signals and GPIO pins.
The same opamps and block interfaces are also connectable to
an array of resistors which allows the construction of a variety of
continuous time functions.
Figure 8-6. Opamp Configurations
a) Voltage Follower
The opamp and resistor array is programmable to perform
various analog functions including
Naked Operational Amplifier - Continuous Mode
Unity-Gain Buffer - Continuous Mode
Opamp
Vout to Pin
Vin
Programmable Gain Amplifier (PGA) - Continuous Mode
Transimpedance Amplifier (TIA) - Continuous Mode
Up/Down Mixer - Continuous Mode
b) External Uncommitted
Opamp
Sample and Hold Mixer (NRZ S/H) - Switched Cap Mode
First Order Analog to Digital Modulator - Switched Cap Mode
8.5.1 Naked Opamp
Vout to GPIO
Opamp
The Naked Opamp presents both inputs and the output for
connection to internal or external signals. The opamp has a unity
gain bandwidth greater than 6.0 MHz and output drive current up
to 650 µA. This is sufficient for buffering internal signals (such as
DAC outputs) and driving external loads greater than 7.5 kohms.
Vp to GPIO
Vn to GPIO
8.5.2 Unity Gain
c) Internal Uncommitted
Opamp
The Unity Gain buffer is a Naked Opamp with the output directly
connected to the inverting input for a gain of 1.00. It has a -3 dB
bandwidth greater than 6.0 MHz.
Vn
8.5.3 PGA
To Internal Signals
The PGA amplifies an external or internal signal. The PGA can
be configured to operate in inverting mode or noninverting mode.
The PGA function may be configured for both positive and
negative gains as high as 50 and 49 respectively. The gain is
adjusted by changing the values of R1 and R2 as illustrated in
Figure 8-7. The schematic in Figure 8-7 shows the configuration
Vout to Pin
GPIO Pin
Opamp
Vp
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and possible resistor settings for the PGA. The gain is switched
from inverting and non inverting by changing the shared select
value of the both the input muxes. The bandwidth for each gain
case is listed in Table 8-2.
Figure 8-8. Continuous Time TIA Schematic
R
fb
Table 8-2. Bandwidth
Gain
1
Bandwidth
6.0 MHz
340 kHz
220 kHz
215 kHz
I
in
24
48
50
V
out
V
ref
Figure 8-7. PGA Resistor Settings
The TIA configuration is used for applications where an external
sensor's output is current as a function of some type of stimulus
such as temperature, light, magnetic flux etc. In a common appli-
cation, the voltage DAC output can be connected to the VREF
TIA input to allow calibration of the external sensor bias current
by adjusting the voltage DAC output voltage.
R1
R2
Vin
0
1
Vref
20k or 40k
20k to 980k
S
8.6 LCD Direct Drive
The PSoC Liquid Crystal Display (LCD) driver system is a highly
configurable peripheral designed to allow PSoC to directly drive
a broad range of LCD glass. All voltages are generated on chip,
eliminating the need for external components. With a high
multiplex ratio of up to 1/16, the CY8C54 family LCD driver
system can drive a maximum of 736 segments. The PSoC LCD
driver module was also designed with the conservative power
budget of portable devices in mind, enabling different LCD drive
modes and power down modes to conserve power.
Vref
Vin
0
1
The PGA is used in applications where the input signal may not
be large enough to achieve the desired resolution in the ADC, or
dynamic range of another SC/CT block such as a mixer. The gain
is adjustable at runtime, including changing the gain of the PGA
prior to each ADC sample.
PSoC Creator provides an LCD segment drive component. The
component wizard provides easy and flexible configuration of
LCD resources. You can specify pins for segments and
commons along with other options. The software configures the
device to meet the required specifications. This is possible
because of the programmability inherent to PSoC devices.
8.5.4 TIA
The Transimpedance Amplifier (TIA) converts an internal or
external current to an output voltage. The TIA uses an internal
feedback resistor in a continuous time configuration to convert
input current to output voltage. For an input current Iin, the output
voltage is Iin x Rfb +Vref, where Vref is the value placed on the
non inverting input. The feedback resistor Rfb is programmable
Key features of the PSoC LCD segment system are:
LCD panel direct driving
Type A (standard) and Type B (low power) waveform support
between 20 K
Ω and 1 MΩ through a configuration register.
Table 8-3 shows the possible values of Rfb and associated
configuration settings.
Wide operating voltage range support (2V to 5V) for LCD
panels
Table 8-3. Feedback Resistor Settings
Static, 1/2, 1/3, 1/4, 1/5 bias voltage levels
Configuration Word
Nominal R
(K
Ω
)
Internal biasvoltage generation through internal resistor ladder
Up to 62 total common and segment outputs
fb
000b
001b
010b
011b
100b
101b
110b
111b
20
30
Up to 1/16 multiplex for a maximum of 16 backplane/common
outputs
40
60
Up to 62 front plane/segment outputs for direct drive
Drives up to 736 total segments (16 backplane x 46 front plane)
Up to 128 levels of software controlled contrast
120
250
500
Ability to move display data from memory buffer to LCD driver
through DMA (without CPU intervention)
1000
Adjustable LCD refresh rate from 10 Hz to 150 Hz
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Ability to invert LCD display for negative image
also produces a DMA request to initiate the transfer of the next
frame of LCD data.
Three LCD driver drive modes, allowing power optimization
8.6.4 LCD DAC
LCD driver configurable to be active when PSoC is in limited
active mode
The LCD DAC generates the contrast control and bias voltage
for the LCD system. The LCD DAC produces up to five LCD drive
voltages plus ground, based on the selected bias ratio. The bias
voltages are driven out to GPIO pins on a dedicated LCD bias
bus, as required.
Figure 8-9. LCD System
LCD
DAC
Global
Clock
8.7 CapSense
The CapSense system provides a versatile and efficient means
for measuring capacitance in applications such as touch sense
buttons, sliders, proximity detection, etc. The CapSense system
uses a configuration of system resources, including a few
hardware functions primarily targeted for CapSense, to realize
various sensing algorithms. Specific resource usage is detailed
in the CapSense component in PSoC Creator.
UDB
PIN
LCD Driver
Block
Display
A capacitive sensing method using a Delta-Sigma Modulator
(CSD) is used. It provides capacitance sensing using a switched
capacitor technique with a delta-sigma modulator to convert the
sensing current to a digital code.
DMA
RAM
8.8 Temp Sensor
PHUB
Die temperature is used to establish programming parameters
for writing Flash. Die temperature is measured using a dedicated
sensor based on a forward biased transistor. The temperature
sensor has its own auxiliary ADC.
8.6.1 LCD Segment Pin Driver
Each GPIO pin contains an LCD driver circuit. The LCD driver
buffers the appropriate output of the LCD DAC to directly drive
the glass of the LCD. A register setting determines whether the
pin is a common or segment. The pin’s LCD driver then selects
one of the six bias voltages to drive the I/O pin, as appropriate
for the display data.
8.9 DAC
The CY8C54 parts contain four Digital to Analog Convertors
(DACs). Each DAC is 8-bit and can be configured for either
voltage or current output. The DACs support CapSense, power
supply regulation, and waveform generation. Each DAC has the
following features.
8.6.2 Display Data Flow
Adjustable voltage or current output in 255 steps
Programmable step size (range selection)
Eight bits of calibration to correct ± 25% of gain error
Source and sink option for current output
8 Msps conversion rate for current output
1 Msps conversion rate for voltage output
Monotonic in nature
The LCD segment driver system reads display data and
generates the proper output voltages to the LCD glass to
produce the desired image. Display data resides in a memory
buffer in the system SRAM. Each time you need to change the
common and segment driver voltages, the next set of pixel data
moves from the memory buffer into the Port Data Registers via
DMA.
8.6.3 UDB and LCD Segment Control
A UDB is configured to generate the global LCD control signals
and clocking. This set of signals is routed to each LCD pin driver
through a set of dedicated LCD global routing channels. In
addition to generating the global LCD control signals, the UDB
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Figure 8-10. DAC Block Diagram
I source Range
1x,8x, 64x
Vout
Reference
Source
Scaler
Iout
R
3R
I sink Range
1x,8x, 64x
8.9.1 Current DAC
Figure 8-11. Mixer Configuration
The current DAC (IDAC) can be configured for the ranges 0 to
32 µA, 0 to 256 µA, and 0 to 2.048 mA. The IDAC can be
configured to source or sink current.
C2 = 1.7 pF
C1 = 850 fF
8.9.2 Voltage DAC
For the voltage DAC (VDAC), the current DAC output is routed
through resistors. The two ranges available for the VDAC are 0
to 1.024V and 0 to 4.096V. In voltage mode any load connected
to the output of a DAC should be purely capacitive (the output of
the VDAC is not buffered).
Rmix 0 20k or 40k
sc_clk
Rmix 0 20k or 40k
Vin
Vout
0
1
8.10 Up/Down Mixer
Vref
In continuous time mode, the SC/CT block components are used
to build an up or down mixer. Any mixing application contains an
input signal frequency and a local oscillator frequency. The
polarity of the clock, Fclk, switches the amplifier between
inverting or noninverting gain. The output is the product of the
input and the switching function from the local oscillator, with
frequency components at the local oscillator plus and minus the
signal frequency (Fclk + Fin and Fclk - Fin) and reduced-level
frequency components at odd integer multiples of the local oscil-
lator frequency. The local oscillator frequency is provided by the
selected clock source for the mixer.
sc_clk
8.11 Sample and Hold
The main application for a sample and hold, is to hold a value
stable while an ADC is performing a conversion. Some applica-
tions require multiple signals to be sampled simultaneously, such
as for power calculations (V and I).
Continuous time up and down mixing works for applications with
input signals and local oscillator frequencies up to 1 MHz.
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Figure 8-12. Sample and Hold Topology
1 and 2 are opposite phases of a clock)
PSoC devices include extensive support for programming,
testing, debugging, and tracing both hardware and firmware.
Four interfaces are available: JTAG, SWD, SWV, and
TRACEPORT. JTAG and SWD support all programming and
debug features of the device. JTAG also supports standard JTAG
scan chains for board level test and chaining multiple JTAG
devices for programming or testing. The SWV and TRACEPORT
provide trace output from the DWT, ETM, and ITM.
TRACEPORT is faster but uses more pins. SWV is slower but
uses only one pin.
(
Φ
Φ
Φ1
Φ 2
Φ1
C1
C2
V i
Vref
n
Vout
Φ 1
Φ2
Φ
2
Cortex-M3 debug and trace functionality enables full device
debugging in the final system using the standard production
device. It does not require special interfaces, debugging pods,
simulators, or emulators. Only the standard programming
connections are required to fully support debug.
Φ1
Φ2
Φ1
Φ2
Φ 1
V ref
The PSoC Creator IDE software provides fully integrated
programming and debug support for PSoC devices. The low cost
MiniProg3 programmer and debugger is designed to provide full
programming and debug support of PSoC devices in conjunction
with the PSoC Creator IDE. PSoC JTAG, SWD, and SWV inter-
faces are fully compatible with industry standard third party tools.
V
ref
C3
C4
Φ
2
8.11.1 Down Mixer
The S+H can be used as a mixer to down convert an input signal.
This circuit is a high bandwidth passive sample network that can
sample input signals up to 14 MHz. This sampled value is then
held using the opamp with a maximum clock rate of 4 MHz. The
output frequency is at the difference between the input frequency
and the highest integer multiple of the Local Oscillator that is less
than the input.
All Cortex-M3 debug and trace modules are disabled by default
and can only be enabled in firmware. If not enabled, the only way
to reenable them is to erase the entire device, clear Flash
protection, and reprogram the device with new firmware that
enables them. Disabling debug and trace features, robust Flash
protection, and hiding custom analog and digital functionality
inside the PSoC device provide a level of security not possible
with multichip application solutions. Additionally, all device inter-
faces can be permanently disabled (Device Security) for applica-
tions concerned about phishing attacks due to a maliciously
reprogrammed device. Permanently disabling interfaces is not
recommended in most applications because the designer then
cannot access the device. Because all programming, debug, and
test interfaces are disabled when Device Security is enabled,
PSoCs with Device Security enabled may not be returned for
failure analysis.
8.11.2 First Order Modulator - SC Mode
A first order modulator is constructed by placing the switched
capacitor block in an integrator mode and using a comparator to
provide a 1-bit feedback to the input. Depending on this bit, a
reference voltage is either subtracted or added to the input
signal. The block output is the output of the comparator and not
the integrator in the modulator case. The signal is downshifted
and buffered and then processed by a decimator to make a
delta-sigma converter or a counter to make an incremental
converter. The accuracy of the sampled data from the first-order
modulator is determined from several factors.
9.1 JTAG Interface
The IEEE 1149.1 compliant JTAG interface exists on four or five
pins (the nTRST pin is optional). The JTAG clock frequency can
be up to 8 MHz. By default, the JTAG pins are enabled on new
devices but the JTAG interface can be disabled, allowing these
pins to be used as General Purpose I/O (GPIO) instead. The
JTAG interface is used for programming the Flash memory,
debugging, I/O scan chains, and JTAG device chaining.
The main application for this modulator is for a low frequency
ADC with high accuracy. Applications include strain gauges,
thermocouples, precision voltage, and current measurement
9. Programming, Debug Interfaces,
Resources
9.2 SWD Interface
The Cortex-M3 has internal debugging components, tightly
integrated with the CPU, providing the following features:
The SWD interface is the preferred alternative to the JTAG
interface. It requires only two pins instead of the four or five
needed by JTAG. SWD provides all of the programming and
debugging features of JTAG at the same speed. SWD does not
provide access to scan chains or device chaining.
JTAG or SWD access
Flash Patch and Breakpoint (FPB) block for implementing
breakpoints and code patches
SWD uses two pins, either two of the JTAG pins (TMS and TCK)
or the USBIO D+ and D- pins. The USBIO pins are useful for in
system programming of USB solutions that would otherwise
require a separate programming connector. One pin is used for
the data clock and the other is used for data input and output.
SWD can be enabled on only one of the pin pairs at a time. This
only happens if, within 8 µs (key window) after reset, that pin pair
Data Watchpoint and Trigger (DWT) block for implementing
watchpoints, trigger resources, and system profiling
Embedded Trace Macrocell (ETM) for instruction trace
InstrumentationTraceMacrocell(ITM)forsupportofprintf-style
debugging
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(JTAG or USB) receives a predetermined sequence of 1s and 0s.
SWD is used for debugging or for programming the Flash
memory.
SWD may be used with either SWV or TRACEPORT, or JTAG
may be used with TRACEPORT, as shown in Table 9-1.
Table 9-1. Debug Configurations
The SWD interface can be enabled from the JTAG interface or
disabled, allowing its pins to be used as GPIO. Unlike JTAG, the
SWD interface can always be reacquired on any device during
the key window. It can then be used to reenable the JTAG
interface, if desired. When using SWD or JTAG pins as standard
GPIO, make sure that the GPIO functionality and PCB circuits do
not interfere with SWD or JTAG use.
Debug and Trace Configuration
All debug and trace disabled
JTAG
GPIO Pins Used
0
4 or 5
SWD
2
SWV
1
9.3 Debug Features
TRACEPORT
5
The CY8C54 supports the following debug features:
JTAG + TRACEPORT
SWD + SWV
9 or 10
Halt and single-step the CPU
3
7
View and change CPU and peripheral registers, and RAM
addresses
SWD + TRACEPORT
Six program address breakpoints and two literal access break-
points
9.6 Programming Features
Data watchpoint events to CPU
The JTAG and SWD interfaces provide full programming
support. The entire device can be erased, programmed, and
verified. Designers can increase Flash protection levels to
protect firmware IP. Flash protection can only be reset after a full
device erase. Individual Flash blocks can be erased,
programmed, and verified, if block security settings permit.
Patch and remap instruction from Flash to SRAM
Debugging at the full speed of the CPU
Debug operations are possible while the device is reset, or in
low power modes
9.7 Device Security
CompatiblewithPSoCCreatorandMiniProg3programmerand
debugger
PSoC 5 offers an advanced security feature called device
security, which permanently disables all test, programming, and
debug ports, protecting your application from external access.
The device security is activated by programming a 32-bit key
(0x50536F43) to a Write Once Latch (WOL).
Standard JTAG programming and debugging interfaces make
CY8C54 compatible with other popular third-party tools (for
example, ARM / Keil)
9.4 Trace Features
The Write Once Latch is a type of nonvolatile latch (NVL). The
cell itself is an NVL with additional logic wrapped around it. Each
WOL device contains four bytes (32 bits) of data. The wrapper
outputs a ‘1’ if a super-majority (28 of 32) of its bits match a
pre-determined pattern (0x50536F43); it outputs a ‘0’ if this
majority is not reached. When the output is 1, the Write Once NV
latch locks the part out of Debug and Test modes; it also perma-
nently gates off the ability to erase or alter the contents of the
latch. Matching all bits is intentionally not required, so that single
(or few) bit failures do not deassert the WOL output. The state of
the NVL bits after wafer processing is truly random with no
tendency toward 1 or 0.
The following trace features are supported:
Instruction trace
Data watchpoint on access to data address, address range, or
data value
Trace trigger on data watchpoint
Debug exception trigger
Code profiling
Counters for measuring clock cycles, folded instructions,
load/store operations, sleep cycles, cycles per instruction,
interrupt overhead
The WOL only locks the part after the correct 32-bit key
(0x50536F43) is loaded into the NVL's volatile memory,
programmed into the NVL's nonvolatile cells, and the part is
reset. The output of the WOL is only sampled on reset and used
to disable the access. This precaution prevents anyone from
reading, erasing, or altering the contents of the internal memory.
Interrupt events trace
Software event monitoring, “printf-style” debugging
The user can write the key into the WOL to lock out external
access only if no Flash protection is set (see “Flash Security”
section on page 15). However, after setting the values in the
WOL, a user still has access to the part until it is reset. Therefore,
a user can write the key into the WOL, program the Flash
protection data, and then reset the part to lock it.
9.5 SWV and TRACEPORT Interfaces
The SWV and TRACEPORT interfaces provide trace data to a
debug host via the Cypress MiniProg3 or an external trace port
analyzer. The 5 pin TRACEPORT is used for rapid transmission
of large trace streams. The single pin SWV mode is used to
minimize the number of trace pins. SWV is shared with a JTAG
pin. If debugging and tracing are done at the same time then
If the device is protected with a WOL setting, Cypress cannot
perform failure analysis and, therefore, cannot accept RMAs
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from customers. The WOL can be read out via Serial Wire Debug
(SWD) port to electrically identify protected parts. The user can
write the key in WOL to lock out external access only if no Flash
protection is set. For more information on how to take full
advantage of the security features in PSoC see the PSoC 5
10. Development Support
The CY8C54 family has a rich set of documentation, devel-
opment tools, and online resources to assist you during your
development process. Visit psoc.cypress.com/getting-started to
find out more.
TRM.
Disclaimer
10.1 Documentation
Note the following details of the Flash code protection features
on Cypress devices.
A suite of documentation, to ensure that you can find answers to
your questions quickly, supports the CY8C54 family. This section
contains a list of some of the key documents.
Cypress products meet the specifications contained in their
particular Cypress data sheets. Cypress believes that its family
of products is one of the most secure families of its kind on the
market today, regardless of how they are used. There may be
methods, unknown to Cypress, that can breach the code
protection features. Any of these methods, to our knowledge,
would be dishonest and possibly illegal. Neither Cypress nor any
other semiconductor manufacturer can guarantee the security of
their code. Code protection does not mean that we are guaran-
teeing the product as “unbreakable.”
Software User Guide: A step-by-step guide for using PSoC
Creator. The software user guide shows you how the PSoC
Creator build process works in detail, how to use source control
with PSoC Creator, and much more.
Component Data Sheets: The flexibility of PSoC allows the
creation of new peripherals (components) long after the device
has gone into production. Component data sheets provide all of
the information needed to select and use a particular component,
including a functional description, API documentation, example
code, and AC/DC specifications.
Cypress is willing to work with the customer who is concerned
about the integrity of their code. Code protection is constantly
evolving. We at Cypress are committed to continuously
improving the code protection features of our products.
Application Notes: PSoC application notes discuss a particular
application of PSoC in depth; examples include brushless DC
motor control and on-chip filtering. Application notes often
include example projects in addition to the application note
document.
Technical Reference Manual: PSoC Creator makes designing
with PSoC as easy as dragging a peripheral onto a schematic,
but, when low level details of the PSoC device are required, use
the technical reference manual (TRM) as your guide.
Note Visit www.arm.com for detailed documentation about the
Cortex-M3 CPU.
10.2 Online
In addition to print documentation, the Cypress PSoC forums
connect you with fellow PSoC users and experts in PSoC from
around the world, 24 hours a day, 7 days a week.
10.3 Tools
With industry standard cores, programming, and debugging
interfaces, the CY8C54 family is part of a development tool
ecosystem. Visit us at www.cypress.com/go/psoccreator for the
latest information on the revolutionary, easy to use CyDesign
IDE, supported third party compilers, programmers, debuggers,
and development kits.
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11. Electrical Specifications
Specifications are valid for -40°C
≤ Ta ≤ 85°C and Tj ≤ 100°C, except where noted. Specifications are valid for 1.71V to 5.5V, except
where noted. The unique flexibility of the PSoC UDBs and analog blocks enable many functions to be implemented in PSoC Creator
components, see the component data sheets for full AC/DC specifications of individual functions. See the “Example Peripherals”
section on page 32 for further explanation of PSoC Creator components.
11.1 Absolute Maximum Ratings
Table 11-1. Absolute Maximum Ratings DC Specifications
Parameter
Tstorag
Description
Storage temperature
Conditions
Min
Typ
Max
Units
Recommended storage temper-
ature is 0°C - 50°C. Exposure to
storage temperatures above 85°C
for extended periods may affect
device reliability.
-55
25
125
°C
Vdda
Vddd
Analog supply voltage relative to
Vssa
-0.5
-0.5
-
-
6
6
V
V
Digital supply voltage relative to
Vssd
Vddio
Vcca
Vccd
Vssa
I/O supply voltage relative to Vssd
Direct analog core voltage input
Direct digital core voltage input
Analog ground voltage
-0.5
-0.5
-
-
-
-
6
V
V
V
V
1.95
1.95
-0.5
Vssd -0.5
Vssd +
0.5
[6]
Vgpio
Vsio
DC input voltage on GPIO
DC input voltage on SIO
Includes signals sourced by Vdda
and routed internal to the pin.
Vssd -0.5
-
Vddio +
0.5
V
Output disabled
Output enabled
Vssd -0.5
Vssd -0.5
0.5
-
-
-
-
-
-
-
-
7
6
V
V
Vind
Vbat
Voltage at boost converter input
Boost converter supply
5.5
5.5
100
200
-
V
Vssd -0.5
-
V
Ivddio
LU
Current per Vddio supply pin
Latch up current
mA
mA
V
-200
ESD
ESD
Electro-static discharge voltage
Electro-static discharge voltage
Human Body Model
Charge Device Model
2000
HBM
CDM
500
-
V
Note Usage above the absolute maximum conditions listed in Table 11-1 may cause permanent damage to the device. Exposure to
maximum conditions for extended periods of time may affect device reliability. When used below maximum conditions but above
normal operating conditions the device may not operate to specification.
Note
6. The Vddio supply voltage must be greater than the maximum analog voltage on the associated GPIO pins. Maximum analog voltage on GPIO pin ≤ Vddio ≤ Vdda.
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11.2 Device Level Specifications
Specifications are valid for -40°C
where noted.
≤ Ta ≤ 85°C and Tj ≤ 100°C, except where noted. Specifications are valid for 1.71V to 5.5V, except
11.2.1 Device Level Specifications
Table 11-2. DC Specifications
Parameter
Description
Conditions
Min
Typ
Max
Units
Vdda
Analog supply voltage and input to Analog core regulator enabled
analog core regulator
1.8
5.5
V
Vdda
Vddd
Vddd
Analog supply voltage, analog
regulator bypassed
Analog core regulator disabled
Digital core regulator enabled
Digital core regulator disabled
1.71
1.8
1.8
1.89
Vdda
1.89
V
V
V
Digital supply voltage relative to
Vssd
Digital supply voltage, digital
regulator bypassed
1.71
1.8
[6]
Vddio
I/O supply voltage relative to Vssio
1.71
1.71
Vdda
1.89
V
V
Vcca
Vccd
Vbat
Direct analog core voltage input
(Analog regulator bypass)
Analog core regulator disabled
Digital core regulator disabled
1.8
1.8
Direct digital core voltage input
(Digital regulator bypass)
1.71
0.5
1.89
5.5
V
V
Voltage supplied to boost converter
Active Mode, VDD = 1.71V - 5.5V
[8]
Idd
Execute from Flash, CPU at 6 MHz T= -40°C
mA
mA
mA
T= 25°C
T= 85°C
2
[7]
Sleep Mode
VDD = VDDIO = 4.5 - 5.5V T= -40°C
µA
µA
µA
µA
µA
µA
µA
µA
µA
CPU OFF
T= 25°C
RTC = ON (= ECO32K ON, in low
power mode)
T= 85°C
VDD = VDDIO = 2.7 - 3.6V T= -40°C
T= 25°C
WDT = OFF
2
I C wake = OFF
2
Comparator = OFF
POR = ON
Boost = OFF
SIO pins in single ended input,
unregulated output mode
T= 85°C
VDD = VDDIO = 1.71 -
1.95V
T= -40°C
T= 25°C
T= 85°C
[7]
Hibernate Mode
VDD = VDDIO = 4.5 - 5.5V T= -40°C
nA
nA
nA
nA
nA
nA
nA
nA
nA
T= 25°C
Hibernate mode current
All regulators and oscillators off.
SRAM retention
GPIO interrupts are active
Boost = OFF
T= 85°C
VDD = VDDIO = 2.7 - 3.6V T= -40°C
T= 25°C
300
T= 85°C
SIO pins in single ended input,
unregulated output mode
VDD = VDDIO = 1.71 -
1.95V
T= -40°C
T= 25°C
T= 85°C
Note
7. If Vccd and Vcca are externally regulated, the voltage difference between Vccd and Vcca must be less than 50 mV.
Document Number: 001-55036 Rev. *A
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[9]
Table 11-3. AC Specifications
Parameter Description
CPU frequency
Conditions
Min
DC
Typ
Max
80
Units
MHz
MHz
F
1.71V
1.71V
≤
≤
Vddd
Vddd
≤
≤
5.5V
5.5V
-
-
-
-
CPU
F
Bus frequency
DC
80
busclk
Svdd
Vdd ramp rate
1.00E-04
-
1.00E+06 V/ms
Tio_init
Time from Vddd/Vdda/Vccd/Vcca
IPOR to I/O ports set to their reset
states
≥
10
µs
µs
µs
µs
Vcca/Vdda = regulated from
Vdda/Vddd, no PLL used, fast boot
≥
mode
-
-
-
-
-
-
9
Time from Vddd/Vdda/Vccd/Vcca
PPOR to CPU executing code at
reset vector
Tstartup
Tsleep
Vcca/Vccd = regulated from
Vdda/Vddd, no PLL used, slow boot
mode
36
12
Wakeup from limited active mode -
Application of external interrupt to
beginning of execution of next CPU
instruction
Thibernate Wakeup form hibernate mode -
Application of external interrupt to
beginning of execution of next CPU
instruction
-
-
-
100
-
µs
µs
External reset pulse width
1
Notes
8. The current consumption of additional peripherals that are implemented only in programmed logic blocks can be found in their respective data sheets, available in
PSoC Creator, the integrated design environment. To compute total current, find CPU current at frequency of interest and add peripheral currents for your particular
system from the device data sheet and component data sheets.
9. Based on device characterization (Not production tested).
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11.3 Power Regulators
Specifications are valid for -40°C
where noted.
≤ Ta ≤ 85°C and Tj ≤ 100°C, except where noted. Specifications are valid for 1.71V to 5.5V, except
11.3.1 Digital Core Regulator
Table 11-4. Digital Core Regulator DC Specifications
Parameter
Vddd
Description
Input voltage
Conditions
Min
Typ
-
Max
Units
V
1.8
5.5
Vccd
Output voltage
-
-
1.80
1.1
-
-
V
Regulator output capacitance
Total capacitance on the two Vccd pins.
Each capacitor is ±10%, X5R ceramic or
better, see Power System on page 22
µF
11.3.2 Analog Core Regulator
Table 11-5. Analog Core Regulator DC Specifications
Parameter
Vdda
Description
Input voltage
Conditions
Min
Typ
-
Max
Units
V
1.8
5.5
Vcca
Output voltage
-
-
1.80
1
-
-
V
Regulator output capacitor
±10%, X5R ceramic or better
µF
11.3.3 Inductive Boost Regulator
Table 11-6. Inductive Boost Regulator DC Specifications
Parameter
Description
Input voltage
Conditions
Includes startup
Min
0.5
-
Typ
Max
5.5
50
Units
V
Vbat
-
-
Vin=1.6-5.5V, Vout=1.6-5.0V, external
diode
mA
Vin=1.6-3.6V, Vout=1.6-3.6V, internal diode
Vin=0.8-1.6V, Vout=1.6-3.6V, internal diode
-
-
-
-
-
-
75
30
20
mA
mA
mA
[10, 11]
Iboost
Load current
Vin=0.8-1.6V, Vout=3.6-5.0V, external
diode
Vin=0.5-0.8V, Vout=1.6-3.6V, internal diode
10 µH spec'd
-
-
15
47
47
-
mA
µH
µF
A
Lboost
Cboost
If
Boost inductor
Filter capacitor
4.7
10
1
10
22
-
[9]
22 µF || 0.1 µF spec'd
External Schottky diode average External Schottky diode is required for
forward current
Vboost > 3.6V
Vr
External Schottky diode peak
reverse voltage
External Schottky diode is required for
Vboost > 3.6V
20
-
-
V
Ilpk
Inductor peak current
Quiescent current
-
-
-
-
700
mA
µA
µA
Boost active mode
200
12
-
-
Booststandbymode, 32khzexternalcrystal
oscillator, Iboost < 1 µA
Notes
10. For output voltages above 3.6V, an external diode is required.
11. Maximum output current applies for output voltages ≤ 4x input voltage.
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Table 11-6. Inductive Boost Regulator DC Specifications (continued)
Parameter
Description
Conditions
Min
Typ
Max
Units
[9]
Boost output voltage range
1.8V
1.9V
1.71
1.81
1.90
2.28
2.57
2.85
3.14
3.42
4.75
90
1.80
1.90
2.00
2.40
2.70
3.00
3.30
3.60
5.00
-
1.89
2.00
2.10
2.52
2.84
3.15
3.47
3.8
V
V
V
V
V
V
V
V
V
%
2.0V
2.4V
Vboost
2.7V
3.0V
3.3V
3.6V
5.0V
External diode required
5.25
-
Efficiency
Vbat = 2.4 V, Vout = 2.7 V, Iout = 10 mA, Fsw
= 400 kHz
Table 11-7. Inductive Boost Regulator AC Specifications
Parameter
Vripple
Description
Conditions
Min
Typ
Max
Units
Ripple voltage (peak-to-peak)
Vout = 1.8V, Fsw = 400 kHz, Iout =
10 mA
-
-
100
mV
Fsw
Switching frequency
Duty cycle
-
0.1, 0.4,
or 2
-
MHz
%
20
-
80
11.4 Inputs and Outputs
Specifications are valid for -40°C
where noted.
≤ Ta ≤ 85°C and Tj ≤ 100°C, except where noted. Specifications are valid for 1.71V to 5.5V, except
11.4.1 GPIO
Table 11-8. GPIO DC Specifications
Parameter
Vih
Description
Conditions
Min
Vddio
Typ
Max
Units
Input voltage high threshold
Input voltage low threshold
Input voltage high threshold
CMOS Input, PRT[x]CTL = 0
CMOS Input, PRT[x]CTL = 0
0.7
×
-
-
-
-
V
V
V
Vil
-
0.3 × Vddio
Vih
LVTTL Input, PRT[x]CTL = 1,Vddio 0.7 x Vddio
< 2.7V
-
Vih
Vil
Input voltage high threshold
Input voltage low threshold
Input voltage low threshold
Output voltage high
LVTTLInput, PRT[x]CTL=1, Vddio
≥ 2.7
2.0
-
-
-
-
V
V
V
V
LVTTL Input, PRT[x]CTL = 1,Vddio
< 2.7V
-
-
0.3 x Vddio
0.8
Vil
LVTTLInput, PRT[x]CTL=1, Vddio
≥ 2.7
V
Voh
Ioh = 4 mA at 3.3 Vddio
Ioh = 1 mA at 1.8 Vddio
Iol = 8 mA at 3.3 Vddio
Iol = 4 mA at 1.8 Vddio
Vddio - 0.6
-
-
-
V
V
V
V
Vddio - 0.5
-
-
Vol
Output voltage low
-
-
0.6
0.6
8
-
Rpullup
Rpulldown
Iil
Pull up resistor
4
4
-
5.6
5.6
-
k
Ω
Ω
Pull down resistor
8
k
Input leakage current (absolute
25°C, Vddio = 3.0V
2
nA
[9]
value)
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Table 11-8. GPIO DC Specifications (continued)
Parameter
Cin
Description
Conditions
Min
Typ
Max
7
Units
pF
[9]
Input capacitance
GPIOs without OpAmp outputs
GPIOs with OpAmp outputs
-
-
-
-
-
18
-
pF
Vh
Input voltage hysteresis
40
mV
[9]
(Schmitt-Trigger)
Idiode
Current through protection diode to
Vddio and Vssio
-
-
100
µA
Rglobal
Rmux
Resistance pin to analog global bus 25°C, Vddio = 3.0V
Resistance pin to analog mux bus 25°C, Vddio = 3.0V
-
-
240
130
-
-
Ω
Ω
Table 11-9. GPIO AC Specifications
Parameter
TriseF
Description
Conditions
3.3V Vddio Cload = 25 pF
3.3V Vddio Cload = 25 pF
3.3V Vddio Cload = 25 pF
3.3V Vddio Cload = 25 pF
Min
2
Typ
Max
12
Units
ns
[9]
[9]
Rise time in Fast Strong Mode
-
-
-
-
[9]
TfallF
TriseS
TfallS
Fall time in Fast Strong Mode
2
12
ns
Rise time in Slow Strong Mode
10
10
60
ns
[9]
Fall time in Slow Strong Mode
60
ns
GPIO output operating frequency
3.3V < Vddio < 5.5V, fast strong
drive mode
90/10% Vddio into 25 pF
-
-
-
-
-
-
-
-
33
20
7
MHz
MHz
MHz
MHz
1.71V < Vddio < 3.3V, fast strong 90/10% Vddio into 25 pF
drive mode
Fgpioout
3.3V < Vddio < 5.5V, slow strong
drive mode
90/10% Vddio into 25 pF
1.71V < Vddio < 3.3V, slow strong 90/10% Vddio into 25 pF
drive mode
3.5
GPIO input operating frequency
Fgpioin
1.71V < Vddio < 5.5V
90/10% Vddio
-
-
79
MHz
11.4.2 SIO
Table 11-10. SIO DC Specifications
Parameter Description
Vinref
Conditions
Min
Typ
Max
Units
Input voltage reference (Differential
input mode)
0.5
-
0.52
×
Vddio
V
Output voltage reference (Regulated output mode)
Vddio > 3.7
Voutref
Vih
1
1
-
-
Vddio-1
V
V
Vddio < 3.7
Vddio - 0.5
Input voltage high threshold
GPIO mode
CMOS input
0.7
×
Vddio
-
-
-
-
V
V
Differential input mode
Input voltage low threshold
GPIO mode
With hysteresis
Vinref+0.05
Vil
CMOS input
-
-
-
-
0.3
×
Vddio
V
V
Differential input mode
Output voltage high
Unregulated mode
Regulated mode
With hysteresis
Vinref-0.05
Ioh = 4 mA, Vddio = 3.3V
Ioh = 1 mA
Vddio - 0.4
Voutref-0.6
Voutref-0.25
-
-
-
-
V
V
V
Voh
Voutref+0.2
Voutref+0.2
Regulated mode
Ioh = 0.1 mA
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Table 11-10. SIO DC Specifications (continued)
Parameter Description
Output voltage low
Conditions
Min
Typ
Max
Units
Vol
Vddio = 3.30V, Iol = 25 mA
Vddio = 1.80V, Iol = 4 mA
-
-
-
0.8
0.4
8
V
V
-
Rpullup
Rpulldown
Iil
Pull up resistor
4
4
5.6
5.6
k
k
Ω
Ω
Pull down resistor
8
Input leakage current (absolute
[9]
value)
Vih < Vddsio
Vih > Vddsio
25°C, Vddsio = 3.0V, Vih = 3.0V
25°C, Vddsio = 0V, Vih = 3.0V
-
-
-
-
-
-
-
-
14
10
7
nA
µA
pF
[9]
Cin
Vh
Input Capacitance
-
Input voltage hysteresis
(Schmitt-Trigger)
Single ended mode (GPIO mode)
Differential mode
40
50
-
-
mV
mV
µA
[9]
-
Current through protection diode to
Vssio
100
Idiode
Table 11-11. SIO AC Specifications
Parameter Description
TriseF
Conditions
Min
Typ
Max
Units
Rise time in Fast Strong Mode
Cload = 25 pF, Vddio = 3.3V
1
-
-
-
-
12
ns
[9]
(90/10%)
TfallF
TriseS
TfallS
Fall time in Fast Strong Mode
(90/10%)
Cload = 25 pF, Vddio = 3.3V
Cload = 25 pF, Vddio = 3.0V
Cload = 25 pF, Vddio = 3.0V
1
12
75
60
ns
ns
ns
[9]
Rise time in Slow Strong Mode
10
10
[9]
(90/10%)
Fall time in Slow Strong Mode
[9]
(90/10%)
SIO output operating frequency
3.3V < Vddio < 5.5V, Unregulated 90/10% Vddio into 25 pF
output (GPIO) mode, fast strong
drive mode
-
-
-
-
-
-
-
-
33
16
5
MHz
MHz
MHz
MHz
1.71V < Vddio < 3.3V, Unregulated 90/10% Vddio into 25 pF
output (GPIO) mode, fast strong
drive mode
3.3V < Vddio < 5.5V, Unregulated 90/10% Vddio into 25 pF
output (GPIO) mode, slow strong
drive mode
Fsioout
1.71V < Vddio < 3.3V, Unregulated 90/10% Vddio into 25 pF
output (GPIO) mode, slow strong
drive mode
4
3.3V < Vddio < 5.5V, Regulated
output mode, fast strong drive mode 25 pF
Output continuously switching into
-
-
-
-
-
-
20
10
MHz
MHz
MHz
1.71V < Vddio < 3.3V, Regulated Output continuously switching into
output mode, fast strong drive mode 25 pF
1.71V < Vddio < 5.5V, Regulated Output continuously switching into
2.5
output mode, slow strong drive
mode
25 pF
SIO input operating frequency
1.71V < Vddio < 5.5V
Fsioin
90/10% Vddio
-
-
79
MHz
11.4.3 USBIO
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Table 11-12. USBIO DC Specifications
Parameter
Rusbi
Description
USB D+ pull up resistance
USB D+ pull up resistance
Static output high
Conditions
Min
0.900
1.425
2.8
Typ
Max
1.575
3.090
3.6
Units
With idle bus
-
-
-
kΩ
Rusba
While receiving traffic
kΩ
Vohusb
15 k
enabled
Ω
±5% to Vss, internal pull up
V
Volusb
Static output low
15 k ±5% to Vss, internal pull up
enabled
Output voltage high, GPIO mode Ioh = 4 mA, Vddio
Ω
-
-
0.3
V
Vohgpio
Volgpio
Vdi
≥
3V
2.4
-
-
-
-
-
-
V
V
V
V
Output voltage low, GPIO mode
Differential input sensitivity
Iol = 4 mA, Vddio
|(D+)-(D-)|
≥
3V
0.3
0.2
2.5
-
Vcm
Differential input common mode
range
0.8
Vse
Single ended receiver threshold
PS/2 pull up resistance
0.8
3
-
-
2
7
V
Rps2
In PS/2 mode, with PS/2 pull up
enabled
kΩ
Rext
External USB series resistor
In series with each USB pin
21.78
(-1%)
22
22.22
(+1%)
Ω
Zo
USB driver output impedance
Including Rext
28
-
-
-
-
44
20
2
Ω
Cin
USB transceiver input capacitance
pF
nA
Input leakage current (absolute
value)
25°C, Vddio = 3.0V
-
Iil
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Table 11-13. USBIO AC Specifications
Parameter
Description
Conditions
Min
Typ
Max
Units
Tdrate
Full-speed data rate average bit rate
12 - 0.25%
12
12 +
0.25%
MHz
Tjr1
Tjr2
Receiver data jitter tolerance to next
transition
-8
-5
-
-
8
ns
ns
Receiver data jitter tolerance to pair
transition
5
Tdj1
Driver differential jitter to next transition
Driver differential jitter to pair transition
-3.5
-4
-
-
-
3.5
4
ns
ns
ns
Tdj2
Tfdeop
Source jitter for differential transition to
SE0 transition
-2
5
Tfeopt
Tfeopr
Tfst
Source SE0 interval of EOP
Receiver SE0 interval of EOP
160
82
-
-
-
-
175
-
ns
ns
ns
Width of SE0 interval during differential
transition
14
Fgpio_out GPIO mode output operating frequency 3V
≤
Vddd
≤
5.5V
-
-
-
-
-
-
-
20
6
MHz
MHz
ns
Vddd = 1.71V
Rise time, GPIO mode, 10%/90% Vddd Vddd > 3V, 25 pF load
Vddd = 1.71V, 25 pF load
-
Tr_gpio
Tf_gpio
1
4
1
4
12
40
12
40
ns
Fall time, GPIO mode, 90%/10% Vddd Vddd > 3V, 25 pF load
Vddd = 1.71V, 25 pF load
ns
ns
Table 11-14. USB Driver AC Specifications
Parameter Description
Tr Transition rise time
Conditions
Min
4
Typ
Max
20
Units
ns
-
-
-
-
Tf
Transition fall time
4
20
ns
TR
Vcrs
Rise/fall time matching
Output signal crossover voltage
90%
1.3
111%
2
V
11.4.4 XRES
Table 11-15. XRES DC Specifications
Parameter
Description
Input voltage high threshold
Input voltage low threshold
Pull up resistor
Conditions
Min
Typ
-
Max
Units
Vih
CMOS Input, PRT[x]CTL = 0
CMOS Input, PRT[x]CTL = 0
0.7
×
Vddio
-
V
V
Vil
-
-
0.3 × Vddio
Rpullup
Cin
4
-
5.6
3
8
kΩ
[9]
Input capacitance
pF
Vh
Input voltage hysteresis
(Schmitt-Trigger)
-
100
-
mV
[9]
Idiode
Current through protection diode to
Vddio and Vssio
-
-
100
µA
Table 11-16. XRES AC Specifications
Parameter
Description
Reset pulse width
Conditions
Min
Typ
Max
Units
Treset
1
-
-
µs
Document Number: 001-55036 Rev. *A
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11.5 Analog Peripherals
Specifications are valid for -40°C
where noted.
≤ Ta ≤ 85°C and Tj ≤ 100°C, except where noted. Specifications are valid for 1.71V to 5.5V, except
11.5.1 Opamp
Table 11-17. Opamp DC Specifications
Parameter
Vioff
Description
Input offset voltage
Conditions
Min
Typ
Max
Units
mV
mV
µv/°C
%
-
-
0.5
12
-
2
Vioff
Input offset voltage
T = 25 °C
-
-
TCVos
Ge1
Input offset voltage drift with temperature
Gain error, unity gain buffer mode
Quiescent current
-
-
Rload = 1 k
Ω
-
0.1
-
Vssa
900
-
-
Vdda
Vdda - 50
-
µA
Vi
Input voltage range
mV
mV
mA
Vo
Iout
Output voltage range
Output load = 1 mA
Vssa + 50
25
-
Output current
Output voltage is between Vssa
+500 mV and Vdda -500 mV, and
Vdda > 2.7V
-
Output current
Output voltage is between Vssa
+500 mV and Vdda -500 mV, and
Vdda > 1.7V and Vdda < 2.7V
16
70
-
-
-
-
mA
dB
Iout
[9]
CMRR
Common mode rejection ratio
Table 11-18. Opamp AC Specifications
Parameter
Description
Conditions
Min
Typ
Max
Units
[9]
GBW
Gain BW
100 mV pk-pk, load capacitance
200 pF
3
-
-
MHz
[9]
Tslew
Slew rate
Load capacitance 200 pF
3
-
-
-
V/µs
[9]
Input noise density
38
-
nv/sqrtHz
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11.5.2 Voltage Reference
Table 11-19. Voltage Reference Specifications
Parameter Description
Vref Precision reference
Conditions
Conditions
Min
Typ
Max
Units
1.023
(-0.1%)
1.024
1.025
(+0.1%)
V
11.5.3 SAR ADC
Table 11-20. SAR ADC DC Specifications
Parameter Description
Min
Typ
Max
Units
Resolution
-
-
-
-
12
bits
Number of channels - single ended
No of
GPIO
Number of channels - differential
Differential pair is formed using a
pair of neighboring GPIO.
-
-
No of
GPIO/2
[9]
Monotonicity
Yes
-
-
-
Gain error
-
±0.1
±0.2
500
Vdda
Vdda
2
%
mV
µA
V
Input offset voltage
Current consumption
-
-
-
Vssa
Vssa
-
-
[9]
Input voltage range - single ended
-
[9]
Input voltage range - differential
-
V
[9]
Input resistance
-
KΩ
[9]
Cin
Input capacitance
7
8
9
pF
Table 11-21. SAR ADC AC Specifications
Parameter
Description
Conditions
Min
Typ
Max
Units
µV/µs
dB
[9]
Sample & hold droop
-
80
80
-
-
1
-
[9]
PSRR
Power supply rejection ratio
-
CMRR
Common mode rejection ratio
-
-
dB
[9]
Sample rate
-
1
-
Msps
dB
[9]
SNR
Signal-to-noise ratio (SNR)
70
-
-
[9]
Input bandwidth
500
-
KHz
LSB
LSB
%
[9]
INL
Integral non linearity
Internal reference
Internal reference
-
-
-
-
±
±
1
1
[9]
DNL
THD
Differential non linearity
-
[9]
Total harmonic distortion
-
0.005
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11.5.4 Analog Globals
Table 11-22. Analog Globals AC Specifications
Parameter
Rppag
Description
Conditions
Vdda = 3.0V
Min
-
Typ
939
633
721
515
39
Max
Units
Ω
Resistance pin-to-pin through
1461
[12]
analog global
Vdda = 1.65V
Vdda = 3.0V
Vdda = 1.65V
-
1012
Ω
Rppmuxbus
BWag
Resistance pin-to-pin through
-
1135
Ω
[12]
analog mux bus
-
843
Ω
3 dB bandwidth of analog globals Vdda = 3.0V
Vdda = 1.65V
24
36
85
87
-
-
-
-
MHz
MHz
dB
56
CMRRag
Common mode rejection for
differential signals
Vdda = 3.0V
91
Vdda = 1.65V
93
dB
11.5.5 Comparator
Table 11-23. Comparator DC Specifications
Parameter
Vioff
Description
Conditions
Factory trim
Min
Typ
Max
Units
mV
Input offset voltage in fast mode
-
-
-
-
-
-
±
±
5
4
Input offset voltage in slow mode Factory trim
-
mV
[12]
Input offset voltage in fast mode
Input offset voltage in slow mode
Custom trim
Custom trim
-
-
±3
±2
-
mV
Vioff
Vioff
[12]
mV
Input offset voltage in ultra low
power mode
±12
mV
Vhyst
Vicm
Hysteresis
Hysteresis enable mode
Fast mode
-
0
0
55
-
10
-
32
mV
V
Input common mode voltage
Vdda-0.1
Slow mode
-
Vdda
-
V
CMRR
Icmp
Common mode rejection ratio
-
dB
µA
µA
µA
[9]
High current mode/fast mode
-
400
100
-
[9]
Low current mode/slow mode
-
-
[9]
Ultra low power mode
-
6
Table 11-24. Comparator AC Specifications
Parameter
Description
Conditions
Min
Typ
Max
Units
Response time, high current
mode
50 mV overdrive, measured
pin-to-pin
-
75
TBD
ns
[9]
[9]
Response time, low current mode 50 mV overdrive, measured
pin-to-pin
-
-
145
55
TBD
-
ns
µs
Tresp
Response time, ultra low power
50 mV overdrive, measured
pin-to-pin
[9]
mode
Note
12. The resistance of the analog global and analog mux bus is high if Vdda ≤ 2.7V, and the chip is in either sleep or hibernate mode. Use of analog global and analog
mux bus under these conditions is not recommended.
13. The recommended procedure for using a custom trim value for the on-chip comparators may be found in the TRM.
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11.5.6 IDAC
Table 11-25. IDAC (Current Digital-to-Analog Converter) DC Specifications
Parameter Description Conditions
Iout Output current
Min
Typ
Max
Units
[9]
High
Code = 255, Vdda
Code = 255, Vdda
≥
≤
2.7V, RL 600
Ω
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0
-
-
-
-
2.048
2.048
256
mA
mA
µA
2.7V, RL 300
Ω
[9]
Medium
Code = 255, RL 600
Code = 255, RL 600
Ω
Ω
[9]
Low
32
µA
INL
DNL
Ezs
Eg
Integral non linearity
Differential non linearity
Zero scale error
Gain error
RL 600
RL 600
Ω
, CL=15 pF
±
1
LSB
LSB
LSB
%
Ω, CL=15 pF
±0.5
±
1
Uncompensated
2.5
TBD
100
500
Temperature compensated
Code = 0
%
[9]
IDAC_ICC
IDAC_ICC
DAC current low speed mode
µA
[9]
DAC current high speed mode
Code = 0
µA
Table 11-26. IDAC (Current Digital-to-Analog Converter) AC Specifications
Parameter
Fdac
Description
Update rate
Conditions
Min
Typ
Max
Units
-
-
8
Msps
Settling time to 0.5LSB
Full scale transition, 600
CL = 15 pF
Ω load,
Fast mode
Independent of IDAC range setting
(Iout)
-
-
-
-
100
ns
ns
Tsettle
Slow mode
Independent of IDAC range setting
(Iout)
1000
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11.5.7 VDAC
Table 11-27. VDAC (Voltage Digital-to-Analog Converter) DC Specifications
Parameter
Description
Conditions
Min
Typ
Max
Units
[9]
Output resistance
Rout
High
Vout = 4V
Vout = 1V
-
-
16
4
-
-
k
k
Ω
Ω
Low
[9]
Output voltage range
Vout
High
Code = 255, Vdda > 5V
Code = 255
-
-
-
-
-
-
-
-
-
4
1
-
-
-
V
Low
V
INL
DNL
Ezs
Eg
Integral non linearity
CL=15 pF
±
1.6
LSB
LSB
LSB
%
Differential non linearity
Zero scale error
Gain error
CL=15 pF
-
±
±
1
1
-
Uncompensated
Temperature compensated
Code = 0
-
3
-
TBD
100
500
%
[9]
VDAC_ICC
VDAC_ICC
DAC current low speed mode
-
µA
[9]
DAC current high speed mode
Code = 0
-
µA
Table 11-28. VDAC (Voltage Digital-to-Analog Converter) AC Specifications
Parameter
Fdac
Description
Conditions
Min
Typ
Max
1
Units
Msps
Ksps
[9]
Update rate
Update rate
1V mode
4V mode
-
-
-
-
[9]
250
[9]
Settling time to 0.5LSB
Full scale transition, CL = 15 pF
Vout = 4V
[9]
Tsettle
High
-
-
-
-
4000
1000
ns
ns
[9]
Low
Vout = 1V
11.5.8 Discrete Time Mixer
The discrete time mixer is used for modulating (shifting signals in frequency down) where the output frequency of the mixer is equal
to the difference of the input frequency and the local oscillator frequency. The discrete time mixer is created using a SC/CT Analog
Block, see the Mixer component data sheet in PSoC Creator for full AC/DC specifications, and APIs and example code.
Table 11-29. Discrete Time Mixer DC Specifications
Parameter
Description
Conditions
Min
Typ.
10
30
-
Max
Units
µV
Analog input noise injection (RMS) 1 MHz clock rate
4 MHz clock rate
-
-
-
-
Vdda
10
µV
[14]
Input voltage
Vssa
V
Input offset voltage
Quiescent current
-
-
-
mV
µA
900
-
Table 11-30. Discrete Time Mixer AC Specifications
Parameter
LO
Description
Conditions
Min
0
Typ
Max
4
Units
MHz
MHz
[9]
Local oscillator frequency
-
-
Input signal frequency for down
0
14
[9]
mixing
Note
14. Bandwidth is guaranteed for input common mode between 0.3V and Vdda-1.2V and for output that is between 0.05V and Vdda-0.05V.
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11.5.9 Continuous Time Mixer
The continuous time mixer is used for modulating (shift) frequencies up or down, to a limit of 1.0 MHz. The continuous time mixer is
created using a SC/CT Analog Block, see the Mixer component data sheet in PSoC Creator for full AC/DC specifications, and APIs
and example code.
Table 11-31. Continuous Time Mixer DC Specifications
Parameter
Description
Conditions
Min
Typ
Max
10
Units
µV
Analog input noise injection (RMS) No input signal
-
-
[14]
Input voltage
Vssa
-
-
Vdda
10
V
Input offset voltage
Quiescent current
-
-
mV
µA
900
-
Table 11-32. Continuous Time Mixer AC Specifications
Parameter
LO
Description
Conditions
Min
Typ
Max
1
Units
MHz
MHz
[9]
Local oscillator frequency
-
-
-
-
[9]
Input signal frequency
1
11.5.10 Transimpedance Amplifier
The TIA is created using a SC/CT Analog Block, see the TIA component data sheet in PSoC Creator for full AC/DC specifications,
and APIs and example code.
Table 11-33. Transimpedance Amplifier (TIA) DC Specifications
Parameter
Vioff
Description
Input offset voltage
Conditions
Min
Typ
Max
Units
-
-
10
mV
[15]
Conversion resistance
R = 20K
40 pF load
40 pF load
40 pF load
40 pF load
40 pF load
40 pF load
40 pF load
40 pF load
-20
-20
-20
-20
-20
-20
-20
-20
-
-
+30
+30
+30
+30
+30
+30
+30
+30
-
%
%
%
%
%
%
%
%
µA
R = 30K
-
R = 40K
-
Rconv
R = 80K
-
R = 120K
-
R = 250K
-
R= 500K
-
-
R = 1M
Quiescent current
900
Table 11-34. Transimpedance Amplifier (TIA) AC Specifications
Parameter
Description
Conditions
Min
Typ
Max
Units
[14]
Input bandwidth (-3 dB) - 20 pF load
R = 20K
1800
330
47
-
-
-
-
-
-
kHz
kHz
kHz
R = 120K
R = 1M
Input bandwidth (3 dB) - 40 pF load
R = 20K
R = 120K
R = 1M
1500
300
46
-
-
-
-
-
-
kHz
kHz
kHz
Note
15. Conversion resistance values are not calibrated. Calibrated values and details about calibration are provided in PSoC Creator component data sheets. External
precision resistors can also be used.
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11.5.11 Programmable Gain Amplifier
The PGA is created using a SC/CT Analog Block, see the PGA component data sheet in PSoC Creator for full AC/DC specifications,
and APIs and example code.
Table 11-35. PGA DC Specifications
Parameter
Vos
Description
Conditions
Min
-
Typ
Max
Units
mV
[9]
Input offset voltage
-
10
[9]
DeltaV/DeltaTa Input offset voltage drift
-
±30
µV/°C
µA
[9]
Output current source capability
Drive setting 3, Vdda = 1.71V
100 kHz
-
-
-
-
-
250
[9]
PSRR
Zin
Power supply rejection ratio
69
38
35
-
-
-
dB
1 MHz
dB
[9]
Input impedance
For non inverting inputs
Non inverting mode, reference = Vssa
Rin of 40K
MΩ
[9]
Gain Error
Ge1
Gain = 1
Gain = 2
Gain = 4
Gain = 8
Gain = 16
Gain = 32
Gain = 50
-
-
±
0.15
%
Ge2
Rin of 40K
±
1
%
Ge4
Rin of 40K
-
-
-
-
-
-
-
-
-
-
-
-
-
±
±
1.03
1.23
%
Ge8
Rin of 40K
%
Ge16
Ge32
Ge50
Vonl
Rin of 40K
±
2.5
%
Rin of 40K
±
±
5
5
%
Rin of 40K
%
% of FSR
V
[9]
DC output non linearity G = 1
0.01
Voh, Vol
Output voltage swing
Vssa +
0.15
Vdda -
0.15
[9]
Quiescent current
-
-
1.65
mA
Table 11-36. PGA AC Specifications
Parameter
Description
Conditions
Min
Typ
Max
Units
[9]
-3 db Bandwidth
BW1
Gain = 1
Gain = 24
Gain = 48
Noninverting mode, 300 mV
≤
≤
≤
Vin
Vin
Vin
7
-
-
-
-
-
-
MHz
kHz
kHz
≤
Vdda - 1.2V, Cl
Noninverting mode, 300 mV
Vdda - 1.2V, Cl 25 pF
Noninverting mode, 300 mV
Vdda - 1.2V, Cl 25 pF
≤ 25 pF
BW24
BW48
360
215
≤
≤
≤
≤
[9]
Slew Rate
Gain = 1
SR1
Vdda = 1.71V 5% to 90% FS output
RC limited
3
-
-
-
-
-
-
V/µs
V/µs
V/µs
SR24
SR48
Gain = 24
Gain = 48
0.5
0.5
RC limited
[9]
Input Noise Voltage Density
Gain = 1
eni1
10 kHz
10 kHz
10 kHz
-
-
-
38
38
38
-
-
-
nV/sqrtHz
nV/sqrtHz
nV/sqrtHz
eni24
eni48
Gain = 24
Gain = 48
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11.5.12 Unity Gain Buffer
The Unity Gain Buffer is created using a SC/CT Analog Block. See the Unity Gain Buffer component data sheet in PSoC Creator for
full AC/DC specifications, and APIs and example code.
Table 11-37. Unity Gain Buffer DC Specifications
Parameter
Vos
Description
Conditions
Min
Typ
Max
10
Units
mV
µv/°C
V
[9]
Input offset voltage
-
-
-
-
-
-
Offset voltage drift
Input voltage range
Output voltage range
30
Vssa
Vdda
Voh, Vol
Vssa +
0.15
Vdda -
0.15
V
[9]
Output current source capability
Quiescent current
Drive setting 3, Vdda = 1.71V
-
-
-
250
-
µA
µA
900
Table 11-38. Unity Gain Buffer AC Specifications
Parameter
Description
Conditions
Min
Typ
Max
Units
[9, 14]
Bandwidth
Noninverting mode, 300 mV
Vdda - 1.2V, Cl 25 pF
≤
Vin
≤
7
-
-
MHz
≤
[9]
Slew rate
Input noise spectral density
Vdda = 1.71V 5% to 90% FS output,
CL = 50 pF
3
-
-
-
-
V/µs
[9]
38
nV/sqrtHz
11.5.13 Temperature Sensor
Table 11-39. Temperature Sensor Specifications
Parameter
Description
Conditions
Min
Typ
Max
Units
Temp sensor accuracy
-40 to +140 range
-
±5
-
°C
11.5.14 LCD Direct Drive
Table 11-40. LCD Direct Drive DC Specifications
Parameter
Icc
Description
Conditions
Min
Typ
Max
Units
LCD operating current
32x4 segment display at 30 Hz.
Segment capacitance is < 500 pF
-
15
-
μA
[17]
.
V
LCD bias range
Vdda must be 3V or higher
2.048
-
5.325
-
V
bias
LCD bias step size
-
-
25.8
500
mV
pF
LCD capacitance per
Drivers may be combined.
5000
segment/common driver
Long term segment offset
Iout per segment driver
Strong drive
-
-
10
mV
120
160
0.5
1
200
µA
µA
µA
Weak drive
-
-
-
-
Weak drive 2
Icc per segment driver
Strong drive
220
260
11
300
µA
µA
µA
nA
Weak drive
-
-
-
-
-
-
Weak drive 2
22
No drive
<25
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Table 11-40. LCD Direct Drive DC Specifications (continued)
Parameter
Description
Static (1 common)
Conditions
Min
Typ
Max
Units
Icc
LCD system operating current
Vbias = 5V
Number of LCD pins: 33 (32x1)
Number of segments: 32
-
12
-
µA
LCD
LCD
[16]
Icc
LCD system operating current
Vbias = 3V
-
10
-
µA
Number of LCD pins: 33 (32x1)
[16]
Number of segments: 32
1/4 duty (4 commons)
Icc
Icc
LCD system operating current
Vbias = 5V
Number of LCD pins: 36 (32x4)
Number of segments: 128
-
-
24
21
-
-
µA
µA
LCD
LCD
[16]
LCD system operating current
Vbias = 3V
Number of LCD pins: 36 (32x4)
Number of segments: 128
[16]
1/16 duty (16 commons)
Icc
Icc
LCD system operating current
Vbias = 5V
Number of LCD pins: 48 (32x16)
Number of segments: 512
-
-
93
83
-
-
µA
µA
LCD
LCD
[16]
LCD system operating current
Vbias = 3V
Number of LCD pins: 48 (32x16)
Number of segments: 512
[16]
Table 11-41. LCD Direct Drive AC Specifications
Parameter
Description
LCD frame rate
Conditions
Min
Typ
Max
Units
f
10
50
150
Hz
LCD
Notes
16. Additional conditions: All segments on; 2000 pF glass capacitance; Type A waveform; 32 Hz LCD refresh rate; Operating temperature = 25°C; Boost converter not
used.
17. Connecting an actual LCD display increases the current consumption based on the size of the LCD glass.
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11.6 Digital Peripherals
Specifications are valid for -40°C
where noted.
≤ Ta ≤ 85°C and Tj ≤ 100°C, except where noted. Specifications are valid for 1.71V to 5.5V, except
11.6.1 Timer
Table 11-42. Timer DC Specifications
Parameter Description
Conditions
Min
Typ
Max
Units
Block current consumption
16-bit timer, at listed input clock
frequency
-
-
-
µA
3 MHz
-
-
-
-
-
8
-
-
-
-
-
µA
µA
µA
µA
µA
12 MHz
48 MHz
67 MHz
80 MHz
30
120
165
195
Table 11-43. Timer AC Specifications
Parameter Description
Operating frequency
Conditions
Min
DC
13
30
13
13
30
13
30
Typ
Max
Units
MHz
ns
-
-
-
-
-
-
-
-
80
-
Capture pulse width (Internal)
Capture pulse width (external)
Timer resolution
-
ns
-
ns
Enable pulse width
-
ns
Enable pulse width (external)
Reset pulse width
-
ns
-
ns
Reset pulse width (external)
-
ns
11.6.2 Counter
Table 11-44. Counter DC Specifications
Parameter
Description
Conditions
Min
Typ
Max
Units
Block current consumption
16-bit counter, at listed input clock
frequency
-
-
-
µA
3 MHz
-
-
-
-
-
8
-
-
-
-
-
µA
µA
µA
µA
µA
12 MHz
48 MHz
67 MHz
80 MHz
30
120
165
195
Table 11-45. Counter AC Specifications
Parameter Description
Operating frequency
Conditions
Min
DC
13
Typ
Max
Units
MHz
ns
-
-
-
-
80
-
Capture pulse
Resolution
13
-
ns
Pulse width
13
-
ns
Pulse width (external)
Enable pulse width
Enable pulse width (external)
30
ns
13
-
-
-
-
ns
30
ns
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Table 11-45. Counter AC Specifications (continued)
Parameter Description
Reset pulse width
Reset pulse width (external)
Conditions
Min
13
Typ
Max
Units
ns
-
-
-
-
30
ns
11.6.3 Pulse Width Modulation
Table 11-46. PWM DC Specifications
Parameter
Description
Conditions
Min
Typ
Max
Units
Block current consumption
16-bit PWM, at listed input clock
frequency
-
-
-
µA
3 MHz
-
-
-
-
-
8
-
-
-
-
-
µA
µA
µA
µA
µA
12 MHz
48 MHz
67 MHz
80 MHz
30
120
165
195
Table 11-47. PWM AC Specifications
Parameter
Description
Operating frequency
Conditions
Min
DC
13
30
13
30
13
30
13
30
Typ
Max
Units
MHz
ns
-
-
-
-
-
-
-
-
-
80
-
Pulse width
Pulse width (external)
Kill pulse width
-
ns
-
ns
Kill pulse width (external)
Enable pulse width
-
ns
-
ns
Enable pulse width (external)
Reset pulse width
-
ns
-
ns
Reset pulse width (external)
-
ns
11.6.4 I2C
2
Table 11-48. Fixed I C DC Specifications
Parameter
Description
Conditions
Min
Typ
Max
64
Units
µA
Block current consumption
Enabled, configured for 100 kbps
Enabled, configured for 400 kbps
Wake from sleep mode
-
-
-
-
-
-
74
µA
TBD
µA
2
Table 11-49. Fixed I C AC Specifications
Parameter
Description
Conditions
Min
Typ
Max
Units
Bit rate
-
-
1
Mbps
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11.6.5 Controller Area Network[18]
Table 11-50. CAN DC Specifications
Parameter
Description
Conditions
Min
Typ
Max
285
330
Units
µA
Block current consumption
500 kbps
1 Mbps
-
-
-
-
µA
Table 11-51. CAN AC Specifications
Parameter Description
Conditions
Min
Typ
Max
Units
Bit rate
Minimum 8 MHz clock
-
-
1
Mbit
11.6.6 Digital Filter Block
Table 11-52. DFB DC Specifications
Parameter
Description
Conditions
64-tap FIR at Fdfb
100 kHz (1.3 ksps)
500 kHz (6.7 ksps)
1 MHz (13.4 ksps)
10 MHz (134 ksps)
48 MHz (644 ksps)
67 MHz (900 ksps)
80 MHz (1.07 Msps)
Min
Typ
Max
Units
DFB operating current
-
-
-
-
-
-
-
0.03
0.16
0.33
3.3
0.05
0.27
0.53
5.3
mA
mA
mA
mA
mA
mA
mA
15.7
21.8
26.1
25.5
35.6
42.5
Table 11-53. DFB AC Specifications
Parameter
Fdfb
Description
Conditions
Min
Typ
Max
Units
DFB operating frequency
DC
-
80
MHz
11.6.7 USB
Table 11-54. USB DC Specifications
Parameter Description
Operating current
Conditions
Min
Typ
Max
Units
USB enabled bus idle
-
0.68
-
mA
Note
18. Refer to ISO 11898 specification for details.
Document Number: 001-55036 Rev. *A
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11.7 Memory
Specifications are valid for -40°C
where noted.
≤ Ta ≤ 85°C and Tj ≤ 100°C, except where noted. Specifications are valid for 1.71V to 5.5V, except
11.7.1 Flash
Table 11-55. Flash DC Specifications
Parameter
Description
Conditions
Conditions
Min
Typ
Max
Units
Erase and program voltage
Vddd pin
1.71
-
5.5
V
Table 11-56. Flash AC Specifications
Parameter
Twrite
Description
Min
Typ
Max
15
10
5
Units
ms
Block write time (erase + program)
Block erase time
-
-
-
-
-
-
-
-
-
-
-
-
Terase
ms
Block program time
ms
[19]
Tbulk
Bulk erase time (16 KB to 64 KB)
35
15
5
ms
[19]
Sector erase time (16 KB)
ms
Total device program time
(including JTAG, etc.)
seconds
Flash endurance
100k
20
-
-
-
-
program/
erase
cycles
Flash data retention time
Retention period measured from
last erase cycle
years
11.7.2 EEPROM
Table 11-57. EEPROM DC Specifications
Parameter
Description
Conditions
Conditions
Min
Typ
Max
Units
Erase and program voltage
1.71
-
5.5
V
Table 11-58. EEPROM AC Specifications
Parameter
Description
Single byte erase/write cycle time
EEPROM endurance
Min
-
Typ
Max
15
-
Units
Twrite
2
-
ms
1M
program/
erase
cycles
EEPROM data retention time
Retention period measured from
last erase cycle (up to 100K cycles)
20
-
-
years
11.7.3 Nonvolatile Latches (NVL))
Table 11-59. NVL DC Specifications
Parameter
Description
Conditions
Min
Typ
Max
Units
Erase and program voltage
Vddd pin
1.71
-
5.5
V
Note
19. ECC not included
Document Number: 001-55036 Rev. *A
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Table 11-60. NVL AC Specifications
Parameter Description
NVL endurance
Conditions
Min
Typ
Max
Units
Programmed at 25°C
1K
-
-
program/
erase
cycles
Programmed at 0 to 70°C
100
-
-
program/
erase
cycles
NVL data retention time
Programmed at 25°C
20
20
-
-
-
-
years
years
Programmed at 0 to 70°C
11.7.4 SRAM
Table 11-61. SRAM DC Specifications
Parameter
Description
Conditions
Conditions
Min
Typ
Max
Units
Vsram
SRAM retention voltage
1.2
-
-
V
Table 11-62. SRAM AC Specifications
Parameter
Description
Min
Typ
Max
Units
Fsram
SRAM operating frequency
DC
-
80
MHz
11.7.5 External Memory Interface
Figure 11-1. Asynchronous Read Cycle Timing
Tcel
EM_CEn
EM_Addr
Taddrv
Taddrh
Address
Toeh
Toev
Toel
EM_OEn
EM_WEn
EM_Data
Tdoesu
Tdoeh
Tdceh
Tdcesu
Data
Table 11-63. Asynchronous Read Cycle Specifications
Parameter
T
Description
EMIF Clock period
Conditions
Min
30.3
2*T-1
-
Typ
Max
Units
ns
-
-
-
-
-
-
Tcel
EM_CEn low time
2*T+2
ns
Taddrv
Taddrh
Toev
EM_CEn low to EM_Addr valid
Address hold time after EM_OEn high
EM_CEn low to EM_OEn low
5
-
ns
2
ns
-5
5
ns
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Table 11-63. Asynchronous Read Cycle Specifications (continued)
Parameter
Toel
Description
EM_OEn low time
Conditions
Min
2*T-1
-5
Typ
Max
Units
ns
-
-
-
-
-
-
2*T+2
Toeh
EM_OEn high to EM_CEn high hold time
Data to EM_OEn high setup time
Data to EM_CEn high setup time
Data hold time after EM_OEn high
Data hold time after EM_CEn high
5
-
ns
Tdoesu
Tdcesu
Tdoeh
Tdceh
T+20
T+20
3
ns
-
ns
-
ns
3
-
ns
Figure 11-2. Asynchronous Write Cycle Timing
Taddrv
Taddrh
EM_Addr
EM_CEn
EM_OEn
Address
Tcel
Twev
Twel
Tweh
Tdweh
Tdcev
EM_Data
Data
Table 11-64. Asynchronous Write Cycle Specifications
Parameter
T
Description
EMIF Clock period
Conditions
Min
Typ
Max
Units
ns
30.3
-
-
-
-
-
-
-
-
-
-
-
Taddrv
Taddrh
Tcel
EM_CEn low to EM_Addr valid
Address hold time after EM_WEn high
EM_CEn low time
5
ns
T+2
2*T-1
-5
-
ns
2*T+2
ns
Twev
EM_CEn low to EM_WEn low
EM_WEn low time
5
ns
Twel
T-1
T
T+2
ns
Tweh
Tdcev
Tdweh
EM_WEn high to EM_CEn high hold time
EM_CEn low to data valid
-
7
-
ns
-
ns
Data hold time after EM_WEn high
T
ns
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Figure 11-3. Synchronous Read Cycle Timing
Tcp
EM_Clock
EM_CEn
Tceld
Taddrv
Toeld
Tcehd
Taddriv
EM_Addr
Address
Toehd
EM_OEn
EM_Data
Tds
Tdh
Data
Tadschd
Tadscld
EM_ ADSCn
Table 11-65. Synchronous Read Cycle Specifications
Parameter
T
Description
EMIF Clock period
Conditions
Min
Typ
Max
Units
ns
30.3
30.3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Tcp
EM_Clock Period
ns
Tceld
EM_Clock low to EM_CEn low
EM_Clock high to EM_CEn high
EM_Clock low to EM_Addr valid
EM_Clock high to EM_Addr invalid
EM_Clock low to EM_OEn low
EM_Clock high to EM_OEn high
Data valid before EM_Clock high
Data valid after EM_Clock high
EM_clock low to EM_ADSCn low
EM_clock high to EM_ADSCn high
5
-
ns
Tcehd
Taddrv
Taddriv
Toeld
Toehd
Tds
T/2 - 2
ns
-
5
-
ns
T/2 - 2
ns
-
T+2
20
5
-
ns
ns
-
ns
Tdh
2
-
ns
Tadscld
Tadschd
-
5
-
ns
T/2 - 2
ns
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Figure 11-4. Synchronous Write Cycle Timing
Tcp
EM_Clock
EM_CEn
Tceld
Tcehd
Taddrv
Tweld
Tds
Taddriv
EM_Addr
Address
Twehd
EM_WEn
EM_Data
Data
Tadschd
Tadscld
EM_ ADSCn
Table 11-66. Synchronous Write Cycle Specifications
Parameter
T
Description
EMIF Clock period
Conditions
Min
Typ
Max
Units
ns
30.3
-
-
-
Tcp
EM_Clock Period
30.3
ns
Tceld
EM_Clock low to EM_CEn low
EM_Clock high to EM_CEn high
EM_Clock low to EM_Addr valid
EM_Clock high to EM_Addr invalid
EM_Clock low to EM_WEn low
EM_Clock high to EM_WEn high
Data valid after EM_Clock low
EM_clock low to EM_ADSCn low
EM_clock high to EM_ADSCn high
-
5
-
ns
Tcehd
Taddrv
Taddriv
Tweld
Twehd
Tds
T/2 - 2
ns
-
5
-
ns
T/2 - 2
ns
-
5
-
ns
T/2 - 2
ns
-
5
5
-
ns
Tadscld
Tadschd
-
ns
T/2 - 2
ns
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11.8 PSoC System Resources
Specifications are valid for -40°C
where noted.
≤ Ta ≤ 85°C and Tj ≤ 100°C, except where noted. Specifications are valid for 1.71V to 5.5V, except
11.8.1 POR with Brown Out
Table 11-67. Power On Reset (POR) with Brown Out DC Specifications
Parameter
Description
Imprecise POR (IPOR)
Rising trip voltage
Falling trip voltage
Hysteresis
Conditions
Min
Typ
Max
Units
0.8
0.75
15
-
-
-
1.45
1.4
V
V
200
mV
Precise POR (PPOR)
Rising trip voltage
Falling trip voltage
1.588
1.562
1.620
1.594
1.652
1.626
V
V
Table 11-68. Power On Reset (POR) with Brown Out AC Specifications
Parameter
Description
Conditions
Min
Typ
Max
Units
PPOR_TR Response time
-
-
1.00E+00
µs
11.8.2 Voltage Monitors
Table 11-69. Voltage Monitors DC Specifications
Parameter
Description
Conditions
Min
Typ
Max
Units
LVI
Trip Voltage
LVI_A/D_SEL[3:0] = 0000b
LVI_A/D_SEL[3:0] = 0001b
LVI_A/D_SEL[3:0] = 0010b
LVI_A/D_SEL[3:0] = 0011b
LVI_A/D_SEL[3:0] = 0100b
LVI_A/D_SEL[3:0] = 0101b
LVI_A/D_SEL[3:0] = 0110b
LVI_A/D_SEL[3:0] = 0111b
LVI_A/D_SEL[3:0] = 1000b
LVI_A/D_SEL[3:0] = 1001b
LVI_A/D_SEL[3:0] = 1010b
LVI_A/D_SEL[3:0] = 1011b
LVI_A/D_SEL[3:0] = 1100b
LVI_A/D_SEL[3:0] = 1101b
LVI_A/D_SEL[3:0] = 1110b
LVI_A/D_SEL[3:0] = 1111b
Trip Voltage
1.667
1.914
2.158
2.404
2.651
2.895
3.144
3.387
3.629
3.875
4.117
4.362
4.607
4.879
5.107
5.356
5.630
1.701
1.953
2.202
2.453
2.705
2.954
3.208
3.456
3.703
3.954
4.201
4.451
4.701
4.979
5.211
5.465
5.745
1.735
1.992
2.246
2.502
2.759
3.013
3.272
3.525
3.777
4.033
4.285
4.540
4.795
5.079
5.315
5.574
5.860
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
HVI
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Table 11-70. Voltage Monitors AC Specifications
Parameter Description
Response time
Conditions
Min
Typ
Max
Units
-
-
1.00E+00
µs
11.8.3 Interrupt Controller
Table 11-71. Interrupt Controller AC Specifications
Parameter Description
Conditions
Min
Typ
Max
Units
Delay from Interrupt signal input to ISR Includes worse case completion of
-
-
20
Tcy CPU
code execution from main line code
longest instruction ???? with ??
cycles
Delay from Interrupt signal input to ISR Includes worse case completion of
-
-
20
Tcy CPU
code execution from ISR code
longest instruction ???? with ??
cycles
11.8.4 JTAG Interface
[9]
Table 11-72. JTAG Interface AC Specifications
Parameter
Description
TCK frequency
Conditions
Min
-
Typ
Max
Units
MHz
ns
-
-
8
-
TCK low
6.5
5.5
2
TCK high
-
-
ns
TDI, TMS setup before TCK high
TDI, TMS hold after TCK high
TDO hold after TCK high
TCK low to TDO valid
TCK to device outputs valid
-
-
ns
3
-
-
ns
4
-
-
ns
4
16
-
-
ns
-
18
ns
11.8.5 SWD Interface
[9]
Table 11-73. SWD Interface AC Specifications
Parameter
Description
SWDCLK frequency
Conditions
Conditions
Min
Typ
Max
Units
-
-
8
MHz
11.8.6 TPIU Interface
Table 11-74. TPIU Interface AC Specifications
Parameter Description
[9]
Min
Typ
Max
33
Units
MHz
Mbit
TRACEPORT (TRACECLK) frequency
SWV bit rate
-
-
-
-
33
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11.9 Clocking
Specifications are valid for -40°C
where noted.
≤
Ta
≤
85°C and Tj
≤
100°C, except where noted. Specifications are valid for 1.71V to 5.5V, except
11.9.1 32 kHz External Crystal
[9]
Table 11-75. 32 kHz External Crystal DC Specifications
Parameter
Description
Operating current
Conditions
Min
Typ
0.25
6
Max
Units
µA
Icc
CL
DL
Low power mode
-
-
-
-
-
External crystal capacitance
Drive level
pF
-
1
µW
Table 11-76. 32 kHz External Crystal AC Specifications
Parameter
Description
Conditions
Min
Typ
32.768
50
Max
Units
kHz
%
F
Frequency
-
20
-
-
80
-
[9]
DC
Ton
Output duty cycle
Startup time
High power mode
1
s
11.9.2 Internal Main Oscillator)
Table 11-77. IMO DC Specifications
Parameter
Description
Supply current
Conditions
Min
Typ
Max
Units
48 MHz
-
-
-
-
-
-
30
160
500
100
80
-
-
-
-
-
-
µA
µA
µA
µA
µA
µA
24 MHz - Non USB mode
24 MHz - USB mode
12 MHz
With oscillator locking to USB bus
6 MHz
3 MHz
70
Table 11-78. IMO AC Specifications
Parameter
Description
Conditions
Min
Typ
Max
Units
IMO frequency stability (with factory trim)
72 MHz
-7
-5
-
-
-
-
-
-
-
-
7
5
%
%
%
%
%
%
%
µs
48 MHz
24 MHz - Non USB mode
24 MHz - USB mode
12 MHz
-4
4
Fimo
With oscillator locking to USB bus
-0.25
-3
0.25
3
6 MHz
-2
2
3 MHz
-1
1
[9]
Startup time
Fromenable(duringnormalsystem
operation) or wakeup from low
power state
-
10
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Table 11-78. IMO AC Specifications (continued)
Parameter
Description
Conditions
Min
Typ
Max
Units
[9]
Jitter (peak to peak)
Jp-p
F = 24 MHz
F = 3 MHz
-
-
0.9
1.6
-
-
ns
ns
[9]
Jitter (long term)
F = 24 MHz
F = 3 MHz
Jperiod
-
-
0.9
12
-
-
ns
ns
11.9.3 Internal Low Speed Oscillator
Table 11-79. ILO DC Specifications
Parameter
Description
Conditions
Min
Typ
0.3
0.5
0.6
Max
Units
µA
Operating current, includes sleep timer Fout = 1 kHz
-
-
-
-
-
-
and WDT
Icc
Fout = 32 kHz
µA
Fout = 100 kHz
µA
[9]
Table 11-80. ILO AC Specifications
Parameter
Description
Conditions
Turbo mode
Min
Typ
0.1
0.6
0.8
50
Max
3
Units
ms
Startup time
Startup time
Startup time
Duty cycle
-
-
Non-turbo mode, pd_mode = 0
Non-turbo mode, pd_mode = 1
2
ms
-
17
55
ms
45
%
ILO frequencies (trimmed)
100 kHz
80
26
100
32
1
130
43
kHz
kHz
kHz
32 kHz
1 kHz
0.75
1.65
Filo
ILO frequencies (untrimmed)
100 kHz
32 kHz
1 kHz
55
18
100
32
1
160
56
kHz
kHz
kHz
0.55
1.75
11.9.4 External Crystal Oscillator
Table 11-81. ECO AC Specifications
Parameter
F
Description
Conditions
Min
Typ
-
Max
33
60
-
Units
MHz
%
Crystal frequency range
4
40
-
[9]
DC
Duty cycle
50
[9]
Jp-p
Jitter (peak to peak)
SIO, GPIO
SIO, GPIO
200
200
ps
[9]
Jperiod
Jitter (long term)
-
-
ps
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11.9.5 External Clock Reference
Table 11-82. External Clock Reference AC Specifications
[9]
Parameter
Description
External frequency range
Input duty cycle range
Input edge rate
Conditions
Min
0
Typ
Max
33
70
-
Units
MHz
%
-
50
-
Measured at Vddio/2
Vil to Vih
30
0.1
V/ns
11.9.6 Phase-Locked Loop
Table 11-83. PLL DC Specifications
Parameter
Idd
Description
PLL operating current
Conditions
Min
Typ
1920
560
Max
Units
µA
FREF = 3 MHz, FVCO=66 MHz
FREF = 3 MHz, FVCO=24 MHz
-
-
-
-
µA
Table 11-84. PLL AC Specifications
Parameter
Fpllinpre
Fpllin
Description
PLL prescaler input frequency
PLL input frequency
Conditions
Min
1
Typ
Max
48
Units
MHz
MHz
MHz
µs
-
-
-
-
-
-
1
3
Fpllout
PLL output frequency
24
-
80
Lock time at startup
250
250
55
[9]
Jperiod-rms Jitter (rms)
-
ps
PLL output duty cycle
All PLL output frequencies
45
%
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12. Ordering Information
In addition to the features listed in Table 12-1, every CY8C54 device includes: up to 256K Flash, 64K SRAM, 2K EEPROM, a precision
2
on-chip voltage reference, precision oscillators, Flash, ECC, DMA, a fixed function I C, JTAG/SWD programming and debug, external
memory interface, and more. In addition to these features, the flexible UDBs and Analog Subsection support a wide range of periph-
erals. To assist you in selecting the ideal part, PSoC Creator makes a part recommendation after you choose the components required
by your application. All CY8C54 derivatives incorporate device and Flash security in user-selectable security levels; see TRM for
details
Table 12-1. CY8C54 Family with ARM Cortex-M3 CPU
MCU Core Analog
.
[22]
Digital
I/O
[23]
Part Number
Package
JTAG ID
32 KB Flash
CY8C5485AXI-044 80 32
CY8C5485LTI-021 80 32
CY8C5485PVI-085 80 32
CY8C5485AXI-062 80 32
CY8C5485PVI-006 80 32
64 KB Flash
8
8
8
8
8
2
2
2
2
2
✔
✔
✔
✔
✔
2x12-bit SAR
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
✔
✔
✔
✔
✔
20
20
20
20
20
4
4
4
4
4
✔
✔
✔
✔
✔
-
-
72
48
31
72
31
62
38
25
62
25
8
8
4
8
4
2
2
2
2
2
100-TQFP 0x0E12C069
68-QFN 0x0E115069
48-SSOP 0x0E155069
100-TQFP 0x0E13E069
48-SSOP 0x0E106069
2x12-bit SAR
2x12-bit SAR
2x12-bit SAR
2x12-bit SAR
-
✔
✔
CY8C5486AXI-064 80 64 16
CY8C5486LTI-063 80 64 16
CY8C5486PVI-094 80 64 16
CY8C5486AXI-039 80 64 16
CY8C5486PVI-046 80 64 16
128 KB Flash
2
2
2
2
2
✔
✔
✔
✔
✔
2x12-bit SAR
2x12-bit SAR
2x12-bit SAR
2x12-bit SAR
2x12-bit SAR
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
✔
✔
✔
✔
✔
24
24
24
24
24
4
4
4
4
4
✔
✔
✔
✔
✔
-
-
72
48
31
72
31
62
38
25
62
25
8
8
4
8
4
2
2
2
2
2
100-TQFP 0x0E140069
68-QFN 0x0E13F069
48-SSOP 0x0E15E069
100-TQFP 0x0E127069
48-SSOP 0x0E12E069
-
✔
✔
CY8C5487AXI-011 80 128 32
CY8C5487LTI-007 80 128 32
CY8C5487PVI-069 80 128 32
CY8C5487AXI-100 80 128 32
CY8C5487PVI-056 80 128 32
256 KB Flash
2
2
2
2
2
✔
✔
✔
✔
✔
2x12-bit SAR
2x12-bit SAR
2x12-bit SAR
2x12-bit SAR
2x12-bit SAR
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
✔
✔
✔
✔
✔
24
24
24
24
24
4
4
4
4
4
✔
✔
✔
✔
✔
-
-
72
48
31
72
31
62
38
25
62
25
8
8
4
8
4
2
2
2
2
2
100-TQFP 0x0E10B069
68-QFN 0x0E107069
48-SSOP 0x0E145069
100-TQFP 0x0E164069
48-SSOP 0x0E138069
-
✔
✔
CY8C5488AXI-018 80 256 64
CY8C5488LTI-037 80 256 64
CY8C5488PVI-103 80 256 64
CY8C5488AXI-097 80 256 64
CY8C5488PVI-077 80 256 64
2
2
2
2
2
✔
✔
✔
✔
✔
2x12-bit SAR
2x12-bit SAR
2x12-bit SAR
2x12-bit SAR
2x12-bit SAR
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
✔
✔
✔
✔
✔
24
24
24
24
24
4
4
4
4
4
✔
✔
✔
✔
✔
-
-
72
48
31
72
31
62
38
25
62
25
8
8
4
8
4
2
2
2
2
2
100-TQFP 0x0E112069
68-QFN 0x0E125069
48-SSOP 0x0E167069
100-TQFP 0x0E161069
48-SSOP 0x0E14D069
-
✔
✔
Notes
20. Analog blocks support a wide variety of functionality including TIA, PGA, and mixers. See Example Peripherals on page 32 for more information on how Analog Blocks
may be used.
21. UDBs support a wide variety of functionality including SPI, LIN, UART, timer, counter, PWM, PRS, and others. Individual functions may use a fraction of a UDB or
multiple UDBs. Multiple functions can share a single UDB. See Example Peripherals on page 32 for more information on how UDBs may be used.
22. The I/O Count includes all types of digital I/O: GPIO, SIO, and the two USB I/O. See I/O System and Routing on page 26 for details on the functionality of each of
these types of I/O.
23. The JTAG ID has three major fields. The most significant nibble (left digit) is the version, followed by a 2 byte part number and a 3 nibble manufacturer ID.
Document Number: 001-55036 Rev. *A
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PSoC®5:CY8C54FamilyData Sheet
12.1 Part Numbering Conventions
PSoC 5 devices follow the part numbering convention described below. All fields are single character alphanumeric (0, 1, 2, …, 9, A,
B, …, Z) unless stated otherwise.
CY8Cabcdefg-xxx
a: Architecture
ef: Package Code
3: PSoC 3
5: PSoC 5
Two character alphanumeric
AX: TQFP
LT: QFN
b: Family Group within Architecture
PV: SSOP
2: CY8C52 family
3: CY8C53 family
4: CY8C54 family
5: CY8C55 family
g: Temperature Range
C: commercial
I: industrial
A: automotive
c: Speed Grade
xxx: Peripheral Set
4: 40 MHz
8: 80 MHz
Three character numeric
No meaning is associated with these three characters
d: Flash Capacity
5: 32 KB
6: 64 KB
7: 128 KB
8: 256 KB
CY8C
5
4
8
8
P V
I
- x x x
Examples
Cypress Prefix
Architecture
5: PSoC5
4: CY8C54 Family
8: 80 MHz
Family Group within Architecture
Speed Grade
8: 256 KB
Flash Capacity
PV: SSOP
Package Code
I: Industrial
Temperature Range
Peripheral Set
All devices in the PSoC 5 CY8C54 family comply to RoHS-6 specifications, demonstrating the commitment by Cypress to lead-free
products. Lead (Pb) is an alloying element in solders that has resulted in environmental concerns due to potential toxicity. Cypress
uses nickel-palladium-gold (NiPdAu) technology for the majority of leadframe-based packages.
A high level review of the Cypress Pb-free position is available on our website. Specific package information is also available. Package
Material Declaration Datasheets (PMDDs) identify all substances contained within Cypress packages. PMDDs also confirm the
absence of many banned substances. The information in the PMDDs will help Cypress customers plan for recycling or other "end of
life" requirements.
Document Number: 001-55036 Rev. *A
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PRELIMINARY
PSoC®5:CY8C54FamilyData Sheet
13. Packaging
Table 13-1. Package Characteristics
Parameter
Ta
Description
Conditions
Min
Typ
25
Max
Units
°C
Operating ambient temperature
Operating junction temperature
-40
85
Tj
-40
-
100
°C
Tja
Tja
Tja
Tjc
Tjc
Tjc
Package
Package
Package
Package
Package
Package
θ
θ
θ
θ
θ
θ
JA (48 SSOP)
-
36.87
10.93
29.50
25.48
6.08
7.32
-
-
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C
JA (68 QFN)
-
-
JA (100 TQFP)
JC (48 SSOP)
JC (68 QFN)
JC (100 TQFP)
-
-
-
-
-
-
-
-
Pb-Free assemblies (20s to 40s) -
Sn-Ag-Cu solder paste reflow
temperature
235
245
Pb-Free assemblies (20s to 40s) -
Sn-Pb solder paste reflow temper-
ature
205
-
220
°C
Figure 13-1. 48-Pin (300 mil) SSOP Package Outline
.020
1
24
0.395
0.420
0.292
0.299
DIMENSIONS IN INCHES MIN.
MAX.
25
48
0.620
0.630
0.005
0.010
SEATING PLANE
0.004
.010
0.088
0.092
0.095
0.110
GAUGE PLANE
0.024
0.040
0.025
BSC
0°-8°
51-85061-*C
0.008
0.016
0.008
0.0135
Document Number: 001-55036 Rev. *A
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PSoC®5:CY8C54FamilyData Sheet
Figure 13-2. 68-Pin QFN 8x8 with 0.4 mm Pitch Package Outline (Sawn Version)
TOP VIEW
SIDE VIEW
BOTTOM VIEW
0.900±0.100
5.7±0.10
8.000±0.100
0.200 REF
PIN1 ID
R 0.20
0.400 PITCH
5
2
6
8
5
2
6
8
1
5
1
5
1
1
PIN 1 DOT
SOLDERABLE
EXPOSED
PAD
LASER MARK
5.7±0.10
0.20±0.05
1
7
3
5
1
7
3
0.400±0.1005
3
4
1
8
0.05 MAX
3
4
1
8
6.40 REF
NOTES:
1. HATCH AREA IS SOLDERABLE EXPOSED METAL.
001-09618 *C
2. REFERENCE JEDEC#: MO-220
3. PACKAGE WEIGHT: 0.17g
4. ALL DIMENSIONS ARE IN MILLIMETERS
Figure 13-3. 100-Pin TQFP (14 x 14 x 1.4 mm) Package Outline
NOTE:
16.00±0.25 SQ
1. JEDEC STD REF MS-026
14.00±0.05 SQ
2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH
MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE
BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH
100
76
1
75
3. DIMENSIONS IN MILLIMETERS
R 0.08 MIN.
0.20 MAX.
0° MIN.
STAND-OFF
0.05 MIN.
0.25
0.15 MAX.
GAUGE PLANE
R 0.08 MIN.
0.20 MAX.
0°-7°
0.50
TYP.
0 0 12.0000
0.60±0.15
A
DETAIL
25
51
26
50
NOTE: PKG. CAN HAVE
OR
12°±1°
(8X)
SEATING PLANE
1.60 MAX.
TOP LEFT CORNER CHAMFER
4 CORNERS CHAMFER
51-85048-*C
1.40±0.05
0.08
0.20 MAX.
A
SEE DETAIL
Document Number: 001-55036 Rev. *A
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PSoC®5:CY8C54FamilyData Sheet
14. Revision History
®
®
Description Title: PSoC 5: CY8C54 Family Data Sheet Programmable System-on-Chip (PSoC )
Document Number: 001-55036
Submission
Date
Orig. of
Change
Rev.
ECN No.
Description of Change
**
2759055
2824626
09/02/09
12/09/09
MKEA
MKEA
New data sheet for new device CY8C54 Family Data Sheet.
*A
Updated I2C section to reflect 1 Mbps. Updated Table 11-6 and 11- 7 (Boost
AC and DC specs); also added Shottky Diode specs. Changed current for
sleep/hibernate mode to include SIO; Added footnote to analog global specs.
Updated Figures 1-1, 6-2, 7-14, and 8-1. Updated Table 6-2 and Table 6-3
(Hibernate and Sleep rows) and Power Modes section. Updated GPIO and
SIO AC specifications. Updated Gain error in IDAC and VDAC specifications.
Updated description of Vdda spec in Table 11-1 and removed GPIO Clamp
Current parameter. Moved FILO from ILO DC to AC table.
Added PCB Layout and PCB Schematic diagrams.
Updated Fgpioout spec (Table 11-9). Added duty cycle frequency in PLL AC
spec table. Added note for Sleep and Hibernate modes and Active Mode
specs in Table 11-2. Linked URL in Section 10.3 to PSoC Creator site.
Updated Ja and Jc values in Table 13-1. Updated Single Sample Mode and
Fast FIR Mode sections. Updated Input Resistance specification in Del-Sig
ADC table. Added Tio_init parameter. Updated PGA and UGB AC Specs.
Removed SPC ADC. Updated Boost Converter section.
Added section 'SIO as Comparator'; updated Hysteresis spec (differential
mode) in Table 11-10.
Updated Vbat condition and deleted Vstart parameter in Table 11-6.
Removed reference to Idle mode. CDT 59671: Updated footnotes and ADC
column in ordering information. Removed CSA (Section 8.7). Updated IMO
table and number of UDBs
Document Number: 001-55036 Rev. *A
Page 92 of 93
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PSoC®5: CY8C54 Family Data Sheet
15. Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at cypress.com/sales.
Products
PSoC
psoc.cypress.com
clocks.cypress.com
wireless.cypress.com
memory.cypress.com
image.cypress.com
Clocks & Buffers
Wireless
Memories
Image Sensors
© Cypress Semiconductor Corporation, 2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any
circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical,
life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical
components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-55036 Rev. *A
Revised December 03, 2009
Page 93 of 93
®
®
®
®
®
CapSense , PSoC 3, PSoC 5, and PSoC Creator™ are trademarks and PSoC is a registered trademark of Cypress Semiconductor Corp. All other trademarks or registered trademarks referenced
herein are property of the respective corporations.
Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided
that the system conforms to the I2C Standard Specification as defined by Philips.
ARM is a registered trademark, and Keil, and RealView are trademarks, of ARM Limited. All products and company names mentioned in this document may be the trademarks of their respective holders.
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