CY8C4146LQI-S432T [CYPRESS]
Multifunction Peripheral,;型号: | CY8C4146LQI-S432T |
厂家: | CYPRESS |
描述: | Multifunction Peripheral, 时钟 |
文件: | 总41页 (文件大小:461K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
PSoC® 4: PSoC 4100S
Family Datasheet
Programmable System-on-Chip (PSoC)
General Description
PSoC® 4 is a scalable and reconfigurable platform architecture for a family of programmable embedded system controllers with an
ARM® Cortex™-M0+ CPU. It combines programmable and reconfigurable analog and digital blocks with flexible automatic routing.
The PSoC 4100S product family is a member of the PSoC 4 platform architecture. It is a combination of a microcontroller with standard
communication and timing peripherals, a capacitive touch-sensing system (CapSense) with best-in-class performance, programmable
general-purpose continuous-time and switched-capacitor analog blocks, and programmable connectivity. PSoC 4100S products will
be upward compatible with members of the PSoC 4 platform for new applications and design needs.
Features
32-bit MCU Subsystem
Serial Communication
■ 48-MHz ARM Cortex-M0+ CPU
■ Up to 64 KB of flash with Read Accelerator
■ Up to 8 KB of SRAM
■ Three independent run-time reconfigurable Serial
Communication Blocks (SCBs) with re-configurable I2C, SPI,
or UART functionality
Timing and Pulse-Width Modulation
Programmable Analog
■ Five 16-bit timer/counter/pulse-width modulator (TCPWM)
blocks
■ Two opamps with reconfigurable high-drive external and
high-bandwidthinternaldriveandComparatormodesandADC
input buffering capability. Opamps can operate in Deep Sleep
low-power mode.
■ Center-aligned, Edge, and Pseudo-random modes
■ Comparator-based triggering of Kill signals for motor drive and
other high-reliability digital logic applications
■ 12-bit 1-Msps SAR ADC with differential and single-ended
modes, and Channel Sequencer with signal averaging
Up to 36 Programmable GPIO Pins
■ Single-slope 10-bit ADC function provided by a capacitance
sensing block
■ 48-pin TQFP, 44-pin TQFP, 40-pin QFN, 32-pin QFN, and
35-ball WLCSP packages
■ Two current DACs (IDACs) for general-purpose or capacitive
sensing applications on any pin
■ Any GPIO pin can be CapSense, analog, or digital
■ Two low-power comparators that operate in Deep Sleep
low-power mode
■ Drive modes, strengths, and slew rates are programmable
PSoC Creator Design Environment
Programmable Digital
■ Integrated Development Environment (IDE) provides
schematic design entry and build (with analog and digital
automatic routing)
■ Programmable logic blocks allowing Boolean operations to be
performed on port inputs and outputs
Low-Power 1.71-V to 5.5-V Operation
■ Applications Programming Interface (API) component for all
■ Deep Sleep mode with operational analog and 2.5-A digital
fixed-function and programmable peripherals
system current
Industry-Standard Tool Compatibility
Capacitive Sensing
■ After schematic entry, development can be done with
■ Cypress CapSense Sigma-Delta (CSD) provides best-in-class
ARM-based industry-standard development tools
signal-to-noise ratio (SNR) (>5:1) and water tolerance
■ Cypress-supplied software component makes capacitive
sensing design easy
■ Automatic hardware tuning (SmartSense™)
LCD Drive Capability
■ LCD segment drive capability on GPIOs
Cypress Semiconductor Corporation
Document Number: 002-00122 Rev. *I
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised April 26, 2017
PSoC® 4: PSoC 4100S
Family Datasheet
Contents
Functional Definition........................................................ 4
CPU and Memory Subsystem..................................... 4
System Resources ...................................................... 4
Analog Blocks.............................................................. 5
Fixed Function Digital.................................................. 5
GPIO ........................................................................... 6
Special Function Peripherals....................................... 6
Pinouts .............................................................................. 7
Alternate Pin Functions ............................................... 9
Power............................................................................... 11
Mode 1: 1.8 V to 5.5 V External Supply .................... 11
Mode 2: 1.8 V ±5% External Supply.......................... 11
Development Support .................................................... 12
Documentation .......................................................... 12
Online........................................................................ 12
Tools.......................................................................... 12
Electrical Specifications ................................................ 13
Absolute Maximum Ratings....................................... 13
Device Level Specifications....................................... 13
Analog Peripherals.................................................... 17
Digital Peripherals ..................................................... 25
Memory ..................................................................... 28
System Resources.................................................... 28
Ordering Information...................................................... 31
Packaging........................................................................ 34
Package Diagrams.................................................... 35
Acronyms........................................................................ 38
Document Conventions ................................................. 40
Units of Measure ....................................................... 40
Revision History ............................................................. 41
Sales, Solutions, and Legal Information ...................... 42
Worldwide Sales and Design Support....................... 42
Products.................................................................... 42
PSoC® Solutions ...................................................... 42
Cypress Developer Community................................. 42
Technical Support ..................................................... 42
Document Number: 002-00122 Rev. *I
Page 2 of 41
PSoC® 4: PSoC 4100S
Family Datasheet
Figure 1. Block Diagram
CPU Subsystem
PSoC 4100S
Architecture
SWD/TC
SPCIF
Cortex
FLASH
64 KB
SRAM
8 KB
ROM
8 KB
M0+
48 MHz
32-bit
FAST MUL
NVIC, IRQMUX
AHB- Lite
Read Accelerator
SRAM Controller
ROM Controller
System Resources
Lite
System Interconnect (Single Layer AHB)
Peripheral Interconnect (MMIO)
Power
Sleep Control
WIC
Peripherals
PCLK
POR
REF
PWRSYS
Clock
Clock Control
WDT
Programmable
Analog
ILO
IMO
SAR ADC
(12-bit)
Reset
Reset Control
XRES
Test
TestMode Entry
Digital DFT
Analog DFT
x1
CTBm
2x Opamp
SARMUX
x1
High Speed I/O Matrix& 2 x Programmable I/O
36x GPIOs, LCD
Power Modes
Active/ Sleep
DeepSleep
I/O Subsystem
PSoC 4100S devices include extensive support for
programming, testing, debugging, and tracing both hardware
and firmware.
The debug circuits are enabled by default and can be disabled
in firmware. If they are not enabled, the only way to re-enable
them is to erase the entire device, clear flash protection, and
reprogram the device with new firmware that enables debugging.
Thus firmware control of debugging cannot be over-ridden
without erasing the firmware thus providing security.
The ARM Serial-Wire Debug (SWD) interface supports all
programming and debug features of the device.
Complete debug-on-chip functionality enables full-device
debugging in the final system using the standard production
device. It does not require special interfaces, debugging pods,
simulators, or emulators. Only the standard programming
connections are required to fully support debug.
Additionally, all device interfaces can be permanently disabled
(device security) for applications concerned about phishing
attacks due to a maliciously reprogrammed device or attempts to
defeat security by starting and interrupting flash programming
sequences. All programming, debug, and test interfaces are
disabled when maximum device security is enabled. Therefore,
PSoC 4100S, with device security enabled, may not be returned
for failure analysis. This is a trade-off the PSoC 4100S allows the
customer to make.
The PSoC Creator IDE provides fully integrated programming
and debug support for the PSoC 4100S devices. The SWD
interface is fully compatible with industry-standard third-party
tools. The PSoC 4100S family provides a level of security not
possible with multi-chip application solutions or with
microcontrollers. It has the following advantages:
■ Allows disabling of debug features
■ Robust flash protection
■ Allows customer-proprietary functionality to be implemented in
on-chip programmable blocks
Document Number: 002-00122 Rev. *I
Page 3 of 41
PSoC® 4: PSoC 4100S
Family Datasheet
between different clock sources without glitching. In addition, the
clock system ensures that there are no metastable conditions.
Functional Definition
CPU and Memory Subsystem
CPU
The clock system for the PSoC 4100S consists of the internal
main oscillator (IMO), internal low-frequency oscillator (ILO), a
32 kHz Watch Crystal Oscillator (WCO) and provision for an
external clock. Clock dividers are provided to generate clocks for
peripherals on a fine-grained basis. Fractional dividers are also
provided to enable clocking of higher data rates for UARTs.
The Cortex-M0+ CPU in the PSoC 4100S is part of the 32-bit
MCU subsystem, which is optimized for low-power operation
with extensive clock gating. Most instructions are 16 bits in length
and the CPU executes a subset of the Thumb-2 instruction set.
It includes a nested vectored interrupt controller (NVIC) block
with eight interrupt inputs and also includes a Wakeup Interrupt
Controller (WIC). The WIC can wake the processor from Deep
Sleep mode, allowing power to be switched off to the main
processor when the chip is in Deep Sleep mode.
Figure 2. PSoC 4100S MCU Clocking Architecture
IMO
HFCLK
Divide By
2,4,8
External Clock
The CPU also includes a debug interface, the serial wire debug
(SWD) interface, which is a two-wire form of JTAG. The debug
configuration used for PSoC 4100S has four breakpoint
(address) comparators and two watchpoint (data) comparators.
ILO
LFCLK
Flash
HFCLK
Prescaler
SYSCLK
The PSoC 4100S device has a flash module with a flash
accelerator, tightly coupled to the CPU to improve average
access times from the flash block. The low-power flash block is
designed to deliver two wait-state (WS) access time at 48 MHz.
The flash accelerator delivers 85% of single-cycle SRAM access
performance on average.
Integer
Dividers
6X 16-bit
Fractional
Dividers
2X 16.5-bit
The HFCLK signal can be divided down to generate
synchronous clocks for the analog and digital peripherals. There
are eight clock dividers for the PSoC 4100S; two of those are
fractional dividers. The 16-bit capability allows flexible
generation of fine-grained frequency values and is fully
supported in PSoC Creator
SRAM
Eight KB of SRAM are provided with zero wait-state access at
48 MHz.
SROM
An 8 KB supervisory ROM that contains boot and configuration
routines is provided.
IMO Clock Source
The IMO is the primary source of internal clocking in the
PSoC 4100S. It is trimmed during testing to achieve the specified
accuracy.The IMO default frequency is 24 MHz and it can be
adjusted from 24 to 48 MHz in steps of 4 MHz. The IMO tolerance
with Cypress-provided calibration settings is ±2%.
System Resources
Power System
The power system is described in detail in the section Power on
page 11. It provides assurance that voltage levels are as required
for each respective mode and either delays mode entry (for
example, on power-on reset (POR)) until voltage levels are as
required for proper functionality, or generates resets (for
example, on brown-out detection). The PSoC 4100S operates
with a single external supply over the range of either 1.8 V ±5%
(externally regulated) or 1.8 to 5.5 V (internally regulated) and
has three different power modes, transitions between which are
managed by the power system. The PSoC 4100S provides
Active, Sleep, and Deep Sleep low-power modes.
ILO Clock Source
The ILO is a very low power, nominally 40-kHz oscillator, which
is primarily used to generate clocks for the watchdog timer
(WDT) and peripheral operation in Deep Sleep mode. ILO-driven
counters can be calibrated to the IMO to improve accuracy.
Cypress provides a software component, which does the
calibration.
Watch Crystal Oscillator (WCO)
The PSoC 4100S clock subsystem also implements a
low-frequency (32-kHz watch crystal) oscillator that can be used
for precision timing applications.
All subsystems are operational in Active mode. The CPU
subsystem (CPU, flash, and SRAM) is clock-gated off in Sleep
mode, while all peripherals and interrupts are active with
instantaneous wake-up on a wake-up event. In Deep Sleep
mode, the high-speed clock and associated circuitry is switched
off; wake-up from this mode takes 35 µs. The opamps can
remain operational in Deep Sleep mode.
Watchdog Timer
A watchdog timer is implemented in the clock block running from
the ILO; this allows watchdog operation during Deep Sleep and
generates a watchdog reset if not serviced before the set timeout
occurs. The watchdog reset is recorded in a Reset Cause
register, which is firmware readable.
Clock System
The PSoC 4100S clock system is responsible for providing
clocks to all subsystems that require clocks and for switching
Document Number: 002-00122 Rev. *I
Page 4 of 41
PSoC® 4: PSoC 4100S
Family Datasheet
Reset
Buffers, Filters, Trans-Impedance Amplifiers, and other functions
can be realized, in some cases with external passives. saving
power, cost, and space. The on-chip opamps are designed with
enough bandwidth to drive the Sample-and-Hold circuit of the
ADC without requiring external buffering.
The PSoC 4100S can be reset from a variety of sources
including a software reset. Reset events are asynchronous and
guarantee reversion to a known state. The reset cause is
recorded in a register, which is sticky through reset and allows
software to determine the cause of the reset. An XRES pin is
reserved for external reset by asserting it active low. The XRES
pin has an internal pull-up resistor that is always enabled.
Low-power Comparators (LPC)
The PSoC 4100S has a pair of low-power comparators, which
can also operate in Deep Sleep modes. This allows the analog
system blocks to be disabled while retaining the ability to monitor
external voltage levels during low-power modes. The
comparator outputs are normally synchronized to avoid
metastability unless operating in an asynchronous power mode
where the system wake-up circuit is activated by a comparator
switch event. The LPC outputs can be routed to pins.
Analog Blocks
12-bit SAR ADC
The 12-bit, 1-Msps SAR ADC can operate at a maximum clock
rate of 18 MHz and requires a minimum of 18 clocks at that
frequency to do a 12-bit conversion.
The Sample-and-Hold (S/H) aperture is programmable allowing
the gain bandwidth requirements of the amplifier driving the SAR
inputs, which determine its settling time, to be relaxed if required.
It is possible to provide an external bypass (through a fixed pin
location) for the internal reference amplifier.
Current DACs
The PSoC 4100S has two IDACs, which can drive any of the pins
on the chip. These IDACs have programmable current ranges.
Analog Multiplexed Buses
The SAR is connected to a fixed set of pins through an 8-input
sequencer. The sequencer cycles through selected channels
autonomously (sequencer scan) with zero switching overhead
(that is, aggregate sampling bandwidth is equal to 1 Msps
whether it is for a single channel or distributed over several
channels). The sequencer switching is effected through a state
machine or through firmware driven switching. A feature
provided by the sequencer is buffering of each channel to reduce
CPU interrupt service requirements. To accommodate signals
with varying source impedance and frequency, it is possible to
have different sample times programmable for each channel.
Also, signal range specification through a pair of range registers
(low and high range values) is implemented with a corresponding
out-of-range interrupt if the digitized value exceeds the
programmed range; this allows fast detection of out-of-range
values without the necessity of having to wait for a sequencer
scan to be completed and the CPU to read the values and check
for out-of-range values in software.
The PSoC 4100S has two concentric independent buses that go
around the periphery of the chip. These buses (called amux
buses) are connected to firmware-programmable analog
switches that allow the chip's internal resources (IDACs,
comparator) to connect to any pin on the I/O Ports.
Programmable Digital Blocks
The Programmable I/O (Smart I/O) block is a fabric of switches
and LUTs that allows Boolean functions to be performed in
signals being routed to the pins of a GPIO port. The Smart I/O
can perform logical operations on input pins to the chip and on
signals going out as outputs.
Fixed Function Digital
Timer/Counter/PWM (TCPWM) Block
The TCPWM block consists of a 16-bit counter with
user-programmable period length. There is a capture register to
record the count value at the time of an event (which may be an
I/O event), a period register that is used to either stop or
auto-reload the counter when its count is equal to the period
register, and compare registers to generate compare value
signals that are used as PWM duty cycle outputs. The block also
provides true and complementary outputs with programmable
offset between them to allow use as dead-band programmable
complementary PWM outputs. It also has a Kill input to force
outputs to a predetermined state; for example, this is used in
motor drive systems when an over-current state is indicated and
the PWM driving the FETs needs to be shut off immediately with
no time for software intervention. There are five TCPWM blocks
in the PSoC 4100S.
The SAR is not available in Deep Sleep mode as it requires a
high-speed clock (up to 18 MHz). The SAR operating range is
1.71 V to 5.5 V.
Figure 3. SAR ADC
AHB System Bus and Programmable Logic
Interconnect
SAR Sequencer
Sequencing
and Control
Data and
Status Flags
POS
SARADC
NEG
External
Reference
Reference and
Selection
Serial Communication Block (SCB)
Bypass
(optional)
VDDA
VREF
VDDA/2
The PSoC 4100S has three serial communication blocks, which
can be programmed to have SPI, I2C, or UART functionality.
Inputs from other Ports
I2C Mode: The hardware I2C block implements a full
Two Opamps (Continuous-Time Block; CTB)
multi-master and slave interface (it is capable of multi-master
arbitration). This block is capable of operating at speeds of up to
400 kbps (Fast Mode) and has flexible buffering options to
reduce interrupt overhead and latency for the CPU. It also
The PSoC 4100S has two opamps with Comparator modes
which allow most common analog functions to be performed
on-chip eliminating external components; PGAs, Voltage
Document Number: 002-00122 Rev. *I
Page 5 of 41
PSoC® 4: PSoC 4100S
Family Datasheet
supports EZI2C that creates a mailbox address range in the
memory of the PSoC 4100S and effectively reduces I2C commu-
nication to reading from and writing to an array in memory. In
addition, the block supports an 8-deep FIFO for receive and
transmit which, by increasing the time given for the CPU to read
data, greatly reduces the need for clock stretching caused by the
CPU not having read data on time.
Data output and pin state registers store, respectively, the values
to be driven on the pins and the states of the pins themselves.
Every I/O pin can generate an interrupt if so enabled and each
I/O port has an interrupt request (IRQ) and interrupt service
routine (ISR) vector associated with it (5 for PSoC 4100S).
Special Function Peripherals
The I2C peripheral is compatible with the I2C Standard-mode and
Fast-mode devices as defined in the NXP I2C-bus specification
and user manual (UM10204). The I2C bus I/O is implemented
with GPIO in open-drain modes.
The PSoC 4100S is not completely compliant with the I2C spec
in the following respect:
CapSense
CapSense is supported in the PSoC 4100S through a CapSense
Sigma-Delta (CSD) block that can be connected to any pins
through an analog multiplex bus via analog switches. CapSense
function can thus be provided on any available pin or group of
pins in a system under software control. A PSoC Creator
component is provided for the CapSense block to make it easy
for the user.
■ GPIO cells are not overvoltage tolerant and, therefore, cannot
be hot-swapped or powered up independently of the rest of the
I2C system.
Shield voltage can be driven on another analog multiplex bus to
provide water-tolerance capability. Water tolerance is provided
by driving the shield electrode in phase with the sense electrode
to keep the shield capacitance from attenuating the sensed
input. Proximity sensing can also be implemented.
UART Mode: This is a full-feature UART operating at up to
1 Mbps. It supports automotive single-wire interface (LIN),
infrared interface (IrDA), and SmartCard (ISO7816) protocols, all
of which are minor variants of the basic UART protocol. In
addition, it supports the 9-bit multiprocessor mode that allows
addressing of peripherals connected over common RX and TX
lines. Common UART functions such as parity error, break
detect, and frame error are supported. An 8-deep FIFO allows
much greater CPU service latencies to be tolerated.
The CapSense block has two IDACs, which can be used for
general purposes if CapSense is not being used (both IDACs are
available in that case) or if CapSense is used without water
tolerance (one IDAC is available).
The CapSense block also provides a 10-bit Slope ADC function
which can be used in conjunction with the CapSense function.
SPI Mode: The SPI mode supports full Motorola SPI, TI SSP
(adds a start pulse used to synchronize SPI Codecs), and
National Microwire (half-duplex form of SPI). The SPI block can
use the FIFO.
The CapSense block is an advanced, low-noise, programmable
block with programmable voltage references and current source
ranges for improved sensitivity and flexibility. It can also use an
external reference voltage. It has a full-wave CSD mode that
alternates sensing to VDDA and ground to null out power-supply
related noise.
GPIO
The PSoC 4100S has up to 36 GPIOs. The GPIO block imple-
ments the following:
LCD Segment Drive
■ Eight drive modes:
❐ Analog input mode (input and output buffers disabled)
❐ Input only
The PSoC 4100S has an LCD controller, which can drive up to
4 commons and up to 32 segments. It uses full digital methods
to drive the LCD segments requiring no generation of internal
LCD voltages. The two methods used are referred to as Digital
Correlation and PWM. Digital Correlation pertains to modulating
the frequency and drive levels of the common and segment
signals to generate the highest RMS voltage across a segment
to light it up or to keep the RMS signal to zero. This method is
good for STN displays but may result in reduced contrast with TN
(cheaper) displays. PWM pertains to driving the panel with PWM
signals to effectively use the capacitance of the panel to provide
the integration of the modulated pulse-width to generate the
desired LCD voltage. This method results in higher power
consumption but can result in better results when driving TN
displays. LCD operation is supported during Deep Sleep
refreshing a small display buffer (4 bits; 1 32-bit register per port).
❐ Weak pull-up with strong pull-down
❐ Strong pull-up with weak pull-down
❐ Open drain with strong pull-down
❐ Open drain with strong pull-up
❐ Strong pull-up with strong pull-down
❐ Weak pull-up with weak pull-down
■ Input threshold select (CMOS or LVTTL).
■ Individual control of input and output buffer enabling/disabling
in addition to the drive strength modes
■ Selectable slew rates for dV/dt related noise control to improve
EMI
The pins are organized in logical entities called ports, which are
8-bit in width (less for Ports 2 and 3). During power-on and reset,
the blocks are forced to the disable state so as not to crowbar
any inputs and/or cause excess turn-on current. A multiplexing
network known as a high-speed I/O matrix is used to multiplex
between various signals that may connect to an I/O pin.
Document Number: 002-00122 Rev. *I
Page 6 of 41
PSoC® 4: PSoC 4100S
Family Datasheet
Pinouts
The following table provides the pin list for PSoC 4100S for the 48-pin TQFP, 44-pin TQFP, 40-pin QFN, 32-pin QFN, and 35-ball CSP
packages. All port pins support GPIO.
Table 1. Pin List
48-TQFP
44-TQFP
Pin
40-QFN
Name
32-QFN
Name
35-CSP
Name
Pin
Name
P0.0
Name
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
XRES
VCCD
Pin
22
23
24
25
26
27
28
29
30
31
DN
32
33
34
35
36
37
38
39
Pin
17
18
19
20
21
22
23
Pin
C3
A5
A4
A3
B3
A6
B4
B5
B6
A7
B7
C7
C7
B7
C4
C5
C6
D7
D4
D5
D6
E7
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
1
24
25
26
27
28
29
30
31
32
33
P0.0
P0.1
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.0
P0.1
P0.1
P0.2
P0.2
P0.2
P0.3
P0.3
P0.3
P0.4
P0.4
P0.4
P0.5
P0.5
P0.5
P0.6
P0.6
P0.6
P0.7
P0.7
P0.7
XRES
VCCD
VSSD
VDDD
VDDA
VSSA
P1.0
XRES
VCCD
VSSD
VDDD
VDDA
VSSA
P1.0
24
25
26
XRES
VCCD
VSSD
XRES
VCCD
VSS
34
35
36
37
38
39
40
41
42
43
44
1
VDDD
VDDA
VSSA
P1.0
VDD
VDD
VSS
27
28
29
30
31
32
VDD
VSSA
P1.0
P1.1
P1.2
P1.3
P1.0
P1.1
P1.1
P1.1
P1.1
P1.2
P1.2
P1.2
P1.2
P1.3
P1.3
P1.3
P1.3
P1.4
P1.4
P1.4
P1.4
P1.5
P1.5
P1.5
P1.6
P1.6
P1.6
P1.7/VREF
P1.7/VREF
VSSD
P2.0
40
P1.7/VREF
1
P1.7/VREF
P1.7/VREF
2
3
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
VSSD
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
2
1
2
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
VSSD
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
2
3
4
5
P2.0
P2.1
P2.2
P2.3
3
P2.1
4
4
P2.2
3
D3
E4
E5
E6
E3
E2
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
5
5
P2.3
4
6
6
P2.4
5
7
7
P2.5
6
6
7
8
P2.5
P2.6
P2.7
8
8
P2.6
7
9
9
P2.7
8
10
12
13
14
16
17
18
10
11
12
13
14
15
16
VSSD
P3.0
9
10
11
12
13
14
15
9
P3.0
P3.1
P3.2
P3.3
E1
D2
D1
C1
C2
P3.0
P3.1
P3.2
P3.3
P3.4
P3.1
10
11
12
P3.2
P3.3
P3.4
P3.5
Document Number: 002-00122 Rev. *I
Page 7 of 41
PSoC® 4: PSoC 4100S
Family Datasheet
Table 1. Pin List (continued)
48-TQFP
44-TQFP
Pin
40-QFN
Name
32-QFN
Name
35-CSP
Pin
19
20
21
22
23
24
25
Name
P3.6
P3.7
VDDD
P4.0
P4.1
P4.2
P4.3
Name
P3.6
P3.7
VDDD
P4.0
P4.1
P4.2
P4.3
Pin
16
Pin
Pin
Name
17
18
19
20
21
22
23
P3.6
P3.7
17
18
19
20
21
P4.0
P4.1
P4.2
P4.3
13
14
15
16
P4.0
P4.1
P4.2
P4.3
B1
B2
A2
A1
P4.0
P4.1
P4.2
P4.3
Notes: Pins 11, 15, 26, and 27 are No Connects (NC) on the 48-pin TQFP.
Descriptions of the Power pins are as follows:
VDDD: Power supply for the digital section.
VDDA: Power supply for the analog section.
VSSD, VSSA: Ground pins for the digital and analog sections respectively.
VCCD: Regulated digital supply (1.8 V ±5%)
VDD: Power supply to all sections of the chip
VSS: Ground for all sections of the chip
Document Number: 002-00122 Rev. *I
Page 8 of 41
PSoC® 4: PSoC 4100S Family
Datasheet
Alternate Pin Functions
Each Port pin has can be assigned to one of multiple functions; it can, for instance, be an analog I/O, a digital peripheral function, an LCD pin, or a CapSense pin. The pin
assignments are shown in the following table.
Port/Pin
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
P1.0
Analog
Smart I/O
Alternate Function 1 Alternate Function 2 Alternate Function 3
Deep Sleep 1
scb[2].i2c_scl:0
scb[2].i2c_sda:0
Deep Sleep 2
scb[0].spi_select1:0
scb[0].spi_select2:0
scb[0].spi_select3:0
scb[2].spi_select0
scb[1].spi_mosi:1
scb[1].spi_miso:1
scb[1].spi_clk:1
lpcomp.in_p[0]
lpcomp.in_n[0]
lpcomp.in_p[1]
lpcomp.in_n[1]
wco.wco_in
tcpwm.tr_in[0]
tcpwm.tr_in[1]
scb[1].uart_rx:0
scb[1].uart_tx:0
scb[1].uart_cts:0
scb[1].uart_rts:0
scb[0].uart_rx:1
scb[2].uart_rx:0
scb[2].uart_tx:0
scb[2].uart_tx:1
scb[1].i2c_scl:0
scb[1].i2c_sda:0
wco.wco_out
srss.ext_clk
tcpwm.line[0]:2
tcpwm.line[2]:1
scb[1].spi_select0:1
scb[0].spi_mosi:1
ctb0_oa0+
ctb0_oa0-
scb[0].i2c_scl:0
scb[0].i2c_sda:0
P1.1
tcpwm.line_compl[2]:1
scb[0].uart_tx:1
scb[0].spi_miso:1
P1.2
P1.3
P1.4
ctb0_oa0_out
ctb0_oa1_out
ctb0_oa1-
tcpwm.line[3]:1
scb[0].uart_cts:1
scb[0].uart_rts:1
tcpwm.tr_in[2]
tcpwm.tr_in[3]
scb[2].i2c_scl:1
scb[2].i2c_sda:1
scb[0].spi_clk:1
scb[0].spi_select0:1
scb[0].spi_select1:1
tcpwm.line_compl[3]:1
P1.5
P1.6
P1.7
ctb0_oa1+
ctb0_oa0+
scb[0].spi_select2:1
scb[0].spi_select3:1
scb[2].spi_clk
ctb0_oa1+
sar_ext_vref0
sar_ext_vref1
P2.0
sarmux[0]
prgio[0].io[0]
tcpwm.line[4]:0
csd.comp
tcpwm.tr_in[4]
tcpwm.tr_in[5]
scb[1].i2c_scl:1
scb[1].i2c_sda:1
scb[1].spi_mosi:2
P2.1
P2.2
P2.3
sarmux[1]
sarmux[2]
sarmux[3]
prgio[0].io[1] tcpwm.line_compl[4]:0
prgio[0].io[2]
scb[1].spi_miso:2
scb[1].spi_clk:2
prgio[0].io[3]
scb[1].spi_select0:2
Document Number: 002-00122 Rev. *I
Page 9 of 41
PSoC® 4: PSoC 4100S Family
Datasheet
Port/Pin
P2.4
Analog
Smart I/O
Alternate Function 1 Alternate Function 2 Alternate Function 3
Deep Sleep 1
Deep Sleep 2
scb[1].spi_select1:1
scb[1].spi_select2:1
scb[1].spi_select3:1
scb[2].spi_mosi
sarmux[4]
sarmux[5]
sarmux[6]
sarmux[7]
prgio[0].io[4]
tcpwm.line[0]:1
P2.5
prgio[0].io[5] tcpwm.line_compl[0]:1
prgio[0].io[6] tcpwm.line[1]:1
prgio[0].io[7] tcpwm.line_compl[1]:1
prgio[1].io[0] tcpwm.line[0]:0
prgio[1].io[1] tcpwm.line_compl[0]:0
P2.6
P2.7
lpcomp.comp[0]:1
scb[1].i2c_scl:2
scb[1].i2c_sda:2
P3.0
scb[1].uart_rx:1
scb[1].uart_tx:1
scb[1].spi_mosi:0
scb[1].spi_miso:0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
P4.0
P4.1
P4.2
prgio[1].io[2]
prgio[1].io[3] tcpwm.line_compl[1]:0
prgio[1].io[4] tcpwm.line[2]:0
prgio[1].io[5] tcpwm.line_compl[2]:0
prgio[1].io[6] tcpwm.line[3]:0
prgio[1].io[7] tcpwm.line_compl[3]:0
tcpwm.line[1]:0
scb[1].uart_cts:1
scb[1].uart_rts:1
cpuss.swd_data
cpuss.swd_clk
scb[1].spi_clk:0
scb[1].spi_select0:0
scb[1].spi_select1:0
scb[1].spi_select2:0
scb[1].spi_select3:0
scb[2].spi_miso
tcpwm.tr_in[6]
lpcomp.comp[1]:1
scb[0].i2c_scl:1
scb[0].i2c_sda:1
lpcomp.comp[0]:0
csd.vref_ext
csd.cshieldpads
csd.cmodpad
scb[0].uart_rx:0
scb[0].uart_tx:0
scb[0].uart_cts:0
scb[0].spi_mosi:0
scb[0].spi_miso:0
scb[0].spi_clk:0
P4.3
csd.csh_tank
scb[0].uart_rts:0
lpcomp.comp[1]:0
scb[0].spi_select0:0
Document Number: 002-00122 Rev. *I
Page 10 of 41
PSoC® 4: PSoC 4100S
Family Datasheet
Mode 1: 1.8 V to 5.5 V External Supply
Power
In this mode, the PSoC 4100S is powered by an external power
supply that can be anywhere in the range of 1.8 to 5.5 V. This
range is also designed for battery-powered operation. For
example, the chip can be powered from a battery system that
starts at 3.5 V and works down to 1.8 V. In this mode, the internal
regulator of the PSoC 4100S supplies the internal logic and its
output is connected to the VCCD pin. The VCCD pin must be
bypassed to ground via an external capacitor (0.1 µF; X5R
ceramic or better) and must not be connected to anything else.
The following power system diagram shows the set of power
supply pins as implemented for the PSoC 4100S. The system
has one regulator in Active mode for the digital circuitry. There is
no analog regulator; the analog circuits run directly from the VDD
input.
Figure 4. Power Supply Connections
VDDA
VDDD
VDDA
VSSA
Mode 2: 1.8 V ±5% External Supply
VDDD
VSSD
Analog
Domain
Digital
Domain
In this mode, the PSoC 4100S is powered by an external power
supply that must be within the range of 1.71 to 1.89 V; note that
this range needs to include the power supply ripple too. In this
mode, the VDD and VCCD pins are shorted together and
bypassed. The internal regulator can be disabled in the firmware.
Bypass capacitors must be used from VDDD to ground. The
typical practice for systems in this frequency range is to use a
capacitor in the 1-µF range, in parallel with a smaller capacitor
(0.1 µF, for example). Note that these are simply rules of thumb
and that, for critical applications, the PCB layout, lead induc-
tance, and the bypass capacitor parasitic should be simulated to
design and obtain optimal bypassing.
VCCD
1.8 Volt
Regulator
An example of a bypass scheme is shown in the following
diagram.
There are two distinct modes of operation. In Mode 1, the supply
voltage range is 1.8 V to 5.5 V (unregulated externally; internal
regulator operational). In Mode 2, the supply range is1.8 V ±5%
(externally regulated; 1.71 to 1.89, internal regulator bypassed).
Figure 5. External Supply Range from 1.8 V to 5.5 V with Internal Regulator Active
Power supply bypass connections example
1.8V to 5.5V
1.8V to 5.5V
PSoC 4100S
VDDA
VDD
F
0.1F
0.1F
VCCD
0.1F
VSS
Document Number: 002-00122 Rev. *I
Page 11 of 41
PSoC® 4: PSoC 4100S
Family Datasheet
Development Support
The PSoC 4100S family has a rich set of documentation,
development tools, and online resources to assist you during
your development process. Visit www.cypress.com/go/psoc4 to
find out more.
Technical Reference Manual: TheTechnical ReferenceManual
(TRM) contains all the technical detail you need to use a PSoC
device, including a complete description of all PSoC registers.
The TRM is available in the Documentation section at
www.cypress.com/psoc4.
Documentation
Online
A suite of documentation supports the PSoC 4100S family to
ensure that you can find answers to your questions quickly. This
section contains a list of some of the key documents.
In addition to print documentation, the Cypress PSoC forums
connect you with fellow PSoC users and experts in PSoC from
around the world, 24 hours a day, 7 days a week.
Software User Guide: A step-by-step guide for using PSoC
Creator. The software user guide shows you how the PSoC
Creator build process works in detail, how to use source control
with PSoC Creator, and much more.
Tools
With industry standard cores, programming, and debugging
interfaces, the PSoC 4100S family is part of a development tool
ecosystem. Visit us at www.cypress.com/go/psoccreator for the
latest information on the revolutionary, easy to use PSoC Creator
IDE, supported third party compilers, programmers, debuggers,
and development kits.
Component Datasheets: The flexibility of PSoC allows the
creation of new peripherals (components) long after the device
has gone into production. Component data sheets provide all of
the information needed to select and use a particular component,
including a functional description, API documentation, example
code, and AC/DC specifications.
Application Notes: PSoC application notes discuss a particular
application of PSoC in depth; examples include brushless DC
motor control and on-chip filtering. Application notes often
include example projects in addition to the application note
document.
Document Number: 002-00122 Rev. *I
Page 12 of 41
PSoC® 4: PSoC 4100S
Family Datasheet
Electrical Specifications
Absolute Maximum Ratings
Table 2. Absolute Maximum Ratings[1]
Details/
Spec ID#
SID1
Parameter
Description
Min
Typ
Max
Units
Conditions
VDDD_ABS
VCCD_ABS
Digital supply relative to VSS
–0.5
–0.5
–
–
6
–
Direct digital core voltage input relative
to VSS
SID2
1.95
V
–
SID3
SID4
VGPIO_ABS
IGPIO_ABS
GPIO voltage
–0.5
–25
–
–
VDD+0.5
25
–
–
Maximum current per GPIO
mA
GPIO injection current, Max for VIH
VDDD, and Min for VIL < VSS
>
Current injected
per pin
SID5
IGPIO_injection
ESD_HBM
–0.5
–
–
0.5
–
Electrostatic discharge human body
model
BID44
2200
–
V
Electrostatic discharge charged device
model
BID45
BID46
ESD_CDM
LU
500
–
–
–
–
–
Pin current for latch-up
–140
140
mA
Device Level Specifications
All specifications are valid for –40 °C TA 85 °C and TJ 100 °C, except where noted. Specifications are valid for 1.71 V to 5.5 V,
except where noted.
Table 3. DC Specifications
Typical values measured at VDD = 3.3 V and 25 °C.
Details/
Spec ID#
SID53
Parameter
VDD
Description
Min
Typ
Max
Units
Conditions
Internally
regulated supply
Power supply input voltage
1.8
–
5.5
Internally
unregulated
supply
Power supply input voltage (VCCD
=
V
SID255
VDD
1.71
–
1.89
VDDD = VDDA
)
SID54
SID55
VCCD
CEFC
Output voltage (for core logic)
–
–
1.8
0.1
–
–
–
X5R ceramic or
better
External regulator voltage bypass
µF
X5R ceramic or
better
SID56
CEXC
Power supply bypass capacitor
–
1
–
Active Mode, VDD = 1.8 V to 5.5 V. Typical values measured at VDD = 3.3 V and 25 °C.
Max is at 85 °C
and 5.5 V
SID10
SID16
SID19
IDD5
IDD8
IDD11
Execute from flash; CPU at 6 MHz
Execute from flash; CPU at 24 MHz
Execute from flash; CPU at 48 MHz
–
–
–
1.8
3.0
5.4
2.7
Max is at 85 °C
and 5.5 V
4.75
6.85
mA
Max is at 85 °C
and 5.5 V
Note
1. Usage above the absolute maximum conditions listed in Table 2 may cause permanent damage to the device. Exposure to Absolute Maximum conditions for extended
periods of time may affect device reliability. The Maximum Storage Temperature is 150 °C in compliance with JEDEC Standard JESD22-A103, High Temperature
Storage Life. When used below Absolute Maximum conditions but above normal operating conditions, the device may not operate to specification.
Document Number: 002-00122 Rev. *I
Page 13 of 41
PSoC® 4: PSoC 4100S
Family Datasheet
Table 3. DC Specifications (continued)
Typical values measured at VDD = 3.3 V and 25 °C.
Details/
Conditions
Spec ID#
Parameter
Description
Min
Typ
Max
Units
Sleep Mode, VDDD = 1.8 V to 5.5 V (Regulator on)
SID22
SID25
IDD17
IDD20
I2C wakeup WDT, and Comparators on
I2C wakeup, WDT, and Comparators on.
–
–
1.7
2.2
2.2
2.5
mA 6 MHZ. Max is at
85 °C and 5.5 V.
12 MHZ. Max is at
85 °C and 5.5 V.
Sleep Mode, VDDD = 1.71 V to 1.89 V (Regulator bypassed)
SID28
IDD23
I2C wakeup, WDT, and Comparators on
–
–
0.7
1
0.9
1.2
mA 6 MHZ. Max is at
85 °C and 5.5 V.
SID28A
IDD23A
I2C wakeup, WDT, and Comparators on
mA 12 MHZ. Max is at
85 °C and 5.5 V.
Deep Sleep Mode, VDD = 1.8 V to 3.6 V (Regulator on)
SID31 IDD26
I2C wakeup and WDT on
–
–
2.5
2.5
60
60
µA
µA
Max is at 3.6 V
and 85 °C.
Deep Sleep Mode, VDD = 3.6 V to 5.5 V (Regulator on)
I2C wakeup and WDT on
Max is at 5.5 V
and 85 °C.
SID34
IDD29
Deep Sleep Mode, VDD = VCCD = 1.71 V to 1.89 V (Regulator bypassed)
Max is at 1.89 V
and 85 °C.
SID37
IDD32
I2C wakeup and WDT on
–
–
2.5
2
65
5
µA
XRES Current
SID307
IDD_XR
Supply current while XRES asserted
mA
–
Table 4. AC Specifications
Spec ID# Parameter
SID48 FCPU
Details/
Description
Min
Typ
Max
Units
Conditions
CPU frequency
DC
–
–
0
48
–
MHz 1.71 VDD 5.5
SID49[3]
SID50[3]
TSLEEP
Wakeup from Sleep mode
Wakeup from Deep Sleep mode
µs
TDEEPSLEEP
–
35
–
Note
2. Guaranteed by characterization.
Document Number: 002-00122 Rev. *I
Page 14 of 41
PSoC® 4: PSoC 4100S
Family Datasheet
GPIO
Table 5. GPIO DC Specifications
Details/
Spec ID#
SID57
Parameter
Description
Min
Typ
–
Max
Units
Conditions
[3]
VIH
Input voltage high threshold
Input voltage low threshold
LVTTL input, VDDD < 2.7 V
LVTTL input, VDDD < 2.7 V
0.7 VDDD
–
CMOS Input
0.3
SID58
VIL
VIH
VIL
–
–
CMOS Input
VDDD
[3]
[3]
SID241
SID242
0.7 VDDD
–
–
–
–
0.3
–
–
VDDD
SID243
SID244
SID59
VIH
VIL
LVTTL input, VDDD 2.7 V
LVTTL input, VDDD 2.7 V
Output voltage high level
2.0
–
–
–
–
–
0.8
–
–
V
–
VOH
VDDD –0.6
IOH = 4 mA at 3 V VDDD
IOH = 1 mA at 1.8 V
VDDD
SID60
SID61
VOH
Output voltage high level
Output voltage low level
VDDD –0.5
–
–
–
–
IOL = 4 mA at 1.8 V
VDDD
VOL
0.6
SID62
SID62A
SID63
SID64
VOL
Output voltage low level
Output voltage low level
Pull-up resistor
–
–
0.6
0.4
8.5
8.5
IOL = 10 mA at 3 V VDDD
VOL
–
–
IOL = 3 mA at 3 V VDDD
RPULLUP
RPULLDOWN
3.5
3.5
5.6
5.6
–
–
kΩ
Pull-down resistor
Input leakage current (absolute
value)
SID65
IIL
–
–
2
nA 25 °C, VDDD = 3.0 V
SID66
CIN
Input capacitance
–
25
–
40
–
7
–
–
–
pF
–
SID67[4]
SID68[4]
SID68A[4]
VHYSTTL
VHYSCMOS
Input hysteresis LVTTL
Input hysteresis CMOS
VDDD 2.7 V
0.05 × VDDD
200
mV VDD < 4.5 V
VDD > 4.5 V
VHYSCMOS5V5 Input hysteresis CMOS
–
Currentthroughprotectiondiodeto
VDD/VSS
SID69[4]
IDIODE
–
–
–
–
100
200
µA
–
Maximum total source or sink chip
current
SID69A[4]
ITOT_GPIO
mA
–
Table 6. GPIO AC Specifications
(Guaranteed by Characterization)
Details/
Spec ID#
SID70
Parameter
TRISEF
Description
Min
Typ
Max
Units
Conditions
3.3 V VDDD, Cload =
25 pF
Rise time in fast strong mode
2
–
–
–
12
12
60
ns
3.3 V VDDD, Cload =
25 pF
SID71
SID72
TFALLF
TRISES
Fall time in fast strong mode
Rise time in slow strong mode
2
3.3 V VDDD, Cload =
25 pF
10
–
Notes
3.
V
must not exceed V
+ 0.2 V.
IH
DDD
4. Guaranteed by characterization.
Document Number: 002-00122 Rev. *I
Page 15 of 41
PSoC® 4: PSoC 4100S
Family Datasheet
Table 6. GPIO AC Specifications
(Guaranteed by Characterization) (continued)
Details/
Spec ID#
SID73
Parameter
TFALLS
Description
Min
Typ
Max
Units
Conditions
3.3 V VDDD, Cload =
25 pF
Fall time in slow strong mode
10
–
60
–
GPIO FOUT; 3.3 V VDDD 5.5 V
90/10%, 25 pF load,
60/40 duty cycle
SID74
SID75
SID76
SID245
SID246
XRES
FGPIOUT1
FGPIOUT2
FGPIOUT3
FGPIOUT4
FGPIOIN
–
–
–
–
–
–
–
–
–
–
33
16.7
7
Fast strong mode
GPIO FOUT; 1.71 VVDDD3.3 V
Fast strong mode
90/10%, 25 pF load,
60/40 duty cycle
GPIO FOUT; 3.3 V VDDD 5.5 V
Slow strong mode
90/10%, 25 pF load,
60/40 duty cycle
MHz
GPIO FOUT; 1.71 V VDDD 3.3 V
Slow strong mode.
90/10%, 25 pF load,
60/40 duty cycle
3.5
48
GPIO input operating frequency;
1.71 V VDDD 5.5 V
90/10% VIO
Table 7. XRES DC Specifications
Details/
Spec ID#
SID77
Parameter
VIH
Description
Input voltage high threshold
Input voltage low threshold
Pull-up resistor
Min
Typ
Max
Units
Conditions
0.7 × VDDD
–
–
–
V
CMOS Input
SID78
VIL
–
–
–
0.3 VDDD
SID79
RPULLUP
CIN
60
–
–
7
kΩ
–
–
SID80
Input capacitance
pF
Typical hysteresis is
200 mV for VDD > 4.5 V
SID81[5]
VHYSXRES
IDIODE
Input voltage hysteresis
–
–
100
–
–
mV
µA
Current through protection diode
to VDD/VSS
SID82
100
Table 8. XRES AC Specifications
Details/
Conditions
Spec ID#
Parameter
Description
Min
Typ
Max
Units
SID83[5]
BID194[5]
TRESETWIDTH Reset pulse width
TRESETWAKE Wake-up time from reset release
1
–
–
–
–
µs
–
–
2.7
ms
Note
5. Guaranteed by characterization.
Document Number: 002-00122 Rev. *I
Page 16 of 41
PSoC® 4: PSoC 4100S
Family Datasheet
Analog Peripherals
Table 9. CTBm Opamp Specifications
Details/
Units
Spec ID#
Parameter
IDD
Description
Min
Typ
Max
Conditions
Opamp block current, External
load
SID269
IDD_HI
power=hi
–
1100
1850
–
µA
SID270
SID271
IDD_MED
IDD_LOW
power=med
–
–
550
150
950
350
–
power=lo
–
Load = 20 pF, 0.1 mA
GBW
VDDA = 2.7 V
Input and output are
0.2 V to VDDA-0.2 V
SID272
SID273
SID274
GBW_HI
GBW_MED
power=hi
6
3
–
–
–
1
–
–
–
Input and output are
MHz
power=med
0.2 V to VDDA-0.2 V
Input and output are
0.2 V to VDDA-0.2 V
GBW_LO
power=lo
IOUT_MAX
IOUT_MAX_HI
VDDA = 2.7 V, 500 mV from rail
power=hi
Output is 0.5 V
VDDA-0.5 V
SID275
SID276
SID277
10
10
–
–
–
5
–
–
–
Output is 0.5 V
mA
IOUT_MAX_MID
power=mid
VDDA-0.5 V
Output is 0.5 V
IOUT_MAX_LO
IOUT
power=lo
VDDA-0.5 V
VDDA = 1.71 V, 500 mV from rail
power=hi
Output is 0.5 V
VDDA-0.5 V
SID278
SID279
SID280
IOUT_MAX_HI
4
4
–
–
–
–
–
–
Output is 0.5 V
VDDA-0.5 V
power=mid
power=lo
IOUT_MAX_MID
IOUT_MAX_LO
IDD_Int
mA
Output is 0.5 V
2
VDDA-0.5 V
Opamp block current Internal
Load
–
–
–
–
8
–
IDD_HI_Int
IDD_MED_Int
IDD_LOW_Int
GBW
SID269_I
SID270_I
power=hi
1500
700
–
1700
900
–
–
–
–
power=med
power=lo
µA
SID271_I
SID272_I
–
–
VDDA = 2.7 V
Output is 0.25 V to
DDA-0.25 V
–
–
GBW_HI_Int
power=hi
MHz
V
Document Number: 002-00122 Rev. *I
Page 17 of 41
PSoC® 4: PSoC 4100S
Family Datasheet
Table 9. CTBm Opamp Specifications (continued)
Details/
Units
Spec ID#
Parameter
Description
Min
Typ
Max
Conditions
General opamp specs for both
internal and external modes
–
–
–
–
VIN
Charge-pump on, VDDA = 2.7 V
VDDA-0.2
VDDA-0.2
SID281
SID282
–0.05
–0.05
V
VCM
Charge-pump on, VDDA = 2.7 V
VDDA = 2.7 V
VOUT
–
–
–
–
VOUT_1
V
V
V
DDA -0.5
DDA -0.2
DDA -0.2
SID283
SID284
power=hi, Iload=10 mA
power=hi, Iload=1 mA
0.5
0.2
VOUT_2
V
–
–
–
–
VOUT_3
VOUT_4
SID285
SID286
power=med, Iload=1 mA
power=lo, Iload=0.1 mA
0.2
0.2
VDDA -0.2
1.0
High mode, input 0 V
to VDDA-0.2 V
VOS_TR
VOS_TR
VOS_TR
SID288
Offset voltage, trimmed
Offset voltage, trimmed
Offset voltage, trimmed
–1.0
–
0.5
1
Medium mode, input
0 V to VDDA-0.2 V
–
–
SID288A
SID288B
mV
Low mode, input 0 V
to VDDA-0.2 V
–
2
VOS_DR_TR
VOS_DR_TR
VOS_DR_TR
SID290
Offset voltage drift, trimmed
Offset voltage drift, trimmed
Offset voltage drift, trimmed
–10
–
10
–
µV/C
µV/C
High mode
Medium mode
Low mode
3
SID290A
SID290B
10
10
–
–
Input is 0 V to
VDDA-0.2 V, Output is
–
–
SID291
SID292
CMRR
PSRR
DC
70
70
80
85
0.2 V to VDDA-0.2 V
dB
VDDD = 3.6 V,
high-power mode,
input is 0.2 V to
VDDA-0.2 V
At 1 kHz, 10-mV ripple
Noise
VN2
–
–
–
–
6
–
–
–
SID294
SID295
SID296
SID297
SID298
Input-referred, 1 kHz, power=Hi
72
28
15
–
3
Input and output are
at 0.2 V to VDDA-0.2 V
Input-referred, 10 kHz,
power=Hi
VN3
nV/rtHz
Input and output are
at 0.2 V to VDDA-0.2 V
Input-referred, 100 kHz,
power=Hi
VN4
Stable up to max. load.
Performance specs at 50 pF.
–
–
CLOAD
125
–
pF
Cload = 50 pF, Power = High,
–
SLEW_RATE
V/µs
VDDA = 2.7 V
Document Number: 002-00122 Rev. *I
Page 18 of 41
PSoC® 4: PSoC 4100S
Family Datasheet
Table 9. CTBm Opamp Specifications (continued)
Details/
Units
Spec ID#
SID299
Parameter
T_OP_WAKE
OL_GAIN
COMP_MODE
TPD1
Description
Min
Typ
Max
25
–
Conditions
From disable to enable, no
external RC dominating
–
–
–
µs
–
SID299A
Open Loop Gain
90
dB
Comparator mode; 50 mV drive,
rise=Tfall (approx.)
T
Input is 0.2 V to
VDDA-0.2 V
–
–
–
–
–
–
–
SID300
SID301
SID302
SID303
SID304
Response time; power=hi
Response time; power=med
Response time; power=lo
Hysteresis
150
500
2500
10
Input is 0.2 V to
VDDA-0.2 V
TPD2
ns
Input is 0.2 V to
–
TPD3
VDDA-0.2 V
–
–
VHYST_OP
WUP_CTB
mV
µs
Wake-up time from Enabled to
Usable
–
–
25
Deep Sleep
Mode
Mode 2 is lowest current range.
Mode 1 has higher GBW.
–
–
–
–
–
–
–
–
–
–
–
–
IDD_HI_M1
SID_DS_1
SID_DS_2
SID_DS_3
SID_DS_4
SID_DS_5
SID_DS_6
Mode 1, High current
Mode 1, Medium current
Mode 1, Low current
Mode 2, High current
Mode 2, Medium current
Mode 2, Low current
1400
700
200
120
60
25 °C
25 °C
25 °C
25 °C
25 °C
25 °C
IDD_MED_M1
IDD_LOW_M1
IDD_HI_M2
µA
IDD_MED_M2
IDD_LOW_M2
15
Document Number: 002-00122 Rev. *I
Page 19 of 41
PSoC® 4: PSoC 4100S
Family Datasheet
Table 9. CTBm Opamp Specifications (continued)
Details/
Units
Spec ID#
Parameter
Description
Min
Typ
Max
Conditions
20-pF load, no DC
load 0.2 V to
–
–
GBW_HI_M1
SID_DS_7
Mode 1, High current
4
VDDA-0.2 V
20-pF load, no DC
load 0.2 V to
–
–
–
–
–
–
–
–
–
–
GBW_MED_M1
GBW_LOW_M!
GBW_HI_M2
SID_DS_8
SID_DS_9
SID_DS_10
SID_DS_11
SID_DS_12
Mode 1, Medium current
Mode 1, Low current
Mode 2, High current
Mode 2, Medium current
Mode 2, Low current
2
VDDA-0.2 V
20-pF load, no DC
load 0.2 V to
0.5
0.5
0.2
0.1
VDDA-0.2 V
MHz
20-pF load, no DC
load 0.2 V to
VDDA-0.2 V
20-pF load, no DC
load 0.2 V to
GBW_MED_M2
VDDA-0.2 V
20-pF load, no DC
load 0.2 V to
GBW_Low_M2
VDDA-0.2 V
With trim 25 °C, 0.2 V
to VDDA-0.2 V
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
VOS_HI_M1
SID_DS_13
SID_DS_14
SID_DS_15
SID_DS_16
SID_DS_17
SID_DS_18
SID_DS_19
SID_DS_20
SID_DS_21
SID_DS_22
SID_DS_23
SID_DS_24
Mode 1, High current
Mode 1, Medium current
Mode 1, Low current
Mode 2, High current
Mode 2, Medium current
Mode 2, Low current
Mode 1, High current
Mode 1, Medium current
Mode 1, Low current
Mode 2, High current
Mode 2, Medium current
Mode 2, Low current
5
5
With trim 25 °C, 0.2 V
to VDDA-0.2 V
VOS_MED_M1
VOS_LOW_M2
VOS_HI_M2
With trim 25 °C, 0.2 V
to VDDA-0.2 V
5
mV
With trim 25 °C, 0.2V
to VDDA-0.2 V
5
With trim 25 °C, 0.2 V
to VDDA-0.2 V
VOS_MED_M2
VOS_LOW_M2
IOUT_HI_M!
5
With trim 25 °C, 0.2 V
to VDDA-0.2 V
5
Output is 0.5 V to
10
10
4
VDDA-0.5 V
Output is 0.5 V to
IOUT_MED_M1
IOUT_LOW_M1
IOUT_HI_M2
VDDA-0.5 V
Output is 0.5 V to
VDDA-0.5 V
mA
1
IOU_MED_M2
IOU_LOW_M2
1
0.5
Note
6. Guaranteed by characterization.
Document Number: 002-00122 Rev. *I
Page 20 of 41
PSoC® 4: PSoC 4100S
Family Datasheet
Table 10. Comparator DC Specifications
Details/
Conditions
Spec ID#
Parameter
Description
Min Typ
Max
Units
SID84
SID85
SID86
SID87
SID247
VOFFSET1
VOFFSET2
VHYST
Input offset voltage, Factory trim
–
–
–
0
0
–
–
±10
±4
Input offset voltage, Custom trim
mV
Hysteresis when enabled
10
–
35
VICM1
Input common mode voltage in normal mode
Input common mode voltage in low power mode
VDDD-0.1
VDDD
Modes 1 and 2
VICM2
–
V
Input common mode voltage in ultra low power
mode
VDDD ≥ 2.2 V at
SID247A
VICM3
0
–
VDDD-1.15
–40 °C
SID88
CMRR
CMRR
ICMP1
ICMP2
Common mode rejection ratio
Common mode rejection ratio
Block current, normal mode
Block current, low power mode
50
42
–
–
–
–
–
–
VDDD ≥ 2.7V
VDDD ≤ 2.7V
dB
SID88A
SID89
–
400
100
SID248
–
µA
VDDD ≥ 2.2 V at
SID259
SID90
ICMP3
ZCMP
Block current in ultra low-power mode
DC Input impedance of comparator
–
–
–
6
–
–40 °C
35
MΩ
Table 11. Comparator AC Specifications
Spec ID# Parameter
Details/
Conditions
Description
Min
–
Typ
38
Max
110
200
Units
ns
SID91
TRESP1
TRESP2
Response time, normal mode, 50 mV overdrive
Response time, low power mode, 50 mV
overdrive
SID258
–
70
Response time, ultra-low power mode, 200 mV
overdrive
VDDD ≥ 2.2 V at
SID92
TRESP3
–
2.3
15
µs
–40 °C
Table 12. Temperature Sensor Specifications
Details /
Conditions
Spec ID# Parameter
Description
Min
Typ
Max
Units
SID93
TSENSACC Temperature sensor accuracy
–5
±1
5
°C
–40 to +85 °C
Table 13. SAR Specifications
Details/
Conditions
Spec ID# Parameter
Description
Min Typ
Max
Units
SAR ADC DC Specifications
SID94
SID95
SID96
A_RES
Resolution
–
–
–
–
–
–
12
16
4
bits
A_CHNLS_S Number of channels - single ended
A-CHNKS_D Number of channels - differential
Diff inputs use
neighboring I/O
SID97
SID98
A-MONO
Monotonicity
–
–
–
–
–
Yes.
A_GAINERR Gain error
±0.1
%
With external
reference.
Document Number: 002-00122 Rev. *I
Page 21 of 41
PSoC® 4: PSoC 4100S
Family Datasheet
Table 13. SAR Specifications (continued)
Details/
Spec ID# Parameter
Description
Input offset voltage
Min Typ
Max
Units
Conditions
SID99
A_OFFSET
–
–
2
mV
Measured with
1-V reference
SID100
SID101
SID102
SID103
SID104
SID260
A_ISAR
Current consumption
–
VSS
VSS
–
–
–
–
–
–
–
1
mA
V
A_VINS
Input voltage range - single ended
Input voltage range - differential[
Input resistance
VDDA
VDDA
2.2
A_VIND
V
A_INRES
A_INCAP
VREFSAR
KΩ
pF
V
Input capacitance
–
10
Trimmed internal reference to SAR
–
TBD
SAR ADC AC Specifications
SID106
SID107
SID108
SID109
SID110
SID111
A_PSRR
A_CMRR
A_SAMP
A_SNR
A_BW
Power supply rejection ratio
Common mode rejection ratio
Sample rate
70
66
–
–
–
–
–
–
–
–
–
dB
dB
–
Measured at 1 V
1
Msps
dB
Signal-to-noise and distortion ratio (SINAD)
Input bandwidth without aliasing
65
–
–
FIN = 10 kHz
A_samp/2
kHz
A_INL
Integral non linearity. VDD = 1.71 to 5.5, 1 Msps –1.7
Integral non linearity. VDDD = 1.71 to 3.6, 1 Msps –1.5
2
LSB VREF = 1 to VDD
SID111A A_INL
1.7
LSB VREF = 1.71 to
VDD
SID111B A_INL
Integral non linearity. VDD = 1.71 to 5.5, 500 ksps –1.5
–
–
1.7
2.2
LSB VREF = 1 to VDD
LSB VREF = 1 to VDD
SID112
A_DNL
Differential non linearity. VDD = 1.71 to 5.5,
1 Msps
–1
–1
–1
SID112A A_DNL
SID112B A_DNL
Differential non linearity. VDD = 1.71 to 3.6,
1 Msps
2
LSB VREF = 1.71 to
VDD
–
Differential non linearity. VDD = 1.71 to 5.5,
500 ksps
2.2
LSB VREF = 1 to VDD
–
–
–
SID113
SID261
A_THD
Total harmonic distortion
–
–
–65
100
dB
Fin = 10 kHz
FSARINTRE SAR operating speed without external ref. bypass
F
ksps 12-bit resolution
Document Number: 002-00122 Rev. *I
Page 22 of 41
PSoC® 4: PSoC 4100S
Family Datasheet
CSD
Table 14. CSD and IDAC Specifications
SPEC ID#
Parameter
Description
Min
Typ
Max
Units
Details / Conditions
SYS.PER#3
VDD_RIPPLE
Max allowed ripple on power supply,
DC to 10 MHz
–
–
±50
VDD > 2 V (with ripple),
25 °C TA, Sensitivity =
0.1 pF
mV
SYS.PER#16
SID.CSD.BLK
VDD_RIPPLE_1.8 Max allowed ripple on power supply,
DC to 10 MHz
–
–
–
–
±25
VDD > 1.75V (with ripple),
25 °C TA, Parasitic Capaci-
tance (CP) < 20 pF,
mV
µA
Sensitivity ≥ 0.4 pF
ICSD
Maximum block current
4000
Maximum block current for
both IDACs in dynamic
(switching) mode including
comparators, buffer, and
reference generator.
SID.CSD#15
VREF
Voltage reference for CSD and
Comparator
0.6
0.6
1.2
VDDA - 0.6
VDDA - 0.6
VDDA - 0.06 or 4.4,
whichever is lower
V
V
SID.CSD#15A
VREF_EXT
External Voltage reference for CSD
and Comparator
VDDA - 0.06 or 4.4,
whichever is lower
SID.CSD#16
SID.CSD#17
SID308
IDAC1IDD
IDAC2IDD
VCSD
IDAC1 (7-bits) block current
IDAC2 (7-bits) block current
Voltage range of operation
–
–
–
–
–
–
1750
1750
µA
µA
V
1.71
0.6
5.5
1.8 V ±5% or 1.8 V to 5.5 V
SID308A
VCOMPIDAC
Voltage compliance range of IDAC
VDDA –0.6
VDDA - 0.06 or 4.4,
whichever is lower
V
SID309
SID310
IDAC1DNL
IDAC1INL
DNL
INL
–1
–2
–
–
1
2
LSB
LSB
INL is ±5.5 LSB for VDDA
2 V
<
<
SID311
SID312
IDAC2DNL
IDAC2INL
DNL
INL
–1
–2
–
–
1
2
LSB
LSB
INL is ±5.5 LSB for VDDA
2 V
SID313
SNR
Ratio of counts of finger to noise.
Guaranteed by characterization
5
–
–
Capacitance range of 5 to
35 pF, 0.1-pF sensitivity. All
use cases. VDDA > 2 V.
Ratio
SID314
SID314A
SID314B
SID314C
SID314D
SID314E
SID315
IDAC1CRT1
IDAC1CRT2
IDAC1CRT3
IDAC1CRT12
IDAC1CRT22
IDAC1CRT32
IDAC2CRT1
IDAC2CRT2
IDAC2CRT3
IDAC2CRT12
IDAC2CRT22
IDAC2CRT32
IDAC3CRT13
Output current of IDAC1 (7 bits) in
low range
4.2
34
275
8
–
–
–
–
–
–
–
–
–
–
–
–
–
5.4
41
LSB = 37.5-nA typ.
LSB = 300-nA typ.
LSB = 2.4-µA typ.
LSB = 75-nA typ.
LSB = 600-nA typ.
LSB = 4.8-µA typ.
LSB = 37.5-nA typ.
LSB = 300-nA typ.
LSB = 2.4-µA typ.
LSB = 75-nA typ.
LSB = 600-nA typ.
LSB = 4.8-µA typ.
LSB = 37.5-nA typ.
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
Output current of IDAC1(7 bits) in
medium range
Output current of IDAC1(7 bits) in
high range
330
10.5
82
Output current of IDAC1 (7 bits) in
low range, 2X mode
Output current of IDAC1(7 bits) in
medium range, 2X mode
69
540
4.2
34
275
8
Output current of IDAC1(7 bits) in
high range, 2X mode
660
5.4
Output current of IDAC2 (7 bits) in
low range
SID315A
SID315B
SID315C
SID315D
SID315E
SID315F
Output current of IDAC2 (7 bits) in
medium range
41
Output current of IDAC2 (7 bits) in
high range
330
10.5
82
Output current of IDAC2 (7 bits) in
low range, 2X mode
Output current of IDAC2(7 bits) in
medium range, 2X mode
69
540
8
Output current of IDAC2(7 bits) in
high range, 2X mode
660
10.5
Output current of IDAC in 8-bit mode
in low range
Document Number: 002-00122 Rev. *I
Page 23 of 41
PSoC® 4: PSoC 4100S
Family Datasheet
Table 14. CSD and IDAC Specifications (continued)
SPEC ID#
Parameter
Description
Min
Typ
Max
Units
Details / Conditions
SID315G
IDAC3CRT23
Output current of IDAC in 8-bit mode
in medium range
69
–
82
LSB = 300-nA typ.
µA
SID315H
SID320
IDAC3CRT33
IDACOFFSET
Output current of IDAC in 8-bit mode
in high range
540
–
–
–
660
1
LSB = 2.4-µA typ.
µA
All zeroes input
Polarity set by Source or
Sink. Offset is 2 LSBs for
37.5 nA/LSB mode
LSB
SID321
SID322
IDACGAIN
Full-scale error less offset
–
–
–
–
±10
9.2
%
IDACMISMATCH1 Mismatch between IDAC1 and
IDAC2 in Low mode
LSB = 37.5-nA typ.
LSB = 300-nA typ.
LSB = 2.4-µA typ.
LSB
SID322A
SID322B
SID323
SID324
SID325
IDACMISMATCH2 Mismatch between IDAC1 and
IDAC2 in Medium mode
–
–
–
–
–
–
–
5.6
6.8
10
10
–
LSB
LSB
µs
IDACMISMATCH3 Mismatch between IDAC1 and
IDAC2 in High mode
IDACSET8
IDACSET7
CMOD
Settling time to 0.5 LSB for 8-bit IDAC
Settling time to 0.5 LSB for 7-bit IDAC
External modulator capacitor.
–
Full-scale transition. No
external load.
–
Full-scale transition. No
external load.
µs
2.2
5-V rating, X7R or NP0 cap.
nF
Table 15. 10-bit CapSense ADC Specifications
Details/
Conditions
Spec ID#
Parameter
A_RES
Description
Min
Typ
Max Units
SIDA94
Resolution
–
–
10
bits Auto-zeroing is required
every millisecond
SIDA95
SIDA97
SIDA98
A_CHNLS_S
A-MONO
Number of channels - single ended
Monotonicity
–
–
–
–
–
–
16
–
Defined by AMUX Bus.
Yes
A_GAINERR
Gain error
±2
%
In VREF (2.4 V) mode
with VDDA bypass
capacitance of 10 µF
SIDA99
A_OFFSET
Input offset voltage
–
–
3
mV In VREF (2.4 V) mode
with VDDA bypass
capacitance of 10 µF
SIDA100
SIDA101
SIDA103
SIDA104
SIDA106
A_ISAR
Current consumption
–
VSSA
–
–
–
0.25
mA
V
A_VINS
Input voltage range - single ended
Input resistance
VDDA
A_INRES
A_INCAP
A_PSRR
2.2
20
60
–
–
–
KΩ
pF
Input capacitance
–
Power supply rejection ratio
–
dB In VREF (2.4 V) mode
with VDDA bypass
capacitance of 10 µF
SIDA107
SIDA108
A_TACQ
Sample acquisition time
–
–
1
–
–
µs
A_CONV8
Conversion time for 8-bit resolution at
conversion rate = Fhclk/(2^(N+2)).
Clock frequency = 48 MHz.
21.3
µs Does not include acqui-
sition time. Equivalent to
44.8 ksps including
acquisition time.
SIDA108A
A_CONV10
Conversion time for 10-bit resolution at
conversion rate = Fhclk/(2^(N+2)).
Clock frequency = 48 MHz.
–
–
85.3
µs Does not include acqui-
sition time. Equivalent to
11.6 ksps including
acquisition time.
Document Number: 002-00122 Rev. *I
Page 24 of 41
PSoC® 4: PSoC 4100S
Family Datasheet
Table 15. 10-bit CapSense ADC Specifications (continued)
Details/
Max Units
Spec ID#
Parameter
A_SND
Description
Min
Typ
Conditions
SIDA109
Signal-to-noise and Distortion ratio
(SINAD)
–
61
–
dB With 10-Hz input sine
wave, external 2.4-V
reference, VREF (2.4 V)
mode
SIDA110
SIDA111
SIDA112
A_BW
A_INL
A_DNL
Input bandwidth without aliasing
Integral Non Linearity. 1 ksps
Differential Non Linearity. 1 ksps
–
–
–
–
–
–
22.4
2
KHz 8-bit resolution
LSB VREF = 2.4 V or greater
LSB
1
Digital Peripherals
Timer Counter Pulse-Width Modulator (TCPWM)
Table 16. TCPWM Specifications
Spec ID
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
SID.TCPWM.1
ITCPWM1
Block current consumption at 3 MHz
–
–
45
All modes (TCPWM)
SID.TCPWM.2
ITCPWM2
Block current consumption at 12 MHz
Block current consumption at 48 MHz
–
–
–
–
155
650
μA All modes (TCPWM)
SID.TCPWM.2A ITCPWM3
All modes (TCPWM)
Fc max = CLK_SYS
MHz
TCPWMFREQ
TPWMENEXT
SID.TCPWM.3
SID.TCPWM.4
Operating frequency
–
–
–
Fc
–
Maximum = 48 MHz
For all trigger events[7]
Input trigger pulse width
2/Fc
Minimum possible width
of Overflow, Underflow,
andCC(Counterequals
Compare value) outputs
TPWMEXT
SID.TCPWM.5
Output trigger pulse widths
2/Fc
–
–
Minimum time between
successive counts
TCRES
SID.TCPWM.5A
SID.TCPWM.5B
Resolution of counter
PWM resolution
1/Fc
1/Fc
–
–
–
–
ns
Minimum pulse width of
PWM Output
PWMRES
Minimum pulse width
between Quadrature
phase inputs
QRES
SID.TCPWM.5C
Quadrature inputs resolution
1/Fc
–
–
I2C
Table 17. Fixed I2C DC Specifications[8]
Spec ID Parameter
SID149 II2C1
Description
Min
–
Typ
–
Max Units
Details/Conditions
–
–
–
Block current consumption at 100 kHz
Block current consumption at 400 kHz
Block current consumption at 1 Mbps
I2C enabled in Deep Sleep mode
50
SID150
SID151
SID152
II2C2
II2C3
II2C4
–
–
135
310
1.4
µA
–
–
–
–
Table 18. Fixed I2C AC Specifications[8]
Spec ID Parameter
SID153 FI2C1
Description
Min
Typ
Max Units
Msps
Details/Conditions
–
Bit rate
–
–
1
Notes
7. Trigger events can be Stop, Start, Reload, Count, Capture, or Kill depending on which mode of operation is selected.
Note
8. Guaranteed by characterization.
Document Number: 002-00122 Rev. *I
Page 25 of 41
PSoC® 4: PSoC 4100S
Family Datasheet
Table 19. SPI DC Specifications[9]
Spec ID Parameter
SID163 ISPI1
Description
Min
–
Typ
–
Max Units
Details/Conditions
Block current consumption at 1 Mbps
Block current consumption at 4 Mbps
Block current consumption at 8 Mbps
360
–
–
–
SID164
SID165
ISPI2
ISPI3
–
–
560
600
µA
–
–
Table 20. SPI AC Specifications[8]
Spec ID
Parameter
FSPI
Description
Min
Typ
Max
Units
Details/Conditions
SPIOperatingfrequency(Master;6X
Oversampling)
SID166
–
–
8
MHz SID166
Fixed SPI Master Mode AC Specifications
SID167
TDMO
MOSI Valid after SClock driving edge
–
–
–
15
–
–
MISO Valid before SClock capturing
edge
Full clock, late MISO
ns sampling
SID168
TDSI
20
Referred to Slave capturing
edge
SID169
THMO
Previous MOSI data hold time
0
–
–
–
Fixed SPI Slave Mode AC Specifications
MOSI Valid before Sclock Capturing
edge
SID170
SID171
TDMI
40
–
–
–
–
–
TCPU = 1/FCPU
–
42 +
3*Tcpu
TDSO
MISO Valid after Sclock driving edge
ns
ns
MISO Valid after Sclock driving edge
in Ext. Clk mode
SID171A TDSO_EXT
SID172 THSO
–
48
Previous MISO data hold time
0
–
–
–
–
–
–
SID172A TSSELSSCK SSEL Valid to first SCK Valid edge
100
Document Number: 002-00122 Rev. *I
Page 26 of 41
PSoC® 4: PSoC 4100S
Family Datasheet
Table 21. UART DC Specifications[9]
Spec ID
Parameter
IUART1
IUART2
Description
Min
Typ
Max
Units
Details/Conditions
Block current consumption at
100 Kbps
SID160
–
–
55
µA
–
Block current consumption at
1000 Kbps
SID161
–
–
312
µA
–
Table 22. UART AC Specifications[9]
Spec ID
Parameter
FUART
Description
Min
Typ
Max
Units
Details/Conditions
SID162
Bit rate
–
–
1
Mbps
–
Table 23. LCD Direct Drive DC Specifications[9]
Spec ID
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
Operating current in low power
mode
16 4 small segment disp. at
50 Hz
SID154
ILCDLOW
5
–
µA
–
LCD capacitance per
segment/common driver
SID155
SID156
SID157
CLCDCAP
LCDOFFSET
ILCDOP1
500
20
2
5000
pF
–
–
–
Long-term segment offset
–
–
mV
–
LCD system operating current
Vbias = 5 V
32 4 segments. 50 Hz. 25 °C
–
–
mA
LCD system operating current
Vbias = 3.3 V
SID158
ILCDOP2
2
–
32 4 segments. 50 Hz. 25 °C
Table 24. LCD Direct Drive AC Specifications[9]
Spec ID
Parameter
FLCD
Description
LCD frame rate
Min
Typ
Max
Units
Details/Conditions
SID159
10
50
150
Hz
–
Note
9. Guaranteed by characterization.
Document Number: 002-00122 Rev. *I
Page 27 of 41
PSoC® 4: PSoC 4100S
Family Datasheet
Memory
Table 25. Flash DC Specifications
Spec ID
SID173
Parameter
VPE
Description
Min
Typ
Max
Units
Details/Conditions
Erase and program voltage
1.71
–
5.5
V
–
Table 26. Flash AC Specifications
Spec ID
SID174
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
Row (block) write time (erase and
program)
[10]
TROWWRITE
–
–
20
Row (block) = 128 bytes
[10]
SID175
SID176
SID178
SID180[11] TDEVPROG
SID181[11] FEND
TROWERASE
Row erase time
–
–
–
–
–
–
16
4
–
–
–
–
–
ms
[10]
TROWPROGRAM
Row program time after erase
Bulk erase time (64 KB)
Total device program time
Flash endurance
–
–
[10]
TBULKERASE
35
7
[10]
–
Seconds
Cycles
100 K
–
Flash retention. TA 55 °C, 100 K
SID182[11] FRET
20
10
2
–
–
–
–
–
–
–
–
–
–
P/E cycles
Years
Flash retention. TA 85 °C, 10 K
P/E cycles
SID182A[11]
SID256
–
CPU execution from
Flash
TWS48
TWS24
Number of Wait states at 48 MHz
Number of Wait states at 24 MHz
CPU execution from
Flash
SID257
1
System Resources
Power-on Reset (POR)
Table 27. Power On Reset (PRES)
Spec ID Parameter
SID.CLK#6 SR_POWER_UP Power supply slew rate
Description
Min
1
Typ
–
Max
67
Units
Details/Conditions
V/ms At power-up
SID185[11] VRISEIPOR
SID186[11] VFALLIPOR
Rising trip voltage
Falling trip voltage
0.80
0.70
–
1.5
1.4
V
–
–
–
Table 28. Brown-out Detect (BOD) for VCCD
Spec ID
SID190[11]
Parameter
VFALLPPOR
Description
Min
Typ
Max
Units
Details/Conditions
BOD trip voltage in active and
sleep modes
1.48
–
1.62
V
–
SID192[11]
VFALLDPSLP
BOD trip voltage in Deep Sleep
1.11
–
1.5
–
Notes
10. It can take as much as 20 milliseconds to write to Flash. During this time the device should not be Reset, or Flash operations will be interrupted and cannot be relied
on to have completed. Reset sources include the XRES pin, software resets, CPU lockup states and privilege violations, improper power supply levels, and watchdogs.
Make certain that these are not inadvertently activated.
11. Guaranteed by characterization.
Document Number: 002-00122 Rev. *I
Page 28 of 41
PSoC® 4: PSoC 4100S
Family Datasheet
SWD Interface
Table 29. SWD Interface Specifications
Spec ID
SID213
SID214
Parameter
Description
3.3 V VDD 5.5 V
1.71 V VDD 3.3 V
Min
Typ
Max
Units
Details/Conditions
SWDCLK ≤ 1/3 CPU
clock frequency
F_SWDCLK1
–
–
14
MHz
SWDCLK ≤ 1/3 CPU
clock frequency
F_SWDCLK2
–
–
7
SID215[12] T_SWDI_SETUP T = 1/f SWDCLK
SID216[12] T_SWDI_HOLD T = 1/f SWDCLK
SID217[12] T_SWDO_VALID T = 1/f SWDCLK
SID217A[12] T_SWDO_HOLD T = 1/f SWDCLK
0.25*T
–
–
–
–
–
–
–
–
–
–
0.25*T
ns
–
1
0.5*T
–
Internal Main Oscillator
Table 30. IMO DC Specifications
(Guaranteed by Design)
Spec ID
SID218
Parameter
IIMO1
IIMO2
Description
Min
–
Typ
Max
250
180
Units
µA
Details/Conditions
IMO operating current at 48 MHz
IMO operating current at 24 MHz
–
–
–
–
SID219
–
µA
Table 31. IMO AC Specifications
Spec ID
Parameter
FIMOTOL1
Description
Min
Typ
Max
Units
Details/Conditions
Frequency variation at 24, 32, and
48 MHz (trimmed)
SID223
–
–
±2
%
SID226
SID228
TSTARTIMO
IMO startup time
–
–
–
7
–
µs
ps
–
–
TJITRMSIMO2
RMS jitter at 24 MHz
145
Internal Low-Speed Oscillator
Table 32. ILO DC Specifications
(Guaranteed by Design)
Spec ID
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
SID231[12] IILO1
ILO operating current
–
0.3
1.05
µA
–
Table 33. ILO AC Specifications
Spec ID Parameter
Description
ILO startup time
Min
–
Typ
–
Max
2
Units
ms
Details/Conditions
SID234[12] TSTARTILO1
SID236[12] TILODUTY
–
–
–
ILO duty cycle
40
20
50
40
60
80
%
SID237
FILOTRIM1
ILO frequency range
kHz
Note
12. Guaranteed by characterization.
Document Number: 002-00122 Rev. *I
Page 29 of 41
PSoC® 4: PSoC 4100S
Family Datasheet
Table 34. Watch Crystal Oscillator (WCO) Specifications
Spec ID#
SID398
SID399
SID400
SID401
SID402
SID403
SID404
SID405
SID406
Parameter
FWCO
Description
Crystal Frequency
Min
–
Typ
Max
–
Units
Details / Conditions
32.768
kHz
FTOL
ESR
Frequency tolerance
–
50
50
–
250
–
ppm With 20-ppm crystal
Equivalent series resistance
Drive Level
–
kꢀ
µW
ms
pF
PD
–
1
TSTART
CL
Startup time
–
–
500
12.5
–
Crystal Load Capacitance
Crystal Shunt Capacitance
Operating Current (high power mode)
Operating Current (low power mode)
6
–
C0
–
1.35
–
pF
IWCO1
IWCO2
–
8
uA
uA
–
–
1
Table 35. External Clock Specifications
Spec ID Parameter
Description
Min
Typ
–
Max
48
Units
MHz
%
Details/Conditions
SID305[13] ExtClkFreq
SID306[13] ExtClkDuty
External clock input frequency
Duty cycle; measured at VDD/2
0
–
–
45
–
55
Table 36. Block Specs
Spec ID
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
SID262[13] TCLKSWITCH
System clock source switching time
3
–
4
Periods
–
Table 37. Smart I/O Pass-through Time (Delay in Bypass Mode)
Spec ID#
Parameter
Description
Min
Typ
Max
Units
Details / Conditions
SID252
PRG_BYPASS Max delay added by Smart I/O in
bypass mode
–
–
1.6
ns
Note
13. Guaranteed by characterization.
Document Number: 002-00122 Rev. *I
Page 30 of 41
PSoC® 4: PSoC 4100S
Family Datasheet
Ordering Information
The marketing part numbers for the PSoC 4100S family are listed in the following table.
Features
Package
Category
MPN
CY8C4124FNI-S403
CY8C4124FNI-S413
CY8C4124LQI-S412
CY8C4124LQI-S413
CY8C4124AZI-S413
CY8C4124FNI-S433
CY8C4124LQI-S432
CY8C4124LQI-S433
CY8C4124AZI-S433
CY8C4125FNI-S423
CY8C4125LQI-S422
CY8C4125LQI-S423
CY8C4125AZI-S423
CY8C4125AXI-S423
CY8C4125FNI-S413
CY8C4125LQI-S412
CY8C4125LQI-S413
CY8C4125AZI-S413
CY8C4125FNI-S433
CY8C4125LQI-S432
CY8C4125LQI-S433
CY8C4125AZI-S433
CY8C4125AXI-S433
CY8C4126AZI-S423
CY8C4126AXI-S423
CY8C4126AZI-S433
CY8C4126AXI-S433
CY8C4145AZI-S423
CY8C4145AXI-S423
CY8C4145AXI-S433
CY8C4146FNI-S423
CY8C4146LQI-S422
CY8C4146LQI-S423
CY8C4146AZI-S423
CY8C4146AXI-S423
CY8C4146FNI-S433
CY8C4146LQI-S432
CY8C4146LQI-S433
CY8C4146AZI-S433
CY8C4146AXI-S433
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
48
48
48
48
48
48
48
48
48
48
48
48
48
16
16
16
16
16
16
16
16
16
32
32
32
32
32
32
32
32
32
32
32
32
32
32
64
64
64
64
32
32
32
64
64
64
64
64
64
64
64
64
64
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
8
8
8
8
4
4
4
8
8
8
8
8
8
8
8
8
8
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
0
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
1
1
0
0
1
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
3
3
3
3
2
2
2
3
3
3
3
3
3
3
3
3
3
8
31
X
X
16 31
16 27
16 34
16 36
16 31
16 27
16 34
16 36
16 31
16 27
16 34
16 36
16 36
16 31
16 27
16 34
16 36
16 31
16 27
16 34
16 36
16 36
16 36
16 36
16 36
16 36
16 36
16 36
16 36
16 31
16 27
16 34
16 36
16 36
16 31
16 27
16 34
16 36
16 36
X
X
X
X
X
X
4124
X
X
X
806 ksps
806 ksps
806 ksps
806 ksps
806 ksps
806 ksps
806 ksps
806 ksps
806 ksps
X
X
X
X
X
X
X
4125
X
X
X
806 ksps
806 ksps
806 ksps
806 ksps
806 ksps
806 ksps
806 ksps
806 ksps
806 ksps
1 Msps
1 Msps
1 Msps
1 Msps
1 Msps
1 Msps
1 Msps
1 Msps
1 Msps
1 Msps
1 Msps
1 Msps
1 Msps
X
X
X
X
X
X
X
4126
4145
X
X
X
X
X
X
X
X
X
X
X
X
4146
Document Number: 002-00122 Rev. *I
Page 31 of 41
PSoC® 4: PSoC 4100S
Family Datasheet
The nomenclature used in the preceding table is based on the following part numbering convention:
Field
Description
Cypress Prefix
Architecture
Family
Values
Meaning
CY8C
4
A
B
4
PSoC 4
1
4100 Family
CPU Speed
2
24 MHz
4
48 MHz
C
Flash Capacity
Package Code
4
16 KB
5
32 KB
6
64 KB
128 KB
7
AX
AZ
LQ
PV
FN
I
DE
TQFP (0.8mm pitch)
TQFP (0.5mm pitch)
QFN
SSOP
CSP
F
S
Temperature Range
Silicon Family
Industrial
S
PSoC 4A-S1, PSoC 4A-S2
PSoC 4A-M
M
L
PSoC 4A-L
BL
000-999
PSoC 4A-BLE
Code of feature set in the specific family
XYZ
Attributes Code
The following is an example of a part number:
Example
CY8C 4 A B C DE F – S XYZ
Cypress Prefix
Architecture
Family within Architecture
CPU Speed
4: PSoC 4
1: 4100 Family
4: 48 MHz
5: 32 KB
Flash Capacity
Package Code
AZ: TQFP
I: Industrial
Temperature Range
Silicon Family
Attributes Code
Document Number: 002-00122 Rev. *I
Page 32 of 41
PSoC® 4: PSoC 4100S
Family Datasheet
Packaging
The PSoC 4100S will be offered in 48-pin TQFP, 44-pin TQFP, 40-pin QFN, 32-pin QFN, and 35-ball WLCSP packages.
Package dimensions and Cypress drawing numbers are in the following table.
Table 38. Package List
Spec ID#
BID20
Package
48-pin TQFP
44-pin TQFP
40-pin QFN
32-pin QFN
Description
Package Dwg
7 × 7 × 1.4-mm height with 0.5-mm pitch
10 × 10 × 1.6-mm height with 0.8-mm pitch
6 × 6 × 0.6-mm height with 0.5-mm pitch
5 × 5 × 0.6-mm height with 0.5-mm pitch
51-85135
51-85064
001-80659
001-42168
BID20A
BID27
BID34A
BID34D
35-ball WLCSP 2.6 × 2.1 × 0.48-mm height with 0.35-mm pitch 002-09958
Table 39. Package Thermal Characteristics
Parameter
Description
Operating Ambient temperature
Operating junction temperature
Package θJA
Package
Min
–40
–40
–
Typ
25
Max
85
100
–
Units
°C
TA
TJ
–
°C
TJA
TJC
TJA
TJC
TJA
TJC
TJA
TJC
TJA
TJC
48-pin TQFP
74.8
35.7
57.2
17.5
17.8
2.8
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
Package θJC
48-pin TQFP
44-pin TQFP
44-pin TQFP
40-pin QFN
–
–
Package θJA
–
–
Package θJC
–
–
Package θJA
–
–
Package θJC
40-pin QFN
–
–
Package θJA
32-pin QFN
–
19.9
4.3
–
Package θJC
32-pin QFN
–
–
Package θJA
35-ball WLCSP
35-ball WLCSP
–
43
–
Package θJC
–
0.3
–
Table 40. Solder Reflow Peak Temperature
Maximum Peak
Package
Maximum Time at Peak Temperature
Temperature
All
260 °C
30 seconds
Table 41. Package Moisture Sensitivity Level (MSL), IPC/JEDEC J-STD-020
Package
MSL
All except WLCSP
35-ball WLCSP
MSL 3
MSL 1
Document Number: 002-00122 Rev. *I
Page 33 of 41
PSoC® 4: PSoC 4100S
Family Datasheet
Package Diagrams
Figure 6. 48-pin TQFP Package Outline
51-85135 *C
Figure 7. 44-pin TQFP Package Outline
51-85064 *G
Document Number: 002-00122 Rev. *I
Page 34 of 41
PSoC® 4: PSoC 4100S
Family Datasheet
Figure 8. 40-pin QFN Package Outline
001-80659 *A
Figure 9. 32-pin QFN Package Outline
001-42168 *E
Document Number: 002-00122 Rev. *I
Page 35 of 41
PSoC® 4: PSoC 4100S
Family Datasheet
Figure 10. 35-Ball WLCSP Package Outline
1
2
3
4
5
6
7
7
6
5
4
3
2
1
A
B
C
D
E
A
B
C
D
E
NOTES:
DIMENSIONS
NOM.
SYMBOL
1. ALL DIMENSIONS ARE IN MILLIMETERS.
MIN.
MAX.
2. JEDEC PUBLICATION 95; DESIGN GUIDE 4.18.
A
A1
D
-
-
0.482
0.173
2.607
0.141
2.557
0.157
2.582
E
2.072
2.097
2.10 BSC
1.40 BSC
7
2.122
D1
E1
MD
ME
N
5
35
b
0.19
0.22
0.35
0.35
0.25
eD
eE
SD
SE
-
-
-
-
0
0.02 BSC
002-09958 *D
Document Number: 002-00122 Rev. *I
Page 36 of 41
PSoC® 4: PSoC 4100S
Family Datasheet
Acronyms
Table 42. Acronyms Used in this Document (continued)
Table 42. Acronyms Used in this Document
Acronym
ETM
Description
embedded trace macrocell
Acronym
abus
Description
analog local bus
FIR
finite impulse response, see also IIR
flash patch and breakpoint
full-speed
ADC
AG
analog-to-digital converter
analog global
FPB
FS
AHB
AMBA (advanced microcontroller bus
architecture) high-performance bus, an ARM
data transfer bus
GPIO
general-purpose input/output, applies to a PSoC
pin
HVI
high-voltage interrupt, see also LVI, LVD
integrated circuit
ALU
arithmetic logic unit
IC
AMUXBUS analog multiplexer bus
IDAC
current DAC, see also DAC, VDAC
integrated development environment
API
application programming interface
IDE
I2C, or IIC
APSR
ARM®
ATM
BW
application program status register
advanced RISC machine, a CPU architecture
automatic thump mode
Inter-Integrated Circuit, a communications
protocol
IIR
infinite impulse response, see also FIR
internal low-speed oscillator, see also IMO
internal main oscillator, see also ILO
integral nonlinearity, see also DNL
input/output, see also GPIO, DIO, SIO, USBIO
initial power-on reset
bandwidth
ILO
IMO
INL
CAN
Controller Area Network, a communications
protocol
CMRR
CPU
common-mode rejection ratio
central processing unit
I/O
IPOR
IPSR
IRQ
ITM
LCD
LIN
CRC
cyclic redundancy check, an error-checking
protocol
interrupt program status register
interrupt request
DAC
DFB
DIO
digital-to-analog converter, see also IDAC, VDAC
digital filter block
instrumentation trace macrocell
liquid crystal display
digital input/output, GPIO with only digital
capabilities, no analog. See GPIO.
Local Interconnect Network, a communications
protocol.
DMIPS
DMA
DNL
Dhrystone million instructions per second
direct memory access, see also TD
differential nonlinearity, see also INL
do not use
LR
link register
LUT
LVD
lookup table
DNU
DR
low-voltage detect, see also LVI
low-voltage interrupt, see also HVI
low-voltage transistor-transistor logic
multiply-accumulate
port write data registers
LVI
DSI
digital system interconnect
data watchpoint and trace
error correcting code
LVTTL
MAC
MCU
MISO
NC
DWT
ECC
microcontroller unit
ECO
EEPROM
external crystal oscillator
master-in slave-out
electrically erasable programmable read-only
memory
no connect
NMI
nonmaskable interrupt
non-return-to-zero
EMI
electromagnetic interference
external memory interface
end of conversion
NRZ
NVIC
NVL
opamp
PAL
EMIF
EOC
EOF
EPSR
ESD
nested vectored interrupt controller
nonvolatile latch, see also WOL
operational amplifier
end of frame
execution program status register
electrostatic discharge
programmable array logic, see also PLD
Document Number: 002-00122 Rev. *I
Page 37 of 41
PSoC® 4: PSoC 4100S
Family Datasheet
Table 42. Acronyms Used in this Document (continued)
Acronym Description
PC
Table 42. Acronyms Used in this Document (continued)
Acronym
SWV
Description
single-wire viewer
program counter
PCB
PGA
PHUB
PHY
PICU
PLA
printed circuit board
TD
transaction descriptor, see also DMA
total harmonic distortion
transimpedance amplifier
technical reference manual
transistor-transistor logic
transmit
programmable gain amplifier
peripheral hub
THD
TIA
physical layer
TRM
TTL
TX
port interrupt control unit
programmable logic array
programmable logic device, see also PAL
phase-locked loop
PLD
UART
Universal Asynchronous Transmitter Receiver, a
communications protocol
PLL
UDB
universal digital block
Universal Serial Bus
PMDD
POR
PRES
PRS
PS
PSoC®
PSRR
PWM
RAM
RISC
RMS
RTC
RTL
package material declaration data sheet
power-on reset
USB
USBIO
USB input/output, PSoC pins used to connect to
a USB port
precise power-on reset
pseudo random sequence
port read data register
Programmable System-on-Chip™
power supply rejection ratio
pulse-width modulator
random-access memory
reduced-instruction-set computing
root-mean-square
VDAC
WDT
voltage DAC, see also DAC, IDAC
watchdog timer
WOL
write once latch, see also NVL
watchdog timer reset
external reset I/O pin
crystal
WRES
XRES
XTAL
real-time clock
register transfer language
remote transmission request
receive
RTR
RX
SAR
SC/CT
SCL
successive approximation register
switched capacitor/continuous time
I2C serial clock
SDA
S/H
I2C serial data
sample and hold
SINAD
SIO
signal to noise and distortion ratio
special input/output, GPIO with advanced
features. See GPIO.
SOC
SOF
SPI
start of conversion
start of frame
Serial Peripheral Interface, a communications
protocol
SR
slew rate
SRAM
SRES
SWD
static random access memory
software reset
serial wire debug, a test protocol
Document Number: 002-00122 Rev. *I
Page 38 of 41
PSoC® 4: PSoC 4100S
Family Datasheet
Document Conventions
Units of Measure
Table 43. Units of Measure
Symbol
°C
Unit of Measure
degrees Celsius
decibel
dB
fF
femto farad
hertz
Hz
KB
kbps
Khr
kHz
k
1024 bytes
kilobits per second
kilohour
kilohertz
kilo ohm
ksps
LSB
Mbps
MHz
M
Msps
µA
kilosamples per second
least significant bit
megabits per second
megahertz
mega-ohm
megasamples per second
microampere
microfarad
µF
µH
microhenry
microsecond
microvolt
µs
µV
µW
mA
ms
mV
nA
microwatt
milliampere
millisecond
millivolt
nanoampere
nanosecond
nanovolt
ns
nV
ohm
pF
picofarad
ppm
ps
parts per million
picosecond
second
s
sps
sqrtHz
V
samples per second
square root of hertz
volt
Document Number: 002-00122 Rev. *I
Page 39 of 41
PSoC® 4: PSoC 4100S
Family Datasheet
Revision History
Description Title: PSoC® 4: PSoC 4100S Family Datasheet Programmable System-on-Chip (PSoC)
Document Number: 002-00122
Orig. of Submission
Revision
ECN
Description of Change
Change
Date
**
4883809
WKA
08/28/2015 New datasheet
Updated Pinouts.
Added VDDD ≥ 2.2V at –40 °C under Conditions for specs SID247A, SID90,
10/30/2015 SID92.
*A
*B
*C
4992376
5037826
5060691
WKA
SLAN
WKA
Updated Table 15.
Updated Ordering Information.
12/08/2015 Changed datasheet status to Preliminary
Updated SCBs from 2 to 3.
Updated SRAM size to 8 KB.
12/22/2015 Changed WLCSP package to 35-ball WLCSP.
Updated Pin List and Alternate Pin Functions.
Updated Ordering Information.
Added Errata.
Added 35 WLCSP package details.
Updated theta JA and JC values for all packages.
Updated copyright information at the end of the document.
*D
*E
5139206
5173961
WKA
WKA
02/16/2016
03/15/2016 Updated values for SID79, BID194. SID175, and SID176.
Updated CSD and IDAC Specifications.
Updated 10-bit CapSense ADC Specifications.
*F
5330930
WKA
07/27/2016 Updated CSD and IDAC Specifications.
Updated 10-bit CapSense ADC Specifications.
Removed errata.
*G
*H
5473409
5561833
WKA
WKA
10/13/2016 Added 44 TQFP pin and package details.
01/09/2017 Updated Figure 3.
Changed PRGIO references to Smart I/O.
Updated DC Specifications.
Updated Ordering Information.
*I
5713158
WKA
04/26/2017 Updated 35-ball WLCSP package diagram.
Updated the Cypress logo.
Document Number: 002-00122 Rev. *I
Page 40 of 41
PSoC® 4: PSoC 4100S
Family Datasheet
Sales, Solutions, and Legal Information
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© Cypress Semiconductor Corporation 2015-2017. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
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Document Number: 002-00122 Rev. *I
Revised April 26, 2017
Page 41 of 41
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