CY8C21634-24LTXI [CYPRESS]
PSoC® Mixed-Signal Array; 的PSoC ™混合信号阵列
| 型号： | CY8C21634-24LTXI |
| 厂家： | 
CYPRESS |
| 描述： | PSoC® Mixed-Signal Array |
| 文件： | 总43页 (文件大小：1151K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY8C21634, CY8C21534
CY8C21434, CY8C21334, CY8C21234
PSoC® Mixed-Signal Array
■ Versatile Analog Mux
❐ Common Internal Analog Bus
Features
■ Powerful Harvard Architecture Processor
❐ M8C Processor Speeds to 24 MHz
❐ Low power at high speed
❐ 2.4V to 5.25V Operating Voltage
❐ Operating Voltages Down to 1.0V using On-Chip Switch
Mode Pump (SMP)
❐ Simultaneous Connection of IO Combinations
❐ Capacitive Sensing Application Capability
■ Additional System Resources
❐ I2C™ Master, Slave and Multi-Master to 400 kHz
❐ Watchdog and Sleep Timers
❐ User-Configurable Low Voltage Detection
❐ Integrated Supervisory Circuit
❐ On-Chip Precision Voltage Reference
❐ Industrial Temperature Range: -40°C to +85°C
■ Advanced Peripherals (PSoC Blocks)
❐ 4 Analog Type “E” PSoC Blocks provide:
• 2 Comparators with DAC Refs
• Single or Dual 8-Bit 28 Channel ADC
❐ 4 Digital PSoC Blocks provide:
Block Diagram
• 8 to 32-Bit Timers, Counters, and PWMs
• CRC and PRS Modules
• Full-Duplex UART, SPI™ Master or Slave
• Connectable to All GPIO Pins
❐ Complex Peripherals by Combining Blocks
■ Flexible On-Chip Memory
❐ 8K Flash Program Storage 50,000 Erase/Write Cycles
❐ 512 Bytes SRAM Data Storage
❐ In-System Serial Programming (ISSP™)
❐ Partial Flash Updates
❐ Flexible Protection Modes
❐ EEPROM Emulation in Flash
■ Complete Development Tools
❐ Free Development Software
(PSoC Designer™)
❐ Full-Featured, In-Circuit Emulator and Programmer
❐ Full Speed Emulation
❐ Complex Breakpoint Structure
❐ 128K Trace Memory
■ Precision, Programmable Clocking
❐ Internal ±2.5% 24/48 MHz Oscillator
❐ Internal Oscillator for Watchdog and Sleep
■ Programmable Pin Configurations
❐ 25 mA Drive on All GPIO
❐ Pull Up, Pull Down, High Z, Strong, or Open Drain Drive
Modes on All GPIO
❐ Up to 8 Analog Inputs on GPIO
❐ Configurable Interrupt on All GPIO
Cypress Semiconductor Corporation
Document Number: 38-12025 Rev. *M
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised April 18, 2008
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®
The Digital System
PSoC Functional Overview
The Digital System consists of 4 digital PSoC blocks. Each block
is an 8-bit resource that is used alone or combined with other
blocks to form 8, 16, 24, and 32-bit peripherals, which are called
user module references. Digital peripheral configurations include
the following.
The PSoC® family consists of many Mixed-Signal Array with
On-Chip Controller devices. These devices are designed to
replace multiple traditional MCU-based system components with
one low cost single-chip programmable component. A PSoC
device includes configurable blocks of analog and digital logic,
and programmable interconnect. This architecture enables the
user to create customized peripheral configurations, to match
the requirements of each individual application. Additionally, a
fast CPU, Flash program memory, SRAM data memory, and
configurable IO are included in a range of convenient pinouts.
■ PWMs (8 to 32 bit)
■ PWMs with Dead band (8 to 32 bit)
■ Counters (8 to 32 bit)
■ Timers (8 to 32 bit)
The PSoC architecture, shown in Figure 1, consists of four main
areas: the Core, the System Resources, the Digital System, and
the Analog System. Configurable global bus resources allow
combining all the device resources into a complete custom
system. Each CY8C21x34 PSoC device includes four digital
blocks and four analog blocks. Depending on the PSoC
package, up to 28 general purpose IO (GPIO) are also included.
The GPIO provide access to the global digital and analog inter-
connects.
■ UART 8 bit with selectable parity
■ SPI master and slave
■ I2C slave and multi-master
■ Cyclical Redundancy Checker/Generator (8 to 32 bit)
■ IrDA
■ Pseudo Random Sequence Generators (8 to 32 bit)
The PSoC Core
The digital blocks are connected to any GPIO through a series
of global buses that can route any signal to any pin. The buses
also allow for signal multiplexing and for performing logic
operations. This configurability frees your designs from the
constraints of a fixed peripheral controller.
The PSoC Core is a powerful engine that supports a rich
instruction set. It encompasses SRAM for data storage, an
interrupt controller, sleep and watchdog timers, and IMO
(internal main oscillator) and ILO (internal low speed oscillator).
The CPU core, called the M8C, is a powerful processor with
speeds up to 24 MHz. The M8C is a four MIPS 8-bit Harvard
architecture microprocessor.
Digital blocks are provided in rows of four, where the number of
blocks varies by PSoC device family. This allows the optimum
choice of system resources for your application. Family
resources are shown in Table 1 on page 4.
System Resources provide the following additional capabilities:
■ Digital clocks to increase the flexibility of the PSoC
mixed-signal arrays.
Figure 1. Digital System Block Diagram
Port 3
Port 1
■ I2C functionality to implement an I2C master and slave.
Port 2
Port 0
■ An internal voltage reference, MultiMaster, that provides an
absolute value of 1.3V to a number of PSoC subsystems.
DigitalClocks
FromCore
ToAnalog
System
To SystemBus
■ A switch mode pump (SMP) that generates normal operating
voltages off a single battery cell.
DIGITAL SYSTEM
■ Various system resets supported by the M8C.
The Digital System consists of an array of digital PSoC blocks
that may be configured into any number of digital peripherals.
The digital blocks are connected to the GPIO through a series of
global buses that can route any signal to any pin, freeing designs
from the constraints of a fixed peripheral controller.
DigitalPSoCBlockArray
Row 0
4
4
DBB00
DBB01
DCB02
DCB03
The Analog System consists of four analog PSoC blocks,
supporting comparators and analog-to-digital conversion up to 8
bits in precision.
8
8
8
8
GIE[7:0]
GIO[7:0]
GOE[7:0]
GOO[7:0]
Global Digital
Interconnect
Document Number: 38-12025 Rev. *M
Page 2 of 43
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The Analog Multiplexer System
The Analog System
The Analog Mux Bus can connect to every GPIO pin. Pins may
be connected to the bus individually or in any combination. The
bus also connects to the analog system for analysis with
comparators and analog-to-digital converters. An additional 8:1
analog input multiplexer provides a second path to bring Port 0
pins to the analog array.
The Analog System consists of 4 configurable blocks that allow
the creation of complex analog signal flows. Analog peripherals
are very flexible and may be customized to support specific
application requirements. Some of the common PSoC analog
functions for this device (most available as user modules) are:
■ Analog-to-digital converters (single or dual, with 8-bit
resolution)
Switch control logic enables selected pins to precharge
continuously under hardware control. This enables capacitive
measurement for applications such as touch sensing. Other
multiplexer applications include:
■ Pin-to-pin comparator
■ Single-ended comparators (up to 2) with absolute (1.3V)
reference or 8-bit DAC reference
■ Track pad, finger sensing.
■ 1.3V reference (as a System Resource)
■ Chip-wide mux that allows analog input from any IO pin.
■ Crosspoint connection between any IO pin combinations.
In most PSoC devices, analog blocks are provided in columns of
three, which includes one CT (Continuous Time) and two SC
(Switched Capacitor) blocks. The CY8C21x34 devices provide
limited functionality Type “E” analog blocks. Each column
contains one CT Type E block and one SC Type E block. Refer
to the PSoC Mixed-Signal Array Technical Reference Manual for
detailed information on the CY8C21x34’s Type E analog blocks.
When designing capacitive sensing applications, refer to the
signal-to-noise system level requirement found in Application
Note
AN2403
on
the
Cypress
web
site
at
http://www.cypress.com.
Additional System Resources
Figure 2. Analog System Block Diagram
System Resources, some of which are listed in the previous
sections, provide additional capability useful to complete
systems. Additional resources include a switch mode pump, low
voltage detection, and power on reset. Brief statements
describing the merits of each system resource follow.
Array Input
Configuration
■ Digital clock dividers provide three customizable clock
frequencies for use in applications. The clocks may be routed
to both the digital and analog systems. Additional clocks can
be generated using digital PSoC blocks as clock dividers.
■ TheI2Cmoduleprovides100and400kHzcommunicationover
two wires. Slave, master, and multi-master modes are all
supported.
ACI0[1:0]
ACI1[1:0]
All IO
■ Low Voltage Detection (LVD) interrupts can signal the
application of falling voltage levels, while the advanced POR
(Power On Reset) circuit eliminates the need for a system
supervisor.
X
X
AC OL 1MU X
X
X
An al o g MuxBus
■ An internal 1.3 voltage reference provides an absolute
reference for the analog system, including ADCs and DACs.
X
Array
■ An integrated switch mode pump (SMP) generates normal
operating voltages from a single 1.2V battery cell, providing a
low cost boost converter.
ACE00
ACE01
ASE11
ASE10
■ Versatile analog multiplexer system.
Document Number: 38-12025 Rev. *M
Page 3 of 43
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contains development kits, C compilers, and all accessories for
PSoC development. Go to the Cypress Online Store web site at
http://www.cypress.com, click the Online Store shopping cart
icon at the bottom of the web page, and click PSoC (Program-
mable System-on-Chip) to view a current list of available items.
PSoC Device Characteristics
Depending on your PSoC device characteristics, the digital and
analog systems can have 16, 8, or 4 digital blocks and 12, 6, or
4 analog blocks. Table 1 lists the resources available for specific
PSoC device groups. The PSoC device covered by this data
sheet is highlighted in this table.
Technical Training Modules
Table 1. PSoC Device Characteristics
Free PSoC technical training modules are available for users
new to PSoC. Training modules cover designing, debugging,
advanced
http://www.cypress.com/techtrain.
analog
and
CapSense.
Go
to
PSoC Part
Number
Consultants
CY8C29x66 upto 4
64
16 12
4
4
4
4
12 2K
32K
Certified PSoC Consultants offer everything from technical
assistance to completed PSoC designs. To contact or become a
PSoC Consultant go to http://www.cypress.com, click on Design
Support located on the left side of the web page, and select
CYPros Consultants.
CY8C27x43 upto 2
44
8
12
12 256 16K
Bytes
CY8C24x94 56
1
4
4
48
12
2
2
2
2
6
6
1K
16K
CY8C24x23A upto 1
24
256 4K
Bytes
Technical Support
PSoC application engineers take pride in fast and accurate
response. They can be reached with a 4-hour guaranteed
response at http://www.cypress.com/support.
a
a
b
CY8C21x34 upto 1
28
4
4
0
28
8
0
0
0
2
2
0
4
4
3
512 8K
Bytes
CY8C21x23 16
1
256 4K
Bytes
Application Notes
A long list of application notes can assist you in every aspect of
your design effort. To view the PSoC application notes, go to the
http://www.cypress.com web site and select Application Notes
under the Design Resources list located in the center of the web
page. Application notes are sorted by date by default.
CY8C20x34 upto 0
28
28
512 8K
Bytes
a. Limited analog functionality.
b. Two analog blocks and one CapSense.
Getting Started
Development Tools
PSoC Designer is a Microsoft® Windows-based, integrated
The quickest path to understanding the PSoC silicon is by
reading this data sheet and using the PSoC Designer Integrated
Development Environment (IDE). This data sheet is an overview
of the PSoC integrated circuit and presents specific pin, register,
and electrical specifications. For in-depth information with
detailed programming information, refer the PSoC Mixed-Signal
development
environment
for
the
Programmable
System-on-Chip (PSoC) devices. The PSoC Designer IDE and
application runs on Windows NT 4.0, Windows 2000, Windows
Millennium (Me), or Windows XP. (See Figure 3 on page 5)
PSoC Designer helps the customer to select an operating
configuration for the PSoC, write application code that uses the
PSoC, and debug the application. This system provides design
database management by project, an integrated debugger with
In-Circuit Emulator, in-system programming support, and the
CYASM macro assembler for the CPUs.
Array
Technical
Reference
Manual
available
at
http://www.cypress.com/psoc.
For up-to-date Ordering, Packaging, and Electrical Specification
information, refer the latest PSoC device data sheets at
http://www.cypress.com.
PSoC Designer also supports a high-level C language compiler
developed specifically for the devices in the family.
Development Kits
Development Kits are available from the following distributors:
Digi-Key, Avnet, Arrow, and Future. The Cypress Online Store
Document Number: 38-12025 Rev. *M
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Figure 3. PSoC Designer Subsystems
Design Browser
The Design Browser enables users to select and import
preconfigured designs into the user’s project. Users can easily
browse
a catalog of preconfigured designs to facilitate
time-to-design. Examples provided in the tools include a
300-baud modem, LIN Bus master and slave, fan controller, and
magnetic card reader.
Application Editor
In the Application Editor you can edit your C language and
Assembly language source code. You can also assemble,
compile, link, and build.
Assembler. The macro assembler allows the seamless
merging of the assembly code with C code. The link libraries
automatically use absolute addressing or are compiled in relative
mode, and linked with other software modules to get absolute
addressing.
C Language Compiler. A C language compiler that supports
the PSoC family of devices is available. Even if you have never
worked in the C language before, the product quickly helps you
create complete C programs for the PSoC family devices.
The embedded, optimizing C compiler provides all the features
of C tailored to the PSoC architecture. It comes complete with
embedded libraries providing port and bus operations, standard
keypad and display support, and extended math functionality.
Debugger
The PSoC Designer Debugger subsystem provides hardware
in-circuit emulation, allowing the designer to test the program in
a physical system while providing an internal view of the PSoC
device. Debugger commands allow the designer to read the
program and read and write data memory, read and write IO
registers, read and write CPU registers, set and clear break-
points, and provide program run, halt, and step control. The
debugger also allows the designer to create a trace buffer of
registers and memory locations of interest.
PSoC Designer Software Subsystems
Device Editor
Online Help System
The device editor subsystem enables the user to select different
onboard analog and digital components called user modules
using the PSoC blocks. Examples of user modules are ADCs,
DACs, Amplifiers, and Filters.
The online help system displays online, context-sensitive help
for the user. Designed for procedural and quick reference, each
functional subsystem has its own context-sensitive help. This
system also provides tutorials and links to FAQs and an Online
Support Forum to aid the designer in getting started.
The device editor also supports easy development of multiple
configurations and dynamic reconfiguration. Dynamic
reconfiguration allows changing configurations at run time.
Hardware Tools
PSoC Designer sets up power on initialization tables for selected
PSoC block configurations and creates source code for an
application framework. The framework contains software to
operate the selected components and, if the project uses more
than one operating configuration, contains routines to switch
between different sets of PSoC block configurations at run time.
PSoC Designer can print out a configuration sheet for a given
project configuration for use during application programming in
conjunction with the Device Data Sheet. After the framework is
generated, the user can add application-specific code to flesh
out the framework. It is also possible to change the selected
components and regenerate the framework.
In-Circuit Emulator
A low cost, high functionality ICE (In-Circuit Emulator) is
available for development support. This hardware has the
capability to program single devices.
The emulator consists of a base unit that connects to the PC by
way of a USB port. The base unit is universal and operates with
all PSoC devices. Emulation pods for each device family are
available separately. The emulation pod takes the place of the
PSoC device in the target board and performs full speed
(24 MHz) operation.
Document Number: 38-12025 Rev. *M
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Figure 4. User Module and Source Code Development Flows
Designing with User Modules
The development process for the PSoC device differs from that
of a traditional fixed function microprocessor. The configurable
analog and digital hardware blocks give the PSoC architecture a
unique flexibility that pays dividends in managing specification
change during development and by lowering inventory costs.
These configurable resources, called PSoC Blocks, have the
ability to implement a wide variety of user-selectable functions.
Each block has several registers that determine its function and
connectivity to other blocks, multiplexers, buses and to the IO
pins. Iterative development cycles permit you to adapt the
hardware and software. This substantially lowers the risk of
having to select a different part to meet the final design
requirements.
Device Editor
Placement
User
Module
Selection
Source
Code
Generator
and
Parameter
-ization
Generate
Application
Application Editor
To speed the development process, the PSoC Designer
Integrated Development Environment (IDE) provides a library of
pre-built, pre-tested hardware peripheral functions, called “User
Modules.” User modules make selecting and implementing
peripheral devices simple, and come in analog, digital, and
mixed signal varieties. The standard User Module library
contains over 50 common peripherals such as ADCs, DACs
Timers, Counters, UARTs, and other uncommon peripherals,
such as DTMF Generators and Bi-Quad analog filter sections.
Source
Code
Editor
Project
Manager
Build
Manager
Build
All
Each user module establishes the basic register settings that
implement the selected function. It also provides parameters that
allow you to tailor its precise configuration to your particular
application. For example, a Pulse Width Modulator User Module
configures one or more digital PSoC blocks, one for each 8 bits
of resolution. The user module parameters permit you to
establish the pulse width and duty cycle. User modules also
provide tested software to cut your development time. The user
module application programming interface (API) provides
high-level functions to control and respond to hardware events
at run time. The API also provides optional interrupt service
routines that you can adapt as needed.
Debugger
Event &
Breakpoint
Manager
Interface
to ICE
Storage
Inspector
The next step is to write your main program, and any
sub-routines using PSoC Designer’s Application Editor
subsystem. The Application Editor includes a Project Manager
that allows you to open the project source code files (including
all generated code files) from a hierarchal view. The source code
editor provides syntax coloring and advanced edit features for
both C and assembly language. File search capabilities include
simple string searches and recursive “grep-style” patterns. A
single mouse click invokes the Build Manager. It employs a
professional-strength “makefile” system to automatically analyze
all file dependencies and run the compiler and assembler as
necessary. Project-level options control optimization strategies
used by the compiler and linker. Syntax errors are displayed in a
console window. Double clicking the error message takes you
directly to the offending line of source code. When all is correct,
the linker builds a HEX file image suitable for programming.
The API functions are documented in user module data sheets
that are viewed directly in the PSoC Designer IDE. These data
sheets explain the internal operation of the user module and
provide performance specifications. Each data sheet describes
the use of each user module parameter and documents the
setting of each register controlled by the user module.
The development process starts when you open a new project
and bring up the Device Editor, a graphical user interface (GUI)
for configuring the hardware. You can pick the user modules you
need for your project and map them onto the PSoC blocks with
point-and-click simplicity. Next, you build signal chains by inter-
connecting user modules to each other and the IO pins. At this
stage, you must also configure the clock source connections and
enter parameter values directly or by selecting values from
drop-down menus. When you are ready to test the hardware
configuration or move on to developing code for the project,
perform the “Generate Application” step. This causes PSoC
Designer to generate source code that automatically configures
the device to your specification and provides the high-level user
module API functions.
The last step in the development process takes place inside the
PSoC Designer’s Debugger subsystem. The Debugger
downloads the HEX image to the In-Circuit Emulator (ICE) where
it runs at full speed. Debugger capabilities rival those of systems
costing many times more. In addition to traditional single-step,
run-to-breakpoint and watch-variable features, the Debugger
provides a large trace buffer and enables you to define complex
breakpoint events that include monitoring address and data bus
values, memory locations, and external signals.
Document Number: 38-12025 Rev. *M
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Units of Measure
Document Conventions
A units of measure table is located in the Electrical Specifications
section. Table 2 on page 7 lists all the abbreviations used to
measure the PSoC devices.
Acronyms Used
The following table lists the acronyms that are used in this
document.
Numeric Naming
Table 2. Acronyms Used
Hexadecimal numbers are represented with all letters in
uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or
‘3Ah’). Hexadecimal numbers may also be represented by a ‘0x’
prefix, the C coding convention. Binary numbers have an
appended lowercase ‘b’ (for example, 01010100b’ or
‘01000011b’). Numbers not indicated by an ‘h’, ‘b’, or 0x are
decimal.
Acronym
AC
Description
alternating current
ADC
API
analog-to-digital converter
application programming interface
central processing unit
continuous time
CPU
CT
DAC
DC
digital-to-analog converter
direct current
ECO
EEPROM
external crystal oscillator
electrically erasable programmable read-only
memory
FSR
GPIO
GUI
full scale range
general purpose IO
graphical user interface
human body model
in-circuit emulator
HBM
ICE
ILO
internal low speed oscillator
internal main oscillator
input/output
IMO
IO
IPOR
LSb
imprecise power on reset
least-significant bit
low voltage detect
LVD
MSb
PC
most-significant bit
program counter
PLL
phase-locked loop
POR
PPOR
PSoC®
PWM
SC
power on reset
precision power on reset
Programmable System-on-Chip™
pulse width modulator
switched capacitor
slow IMO
SLIMO
SMP
SRAM
switch mode pump
static random access memory
Document Number: 38-12025 Rev. *M
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Pin Information
The CY8C21x34 PSoC device is available in a variety of packages which are listed in the following tables. Every port pin (labeled with
a “P”) is capable of Digital IO and connection to the common analog bus. However, Vss, Vdd, SMP, and XRES are not capable of
Digital IO.
16-Pin Part Pinout
Figure 5. CY8C21234 16-Pin PSoC Device
A, I,M, P0[7]
A, I,M, P0[5]
A, I,M, P0[3]
A, I,M, P0[1]
SMP
Vdd
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
P0[6], A,I, M
P0[4], A,I, M
P0[2], A,I, M
P0[0], A,I, M
P1[4],EXTCLK,M
P1[2],M
SOIC
Vss
M,I2C SCL,P1[1]
Vss
P1[0],I2CSDA,M
Table 3. Pin Definitions - CY8C21234 16-Pin (SOIC)
Type
Pin No.
Name
Description
Digital
IO
Analog
I, M
1
P0[7]
Analog column mux input.
Analog column mux input.
2
IO
I, M
I, M
I, M
P0[5]
P0[3]
P0[1]
SMP
Vss
3
IO
Analog column mux input, integrating input.
Analog column mux input, integrating input.
Switch Mode Pump (SMP) connection to required external components.
Ground connection.
4
IO
5
Power
Power
IO
6
7
M
P1[1]
Vss
I2C Serial Clock (SCL), ISSP-SCLK*.
Ground connection.
8
Power
IO
9
M
P1[0]
P1[2]
P1[4]
P0[0]
P0[2]
P0[4]
P0[6]
Vdd
I2C Serial Data (SDA), ISSP-SDATA*.
10
11
12
13
14
15
16
IO
M
IO
M
Optional External Clock Input (EXTCLK).
Analog column mux input.
Analog column mux input.
Analog column mux input.
Analog column mux input.
Supply voltage.
IO
I, M
I, M
I, M
I, M
IO
IO
IO
Power
LEGEND A = Analog, I = Input, O = Output, and M = Analog Mux Input.
* These are the ISSP pins, which are not High Z at POR (Power On Reset). See the PSoC Mixed-Signal Array Technical Reference Manual for details.
Document Number: 38-12025 Rev. *M
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20-Pin Part Pinout
Figure 6. CY8C21334 20-Pin PSoC Device
A, I,M, P0[7]
A, I,M, P0[5]
A, I,M, P0[3]
A, I,M, P0[1]
Vss
Vdd
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
P0[6], A,I, M
P0[4], A,I, M
P0[2], A,I, M
P0[0], A,I, M
XRES
P1[6],M
P1[4],EXTCLK,M
P1[2],M
SSOP
M,I2C SCL,P1[7]
M,I2C SDA,P1[5]
M,P1[3]
M,I2C
SCL,P1[1]
Vss
P1[0],I2C SDA,M
10
Table 4. Pin Definitions - CY8C21334 20-Pin (SSOP)
Type
Pin No.
Name
Description
Digital
IO
Analog
I, M
1
P0[7]
P0[5]
P0[3]
P0[1]
Vss
Analog column mux input.
Analog column mux input.
2
IO
I, M
I, M
I, M
3
IO
Analog column mux input, integrating input.
Analog column mux input, integrating input.
Ground connection.
4
IO
5
Power
IO
6
M
M
M
M
P1[7]
P1[5]
P1[3]
P1[1]
Vss
I2C Serial Clock (SCL).
7
IO
I2C Serial Data (SDA).
8
IO
9
IO
I2C Serial Clock (SCL), ISSP-SCLK*.
Ground connection.
10
11
12
13
14
15
16
17
18
19
20
Power
IO
M
M
M
M
P1[0]
P1[2]
P1[4]
P1[6]
I2C Serial Data (SDA), ISSP-SDATA*.
IO
IO
Optional External Clock Input (EXTCLK).
IO
Input
IO
XRES Active high external reset with internal pull down.
I, M
I, M
I, M
I, M
P0[0]
P0[2]
P0[4]
P0[6]
Vdd
Analog column mux input.
Analog column mux input.
Analog column mux input.
Analog column mux input.
Supply voltage.
IO
IO
IO
Power
LEGEND A = Analog, I = Input, O = Output, and M = Analog Mux Input.
* These are the ISSP pins, which are not High Z at POR (Power On Reset). See the PSoC Mixed-Signal Array Technical Reference Manual for details.
Document Number: 38-12025 Rev. *M
Page 9 of 43
[+] Feedback
CY8C21634, CY8C21534
CY8C21434, CY8C21334, CY8C21234
28-Pin Part Pinout
Figure 7. CY8C21534 28-Pin PSoC Device
A, I,M, P0[7]
A, I,M, P0[5]
A, I,M, P0[3]
A, I,M, P0[1]
M,P2[7]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Vdd
28
27
26
25
24
23
22
21
20
19
18
17
16
15
P0[6], A,I, M
P0[4], A,I, M
P0[2], A,I, M
P0[0], A,I, M
P2[6],M
M,P2[5]
M, P2[3]
M, P2[1]
P2[4],M
P2[2],M
SSOP
Vss
P2[0],M
XRES
P1[6],M
M,I2C SCL,P1[7]
M,I2C SDA,P1[5]
M,P1[3]
P1[4],EXTCLK,M
P1[2],M
P1[0],I2CSDA,M
M,I2C SCL,P1[1]
Vss
Table 5. Pin Definitions - CY8C21534 28-Pin (SSOP)
Type
Pin No.
Name
Description
Digital
Analog
I, M
1
2
3
4
5
6
7
8
9
IO
IO
IO
IO
IO
IO
IO
IO
P0[7]
Analog column mux input.
I, M
I, M
I, M
M
P0[5]
P0[3]
P0[1]
P2[7]
P2[5]
P2[3]
P2[1]
Vss
Analog column mux input and column output.
Analog column mux input and column output, integrating input.
Analog column mux input, integrating input.
M
I, M
I, M
Direct switched capacitor block input.
Direct switched capacitor block input.
Ground connection.
Power
IO
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
M
M
M
M
P1[7]
P1[5]
P1[3]
P1[1]
Vss
I2C Serial Clock (SCL).
IO
I2C Serial Data (SDA).
IO
IO
I2C Serial Clock (SCL), ISSP-SCLK*.
Ground connection.
Power
IO
M
M
M
M
P1[0]
P1[2]
P1[4]
P1[6]
XRES
P2[0]
P2[2]
P2[4]
P2[6]
P0[0]
P0[2]
P0[4]
P0[6]
Vdd
I2C Serial Data (SDA), ISSP-SDATA*.
IO
IO
Optional External Clock Input (EXTCLK).
IO
Input
IO
Active high external reset with internal pull down.
Direct switched capacitor block input.
I, M
I, M
M
IO
Direct switched capacitor block input.
IO
IO
M
IO
I, M
I, M
I, M
I, M
Analog column mux input.
Analog column mux input.
Analog column mux input
Analog column mux input.
Supply voltage.
IO
IO
IO
Power
LEGEND A: Analog, I: Input, O = Output, and M = Analog Mux Input.
* These are the ISSP pins, which are not High Z at POR (Power On Reset). See the PSoC Mixed-Signal Array Technical Reference Manual for details.
Document Number: 38-12025 Rev. *M
Page 10 of 43
[+] Feedback
CY8C21634, CY8C21534
CY8C21434, CY8C21334, CY8C21234
32-Pin Part Pinout
Figure 9. CY8C21634 32-Pin PSoC Device
Figure 8. CY8C21434 32-Pin PSoC Device
Figure 10. CY8C21434 32-Pin Sawn PSoC Device
Figure 11. CY8C21634 32-Pin Sawn PSoC Device
A, I, M, P0[1]
M, P2[7]
M, P2[5]
M, P2[3]
M, P2[1]
M, P3[3]
A, I, M, P0[1]
M, P2[7]
M, P2[5]
M, P2[3]
M, P2[1]
SMP
1
2
3
4
5
6
7
8
P0[0], A, I, M
1
2
3
4
5
6
7
8
P0[0], A, I, M
24
24
23 P2[6], M
22 P2[4], M
P2[2], M
20 P2[0], M
P3[2], M
23 P2[6], M
22 P2[4], M
P2[2], M
20 P2[0], M
P3[2], M
21
21
QFN
(Top View)
QFN
(Top View)
19
19
M, P3[1]
M, 12C SCL, P1[7]
Vss
18 P3[0], M
17 XRES
18 P3[0], M
17 XRES
M, 12C SCL, P1[7]
Document Number: 38-12025 Rev. *M
Page 11 of 43
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CY8C21634, CY8C21534
CY8C21434, CY8C21334, CY8C21234
Table 6. Pin Definitions - CY8C21434/CY8C21634 32-Pin (QFN**)
Type
Analog
I, M
Pin
No.
Name
P0[1]
Description
Digital
IO
1
2
3
4
5
6
6
Analog column mux input, integrating input.
IO
M
M
M
M
M
P2[7]
P2[5]
P2[3]
P2[1]
P3[3]
SMP
IO
IO
IO
IO
In CY8C21434 part.
Power
Switch Mode Pump (SMP) connection to required external components in
CY8C21634 part.
7
7
8
9
IO
M
P3[1]
Vss
In CY8C21434 part.
Power
IO
Ground connection in CY8C21634 part.
I2C Serial Clock (SCL).
M
M
M
M
P1[7]
P1[5]
P1[3]
P1[1]
Vss
IO
I2C Serial Data (SDA).
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
IO
IO
I2C Serial Clock (SCL), ISSP-SCLK*.
Ground connection.
Power
IO
M
M
M
M
P1[0]
P1[2]
P1[4]
P1[6]
XRES
P3[0]
P3[2]
P2[0]
P2[2]
P2[4]
P2[6]
P0[0]
P0[2]
P0[4]
P0[6]
Vdd
I2C Serial Data (SDA), ISSP-SDATA*.
IO
IO
Optional External Clock Input (EXTCLK).
IO
Input
IO
Active high external reset with internal pull down.
M
IO
M
IO
M
IO
M
IO
M
IO
M
IO
I, M
I, M
I, M
I, M
Analog column mux input.
Analog column mux input.
Analog column mux input.
Analog column mux input.
Supply voltage.
IO
IO
IO
Power
IO
I, M
I, M
I, M
P0[7]
P0[5]
P0[3]
Vss
Analog column mux input.
Analog column mux input.
Analog column mux input, integrating input.
Ground connection.
IO
IO
Power
LEGEND A = Analog, I = Input, O = Output, and M = Analog Mux Input.
* These are the ISSP pins, which are not High Z at POR (Power On Reset). See the PSoC Mixed-Signal Array Technical Reference Manual for details.
** The center pad on the QFN package must be connected to ground (Vss) for best mechanical, thermal, and electrical performance. If not connected to ground, it must
be electrically floated and not connected to any other signal.
Document Number: 38-12025 Rev. *M
Page 12 of 43
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CY8C21634, CY8C21534
CY8C21434, CY8C21334, CY8C21234
56-Pin Part Pinout
The 56-pin SSOP part is for the CY8C21001 On-Chip Debug (OCD) PSoC device.
Note This part is only used for in-circuit debugging. It is NOT available for production.
Figure 12. CY8C21001 56-Pin PSoC Device
Vss
56
55
Vdd
1
2
AI, P0[7]
AI, P0[5]
AI, P0[3]
P0[6], AI
P0[4], AI
P0[2], AI
3
4
5
6
54
53
AI, P0[1]
P2[7]
P2[5]
P2[3]
P2[1]
NC
P0[0], AI
P2[6]
52
51
P2[4]
P2[2]
P2[0]
NC
7
8
9
50
49
48
10
47
46
45
44
43
42
41
40
39
38
37
36
35
34
NC
NC
NC
NC
11
12
13
P3[2]
P3[0]
CCLK
HCLK
XRES
NC
OCDE
OCDO
SMP
14
SSOP
15
16
17
Vss
Vss
NC
NC
NC
18
19
20
P3[3]
P3[1]
NC
NC
21
22
23
NC
NC
P1[6]
I2C SCL, P1[7]
P1[4], EXTCLK
P1[2]
I2C SDA, P1[5]
NC
24
25
33
32
P1[3]
SCLK, I2C SCL, P1[1]
Vss
P1[0], I2C
NC
SDA, SDATA
26
27
28
31
30
NC
29
Table 7. Pin Definitions - CY8C21001 56-Pin (SSOP)
Type
Pin No.
Pin Name
Description
Digital
Power
Analog
1
Vss
Ground connection.
Analog column mux input.
2
IO
IO
IO
IO
IO
IO
IO
IO
I
I
I
I
P0[7]
P0[5]
P0[3]
P0[1]
P2[7]
P2[5]
P2[3]
P2[1]
NC
3
Analog column mux input and column output.
Analog column mux input and column output.
Analog column mux input.
4
5
6
7
8
I
I
Direct switched capacitor block input.
Direct switched capacitor block input.
No connection.
9
10
11
12
13
14
15
16
17
18
19
NC
No connection.
NC
No connection.
NC
No connection.
OCD
OCD
Power
Power
Power
IO
OCDE
OCDO
SMP
Vss
OCD even data IO.
OCD odd data output.
Switch Mode Pump (SMP) connection to required external components.
Ground connection.
Vss
Ground connection.
P3[3]
Document Number: 38-12025 Rev. *M
Page 13 of 43
[+] Feedback
CY8C21634, CY8C21534
CY8C21434, CY8C21334, CY8C21234
Table 7. Pin Definitions - CY8C21001 56-Pin (SSOP) (continued)
Type
Pin No.
20
Pin Name
Description
Digital
Analog
IO
P3[1]
NC
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
No connection.
No connection.
NC
IO
IO
P1[7]
P1[5]
NC
I2C Serial Clock (SCL).
I2C Serial Data (SDA).
No connection.
IO
IO
P1[3]
P1[1]
Vss
I
.
FMTEST
Crystal Input (XTALin), I2C Serial Clock (SCL), ISSP-SCLK*.
Ground connection.
Power
NC
No connection.
NC
No connection.
IO
IO
IO
IO
P1[0]
P1[2]
P1[4]
P1[6]
NC
Crystal Output (XTALout), I2C Serial Data (SDA), ISSP-SDATA*.
V
.
FMTEST
Optional External Clock Input (EXTCLK).
No connection.
NC
No connection.
NC
No connection.
NC
No connection.
NC
No connection.
NC
No connection.
Input
OCD
OCD
IO
XRES
HCLK
CCLK
P3[0]
P3[2]
NC
Active high external reset with internal pull down.
OCD high-speed clock output.
OCD CPU clock output.
IO
No connection.
No connection.
NC
IO
I
I
P2[0]
P2[2]
P2[4]
P2[6]
P0[0]
P0[2]
P0[4]
P0[6]
Vdd
IO
IO
IO
IO
I
I
I
I
Analog column mux input.
IO
Analog column mux input and column output.
Analog column mux input and column output.
Analog column mux input.
IO
IO
Power
Supply voltage.
LEGEND: A = Analog, I = Input, O = Output, and OCD = On-Chip Debug.
* These are the ISSP pins, which are not High Z at POR (Power On Reset). See the PSoC Mixed-Signal Array Technical Reference Manual for details.
Document Number: 38-12025 Rev. *M
Page 14 of 43
[+] Feedback
CY8C21634, CY8C21534
CY8C21434, CY8C21334, CY8C21234
Register Reference
This chapter lists the registers of the CY8C21x34 PSoC device. For detailed register information, refer the PSoC Mixed-Signal Array
Technical Reference Manual.
Register Conventions
The register conventions specific to this section are listed in Table 8.
Table 8. Register Conventions
Convention
Description
Read register or bit(s)
R
W
L
Write register or bit(s)
Logical register or bit(s)
Clearable register or bit(s)
Access is bit specific
C
#
Register Mapping Tables
The PSoC device has a total register address space of 512 bytes. The register space is referred to as IO space and is divided into
two banks. The XOI bit in the Flag register (CPU_F) determines which bank the user is currently in. When the XOI bit is set the user
is in Bank 1.
Note In the following register mapping tables, blank fields are Reserved and must not be accessed.
Table 9. Register Map 0 Table: User Space
PRT0DR
PRT0IE
PRT0GS
PRT0DM2
PRT1DR
PRT1IE
PRT1GS
PRT1DM2
PRT2DR
PRT2IE
PRT2GS
PRT2DM2
PRT3DR
PRT3IE
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
ASE10CR0
ASE11CR0
80
81
82
83
84
85
86
87
88
89
8A
8B
8C
8D
8E
8F
90
91
92
93
94
95
96
97
98
99
9A
9B
9C
9D
9E
9F
RW
RW
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
DD
DE
DF
PRT3GS
PRT3DM2
CUR_PP
STK_PP
RW
RW
IDX_PP
RW
RW
RW
RW
#
RW
#
RW
RW
MVR_PP
MVW_PP
I2C_CFG
I2C_SCR
I2C_DR
I2C_MSCR
INT_CLR0
INT_CLR1
INT_CLR3
INT_MSK3
RW
RW
Blank fields are Reserved and must not be accessed.
# Access is bit specific.
Document Number: 38-12025 Rev. *M
Page 15 of 43
[+] Feedback
CY8C21634, CY8C21534
CY8C21434, CY8C21334, CY8C21234
Table 9. Register Map 0 Table: User Space (continued)
DBB00DR0
DBB00DR1
DBB00DR2
DBB00CR0
DBB01DR0
DBB01DR1
DBB01DR2
DBB01CR0
DCB02DR0
DCB02DR1
DCB02DR2
DCB02CR0
DCB03DR0
DCB03DR1
DCB03DR2
DCB03CR0
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
#
AMX_IN
AMUXCFG
PWM_CR
60
61
62
63
64
65
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73
74
75
76
77
78
79
7A
7B
7C
7D
7E
7F
RW
RW
RW
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
BA
BB
BC
BD
BE
BF
INT_MSK0
INT_MSK1
INT_VC
E0
E1
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FD
FE
FF
RW
RW
RC
W
W
RW
#
RES_WDT
#
CMP_CR0
CMP_CR1
#
W
RW
#
RW
DEC_CR0
DEC_CR1
RW
RW
#
#
#
ADC0_CR
ADC1_CR
W
RW
#
#
TMP_DR0
TMP_DR1
TMP_DR2
TMP_DR3
RW
RW
RW
RW
W
RW
#
RDI0RI
RDI0SYN
RDI0IS
RDI0LT0
RDI0LT1
RDI0RO0
RDI0RO1
RW
RW
RW
RW
RW
RW
RW
ACE00CR1
ACE00CR2
RW
RW
ACE01CR1
ACE01CR2
RW
RW
CPU_F
RL
DAC_D
CPU_SCR1
CPU_SCR0
RW
#
#
Blank fields are Reserved and must not be accessed.
# Access is bit specific.
Table 10. Register Map 1 Table: Configuration Space
PRT0DM0
PRT0DM1
PRT0IC0
PRT0IC1
PRT1DM0
PRT1DM1
PRT1IC0
PRT1IC1
PRT2DM0
PRT2DM1
PRT2IC0
PRT2IC1
PRT3DM0
PRT3DM1
PRT3IC0
PRT3IC1
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
ASE10CR0
ASE11CR0
80
81
82
83
84
85
86
87
88
89
8A
8B
8C
8D
8E
8F
90
91
92
93
94
RW
RW
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
D0
D1
D2
D3
D4
GDI_O_IN
GDI_E_IN
GDI_O_OU
GDI_E_OU
RW
RW
RW
RW
12
13
14
Blank fields are Reserved and must not be accessed.
# Access is bit specific.
Document Number: 38-12025 Rev. *M
Page 16 of 43
[+] Feedback
CY8C21634, CY8C21534
CY8C21434, CY8C21334, CY8C21234
Table 10. Register Map 1 Table: Configuration Space (continued)
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
55
56
57
58
59
5A
5B
5C
5D
5E
5F
60
61
62
63
95
96
97
98
D5
D6
D7
D8
D9
DA
DB
DC
MUX_CR0
MUX_CR1
MUX_CR2
MUX_CR3
RW
RW
RW
RW
99
9A
9B
9C
9D
9E
9F
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
BA
BB
BC
BD
BE
BF
OSC_GO_EN DD
RW
RW
RW
RW
RW
RW
RW
R
OSC_CR4
OSC_CR3
OSC_CR0
OSC_CR1
OSC_CR2
VLT_CR
VLT_CMP
ADC0_TR
ADC1_TR
DE
DF
E0
E1
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FD
FE
FF
DBB00FN
DBB00IN
DBB00OU
RW
RW
RW
CLK_CR0
CLK_CR1
ABF_CR0
AMD_CR0
RW
RW
RW
RW
RW
DBB01FN
DBB01IN
DBB01OU
RW
RW
RW
CMP_GO_EN 64
65
RW
RW
AMD_CR1
ALT_CR0
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73
74
75
76
77
78
79
7A
7B
7C
7D
7E
7F
RW
RW
DCB02FN
DCB02IN
DCB02OU
RW
RW
RW
IMO_TR
ILO_TR
BDG_TR
ECO_TR
W
W
RW
W
CLK_CR3
TMP_DR0
TMP_DR1
TMP_DR2
TMP_DR3
RW
RW
RW
RW
RW
DCB03FN
DCB03IN
DCB03OU
RW
RW
RW
RDI0RI
RDI0SYN
RDI0IS
RDI0LT0
RDI0LT1
RDI0RO0
RDI0RO1
RW
RW
RW
RW
RW
RW
RW
ACE00CR1
ACE00CR2
RW
RW
ACE01CR1
ACE01CR2
RW
RW
CPU_F
RL
FLS_PR1
RW
DAC_CR
CPU_SCR1
CPU_SCR0
RW
#
#
Blank fields are Reserved and must not be accessed.
# Access is bit specific.
Document Number: 38-12025 Rev. *M
Page 17 of 43
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CY8C21434, CY8C21334, CY8C21234
Electrical Specifications
This section presents the DC and AC electrical specifications of the CY8C21x34 PSoC device. For up to date electrical specifications,
visit the web site http://www.cypress.com/psoc.
o
o
o
Specifications are valid for -40 C ≤ T ≤ 85 C and T ≤ 100 C as specified, except where noted.
A
J
Refer Table 25 on page 26 for the electrical specifications on the internal main oscillator (IMO) using SLIMO mode.
Figure 13. Voltage versus CPU Frequency
Figure 14. IMO Frequency Trim Options
5.25
4.75
5.25
4.75
SLIMO
Mode=1
SLIMO
Mode=0
3.60
3.00
2.40
SLIMO
Mode=1
SLIMO
Mode=0
3.00
2.40
SLIMO SLIMO
Mode=1 Mode=1
93 kHz
12 MHz
CPUFrequency
24 MHz
3 MHz
93 kHz
6 MHz
12 MHz
24 MHz
IMOFrequency
Table 11 lists the units of measure that are used in this section.
Table 11. Units of Measure
Symbol
Unit of Measure
degree Celsius
Symbol
Unit of Measure
microwatts
o
C
μW
mA
ms
mV
nA
ns
dB
decibels
milli-ampere
milli-second
milli-volts
fF
femto farad
hertz
Hz
KB
Kbit
kHz
kΩ
1024 bytes
1024 bits
nanoampere
nanosecond
nanovolts
kilohertz
nV
W
kilohm
ohm
MHz
MΩ
μA
μF
μH
μs
μV
μVrms
megahertz
megaohm
pA
pF
pp
ppm
ps
picoampere
picofarad
microampere
microfarad
microhenry
microsecond
microvolts
peak-to-peak
parts per million
picosecond
samples per second
sps
s
sigma: one standard deviation
volts
microvolts root-mean-square
V
Document Number: 38-12025 Rev. *M
Page 18 of 43
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CY8C21434, CY8C21334, CY8C21234
Absolute Maximum Ratings
Table 12. Absolute Maximum Ratings
Symbol
Description
Storage Temperature
Min
-55
Typ
25
Max
Units
Notes
o
T
+100
C
Higher storage temperatures
STG
reduce data retention time. Recom-
mended storage temperature is
o
o
+25 C ± 25 C. Extended duration
o
storage temperatures above 65 C
degrade reliability.
o
T
Ambient Temperature with Power Applied
Supply Voltage on Vdd Relative to Vss
DC Input Voltage
-40
–
–
–
+85
C
A
Vdd
-0.5
+6.0
V
V
V
Vss -
0.5
Vdd +
0.5
IO
V
DC Voltage Applied to Tri-state
Vss -
0.5
–
Vdd +
0.5
V
IOZ
I
Maximum Current into any Port Pin
Electro Static Discharge Voltage
Latch-up Current
-25
2000
–
–
–
–
+50
–
mA
V
MIO
ESD
LU
Human Body Model ESD.
200
mA
Operating Temperature
Table 13. Operating Temperature
Symbol
Description
Ambient Temperature
Junction Temperature
Min
-40
Typ
Max
+85
Units
Notes
o
T
–
–
C
o
A
T
-40
+100
C
The temperature rise from ambient
to junction is package specific. See
Table 40 on page 38. The user must
limit the power consumption to
comply with this requirement.
J
DC Electrical Characteristics
DC Chip-Level Specifications
Table 14 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C
≤ T ≤ 85°C, 3.0V to 3.6V and -40°C ≤ T ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ T ≤ 85°C, respectively. Typical parameters apply to
A
A
A
5V, 3.3V, or 2.7V at 25°C and are for design guidance only.
Table 14. DC Chip-Level Specifications
Symbol
Description
Min
2.40
Typ
Max
Units
Notes
Vdd
Supply Voltage
–
3
5.25
V
See Table 23 on page 24.
I
I
I
Supply Current, IMO = 24 MHz
–
–
–
4
mA
mA
mA
Conditions are Vdd = 5.0V,
T = 25 C, CPU = 3 MHz, 48 MHz
disabled. VC1 = 1.5 MHz,
VC2 = 93.75 kHz, VC3 = 0.366 kHz.
DD
o
A
Supply Current, IMO = 6 MHz using SLIMO
mode.
1.2
1.1
2
Conditions are Vdd = 3.3V,
T = 25 C, CPU = 3 MHz, clock
doubler disabled. VC1 = 375 kHz,
VC2 = 23.4 kHz, VC3 = 0.091 kHz.
DD3
DD27
o
A
Supply Current, IMO = 6 MHz using SLIMO
mode.
1.5
Conditions are Vdd = 2.55V,
T = 25 C, CPU = 3 MHz, clock
o
A
doubler disabled. VC1 = 375 kHz,
VC2 = 23.4 kHz, VC3 = 0.091 kHz.
Document Number: 38-12025 Rev. *M
Page 19 of 43
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CY8C21434, CY8C21334, CY8C21234
Table 14. DC Chip-Level Specifications (continued)
Symbol
Description
Min
Typ
2.6
Max
Units
μA
Notes
o
o
I
Sleep (Mode) Current with POR, LVD, Sleep
Timer, WDT, and internal slow oscillator active.
Mid temperature range.
–
–
4.
Vdd = 2.55V, 0 C ≤ T ≤ 40 C.
SB27
A
o
o
I
Sleep (Mode) Current with POR, LVD, Sleep
Timer, WDT, and internal slow oscillator active.
2.8
5
μA
V
Vdd = 3.3V, -40 C ≤ T ≤ 85 C.
SB
A
V
V
Reference Voltage (Bandgap)
Reference Voltage (Bandgap)
Analog Ground
1.28
1.16
1.30
1.30
1.32
1.33
Trimmed for appropriate Vdd.
Vdd = 3.0V to 5.25V.
REF
V
Trimmed for appropriate Vdd. Vdd =
2.4V to 3.0V.
REF27
AGND
V
V
V
REF
V
REF
REF
- 0.003
+ 0.003
DC General Purpose IO Specifications
The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ T ≤ 85°C, 3.0V to 3.6V and -40°C ≤ T ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ T ≤ 85°C, respectively. Typical parameters
A
A
A
apply to 5V, 3.3V, and 2.7V at 25°C and are for design guidance only.
Table 15. 5V and 3.3V DC GPIO Specifications
Symbol
Description
Min
Typ
5.6
Max
Units
Notes
R
Pull up Resistor
4
4
8
8
–
kΩ
PU
PD
OH
R
Pull down Resistor
High Output Level
5.6
–
kΩ
V
Vdd -
1.0
V
IOH = 10 mA, Vdd = 4.75 to 5.25V (8
total loads, 4 on even port pins (for
example, P0[2], P1[4]), 4 on odd port
pins (for example, P0[3], P1[5])).
V
Low Output Level
–
–
0.75
0.8
V
IOL = 25 mA, Vdd = 4.75 to 5.25V (8
total loads, 4 on even port pins (for
example, P0[2], P1[4]), 4 on odd port
pins (for example, P0[3], P1[5])).
OL
V
V
V
I
Input Low Level
–
–
V
Vdd = 3.0 to 5.25.
Vdd = 3.0 to 5.25.
IL
IH
H
Input High Level
2.1
–
–
V
Input Hysteresis
60
1
–
mV
nA
pF
Input Leakage (Absolute Value)
Capacitive Load on Pins as Input
–
–
Gross tested to 1 μA.
IL
C
–
3.5
10
Package and pin dependent.
IN
o
Temp = 25 C.
C
Capacitive Load on Pins as Output
–
3.5
10
pF
Package and pin dependent.
Temp = 25 C.
OUT
o
Table 16. 2.7V DC GPIO Specifications
Symbol Description
Min
Typ
Max
Units
Notes
R
Pull up Resistor
4
4
5.6
5.6
–
8
8
–
kΩ
kΩ
V
PU
PD
OH
R
Pull down Resistor
High Output Level
V
V
V
Vdd -
0.4
IOH = 2.5 mA (6.25 Typ), Vdd = 2.4
to 3.0V (16 mA maximum, 50 mA Typ
combined IOH budget).
Low Output Level
Input Low Level
–
–
–
–
0.75
0.75
V
V
IOL = 10 mA, Vdd = 2.4 to 3.0V (90
mA maximum combined IOL
budget).
OL
IL
Vdd = 2.4 to 3.0.
Document Number: 38-12025 Rev. *M
Page 20 of 43
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CY8C21434, CY8C21334, CY8C21234
Table 16. 2.7V DC GPIO Specifications (continued)
Symbol Description
Min
2.0
Typ
Max
Units
Notes
Vdd = 2.4 to 3.0.
V
Input High Level
Input Hysteresis
–
–
–
–
V
IH
H
V
I
–
–
–
90
1
mV
nA
pF
Input Leakage (Absolute Value)
Capacitive Load on Pins as Input
Gross tested to 1 μA.
IL
C
3.5
10
Package and pin dependent.
IN
o
Temp = 25 C.
C
Capacitive Load on Pins as Output
–
3.5
10
pF
Package and pin dependent.
Temp = 25 C.
OUT
o
DC Operational Amplifier Specifications
The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ T ≤ 85°C, 3.0V to 3.6V and -40°C ≤ T ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ T ≤ 85°C, respectively. Typical parameters
A
A
A
apply to 5V, 3.3V, or 2.7V at 25°C and are for design guidance only.
Table 17. 5V DC Operational Amplifier Specifications
Symbol
Description
Min
Typ
2.5
Max
Units
mV
Notes
V
Input Offset Voltage (absolute value)
Average Input Offset Voltage Drift
Input Leakage Current (Port 0 Analog Pins)
Input Capacitance (Port 0 Analog Pins)
–
–
–
–
15
–
OSOA
o
TCV
10
μV/ C
pA
OSOA
a
I
200
4.5
–
Gross tested to 1 μA.
EBOA
C
9.5
pF
Package and pin dependent.
Temp = 25 C.
INOA
o
V
Common Mode Voltage Range
0.0
–
Vdd - 1
V
CMOA
G
I
Open Loop Gain
–
–
80
10
–
dB
OLOA
Amplifier Supply Current
30
μA
SOA
a. Atypical behavior: IEBOA of Port 0 Pin 0 is below 1 nA at 25°C; 50 nA over temperature. Use Port 0 Pins 1-7 for the lowest leakage of 200 nA.
Table 18. 3.3V DC Operational Amplifier Specifications
Symbol
Description
Min
Typ
2.5
Max
15
Units
mV
Notes
V
Input Offset Voltage (absolute value)
Average Input Offset Voltage Drift
Input Leakage Current (Port 0 Analog Pins)
Input Capacitance (Port 0 Analog Pins)
–
–
–
–
OSOA
o
TCV
10
–
μV/ C
OSOA
a
I
200
4.5
–
pA
pF
Gross tested to 1 μA.
EBOA
C
9.5
Package and pin dependent.
Temp = 25 C.
INOA
o
V
Common Mode Voltage Range
Open Loop Gain
0
–
–
–
Vdd - 1
V
CMOA
G
I
80
10
–
dB
μA
OLOA
Amplifier Supply Current
30
SOA
a.Atypical behavior: IEBOA of Port 0 Pin 0 is below 1 nA at 25°C; 50 nA over temperature. Use Port 0 Pins 1-7 for the lowest leakage of 200 nA.
Table 19. 2.7V DC Operational Amplifier Specifications
Symbol
Description
Min
Typ
Max
15
Units
mV
Notes
V
Input Offset Voltage (absolute value)
Average Input Offset Voltage Drift
Input Leakage Current (Port 0 Analog Pins)
Input Capacitance (Port 0 Analog Pins)
–
–
–
–
2.5
10
OSOA
o
TCV
–
μV/ C
OSOA
a
I
200
4.5
–
pA
pF
Gross tested to 1 μA.
EBOA
C
9.5
Package and pin dependent.
Temp = 25 C.
INOA
o
Document Number: 38-12025 Rev. *M
Page 21 of 43
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CY8C21434, CY8C21334, CY8C21234
Table 19. 2.7V DC Operational Amplifier Specifications (continued)
Symbol
Description
Common Mode Voltage Range
Open Loop Gain
Min
Typ
Max
Vdd - 1
–
Units
Notes
V
0
–
–
–
V
CMOA
G
80
10
dB
OLOA
I
Amplifier Supply Current
30
μA
SOA
a. Atypical behavior: IEBOA of Port 0 Pin 0 is below 1 nA at 25°C; 50 nA over temperature. Use Port 0 Pins 1-7 for the lowest leakage of 200 nA.
DC Low Power Comparator Specifications
Table 20 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C
≤ T ≤ 85°C, 3.0V to 3.6V and -40°C ≤ T ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ T ≤ 85°C, respectively. Typical parameters apply to
A
A
A
5V at 25°C and are for design guidance only.
Table 20. DC Low Power Comparator Specifications
Symbol
Description
Min
0.2
Typ
Max
Units
Notes
V
Low power comparator (LPC) reference
voltage range
–
Vdd - 1
V
REFLPC
I
LPC supply current
LPC voltage offset
–
–
10
40
30
μA
mV
SLPC
V
2.5
OSLPC
DC Switch Mode Pump Specifications
Table 21 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C
≤ T ≤ 85°C, 3.0V to 3.6V and -40°C ≤ T ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ T ≤ 85°C, respectively. Typical parameters apply to
A
A
A
5V, 3.3V, or 2.7V at 25°C and are for design guidance only.
Table 21. DC Switch Mode Pump (SMP) Specifications
Symbol
Description
Min
4.75
Typ
5.0
Max
Units
Notes
a
V
5V Output Voltage from Pump
5.25
3.60
2.80
V
V
V
Configuration of footnote.
Average, neglecting ripple.
SMP trip voltage is set to 5.0V.
PUMP5V
PUMP3V
PUMP2V
PUMP
a
V
V
3.3V Output Voltage from Pump
2.6V Output Voltage from Pump
Available Output Current
3.00
2.45
3.25
2.55
Configuration of footnote.
Average, neglecting ripple.
SMP trip voltage is set to 3.25V.
a
Configuration of footnote.
Average, neglecting ripple.
SMP trip voltage is set to 2.55V.
a
I
Configuration of footnote.
V
V
V
= 1.8V, V
= 1.5V, V
= 1.3V, V
= 5.0V
= 3.25V
= 2.55V
5
8
8
–
–
–
–
–
–
mA
mA
mA
SMP trip voltage is set to 5.0V.
SMP trip voltage is set to 3.25V.
SMP trip voltage is set to 2.55V.
BAT
BAT
BAT
PUMP
PUMP
PUMP
a
V
V
V
V
Input Voltage Range from Battery
Input Voltage Range from Battery
Input Voltage Range from Battery
1.8
1.0
1.0
–
–
–
–
5
5.0
3.3
2.8
–
V
Configuration of footnote.
BAT5V
BAT3V
BAT2V
BATSTA
SMP trip voltage is set to 5.0V.
a
V
Configuration of footnote.
SMP trip voltage is set to 3.25V.
a
V
Configuration of footnote.
SMP trip voltage is set to 2.55V.
a
o
Minimum Input Voltage from Battery to Start 1.2
Pump
V
Configuration of footnote. 0 C
o
≤ T ≤ 100. 1.25V at T = -40 C.
RT
A
A
a
ΔV
Line
Line Regulation (over Vi range)
–
–
%V
Configuration of footnote. V
is the “Vdd Value for PUMP
PUMP_
O
O
Trip” specified by the VM[2:0]
setting in the DC POR and LVD
Specification, Table 23 on page
24.
Document Number: 38-12025 Rev. *M
Page 22 of 43
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CY8C21434, CY8C21334, CY8C21234
Table 21. DC Switch Mode Pump (SMP) Specifications (continued)
Symbol
Description
Load Regulation
Min
Typ
Max
Units
Notes
a
ΔV
–
5
–
%V
Configuration of footnote. V
is the “Vdd Value for PUMP
PUMP_
O
O
Load
Trip” specified by the VM[2:0]
setting in the DC POR and LVD
Specification, Table 23 on page
24.
a
ΔV
Ripple
Output Voltage Ripple (depends on cap/load) –
100
50
–
–
mVpp
%
Configuration of footnote.
Load is 5 mA.
PUMP_
a
E
Efficiency
Efficiency
35
Configuration of footnote.
3
Load is 5 mA. SMP trip voltage
is set to 3.25V.
E
35
80
–
%
For I load = 1mA, V
=
2
PUMP
2.55V, V
= 1.3V,
BAT
10 uH inductor, 1 uF capacitor,
and Schottky diode.
F
Switching Frequency
Switching Duty Cycle
–
–
1.3
50
–
–
MHz
%
PUMP
DC
PUMP
a. L1 = 2 mH inductor, C1 = 10 mF capacitor, D1 = Schottky diode. See Figure 15.
Figure 15. Basic Switch Mode Pump Circuit
D1
Vdd
VPUMP
L1
SMP
Vss
+
C1
VBAT
Battery
PSoC
Document Number: 38-12025 Rev. *M
Page 23 of 43
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CY8C21434, CY8C21334, CY8C21234
DC Analog Mux Bus Specifications
Table 22 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C
≤ T ≤ 85°C, 3.0V to 3.6V and -40°C ≤ T ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ T ≤ 85°C, respectively. Typical parameters apply to
A
A
A
5V, 3.3V, or 2.7V at 25°C and are for design guidance only.
Table 22. DC Analog Mux Bus Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
R
Switch Resistance to Common Analog Bus
–
–
–
–
400
800
W
W
Vdd ≥ 2.7V
2.4V ≤ Vdd ≤ 2.7V
SW
R
Resistance of Initialization Switch to Vdd
800
W
VDD
DC POR and LVD Specifications
Table 23 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C
≤ T ≤ 85°C, 3.0V to 3.6V and -40°C ≤ T ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ T ≤ 85°C, respectively. Typical parameters apply to
A
A
A
5V, 3.3V, or 2.7V at 25°C and are for design guidance only.
Table 23. DC POR and LVD Specifications
Symbol
Description
Vdd Value for PPOR Trip
PORLEV[1:0] = 00b
PORLEV[1:0] = 01b
PORLEV[1:0] = 10b
Min
Typ
2.36
2.82
4.55
Max
Units
Notes
Vdd must be greater than or equal
to 2.5V during startup, reset from
the XRES pin, or reset from
Watchdog.
V
2.40
2.95
4.70
V
V
V
PPOR0
PPOR1
PPOR2
V
–
V
Vdd Value for LVD Trip
VM[2:0] = 000b
VM[2:0] = 001b
VM[2:0] = 010b
VM[2:0] = 011b
VM[2:0] = 100b
VM[2:0] = 101b
VM[2:0] = 110b
VM[2:0] = 111b
a
b
V
V
V
V
V
V
V
V
2.40
2.85
2.95
3.06
4.37
4.50
4.62
4.71
2.45
2.92
3.02
3.13
4.48
4.64
4.73
4.81
2.51
2.99
3.09
3.20
4.55
4.75
4.83
4.95
V
V
V
V
V
V
V
V
LVD0
LVD1
LVD2
LVD3
LVD4
LVD5
LVD6
LVD7
Vdd Value for PUMP Trip
VM[2:0] = 000b
VM[2:0] = 001b
VM[2:0] = 010b
VM[2:0] = 011b
VM[2:0] = 100b
VM[2:0] = 101b
VM[2:0] = 110b
VM[2:0] = 111b
c
V
V
V
V
V
V
V
V
2.45
2.96
3.03
3.18
4.54
4.62
4.71
4.89
2.55
3.02
3.10
3.25
4.64
4.73
4.82
5.00
2.62
3.09
3.16
3.32
4.74
4.83
4.92
5.12
V
V
V
V
V
V
V
V
PUMP0
PUMP1
PUMP2
PUMP3
PUMP4
PUMP5
PUMP6
PUMP7
d
a. Always greater than 50 mV above VPPOR (PORLEV = 00) for falling supply.
b. Always greater than 50 mV above VPPOR (PORLEV = 01) for falling supply.
c. Always greater than 50 mV above VLVD0
d. Always greater than 50 mV above VLVD3
.
.
Document Number: 38-12025 Rev. *M
Page 24 of 43
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DC Programming Specifications
Table 24 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C
≤ T ≤ 85°C, 3.0V to 3.6V and -40°C ≤ T ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ T ≤ 85°C, respectively. Typical parameters apply to
A
A
A
5V, 3.3V, or 2.7V at 25°C and are for design guidance only.
Table 24. DC Programming Specifications
Symbol
Vdd
Description
Min
2.70
Typ
Max
Units
Notes
Supply Voltage for Flash Write Operations
Supply Current During Programming or Verify
–
5
–
–
V
IWRITE
DDP
I
–
–
25
mA
V
V
Input Low Voltage During Programming or
Verify
0.8
ILP
V
Input High Voltage During Programming or
Verify
2.2
–
–
–
–
–
–
–
V
IHP
I
I
Input Current when Applying Vilp to P1[0] or
P1[1] During Programming or Verify
0.2
1.5
mA
mA
V
Driving internal pull down resistor.
Driving internal pull down resistor.
ILP
Input Current when Applying Vihp to P1[0] or
P1[1] During Programming or Verify
–
IHP
V
V
Output Low Voltage During Programming or
Verify
–
Vss +
0.75
OLV
Output High Voltage During Programming or Vdd -
Vdd
V
OHV
Verify
1.0
Flash
Flash
Flash Endurance (per block)
50,000 –
–
–
–
–
Erase/write cycles per block.
Erase/write cycles.
ENPB
ENT
a
Flash Endurance (total)
1,800,
000
–
–
Flash
Flash Data Retention
10
–
Years
DR
a. A maximum of 36 x 50,000 block endurance cycles is allowed. This may be balanced between operations on 36x1 blocks of 50,000 maximum
cycles each, 36x2 blocks of 25,000 maximum cycles each, or 36x4 blocks of 12,500 maximum cycles each (to limit the total number of cycles
to 36x50,000 and that no single block ever sees more than 50,000 cycles).
b
For the full industrial range, the user must employ a temperature sensor user module (FlashTemp) and feed the result to the temperature
argument before writing. Refer to the Flash APIs Application Note AN2015 at http://www.cypress.com under Application Notes for more
information.
Document Number: 38-12025 Rev. *M
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AC Electrical Characteristics
AC Chip-Level Specifications
The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ T ≤ 85°C, 3.0V to 3.6V and -40°C ≤ T ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ T ≤ 85°C, respectively. Typical parameters
A
A
A
apply to 5V, 3.3V, or 2.7V at 25°C and are for design guidance only.
Table 25. 5V and 3.3V AC Chip-Level Specifications
Symbol
Description
Min
Typ
24
Max
Units
Notes
a,b,
a,b,
a,b
F
F
Internal Main Oscillator Frequency for 24 MHz 23.4
24.6
MHz
Trimmed for 5V or 3.3V operation
using factory trim values. See
Figure 14 on page 18. SLIMO
mode = 0.
IMO24
c
Internal Main Oscillator Frequency for 6 MHz 5.75
6
6.35
MHz
MHz
Trimmed for 5V or 3.3V operation
using factory trim values. See
Figure 14 on page 18. SLIMO
mode = 1.
IMO6
c
F
F
F
CPU Frequency (5V Nominal)
CPU Frequency (3.3V Nominal)
0.93
0.93
0
24
12
48
24.6
24 MHz only for SLIMO mode = 0.
CPU1
CPU2
BLK5
12.3b,c MHz
0
a,b,
Digital PSoC Block Frequency (5V Nominal)
49.2
MHz
Refer to the AC Digital Block
Specifications.
d
b,d
F
F
Digital PSoC Block Frequency (3.3V Nominal) 0
24
24.6
64
200
–
MHz
kHz
ns
BLK33
32K1
Internal Low Speed Oscillator Frequency
32 kHz RMS Period Jitter
15
32
Jitter32k
Jitter32k
–
100
1400
–
32 kHz Peak-to-Peak Period Jitter
External Reset Pulse Width
24 MHz Duty Cycle
–
T
10
40
–
–
μs
%
XRST
DC24M
50
60
–
Step24M
Fout48M
24 MHz Trim Step Size
50
kHz
MHz
a,c
48 MHz Output Frequency
46.8
48.0
49.2
Trimmed. Using factory trim
values.
Jitter24M1 24 MHz Peak-to-Peak Period Jitter (IMO)
–
–
600
–
ps
F
Maximum frequency of signal on row input or
row output.
12.3
–
MHz
MAX
T
Supply Ramp Time
0
–
μs
RAMP
a. 4.75V < Vdd < 5.25V.
b. Accuracy derived from Internal Main Oscillator with appropriate trim for Vdd range.
c. 3.0V < Vdd < 3.6V. See Application Note AN2012 “Adjusting PSoC Microcontroller Trims for Dual Voltage-Range Operation” for information
on trimming for operation at 3.3V.
d. See the individual user module data sheets for information on maximum frequencies for user modules.
Table 26. 2.7V AC Chip-Level Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
0
a,b,
F
F
Internal Main Oscillator Frequency for 12 MHz 11.5
12
12.7
MHz
Trimmedfor2.7Voperationusing
factorytrimvalues. SeeFigure14
on page 18. SLIMO mode = 1.
IMO12
c
a,b,
Internal Main Oscillator Frequency for 6 MHz 5.75
6
6.35
MHz
Trimmedfor2.7Voperationusing
factorytrimvalues. SeeFigure14
on page 18. SLIMO mode = 1.
IMO6
c
a,b
F
F
CPU Frequency (2.7V Nominal)
0.093
3
3.15
MHz
MHz
24 MHz only for SLIMO mode = 0.
CPU1
a,b,
Digital PSoC Block Frequency (2.7V Nominal) 0
12
12.5
Refer to the AC Digital Block
Specifications.
BLK27
c
F
Internal Low Speed Oscillator Frequency
8
32
96
kHz
32K1
Document Number: 38-12025 Rev. *M
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Table 26. 2.7V AC Chip-Level Specifications (continued)
Symbol
Jitter32k
Jitter32k
Description
32 kHz RMS Period Jitter
Min
Typ
150
Max
200
Units
ns
Notes
–
–
32 kHz Peak-to-Peak Period Jitter
External Reset Pulse Width
1400
–
T
10
–
–
–
–
μs
MHz
XRST
F
Maximum frequency of signal on row input or
row output.
12.3
MAX
T
Supply Ramp Time
0
–
–
μs
RAMP
a. 2.4V < Vdd < 3.0V.
b. Accuracy derived from Internal Main Oscillator with appropriate trim for Vdd range.
c. See Application Note AN2012 “Adjusting PSoC Microcontroller Trims for Dual Voltage-Range Operation” for information on maximum
frequency for user modules.
Figure 16. 24 MHz Period Jitter (IMO) Timing Diagram
Jitter24M1
F24M
Figure 17. 32 kHz Period Jitter (ILO) Timing Diagram
Jitter32k
F32K1
AC General Purpose IO Specifications
The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ T ≤ 85°C, 3.0V to 3.6V and -40°C ≤ T ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ T ≤ 85°C, respectively. Typical parameters
A
A
A
apply to 5V, 3.3V, or 2.7V at 25°C and are for design guidance only.
Table 27. 5V and 3.3V AC GPIO Specifications
Symbol
Description
Min
Typ
Max
12
Units
MHz
ns
Notes
F
GPIO Operating Frequency
0
–
–
–
Normal Strong Mode
GPIO
TRiseF
TFallF
TRiseS
TFallS
Rise Time, Normal Strong Mode, Cload = 50 pF 3
Fall Time, Normal Strong Mode, Cload = 50 pF 2
18
18
–
Vdd = 4.5 to 5.25V, 10% - 90%
Vdd = 4.5 to 5.25V, 10% - 90%
Vdd = 3 to 5.25V, 10% - 90%
Vdd = 3 to 5.25V, 10% - 90%
ns
Rise Time, Slow Strong Mode, Cload = 50 pF
Fall Time, Slow Strong Mode, Cload = 50 pF
7
7
27
22
ns
–
ns
Table 28. 2.7V AC GPIO Specifications
Symbol
Description
Min
Typ
Max
Units
MHz
ns
Notes
F
GPIO Operating Frequency
0
–
3
Normal Strong Mode
GPIO
TRiseF
TFallF
TRiseS
TFallS
Rise Time, Normal Strong Mode, Cload = 50 pF 6
Fall Time, Normal Strong Mode, Cload = 50 pF 6
–
50
Vdd = 2.4 to 3.0V, 10% - 90%
Vdd = 2.4 to 3.0V, 10% - 90%
Vdd = 2.4 to 3.0V, 10% - 90%
Vdd = 2.4 to 3.0V, 10% - 90%
–
50
ns
Rise Time, Slow Strong Mode, Cload = 50 pF 18
Fall Time, Slow Strong Mode, Cload = 50 pF 18
40
40
120
120
ns
ns
Document Number: 38-12025 Rev. *M
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Figure 18. GPIO Timing Diagram
90%
GPIO
Pin
Output
Voltage
10%
TRiseF
TRiseS
TFallF
TFallS
AC Operational Amplifier Specifications
Table 29 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C
≤ T ≤ 85°C, 3.0V to 3.6V and -40°C ≤ T ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ T ≤ 85°C, respectively. Typical parameters apply to
A
A
A
5V, 3.3V, or 2.7V at 25°C and are for design guidance only.
Table 29. AC Operational Amplifier Specifications
Symbol
Description
Min
Typ
Max
Units
ns
ns
Notes
T
Comparator Mode Response Time, 50 mV
Overdrive
100
200
Vdd ≥ 3.0V.
2.4V < Vcc < 3.0V.
COMP
AC Low Power Comparator Specifications
Table 30 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C
≤ T ≤ 85°C, 3.0V to 3.6V and -40°C ≤ T ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ T ≤ 85°C, respectively. Typical parameters apply to
A
A
A
5V at 25°C and are for design guidance only.
Table 30. AC Low Power Comparator Specifications
Symbol
Description
LPC response time
Min
Typ
Max
Units
μs
Notes
T
–
–
50
≥ 50 mV overdrive comparator
reference set within V
RLPC
.
REFLPC
AC Analog Mux Bus Specifications
Table 31 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C
≤ T ≤ 85°C, 3.0V to 3.6V and -40°C ≤ T ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ T ≤ 85°C, respectively. Typical parameters apply to
A
A
A
5V, 3.3V, or 2.7V at 25°C and are for design guidance only.
Table 31. AC Analog Mux Bus Specifications
Symbol
Description
Min
Typ
Max
3.17
Units
Notes
F
Switch Rate
–
–
MHz
SW
Document Number: 38-12025 Rev. *M
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AC Digital Block Specifications
The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ T ≤ 85°C, 3.0V to 3.6V and -40°C ≤ T ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ T ≤ 85°C, respectively. Typical parameters
A
A
A
apply to 5V, 3.3V, or 2.7V at 25°C and are for design guidance only.
Table 32. 5V and 3.3V AC Digital Block Specifications
Function
All
Functions
Description
Min
Typ
Max
49.2
Units
MHz
MHz
ns
Notes
4.75V < Vdd < 5.25V.
3.0V < Vdd < 4.75V.
Maximum Block Clocking Frequency (> 4.75V)
Maximum Block Clocking Frequency (< 4.75V)
Capture Pulse Width
24.6
–
a
Timer
50
–
–
–
–
–
–
Maximum Frequency, No Capture
–
49.2
24.6
–
MHz
MHz
ns
4.75V < Vdd < 5.25V.
4.75V < Vdd < 5.25V.
Maximum Frequency, With or Without Capture –
Counter
Enable Pulse Width
50
Maximum Frequency, No Enable Input
Maximum Frequency, Enable Input
–
–
49.2
24.6
MHz
MHz
Dead Band Kill Pulse Width:
Asynchronous Restart Mode
20
50
50
–
–
–
–
–
–
–
ns
Synchronous Restart Mode
Disable Mode
–
ns
–
ns
Maximum Frequency
49.2
49.2
MHz
MHz
4.75V < Vdd < 5.25V.
4.75V < Vdd < 5.25V.
CRCPRS Maximum Input Clock Frequency
–
(PRS
Mode)
CRCPRS Maximum Input Clock Frequency
(CRC
Mode)
–
–
–
24.6
8.2
MHz
MHz
SPIM
Maximum Input Clock Frequency
Maximum Input Clock Frequency
–
–
Maximum data rate at 4.1 MHz
due to 2 x over clocking.
SPIS
–
–
–
4.1
–
MHz
ns
Width of SS_ Negated Between Transmissions 50
Transmitter Maximum Input Clock Frequency
–
24.6
MHz
Maximum data rate at 3.08 MHz
due to 8 x over clocking.
Maximum data rate at 6.15 MHz
due to 8 x over clocking.
Maximum Input Clock Frequency with Vdd ≥
4.75V, 2 Stop Bits
–
–
49.2
MHz
Receiver
Maximum Input Clock Frequency
–
–
–
–
24.6
49.2
MHz
MHz
Maximum data rate at 3.08 MHz
due to 8 x over clocking.
Maximum data rate at 6.15 MHz
due to 8 x over clocking.
Maximum Input Clock Frequency with Vdd ≥
4.75V, 2 Stop Bits
a. 50 ns minimum input pulse width is based on the input synchronizers running at 12 MHz (84 ns nominal period).
Document Number: 38-12025 Rev. *M
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Table 33. 2.7V AC Digital Block Specifications
Function
All
Description
Min
Typ
Max
12.7
Units
Notes
Maximum Block Clocking Frequency
MHz
2.4V < Vdd < 3.0V.
Functions
a
Timer
Capture Pulse Width
100
–
–
–
–
–
–
ns
Maximum Frequency, With or Without Capture –
12.7
–
MHz
ns
Counter
Enable Pulse Width
100
Maximum Frequency, No Enable Input
Maximum Frequency, Enable Input
–
–
12.7
12.7
MHz
MHz
Dead Band Kill Pulse Width:
Asynchronous Restart Mode
20
100
100
–
–
–
–
–
–
–
ns
Synchronous Restart Mode
Disable Mode
–
ns
–
ns
Maximum Frequency
12.7
12.7
MHz
MHz
CRCPRS Maximum Input Clock Frequency
–
(PRS
Mode)
CRCPRS Maximum Input Clock Frequency
(CRC
Mode)
–
–
–
12.7
6.35
MHz
MHz
SPIM
Maximum Input Clock Frequency
Maximum Input Clock Frequency
–
–
Maximum data rate at 3.17 MHz
due to 2 x over clocking.
SPIS
–
–
–
4.1
–
MHz
ns
Width of SS_ Negated Between Transmissions 100
Transmitter Maximum Input Clock Frequency
–
12.7
MHz
Maximum data rate at 1.59 MHz
due to 8 x over clocking.
Receiver Maximum Input Clock Frequency
–
–
12.7
MHz
Maximum data rate at 1.59 MHz
due to 8 x over clocking.
a. 100 ns minimum input pulse width is based on the input synchronizers running at 12 MHz (84 ns nominal period).
AC External Clock Specifications
The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ T ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ T ≤ 85°C, respectively. Typical parameters apply to 5V, 3.3V, or 2.7V at 25°C
A
A
and are for design guidance only.
Table 34. 5V AC External Clock Specifications
Symbol
Description
Min
Typ
Max
Units
MHz
ns
F
–
–
–
Frequency
High Period
Low Period
0.093
20.6
20.6
150
–
–
–
–
24.6
5300
–
OSCEXT
ns
Power Up IMO to Switch
–
μs
Document Number: 38-12025 Rev. *M
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Table 35. 3.3V AC External Clock Specifications
Symbol
Description
Min
Typ
Max
12.3
Units
Notes
F
Frequency with CPU Clock divide by 1
0.093
–
–
MHz
Maximum CPU frequency is 12
MHz at 3.3V. With the CPU clock
divider set to 1, the external clock
must adhere to the maximum
frequency and duty cycle
OSCEXT
requirements.
F
Frequency with CPU Clock divide by 2 or
greater
0.186
24.6
MHz
Ifthefrequencyoftheexternalclock
is greater than 12 MHz, the CPU
clock divider must be set to 2 or
greater. In this case, the CPU clock
divider ensures that the fifty percent
duty cycle requirement is met.
OSCEXT
–
–
–
High Period with CPU Clock divide by 1
Low Period with CPU Clock divide by 1
Power Up IMO to Switch
41.7
41.7
150
–
–
–
5300
ns
ns
μs
–
–
Table 36. 2.7V AC External Clock Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
0
F
Frequency with CPU Clock divide by 1
0.093
–
–
3.08
MHz
Maximum CPU frequency is 3 MHz
at 2.7V. With the CPU clock divider
set to 1, the external clock must
adhere to the maximum frequency
and duty cycle requirements.
OSCEXT
F
Frequency with CPU Clock divide by 2 or
greater
0.186
6.35
MHz
Ifthefrequencyoftheexternalclock
is greater than 3 MHz, the CPU
clock divider must be set to 2 or
greater. In this case, the CPU clock
divider ensures that the fifty percent
duty cycle requirement is met.
OSCEXT
–
–
–
High Period with CPU Clock divide by 1
Low Period with CPU Clock divide by 1
Power Up IMO to Switch
160
160
150
–
–
–
5300
ns
ns
μs
–
–
AC Programming Specifications
Table 37 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C
≤ T ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ T ≤ 85°C, respectively. Typical parameters apply to 5V, 3.3V, or 2.7V at 25°C and are for
A
A
design guidance only.
Table 37. AC Programming Specifications
Symbol
Description
Rise Time of SCLK
Fall Time of SCLK
Min
Typ
Max
20
Units
ns
Notes
T
T
T
T
F
T
1
1
–
–
–
–
–
RSCLK
FSCLK
SSCLK
HSCLK
SCLK
20
–
ns
Data Set up Time to Falling Edge of SCLK 40
Data Hold Time from Falling Edge of SCLK 40
ns
–
ns
Frequency of SCLK
0
–
8
MHz
ms
Flash Erase Time (Block)
15
–
ERASEB
Document Number: 38-12025 Rev. *M
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Table 37. AC Programming Specifications (continued)
Symbol
Description
Flash Block Write Time
Min
Typ
30
Max
Units
ms
Notes
T
T
T
T
–
–
–
–
–
WRITE
Data Out Delay from Falling Edge of SCLK
Data Out Delay from Falling Edge of SCLK
Data Out Delay from Falling Edge of SCLK
–
–
–
45
50
70
ns
ns
ns
3.6 < Vdd
DSCLK
DSCLK3
DSCLK2
3.0 ≤ Vdd ≤ 3.6
2.4 ≤ Vdd ≤ 3.0
AC I2C Specifications
The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ T ≤ 85°C, 3.0V to 3.6V and -40°C ≤ T ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ T ≤ 85°C, respectively. Typical parameters
A
A
A
apply to 5V, 3.3V, or 2.7V at 25°C and are for design guidance only.
Table 38. AC Characteristics of the I2C SDA and SCL Pins for Vdd ≥ 3.0V
Standard Mode
Min Max
Fast Mode
Symbol
Description
SCL Clock Frequency
Units
Min
Max
F
T
0
100
–
0
400
–
kHz
SCLI2C
Hold Time (repeated) START Condition.
After this period, the first clock pulse is
generated.
4.0
0.6
μs
HDSTAI2C
T
T
T
LOW Period of the SCL Clock
HIGH Period of the SCL Clock
4.7
4.0
4.7
–
–
–
1.3
0.6
0.6
–
–
–
μs
μs
μs
LOWI2C
HIGHI2C
SUSTAI2C
Set-up Time for a Repeated START
Condition
T
T
T
T
Data Hold Time
0
–
–
–
–
0
–
–
–
–
μs
ns
μs
μs
HDDATI2C
SUDATI2C
SUSTOI2C
BUFI2C
a
Data Set-up Time
250
4.0
100
0.6
1.3
Set-up Time for STOP Condition
Bus Free Time Between a STOP and START 4.7
Condition
T
Pulse Width of spikes are suppressed by the –
input filter.
–
0
50
ns
SPI2C
a. A Fast-Mode I2C-bus device may be used in a Standard-Mode I2C-bus system, but the requirement tSU;DAT ≥ 250 ns must then be met. This
is automatically the case if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the
SCL signal, it must output the next data bit to the SDA line trmax + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus
specification) before the SCL line is released.
Table 39. 2.7V AC Characteristics of the I2C SDA and SCL Pins (Fast Mode not Supported)
Standard Mode
Fast Mode
Symbol
Description
Units
Min
Max
Min
Max
F
T
SCL Clock Frequency
0
100
–
–
–
–
–
kHz
SCLI2C
Hold Time (repeated) START Condition.
After this period, the first clock pulse is
generated.
4.0
μs
HDSTAI2C
T
T
T
LOW Period of the SCL Clock
HIGH Period of the SCL Clock
4.7
4.0
4.7
–
–
–
–
–
–
–
–
–
μs
μs
μs
LOWI2C
HIGHI2C
SUSTAI2C
Set up Time for a Repeated START
Condition
T
Data Hold Time
0
–
–
–
μs
HDDATI2C
Document Number: 38-12025 Rev. *M
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CY8C21634, CY8C21534
CY8C21434, CY8C21334, CY8C21234
Table 39. 2.7V AC Characteristics of the I2C SDA and SCL Pins (Fast Mode not Supported) (continued)
Standard Mode
Min Max
Fast Mode
Symbol
Description
Units
ns
Min
Max
T
T
T
Data Set-up Time
Set up Time for STOP Condition
250
4.0
–
–
–
–
–
–
–
–
–
SUDATI2C
SUSTOI2C
BUFI2C
μs
μs
Bus Free Time Between a STOP and START 4.7
Condition
T
Pulse Width of spikes are suppressed by the –
input filter.
–
–
–
ns
SPI2C
Figure 19. Definition for Timing for Fast/Standard Mode on the I2C Bus
SDA
SCL
TSPI2C
T
LOWI2C
TSUDATI2C
THDSTAI2C
TBUFI2C
TSUSTOI2C
TSUSTAI2C
THDDATI2C
THDSTAI2C
THIGHI2C
S
Sr
P
S
Document Number: 38-12025 Rev. *M
Page 33 of 43
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CY8C21634, CY8C21534
CY8C21434, CY8C21334, CY8C21234
Packaging Information
This section shows the packaging specifications for the CY8C21x34 PSoC device with the thermal impedances for each package.
Important Note Emulation tools may require a larger area on the target PCB than the chip’s footprint. For a detailed description of
the emulation tools’ dimensions, refer to the document titled PSoC Emulator Pod Dimensions at
http://www.cypress.com/design/MR10161.
Packaging Dimensions
Figure 20. 16-Pin (150-Mil) SOIC
PIN 1 ID
8
1
DIMENSIONS IN INCHES[MM] MIN.
MAX.
REFERENCE JEDEC MS-012
PACKAGE WEIGHT 0.15gms
0.150[3.810]
0.157[3.987]
0.230[5.842]
0.244[6.197]
PART #
S16.15 STANDARD PKG.
SZ16.15 LEAD FREE PKG.
9
16
0.010[0.254]
0.016[0.406]
X 45°
0.386[9.804]
0.393[9.982]
SEATING PLANE
0.061[1.549]
0.068[1.727]
0.004[0.102]
0.050[1.270]
BSC
0.0075[0.190]
0.0098[0.249]
0.016[0.406]
0.035[0.889]
0°~8°
0.0138[0.350]
0.0192[0.487]
0.004[0.102]
0.0098[0.249]
51-85068 *B
Figure 21. 20-Pin (210-MIL) SSOP
51-85077 *C
Document Number: 38-12025 Rev. *M
Page 34 of 43
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CY8C21634, CY8C21534
CY8C21434, CY8C21334, CY8C21234
Figure 22. 28-Pin (210-Mil) SSOP
51-85079 *C
Figure 23. 32-Pin (5x5 mm 0.93 MAX) QFN
E-PAD X, Y for this product is 3.53 mm, 3.53 mm (+/-0.11 mm)
51-85188 *B
Document Number: 38-12025 Rev. *M
Page 35 of 43
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CY8C21634, CY8C21534
CY8C21434, CY8C21334, CY8C21234
Figure 24. 32-Pin (5x5 mm 0.60 MAX) QFN
E-PAD X, Y for this product is 3.53 mm, 3.53 mm (+/-0.11 mm)
001-06392 *A
Important Note For information on the preferred dimensions for mounting QFN packages, see the following Application Note at
http://www.amkor.com/products/notes_papers/MLFAppNote.pdf.
Figure 25. 32-Pin Sawn QFN Package
SIDE VIEW
TOP VIEW
BOTTOM VIEW
3.50
0.50
4.90
5.10
(0.93 MAX)
PIN #1 CORNER
0.20 DIA TYP.
0.23±0.05
0.20 REF
PIN #1 I.D.
R0.20
N
N
1
2
1
2
0.45
SOLDERABLE
EXPOSED
4.90
5.10
3.50
3.50
PAD
-0.20
2X
(0.05 MAX)
2X
3.50
001-30999 **
Document Number: 38-12025 Rev. *M
Page 36 of 43
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CY8C21634, CY8C21534
CY8C21434, CY8C21334, CY8C21234
Figure 26. 32-Pin Thin Sawn QFN Package
SIDE VIEW
TOP VIEW
BOTTOM VIEW
3.55
0.50
4.90
5.10
R
PIN #1 CORNER
0.20 DIA TYP.
0.23 +/-0.05
R0.30
N
N
1
2
1
2
0.45
SOLDERABLE
EXPOSED
PAD
4.90
5.10
3.55
3.5
2X
-0.20
(0.05 MAX)
2X
3.5
NOTES:
1.
HATCH AREA IS SOLDERABLE EXPOSED PAD
2. BASED ON REF JEDEC # MO-248
3. PACKAGE WEIGHT: 0.0388g
4. DIMENSIONS ARE IN MILLIMETERS [MIN/MAX]
5. MAXIMUM ALLOWABLE BURRS IS 0.076mm
IN ALL DIRECTIONS.
6. PACKAGE CODE
PART NO.
LR32D
DESCRIPTION
STANDARD
PB-FREE
001-42168 *A
LQ32D
Figure 27. 56-Pin (300-Mil) SSOP
51-85062 *C
Document Number: 38-12025 Rev. *M
Page 37 of 43
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CY8C21434, CY8C21334, CY8C21234
Thermal Impedances
Table 40. Thermal Impedances per Package
Package
Typical θ
*
Typical θ
JA
JC
o
o
16 SOIC
123 C/W
55 C/W
o
o
20 SSOP
117 C/W
41 C/W
o
o
28 SSOP
96 C/W
39 C/W
o
o
32 QFN** 5x5 mm 0.60 MAX
32 QFN** 5x5 mm 0.93 MAX
27 C/W
15 C/W
o
o
22 C/W
12 C/W
* TJ = TA + Power x θ
JA
** To achieve the thermal impedance specified for the QFN package, the center thermal pad must be soldered to the PCB ground plane.
Solder Reflow Peak Temperature
Following is the minimum solder reflow peak temperature to achieve good solderability.
Table 41. Solder Reflow Peak Temperature
Package
Minimum Peak Temperature*
Maximum Peak Temperature
o
o
16 SOIC
20 SSOP
28 SSOP
32 QFN
240 C
260 C
o
o
240 C
260 C
o
o
240 C
260 C
o
o
240 C
260 C
*Higher temperatures may be required based on the solder melting point. Typical temperatures for solder are 220 ± 5oC with Sn-Pb or 245 ± 5oC with
Sn-Ag-Cu paste. Refer to the solder manufacturer specifications.
Document Number: 38-12025 Rev. *M
Page 38 of 43
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CY8C21634, CY8C21534
CY8C21434, CY8C21334, CY8C21234
■ Mini-Eval Programming Board
Development Tool Selection
■ 110 ~ 240V Power Supply, Euro-Plug Adapter
■ iMAGEcraft C Compiler (Registration Required)
■ ISSP Cable
This section presents the development tools available for all
current PSoC device families including the CY8C21x34 family.
Software
■ USB 2.0 Cable and Blue Cat-5 Cable
■ 2 CY8C29466-24PXI 28-PDIP Chip Samples
PSoC Designer™
At the core of the PSoC development software suite is PSoC
Designer. Used by thousands of PSoC developers, this robust
software has been facilitating PSoC designs for half a decade.
PSoC Designer is available free of charge at
http://www.cypress.com under DESIGN RESOURCES >>
Software and Drivers.
CY3210-ExpressDK PSoC Express Development Kit
The CY3210-ExpressDK is for advanced prototyping and
development with PSoC Express (may be used with ICE-Cube
2
In-Circuit Emulator). It provides access to I C buses, voltage
reference, switches, upgradeable modules and more. The kit
includes:
PSoC Express™
As the newest addition to the PSoC development software suite,
PSoC Express is the first visual embedded system design tool
that allows a user to create an entire PSoC project and generate
a schematic, BOM, and data sheet without writing a single line
of code. Users work directly with application objects such as
LEDs, switches, sensors, and fans. PSoC Express is available
free of charge at http://www.cypress.com/psocexpress.
■ PSoC Express Software CD
■ Express Development Board
■ 4 Fan Modules
■ 2 Proto Modules
■ MiniProg In-System Serial Programmer
■ MiniEval PCB Evaluation Board
■ Jumper Wire Kit
PSoC Programmer
Flexible enough to be used on the bench in development, yet
suitable for factory programming, PSoC Programmer works
either as a standalone programming application or operates
directly from PSoC Designer or PSoC Express. PSoC
Programmer software is compatible with both PSoC ICE-Cube
In-Circuit Emulator and PSoC MiniProg. PSoC programmer is
available free ofcharge at http://www.cypress.com/psocpro-
grammer.
■ USB 2.0 Cable
■ Serial Cable (DB9)
■ 110 ~ 240V Power Supply, Euro-Plug Adapter
■ 2 CY8C24423A-24PXI 28-PDIP Chip Samples
■ 2 CY8C27443-24PXI 28-PDIP Chip Samples
■ 2 CY8C29466-24PXI 28-PDIP Chip Samples
CY3202-C iMAGEcraft C Compiler
CY3202 is the optional upgrade to PSoC Designer that enables
the iMAGEcraft C compiler. It can be purchased from the
Cypress Online Store. At http://www.cypress.com, click the
Online Store shopping cart icon at the bottom of the web page,
and click PSoC (Programmable System-on-Chip) to view a
current list of available items.
Evaluation Tools
All evaluation tools can be purchased from the Cypress Online
Store.
CY3210-MiniProg1
Development Kits
The CY3210-MiniProg1 kit allows a user to program PSoC
devices through the MiniProg1 programming unit. The MiniProg
is a small, compact prototyping programmer that connects to the
PC through a provided USB 2.0 cable. The kit includes:
All development kits can be purchased from the Cypress Online
Store.
CY3215-DK Basic Development Kit
The CY3215-DK is for prototyping and development with PSoC
Designer. This kit supports in-circuit emulation and the software
interface allows users to run, halt, and single step the processor
and view the content of specific memory locations. Advance
emulation features also supported through PSoC Designer. The
kit includes:
■ MiniProg Programming Unit
■ MiniEval Socket Programming and Evaluation Board
■ 28-Pin CY8C29466-24PXI PDIP PSoC Device Sample
■ 28-Pin CY8C27443-24PXI PDIP PSoC Device Sample
■ PSoC Designer Software CD
■ PSoC Designer Software CD
■ ICE-Cube In-Circuit Emulator
■ ICE Flex-Pod for CY8C29x66 Family
■ Cat-5 Adapter
■ Getting Started Guide
■ USB 2.0 Cable
Document Number: 38-12025 Rev. *M
Page 39 of 43
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CY8C21634, CY8C21534
CY8C21434, CY8C21334, CY8C21234
CY3210-PSoCEval1
Device Programmers
The CY3210-PSoCEval1 kit features an evaluation board and
the MiniProg1 programming unit. The evaluation board includes
an LCD module, potentiometer, LEDs, and plenty of bread-
boarding space to meet all of your evaluation needs. The kit
includes:
All device programmers can be purchased from the Cypress
Online Store.
CY3216 Modular Programmer
The CY3216 Modular Programmer kit features a modular
programmer and the MiniProg1 programming unit. The modular
programmer includes three programming module cards and
supports multiple Cypress products. The kit includes:
■ Evaluation Board with LCD Module
■ MiniProg Programming Unit
■ 28-Pin CY8C29466-24PXI PDIP PSoC Device Sample (2)
■ PSoC Designer Software CD
■ Getting Started Guide
■ Modular Programmer Base
■ 3 Programming Module Cards
■ MiniProg Programming Unit
■ PSoC Designer Software CD
■ Getting Started Guide
■ USB 2.0 Cable
CY3214-PSoCEvalUSB
The CY3214-PSoCEvalUSB evaluation kit features
a
■ USB 2.0 Cable
development board for the CY8C24794-24LFXI PSoC device.
Special features of the board include both USB and capacitive
sensing development and debugging support. This evaluation
board also includes an LCD module, potentiometer, LEDs, an
enunciator and plenty of bread boarding space to meet all of your
evaluation needs. The kit includes:
CY3207ISSP In-System Serial Programmer (ISSP)
The CY3207ISSP is a production programmer. It includes
protection circuitry and an industrial case that is more robust than
the MiniProg in a production-programming environment.
Note CY3207ISSP needs special software and is not compatible
with PSoC Programmer. The kit includes:
■ PSoCEvalUSB Board
■ LCD Module
■ CY3207 Programmer Unit
■ PSoC ISSP Software CD
■ MIniProg Programming Unit
■ Mini USB Cable
■ 110 ~ 240V Power Supply, Euro-Plug Adapter
■ USB 2.0 Cable
■ PSoC Designer and Example Projects CD
■ Getting Started Guide
■ Wire Pack
Accessories (Emulation and Programming)
Table 42. Emulation and Programming Accessories
Part #
Pin Package
16 SOIC
Flex-Pod Kita
CY3250-21X34
Foot Kitb
Adapter
CY8C21234-24S
CY3250-16SOIC-FK
CY3250-20SSOP-FK
CY3250-32QFN-FK
CY3250-28SSOP-FK
CY3250-32QFN-FK
Programmingadapterconverts
non-DIP package to DIP
footprint. Specific details and
orderinginformationforeachof
the adapters can be found at
http://www.emulation.com.
CY8C21334-24PVXI
CY8C21434-24LFXI
CY8C21534-24PVXI
CY8C21634-24LFXI
20 SSOP
32 QFN
28 SSOP
32 QFN
CY3250-21X34
CY3250-21X34QFN
CY3250-21X34
CY3250-21X34QFN
a. Flex-Pod kit includes a practice flex-pod and a practice PCB, in addition to two flex-pods.
b. Foot kit includes surface mount feet that can be soldered to the target PCB.
3rd-Party Tools
Build a PSoC Emulator into Your Board
Several tools have been specially designed by the following
3rd-party vendors to accompany PSoC devices during devel-
opment and production. Specific details for each of these tools
can be found at http://www.cypress.com under DESIGN
RESOURCES >> Evaluation Boards.
For details on how to emulate your circuit before going to volume
production using an on-chip debug (OCD) non-production PSoC
device, see Application Note AN2323 “Debugging - Build a PSoC
Emulator into Your Board”.
Document Number: 38-12025 Rev. *M
Page 40 of 43
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CY8C21634, CY8C21534
CY8C21434, CY8C21334, CY8C21234
Ordering Information
a
16 Pin (150-Mil) SOIC
CY8C21234-24SXI
CY8C21234-24SXIT
8K
8K
512 Yes -40°C to +85°C
512 Yes -40°C to +85°C
4
4
4
4
12
12
12
12
0
0
No
No
a
16 Pin (150-Mil) SOIC
(Tape and Reel)
a
a
20 Pin (210-Mil) SSOP
CY8C21334-24PVXI
8K
512 No
512 No
-40°C to +85°C
-40°C to +85°C
4
4
4
4
16
16
16
16
0
0
Yes
Yes
20 Pin (210-Mil) SSOP
(Tape and Reel)
CY8C21334-24PVXIT 8K
a
a
28 Pin (210-Mil) SSOP
CY8C21534-24PVXI
8K
512 No
512 No
-40°C to +85°C
-40°C to +85°C
4
4
4
4
24
24
24
24
0
0
Yes
Yes
28 Pin (210-Mil) SSOP
(Tape and Reel)
CY8C21534-24PVXIT 8K
a
a
a
a
a
a
a
a
a
a
32 Pin (5x5 mm 0.93 MAX)
QFN
CY8C21434-24LFXI
CY8C21434-24LFXIT 8K
CY8C21434-24LKXI 8K
CY8C21434-24LKXIT 8K
CY8C21634-24LFXI 8K
CY8C21634-24LFXIT 8K
CY8C21434-24LTXI 8K
CY8C21434-24LTXIT 8K
8K
512 No
512 No
512 No
512 No
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
28
28
28
28
26
26
28
28
28
28
28
28
28
28
26
26
28
28
28
28
0
0
0
0
0
0
0
0
0
0
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
b
32 Pin (5x5 mm 0.93 MAX)
QFN b (Tape and Reel)
32 Pin (5x5 mm 0.60 MAX)
b
QFN
32 Pin (5x5 mm 0.60 MAX)
b
QFN (Tape and Reel)
32 Pin (5x5 mm 0.93 MAX)
512 Yes -40°C to +85°C
512 Yes -40°C to +85°C
b
QFN
32 Pin (5x5 mm 0.93 MAX)
b
QFN (Tape and Reel)
32 Pin (5x5 mm 0.93 MAX)
SAWN QFN
512 No
512 No
512 No
512 No
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
32 Pin (5x5 mm 0.93 MAX)
b
SAWN QFN (Tape and Reel)
32 Pin (5x5 mm 0.60 MAX)
THIN SAWN QFN
CY8C21434-24LQXI
8K
32 Pin (5x5 mm 0.60 MAX)
THIN SAWN QFN
CY8C21434-24LQXIT 8K
(Tape and Reel)
a
a
a
32 Pin (5x5 mm 0.93 MAX)
SAWN QFN
CY8C21634-24LTXI
8K
512 Yes -40°C to +85°C
512 Yes -40°C to +85°C
512 Yes -40°C to +85°C
4
4
4
4
4
4
26
26
26
26
26
26
0
0
0
Yes
Yes
Yes
b
32 Pin (5x5 mm 0.93 MAX)
CY8C21634-24LTXIT 8K
b
SAWN QFN (Tape and Reel)
56 Pin OCD SSOP
CY8C21001-24PVXI
8K
a. All Digital IO Pins also connect to the common analog mux.
b. Refer to the section 32-Pin Part Pinout on page 11 for pin differences.
Document Number: 38-12025 Rev. *M
Page 41 of 43
[+] Feedback
CY8C21634, CY8C21534
CY8C21434, CY8C21334, CY8C21234
Ordering Code Definitions
CY 8 C 21 xxx-24xx
Package Type:
Thermal Rating:
C = Commercial
I = Industrial
PX = PDIP Pb-Free
SX = SOIC Pb-Free
PVX = SSOP Pb-Free
LFX/LKX = QFN Pb-Free
AX = TQFP Pb-Free
E = Extended
Speed: 24 MHz
Part Number
Family Code
Technology Code: C = CMOS
Marketing Code: 8 = Cypress PSoC
Company ID: CY = Cypress
Document Number: 38-12025 Rev. *M
Page 42 of 43
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CY8C21434, CY8C21334, CY8C21234
Document History Page
Document Title: CY8C21234/CY8C21334/CY8C21434/CY8C21534/CY8C21634 PSoC® Mixed-Signal Array
Document Number: 38-12025
Orig. of
Change
Revision
ECN
Description of Change
**
227340
235992
HMT
New silicon and document (Revision **).
*A
*B
SFV
Updated Overview and Electrical Spec. chapters, along with revisions to the 24-pin pinout part.
Revised the register mapping tables. Added a SSOP 28-pin part.
248572
277832
SFV
Changed title to include all part #s. Changed 28-pin SSOP from CY8C21434 to CY8C21534.
Changed pin 9 on the 28-pin SSOP from SMP pin to Vss pin. Added SMP block to architecture
diagram. Update Electrical Specifications. Added another 32-pin MLF part: CY8C21634.
*C
HMT
Verify data sheet standards from SFV memo. Add Analog Input Mux to applicable pin outs.
Update PSoC Characteristics table. Update diagrams and specs. Final.
*D
*E
*F
285293
301739
329104
HMT
HMT
HMT
Update 2.7V DC GPIO spec. Add Reflow Peak Temp. table.
DC Chip-Level Specification changes. Update links to new CY.com Portal.
Re-add pinout ISSP notation. Fix TMP register names. Clarify ADC feature. Update Electrical
Specifications. Update Reflow Peak Temp. table. Add 32 MLF E-PAD dimensions. Add ThetaJC
to Thermal Impedance table. Fix 20-pin package order number. Add CY logo. Update CY
copyright.
*G
352736
HMT
Add new color and logo. Add URL to preferred dimensions for mounting MLF packages. Update
Transmitter and Receiver AC Digital Block Electrical Specifications.
*H
*I
390152
413404
430185
HMT
HMT
HMT
Clarify MLF thermal pad connection info. Replace 16-pin 300-MIL SOIC with correct 150-MIL.
Update 32-pin QFN E-Pad dimensions and rev. *A. Update CY branding and QFN convention.
*J
Add new 32-pin 5x5 mm 0.60 thickness QFN package and diagram, CY8C21434-24LKXI.
Update thermal resistance data. Add 56-pin SSOP on-chip debug non-production part,
CY8C21001-24PVXI. Update typical and recommended Storage Temperature per industrial
specs. Update copyright and trademarks.
*K
677717
HMT
Add CapSense SNR requirement reference. Add new Dev. Tool section. Add CY8C20x34 to
PSoC Device Characteristics table. Add Low Power Comparator (LPC) AC/DC electrical spec.
tables. Update rev. of 32-Lead (5x5 mm 0.60 MAX) QFN package diagram.
*L
2147847 UVS/PYRS Added 32-Pin QFN Sawn pin diagram, package diagram, and ordering information.
2273246 UVS/AESA Added 32 pin thin sawn package diagram.
*M
© Cypress Semiconductor Corporation, 2004-2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 38-12025 Rev. *M
Revised April 18, 2008
Page 43 of 43
All products and company names mentioned in this document may be the trademarks of their respective holders.
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相关型号：
CY8C21634B-24LCXI
Multifunction Peripheral, CMOS, 5 X 5 MM 0.40 MM HEIGHT, LEAD FREE, MO-220, QFN-32
CYPRESS
CY8C21634B-24LQXI
Multifunction Peripheral, CMOS, 5 X 5 MM 0.60 MM HEIGHT, LEAD FREE, MO-248, QFN-32
CYPRESS
CY8C21634B-24LQXIT
Multifunction Peripheral, CMOS, 5 X 5 MM 0.60 MM HEIGHT, LEAD FREE, MO-248, QFN-32
CYPRESS
CY8C21634B-24LTXI
Multifunction Peripheral, CMOS, 5 X 5 MM 1.00 MM HEIGHT, LEAD FREE, MO-220, QFN-32
CYPRESS
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