CY8C20XX7 [CYPRESS]
1.8 V CapSense® Controller with SmartSense⢠Auto-tuning 31 Buttons, 6 Sliders, Proximity Sensors; 1.8 V CapSense®控制器SmartSenseâ ?? ¢自动调整31按钮，滑块6 ，接近传感器
| 型号： | CY8C20XX7 |
| 厂家： | 
CYPRESS |
| 描述： | 1.8 V CapSense® Controller with SmartSense⢠Auto-tuning 31 Buttons, 6 Sliders, Proximity Sensors |
| 文件： | 总43页 (文件大小：689K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY8C20xx7/S
1.8 V CapSense® Controller with
SmartSense™ Auto-tuning
31 Buttons, 6 Sliders, Proximity Sensors
1.8
V CapSense® Controller with SmartSense™ Auto-tuning 31 Buttons, 6 Sliders, Proximity Sensors
■ 4 Clock Sources
Features
❐ Internal main oscillator (IMO): 6/12/24 MHz
❐ Internal low-speed oscillator (ILO) at 32 kHz for watchdog
■ QuietZone™ Controller
❐ Patented Capacitive Sigma Delta PLUS (CSD PLUS™)
sensing algorithm for robust performance
❐ High Sensitivity (0.1 pF) and best-in-class SNR performance
to support:
and sleep timers
❐ External 32 KHz Crystal Oscillator
❐ External Clock Input
■ Programmable pin configurations
❐ Up to 34 general-purpose I/Os (GPIOs)
❐ Dual mode GPIO (Analog and Digital)
❐ High sink current of 25 mA per GPIO
• Max sink current 120 mA for all I/Os combined
❐ Source Current
• 5 mA on ports 0 and 1
• 1 mA on ports 2,3 and 4
❐ Configurable internal pull-up, high-Z and open drain modes
❐ Selectable, regulated digital I/O on port 1
❐ Configurable input threshold on port 1
• Overlay thickness of 15 mm for glass and 5 mm plastic
• Proximity Solutions
❐ Superiornoiseimmunityperformanceagainstconductedand
radiated noise and ultra low radiated emissions
• Standardized user modules for overcoming noise
■ Low power CapSense® block with SmartSense Auto-tuning
❐ Low average power consumption –
• 28 µA/sensor in run time (wake-up and scan once every
125 ms)
❐ SmartSense_EMC_PLUS Auto-Tuning
• Sets and maintains optimal sensor performance during run
time
■ Versatile Analog functions
❐ Internal analog bus supports connection of multiple sensors
• Eliminates system tuning during development and
production
• Compensates for variations in manufacturing process
to form ganged proximity sensor
❐ Internal Low-Dropout voltage regulator for high power supply
rejection ratio (PSRR)
■ Driven shield available on five GPIO pins
❐ Delivers best-in class water tolerant designs
❐ Robust proximity sensing in the presence of metal objects
❐ Supports longer trace lengths
■ Additional system resources
❐ I2C Slave:
• Selectable to 50 kHz, 100 kHz, or 400 kHz
• Selectable Clock stretch or Forced Nack Mode
• I2C wake from sleep with Hardware address match
❐ 12 MHz (Configurable) SPI master and slave
❐ Three 16-bit timers
❐ Max load of 100 pF (3 MHz)
■ Powerful Harvard-architecture processor
❐ M8C CPU with a max speed of 24 MHz
❐ Watchdog and sleep timers
❐ Integrated supervisory circuit
❐ 10-bit incremental analog-to-digital converter (ADC) with
internal voltage reference
❐ Two general-purpose high speed, low power analog
comparators
■ Operating Range: 1.71 V to 5.5 V
❐ Standby Mode 1.1 μA (Typ)
❐ Deep Sleep 0.1 μA (Typ)
■ Operating Temperature range: –40 oC to +85 oC
■ Flexible on-chip memory
■ Complete development tools
❐ 8 KB flash, 1 KB SRAM
❐ 16 KB flash, 2 KB SRAM
❐ Free development tool (PSoC Designer™)
❐ 32 KB flash, 2 KB SRAM
■ Sensor and Package options
❐ 50,000 flash erase/write cycles
❐ Read while Write with EEPROM emulation
❐ In-system programming simplifies manufacturing process
❐ 10 Sensing Inputs – 16-pin QFN, 16-pin SOIC
❐ 16 Sensing Inputs – 24-pin QFN
❐ 24 Sensing Inputs – 30-pin WLCSP [1]
❐ 25 Sensing Inputs – 32-pin QFN
❐ 31 Sensing Inputs – 48-pin QFN
Note
1. Please contact your nearest sales office for additional details.
Cypress Semiconductor Corporation
Document Number: 001-69257 Rev. *I
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised May 7, 2013
CY8C20xx7/S
Logic Block Diagram
1.8/2.5/3 V
LDO
PWRSYS
[2]
(Regulator)
Port 4
Port 3
Port2
Port 1
Port 0
PSoC CORE
SYSTEM BUS
Global Analog Interconnect
1K/2 K
SRAM
8K/16K/32 K Flash
Nonvolatile Memory
Supervisory ROM(SROM)
Interrupt
Controller
Sleep and
Watchdog
CPU Core(M8C)
6/12/ 24 MHz Internal Main Oscillator
(IMO)
Internal Low Speed Oscillator (ILO)
Multiple Clock Sources
CAPSENSE
SYSTEM
Analog
Reference
CapSense
Module
Comparator #1
Comparator #2
Analog
Mux
SYSTEM BUS
Internal
Voltage
References
POR
and
LVD
SPI
Master/
Slave
Three16- Bit
Programmable
Timers
I2C
Slave
System
Resets
Digital
Clocks
SYSTEM RESOURCES
Note
2. Internal voltage regulator for internal circuitry
Document Number: 001-69257 Rev. *I
Page 2 of 43
CY8C20xx7/S
Contents
PSoC® Functional Overview ............................................4
PSoC Core ..................................................................4
CapSense System .......................................................4
Additional System Resources .....................................5
Getting Started ..................................................................5
Application Notes/Design Guides ................................5
Development Kits ........................................................5
Training .......................................................................5
CYPros Consultants ....................................................5
Solutions Library ..........................................................5
Technical Support .......................................................5
Designing with PSoC Designer .......................................6
Select Components .....................................................6
Configure Components ...............................................6
Organize and Connect ................................................6
Generate, Verify, and Debug .......................................6
Pinouts ..............................................................................7
16-pin SOIC (10 Sensing Inputs) ................................7
16-pin QFN (10 Sensing Inputs)[7] .............................8
24-pin QFN (16 Sensing Inputs)[11] ...........................9
30-ball WLCSP (24 Sensing Inputs) ..........................10
32-pin QFN (25 Sensing Inputs)[18] ..........................11
48-pin QFN (31 Sensing Inputs)[22] ..........................12
Electrical Specifications ................................................13
Absolute Maximum Ratings .......................................13
Operating Temperature .............................................13
DC Chip-Level Specifications ....................................14
DC GPIO Specifications ............................................15
DC Analog Mux Bus Specifications ...........................17
DC Low Power Comparator Specifications ...............17
Comparator User Module Electrical Specifications ...18
ADC Electrical Specifications ....................................18
DC POR and LVD Specifications ..............................19
DC Programming Specifications ...............................19
DC I2C Specifications ...............................................20
Shield Driver DC Specifications ................................20
DC IDAC Specifications ............................................20
AC Chip-Level Specifications ....................................21
AC General Purpose I/O Specifications ....................22
AC Comparator Specifications ..................................22
AC External Clock Specifications ..............................22
AC Programming Specifications ................................23
AC I2C Specifications ................................................24
Packaging Information ...................................................27
Thermal Impedances .................................................30
Capacitance on Crystal Pins .....................................30
Solder Reflow Peak Temperature .............................30
Development Tool Selection .........................................31
Software ....................................................................31
Development Kits ......................................................31
Evaluation Tools ........................................................31
Device Programmers .................................................31
Accessories (Emulation and Programming) ..............32
Third Party Tools .......................................................32
Build a PSoC Emulator into Your Board ....................32
Ordering Information ......................................................33
Ordering Code Definitions .........................................34
Acronyms ........................................................................35
Reference Documents ....................................................35
Document Conventions .............................................35
Units of Measure .......................................................35
Numeric Naming ........................................................36
Glossary ..........................................................................36
Appendix: Silicon Errata for the
CY8C20xx7/S Family ......................................................37
CY8C20xx7/S Qualification Status ............................37
CY8C20xx7/S Errata Summary .................................37
Document History Page .................................................41
Sales, Solutions, and Legal Information ......................43
Worldwide Sales and Design Support .......................43
Products ....................................................................43
PSoC Solutions .........................................................43
Document Number: 001-69257 Rev. *I
Page 3 of 43
CY8C20xx7/S
®
Figure 1. CapSense System Block Diagram
PSoC Functional Overview
The PSoC family consists of many devices with on-chip
controllers. These devices are designed to replace multiple
traditional MCU-based system components with one low-cost
single-chip programmable component. A PSoC device includes
configurable blocks of analog and digital logic, and
programmable interconnect. This architecture makes it possible
for you to create customized peripheral configurations, to match
the requirements of each individual application. Additionally, a
fast central processing unit (CPU), flash program memory,
SRAM data memory, and configurable I/O are included in a
range of convenient pinouts.
CS1
CS2
IDAC
CSN
Vr
The architecture for this device family, as shown in the Logic
Block Diagram on page 2, consists of three main areas:
Reference
Buffer
■ The core
Cexternal (P0[1]
or P0[3])
Comparator
■ CapSense analog system
■ System resources
Mux
Mux
Refs
A common, versatile bus allows connection between I/O and the
analog system.
Each CY8C20x37/47/67/S PSoC device includes a dedicated
CapSense block that provides sensing and scanning control
circuitry for capacitive sensing applications. Depending on the
PSoC package, up to 34 GPIOs are also included. The GPIOs
provide access to the MCU and analog mux.
Cap Sense Counters
CSCLK
PSoC Core
CapSense
Clock Select
IMO
Oscillator
The PSoC core is a powerful engine that supports a rich
instruction set. It encompasses SRAM for data storage, an
interrupt controller, sleep and watchdog timers, and IMO and
ILO. The CPU core, called the M8C, is a powerful processor with
speeds up to 24 MHz. The M8C is a 4-million instructions per
second (MIPS), 8-bit Harvard-architecture microprocessor.
Analog Multiplexer System
The analog mux bus can connect to every GPIO pin. Pins are
connected to the bus individually or in any combination. The bus
also connects to the analog system for analysis with the
CapSense block comparator.
CapSense System
The analog system contains the capacitive sensing hardware.
Several hardware algorithms are supported. This hardware
performs capacitive sensing and scanning without requiring
external components. The analog system is composed of the
CapSense PSoC block and an internal 1 V or 1.2 V analog
reference, which together support capacitive sensing of up to 31
inputs[3]. Capacitive sensing is configurable on each GPIO pin.
Scanning of enabled CapSense pins is completed quickly and
easily across multiple ports.
Switch-control logic enables selected pins to precharge
continuously under hardware control. This enables capacitive
measurement for applications such as touch sensing. Other
multiplexer applications include:
■ Complex capacitive sensing interfaces, such as sliders and
touchpads.
■ Chip-wide mux that allows analog input from any I/O pin.
■ Crosspoint connection between any I/O pin combinations.
SmartSense™ Auto-tuning
SmartSense auto-tuning is an innovative solution from Cypress
that removes manual tuning of CapSense applications. This
solution is easy to use and provides robust noise immunity. It is
the only auto-tuning solution that establishes, monitors, and
maintains all required tuning parameters of each sensor during
run time. SmartSense auto-tuning allows engineers to go from
prototyping to mass production without retuning for
manufacturing variations in PCB and/or overlay material
properties.
Note
3. 34 GPIOs = 31 pins for capacitive sensing+2 pins for I2C + 1 pin for modulator capacitor.
Document Number: 001-69257 Rev. *I
Page 4 of 43
CY8C20xx7/S
Additional System Resources
Getting Started
System resources provide additional capability, such as
configurable I2C slave, SPI master/slave communication
interface, three 16-bit programmable timers, various system
resets supported by the M8C low voltage detection and power-
on reset. The merits of each system resource are listed here:
The quickest way to understand PSoC silicon is to read this
datasheet and then use the PSoC Designer Integrated
Development Environment (IDE). This datasheet is an overview
of the PSoC integrated circuit and presents specific pin, register,
and electrical specifications.
■ The I2C slave/SPI master-slave module provides 50/100/
400 kHz communication over two wires. SPI communication
over three or four wires runs at speeds of 46.9 kHz to 3 MHz
(lower for a slower system clock).
For in depth information, along with detailed programming
details, see the Technical Reference Manual for the CY8C20x37/
47/67/S PSoC devices.
For up-to-date ordering, packaging, and electrical specification
information, see the latest PSoC device datasheets on the web
at www.cypress.com/psoc.
■ The I2C hardware address recognition feature reduces the
already low power consumption by eliminating the need for
CPU intervention until a packet addressed to the target device
is received.
Application Notes/Design Guides
■ The I2C enhanced slave interface appears as a 32-byte RAM
buffer to the external I2C master. Using a simple predefined
protocol, the master controls the read and write pointers into
the RAM. When this method is enabled, the slave does not stall
the bus when receiving data bytes in active mode. For usage
details, see the applicationnote I2CEnhancedSlaveOperation
- AN56007.
Application notes and design guides are an excellent
introduction to the wide variety of possible PSoC designs. They
are located at www.cypress.com/gocapsense. Select
Application Notes under the Related Documentation tab.
Development Kits
PSoC Development Kits are available online from Cypress at
www.cypress.com/shop and through a growing number of
regional and global distributors, which include Arrow, Avnet, Digi-
Key, Farnell, Future Electronics, and Newark. See Development
Kits on page 31.
■ Low-voltage detection (LVD) interrupts can signal the
application of falling voltage levels, while the advanced power-
on reset (POR) circuit eliminates the need for a system
supervisor.
Training
■ An internal reference provides an absolute reference for
capacitive sensing.
Free PSoC and CapSense technical training (on demand,
webinars, and workshops) is available online at
www.cypress.com/training. The training covers a wide variety of
topics and skill levels to assist you in your designs.
■ A register-controlled bypass mode allows the user to disable
the LDO regulator.
CYPros Consultants
Certified PSoC Consultants offer everything from technical
assistance to completed PSoC designs. To contact or become a
PSoC Consultant go to www.cypress.com/cypros.
Solutions Library
Visit our growing library of solution focused designs at
www.cypress.com/solutions. Here you can find various
application designs that include firmware and hardware design
files that enable you to complete your designs quickly.
Technical Support
For assistance with technical issues, search KnowledgeBase
articles and forums at www.cypress.com/support. If you cannot
find an answer to your question, create a technical support case
or call technical support at 1-800-541-4736.
Document Number: 001-69257 Rev. *I
Page 5 of 43
CY8C20xx7/S
Organize and Connect
Designing with PSoC Designer
You build signal chains at the chip level by interconnecting user
modules to each other and the I/O pins. You perform the
selection, configuration, and routing so that you have complete
control over all on-chip resources.
The PSoC development process can be summarized in the
following four steps:
1. Select User Modules
2. Configure User Modules
3. Organize and Connect
4. Generate and Verify
Generate, Verify, and Debug
When you are ready to test the hardware configuration or move
on to developing code for the project, you perform the “Generate
Configuration Files” step. This causes PSoC Designer to
generate source code that automatically configures the device to
your specification and provides the software for the system. The
generated code provides application programming interfaces
(APIs) with high-level functions to control and respond to
hardware events at run time and interrupt service routines that
you can adapt as needed.
Select Components
PSoC Designer provides a library of pre-built, pre-tested
hardware peripheral components called “user modules”. User
modules make selecting and implementing peripheral devices,
both analog and digital, simple.
Configure Components
A complete code development environment allows you to
develop and customize your applications in C, assembly
language, or both.
Each of the User Modules you select establishes the basic
register settings that implement the selected function. They also
provide parameters and properties that allow you to tailor their
precise configuration to your particular application. The user
module parameters permit you to establish the pulse width and
duty cycle. Configure the parameters and properties to
correspond to your chosen application. Enter values directly or
by selecting values from drop-down menus. All the user modules
are documented in datasheets that may be viewed directly in
PSoC Designer or on the Cypress website. These user module
datasheets explain the internal operation of the User Module and
provide performance specifications. Each datasheet describes
the use of each user module parameter, and other information
you may need to successfully implement your design.
Document Number: 001-69257 Rev. *I
Page 6 of 43
CY8C20xx7/S
Pinouts
The CY8C20x37/47/67/S PSoC device is available in a variety of packages, which are listed and illustrated in the following tables.
Every port pin (labeled with a “P”) is capable of digital I/O and connection to the common analog bus. However, VSS, VDD, and XRES
are not capable of digital I/O.
16-pin SOIC (10 Sensing Inputs)
Table 1. Pin Definitions – CY8C20237-24SXI, CY8C20247/S-24SXI [4]
Type
Figure 2. CY8C20237-24SXI, CY8C20247/S-24SXI
Device
Pin
No.
Name
Description
Digital Analog
1
2
3
4
5
6
7
8
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I
I
I
I
I
I
P0[3] Integrating Input
P0[1] Integrating Input
P2[5] Crystal output (XOut)
P2[3] Crystal input (XIn)
P1[7] I2C SCL, SPI SS
P1[5] I2C SDA, SPI MISO
P1[3]
AI, P0[3]
P0[7], AI
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
AI, P0[1]
AI, P2[5]
VDD
P0[4], AI
AI, P2[3]
AI, P1[7]
XRES
P1[4], EXTCLK
SOIC
AI, P1[5]
AI, P1[3]
P1[2], AI
P1[0], ISSP DATA, I2C SDA, SPI CLK, AI
AI, ISSP CLK, I2C SCL, SPI MOSI, P1[1]
VSS
P1[1] ISSP CLK[5], I2C SCL, SPI
MOSI
9
Power
VSS Ground connection
10
I/O
I
P1[0] ISSP DATA[5], I2C SDA, SPI
CLK[6]
11
12
I/O
I/O
I
I
P1[2] Driven Shield Output (optional)
P1[4] Optional external clock
(EXTCLK)
13
INPUT
Power
XRES Active high external reset with
internal pull-down
14
15
16
I/O
I/O
I
I
P0[4]
VDD Supply voltage
P0[7]
LEGEND A = Analog, I = Input, O = Output, OH = 5 mA High Output Drive, R = Regulated Output.
Notes
4. 13 GPIOs = 10 pins for capacitive sensing+2 pins for I2C + 1 pin for modulator capacitor.
5. On power-up, the SDA(P1[0]) drives a strong high for 256 sleep clock cycles and drives resistive low for the next 256 sleep clock cycles. The SCL(P1[1]) line drives
resistive low for 512 sleep clock cycles and both the pins transition to high impedance state. On reset, after XRES de-asserts, the SDA and the SCL lines drive
resistive low for 8 sleep clock cycles and transition to high impedance state. Hence, during power-up or reset event, P1[1] and P1[0] may disturb the I2C bus. Use
alternate pins if you encounter issues.
6. Alternate SPI clock.
Document Number: 001-69257 Rev. *I
Page 7 of 43
CY8C20xx7/S
[7]
16-pin QFN (10 Sensing Inputs)
Table 2. Pin Definitions – CY8C20237, CY8C20247/S [8]
Type
Pin
Figure 3. CY8C20237, CY8C20247/S Device
Name
Description
No.
Digital Analog
1
2
3
4
5
6
I/O
I
I
I
I
I
I
P2[5] Crystal output (XOut)
P2[3] Crystal input (XIn)
P1[7] I2C SCL, SPI SS
P1[5] I2C SDA, SPI MISO
P1[3] SPI CLK
I/O
AI, XOut,P2[5]
AI, XIn,P2[3]
1
2
P0[4] , AI
XRES
IOHR
IOHR
IOHR
IOHR
12
11
QFN
3
4
(Top View)10 P1[4], EXTCLK, AI
AI,I2 C SCL, SPI SS, P1[7]
AI,I2 C SDA, SPI MISO, P1[5]
9
P1[2] , AI
P1[1] ISSP CLK[9], I2C SCL, SPI
MOSI
7
8
Power
VSS Ground connection
IOHR
I
P1[0] ISSP DATA[9], I2C SDA, SPI
CLK[10]
9
IOHR
IOHR
I
I
P1[2] Driven Shield Output (optional)
10
P1[4] Optional external clock
(EXTCLK)
11
Input
XRES Active high external reset with
internal pull-down
12
13
14
15
16
IOH
Power
I
P0[4]
VDD Supply voltage
P0[7]
IOH
IOH
IOH
I
I
I
P0[3] Integrating input
P0[1] Integrating input
LEGEND A = Analog, I = Input, O = Output, OH = 5 mA High Output Drive, R = Regulated Output.
Notes
7. No center pad.
8. 13 GPIOs = 10 pins for capacitive sensing+2 pins for I2C + 1 pin for modulator capacitor.
9. On power-up, the SDA(P1[0]) drives a strong high for 256 sleep clock cycles and drives resistive low for the next 256 sleep clock cycles. The SCL(P1[1]) line drives
resistive low for 512 sleep clock cycles and both the pins transition to high impedance state. On reset, after XRES de-asserts, the SDA and the SCL lines drive
resistive low for 8 sleep clock cycles and transition to high impedance state. Hence, during power-up or reset event, P1[1] and P1[0] may disturb the I2C bus. Use
alternate pins if you encounter issues.
10. Alternate SPI clock.
Document Number: 001-69257 Rev. *I
Page 8 of 43
CY8C20xx7/S
[11]
24-pin QFN (16 Sensing Inputs)
Table 3. Pin Definitions – CY8C20337, CY8C20347/S [12]
Type
Pin
Figure 4. CY8C20337, CY8C20347/S Device
Name
Description
No.
Digital Analog
1
2
3
4
5
6
7
I/O
I/O
I
I
I
I
I
I
I
P2[5] Crystal output (XOut)
P2[3] Crystal input (XIn)
P2[1]
P1[7] I2C SCL, SPI SS
P1[5] I2C SDA, SPI MISO
P1[3] SPI CLK
18
17
16
15
AI, XOut, P2[5]
AI, XIn, P2[3]
1
2
3
4
5
6
P0[2], AI
P0[0], AI
P2[4], AI
P2[2], AI
XRES
I/O
IOHR
IOHR
IOHR
IOHR
AI, P2[1]
QFN
(Top View)
AI, I2C SCL, SPI SS, P1[7]
AI, I2C SDA, SPI MISO, P1[5]
AI, SPI CLK, P1[3]
14
13
P1[6], AI
P1[1] ISSP CLK[13], I2C SCL, SPI
MOSI
8
NC
No connection
9
Power
VSS
Ground connection
10
IOHR
IOHR
IOHR
IOHR
I
I
I
I
P1[0] ISSPDATA[13], I2CSDA, SPI
CLK[14]
11
12
P1[2] Driven Shield Output
(optional)
P1[4] Optional external clock input
(EXTCLK)
13
14
P1[6]
Input
XRES Active high external reset
with internal pull-down
15
16
17
18
I/O
I/O
I
I
I
I
I
P2[2] Driven Shield Output
(optional)
P2[4] Driven Shield Output
(optional)
IOH
IOH
IOH
P0[0] Driven Shield Output
(optional)
P0[2] Driven Shield Output
(optional)
19
20
21
22
23
24
CP
P0[4]
Power
VDD
Supply voltage
IOH
IOH
I
I
P0[7]
P0[3] Integrating input
VSS Ground connection
P0[1] Integrating input
Power
IOH
Power
I
VSS
Center pad must be
connected to ground
LEGEND A = Analog, I = Input, O = Output, OH = 5 mA High Output Drive, R = Regulated Output.
Notes
11. The center pad (CP) on the QFN package must be connected to ground (VSS) for best mechanical, thermal, and electrical performance. If not connected to ground,
it must be electrically floated and not connected to any other signal.
12. 19 GPIOs = 16 pins for capacitive sensing+2 pins for I2C + 1 pin for modulator capacitor.
13. On power-up, the SDA(P1[0]) drives a strong high for 256 sleep clock cycles and drives resistive low for the next 256 sleep clock cycles. The SCL(P1[1]) line drives
resistive low for 512 sleep clock cycles and both the pins transition to high impedance state. On reset, after XRES de-asserts, the SDA and the SCL lines drive
resistive low for 8 sleep clock cycles and transition to high impedance state. Hence, during power-up or reset event, P1[1] and P1[0] may disturb the I2C bus. Use
alternate pins if you encounter issues.
14. Alternate SPI clock.
Document Number: 001-69257 Rev. *I
Page 9 of 43
CY8C20xx7/S
30-ball WLCSP (24 Sensing Inputs)
Table 4. Pin Definitions – CY8C20767, CY8C20747 30-ball Part Pinout (WLCSP) [15]
Type
Pin No.
Name
Description
Figure 5. CY8C20767, CY8C20747 30-ball
WLCSP
Digital
Analog
A1
A2
A3
A4
A5
B1
B2
B3
B4
B5
C1
C2
C3
C4
C5
D1
D2
D3
D4
D5
E1
IOH
IOH
I
I
P0[2]
P0[6]
VDD
Driven Shield Output (optional)
Bottom View
5
4
3
2
1
Power
Supply voltage
A
B
C
D
E
F
IOH
I/O
I/O
IOH
IOH
IOH
I/O
I/O
I/O
I/O
IOH
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
P0[1]
P2[7]
P4[2]
P0[0]
P0[4]
P0[3]
P2[5]
P2[2]
P2[4]
P0[7]
P3[2]
P2[3]
P2[0]
P3[0]
P3[1]
P3[3]
P2[1]
XRES
Integrating Input
Driven Shield Output (optional)
Integrating Input
Crystal Output (Xout)
Driven Shield Output (optional)
Driven Shield Output (optional)
Top View
1
2
3
4
5
Crystal Input (Xin)
A
B
C
Input
Active high external reset with
internal pull-down
D
E
E2
E3
IOHR
IOHR
I
I
P1[6]
P1[4]
Optional external clock input
(EXT CLK)
F
E4
E5
F1
F2
IOHR
IOHR
IOHR
IOHR
I
I
I
I
P1[7]
P1[5]
P1[2]
P1[0]
I2C SCL, SPI SS
I2C SDA, SPI MISO
Driven Shield Output (optional)
ISSP DATA[16], I2C SDA, SPI
CLK[17]
VSS
F3
F4
Power
IOHR
Supply ground
ISSP CLK[16], I2C SCL, SPI
MOSI
I
I
P1[1]
F5
IOHR
P1[3]
SPI CLK
LEGEND: A = Analog, I = Input, O = Output, OH = 5 mA High Output Drive, R = Regulated Output
Notes
15. 27 GPIOs = 24 pins for capacitive sensing+2 pins for I2C + 1 pin for modulator capacitor.
16. On power-up, the SDA(P1[0]) drives a strong high for 256 sleep clock cycles and drives resistive low for the next 256 sleep clock cycles. The SCL(P1[1]) line drives
resistive low for 512 sleep clock cycles and both the pins transition to high impedance state. On reset, after XRES de-asserts, the SDA and the SCL lines drive
resistive low for 8 sleep clock cycles and transition to high impedance state. Hence, during power-up or reset event, P1[1] and P1[0] may disturb the I2C bus. Use
alternate pins if you encounter issues.
17. Alternate SPI clock.
Document Number: 001-69257 Rev. *I
Page 10 of 43
CY8C20xx7/S
[18]
32-pin QFN (25 Sensing Inputs)
Table 5. Pin Definitions – CY8C20437, CY8C20447/S, CY8C20467/S [19]
Type
Figure 6. CY8C20437, CY8C20447/S, CY8C20467/S Device
Pin
No.
Name
Description
Digital Analog
1
IOH
I/O
I
I
I
I
I
I
I
I
I
I
I
P0[1] Integrating input
P2[5] Crystal output (XOut)
P2[3] Crystal input (XIn)
P2[1]
2
3
I/O
AI , XOut,P0[1]
AI ,XIn,P2[5]
1
2
3
4
5
6
7
8
24 P2[4] ,AI
23 P2[2] ,AI
22 P2[0] ,AI
21 P4[2] ,AI
20 P4[0] ,AI
19 P3[2] ,AI
18 P3[0] ,AI
17 XRES
4
I/O
5
I/O
P4[3]
AI
AI
,P2[3]
,P2[1]
QFN
(Top View)
6
I/O
P3[3]
AI ,P4[3]
AI ,P3[3]
7
I/O
P3[1]
P1[7] I2C SCL, SPI SS
P1[5] I2C SDA, SPI MISO
P1[3] SPI CLK.
AI ,P3[1]
AI ,I2 C SCL, SPI SS,P1[7]
8
IOHR
IOHR
IOHR
IOHR
9
10
11
P1[1] ISSP CLK[20], I2C SCL, SPI
MOSI.
12
13
Power
VSS
Ground connection
IOHR
I
P1[0] ISSP DATA[20], I2C SDA,
SPI CLK[21]
14
15
IOHR
IOHR
I
I
P1[2] Driven Shield Output (optional)
P1[4] Optional external clock input
(EXTCLK)
16
17
IOHR
I
P1[6]
Input
XRES Active high external reset with
internal pull-down
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
CP
I/O
I/O
I
I
I
I
I
I
I
I
I
I
I
P3[0]
P3[2]
I/O
P4[0]
I/O
P4[2]
I/O
P2[0]
I/O
P2[2] Driven Shield Output (optional)
I/O
P2[4] Driven Shield Output (optional)
IOH
IOH
IOH
IOH
P0[0] Driven Shield Output (optional)
P0[2] Driven Shield Output (optional)
P0[4]
P0[6]
Power
VDD
IOH
IOH
I
I
P0[7]
P0[3] Integrating input
Power
Power
VSS
VSS
Ground connection
Centerpadmustbeconnectedto
ground
LEGEND A = Analog, I = Input, O = Output, OH = 5 mA High Output Drive, R = Regulated Output.
Notes
18. The center pad (CP) on the QFN package must be connected to ground (VSS) for best mechanical, thermal, and electrical performance. If not connected to ground,
it must be electrically floated and not connected to any other signal.
19. 28 GPIOs = 25 pins for capacitive sensing+2 pins for I2C + 1 pin for modulator capacitor.
20. On power-up, the SDA(P1[0]) drives a strong high for 256 sleep clock cycles and drives resistive low for the next 256 sleep clock cycles. The SCL(P1[1]) line drives
resistive low for 512 sleep clock cycles and both the pins transition to high impedance state. On reset, after XRES de-asserts, the SDA and the SCL lines drive
resistive low for 8 sleep clock cycles and transition to high impedance state. Hence, during power-up or reset event, P1[1] and P1[0] may disturb the I2C bus. Use
alternate pins if you encounter issues.
21. Alternate SPI clock.
Document Number: 001-69257 Rev. *I
Page 11 of 43
CY8C20xx7/S
[22]
48-pin QFN (31 Sensing Inputs)
Table 6. Pin Definitions – CY8C20637, CY8C20647/S, CY8C20667/S
Figure 7. CY8C20637, CY8C20647/S, CY8C20667/S Device
[23]
1
NC
No connection
NC
AI ,P2[7]
NC
36
35
34
33
32
31
1
2
2
I/O
I/O
I
I
I
I
I
I
I
I
I
I
I
I
P2[7]
P2[5]
P2[3]
P2[1]
P4[3]
P4[1]
P3[7]
P3[5]
P3[3]
P3[1]
P1[7]
P1[5]
NC
P2[4],
AI
3
Crystal output (XOut)
Crystal input (XIn)
AI , XOut,P2[5]
3
4
5
6
P2[2],
P2[0],
P4[2],
P4[0],
AI
AI
AI
AI
4
I/O
AI , XIn ,P2[3]
AI ,P2[1]
AI ,P4[3]
AI ,P4[1]
AI ,P3[7]
AI ,P3[5]
AI ,P3[3]
5
I/O
6
I/O
QFN
(Top View)
7
I/O
30
29
28
27
P3[6],
P3[4],
P3[2],
7
8
9
10
AI
AI
8
I/O
9
I/O
AI
AI
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
I/O
],
P3[0
AI P
3[1]
I/O
XRES
26
25
11
12
2
AI ,I2 C SCL, SPI SS,P1[7]
P1[6],AI
IOHR
IOHR
I C SCL, SPI SS
2
I C SDA, SPI MISO
No connection
No connection
SPI CLK
NC
IOHR
IOHR
I
I
P1[3]
P1[1]
[24]
2
ISSP CLK , I C SCL, SPI MOSI
Ground connection
No connection
Power
V
SS
NC
NC
No connection
Power
IOHR
V
Supply voltage
DD
[24]
2
[25]
I
I
I
P1[0]
P1[2]
P1[4]
ISSP DATA , I C SDA, SPI CLK
Driven Shield Output (optional)
Optional external clock input
(EXTCLK)
IOHR
IOHR
25
26
IOHR
I
P1[6]
Input
XRES
Active high external reset with
internal pull-down
27
28
29
I/O
I/O
I/O
I
I
I
P3[0]
P3[2]
P3[4]
30
31
32
33
34
35
36
37
38
39
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I
I
I
I
P3[6]
P4[0]
P4[2]
P2[0]
P2[2]
P2[4]
NC
40
41
42
43
44
45
46
47
48
CP
IOH
I
P0[6]
Power
V
Supply voltage
No connection
No connection
DD
NC
NC
Driven Shield Output (optional)
Driven Shield Output (optional)
No connection
IOH
IOH
I
I
P0[7]
NC
No connection
P0[3]
Integrating input
Ground connection
Integrating input
IOH
IOH
IOH
I
I
I
P0[0]
P0[2]
P0[4]
Driven Shield Output (optional)
Driven Shield Output (optional)
Power
V
SS
IOH
I
P0[1]
Power
V
Center pad must be connected to ground
SS
LEGEND A = Analog, I = Input, O = Output, NC = No Connection H = 5 mA High Output Drive, R = Regulated Output.
Notes
22. The center pad (CP) on the QFN package must be connected to ground (VSS) for best mechanical, thermal, and electrical performance. If not connected to ground,
it must be electrically floated and not connected to any other signal.
23. 34 GPIOs = 31 pins for capacitive sensing+2 pins for I2C + 1 pin for modulator capacitor.
24. On power-up, the SDA(P1[0]) drives a strong high for 256 sleep clock cycles and drives resistive low for the next 256 sleep clock cycles. The SCL(P1[1]) line drives
resistive low for 512 sleep clock cycles and both the pins transition to high impedance state. On reset, after XRES de-asserts, the SDA and the SCL lines drive
resistive low for 8 sleep clock cycles and transition to high impedance state. Hence, during power-up or reset event, P1[1] and P1[0] may disturb the I2C bus. Use
alternate pins if you encounter issues.
25. Alternate SPI clock.
Document Number: 001-69257 Rev. *I
Page 12 of 43
CY8C20xx7/S
Electrical Specifications
This section presents the DC and AC electrical specifications of the CY8C20x37/47/67/S PSoC devices. For the latest electrical
specifications, confirm that you have the most recent datasheet by visiting the web at http://www.cypress.com/psoc.
Figure 8. Voltage versus CPU Frequency
5.5 V
1.71 V
750kHz
3 MHz
24MHz
CPU Frequency
Absolute Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested.
Table 7. Absolute Maximum Ratings
Symbol
Description
Storage temperature
Conditions
Min
Typ
Max
Units
T
Higher storage temperatures reduce data
retention time. Recommended Storage
Temperature is +25 °C ± 25 °C. Extended
duration storage temperatures above 85 °C
degrades reliability.
–55
+25
+125
°C
STG
V
V
V
Supply voltage relative to V
DC input voltage
–
–0.5
–
–
–
–
–
–
+6.0
V
V
DD
SS
–
V
V
– 0.5
V
V
+ 0.5
IO
SS
SS
DD
DD
DC voltage applied to tristate
Maximum current into any port pin
Electro static discharge voltage
Latch up current
–
– 0.5
+ 0.5
V
IOZ
MIO
I
–
–25
+50
mA
V
ESD
LU
Human body model ESD
2000
–
–
In accordance with JESD78 standard
200
mA
Operating Temperature
Table 8. Operating Temperature
Symbol
Description
Conditions
Min
–40
0
Typ
Max
+85
70
Units
°C
T
Ambient temperature
–
–
A
T
Commercial temperature range
Operational die temperature
–
°C
C
J
T
The temperature rise from ambient to junction
is package specific. See the Thermal Imped-
ances on page 30. The user must limit the
power consumption to comply with this
requirement.
–40
–
+100
°C
Document Number: 001-69257 Rev. *I
Page 13 of 43
CY8C20xx7/S
DC Chip-Level Specifications
The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 9. DC Chip-Level Specifications
Symbol
Description
Supply voltage
Conditions
Min
Typ
Max Units
[26, 27, 28]
V
I
See table DC POR and LVD Specifications on
page 19
1.71
–
5.50
V
DD
Supply current, IMO = 24 MHz Conditions are V 3.0 V, T = 25 °C,
–
–
–
2.88
1.71
1.16
4.00
mA
DD24
DD12
DD6
DD
A
CPU = 24 MHz. CapSense running at 12 MHz,
no I/O sourcing current
I
I
Supply current, IMO = 12 MHz Conditions are V 3.0 V, T = 25 °C,
2.60
1.80
mA
mA
DD
A
CPU = 12 MHz. CapSense running at
12 MHz, no I/O sourcing current
Supply current, IMO = 6 MHz
Conditions are V 3.0 V, T = 25 °C,
DD
A
CPU = 6 MHz. CapSense running at 6 MHz,
no I/O sourcing current
I
I
Deep sleep current
V
3.0 V, T = 25 °C, I/O regulator turned off
–
–
0.10
1.07
1.1
A
A
SB0
DD
A
Standby current with POR, LVD V 3.0 V, T = 25 °C, I/O regulator turned off
and sleep timer
1.50
SB1
DD
A
2
I
Standby current with I C
enabled
Conditions are V = 3.3 V, T = 25 °C and
CPU = 24 MHz
–
1.64
–
A
SBI2C
DD
A
Notes
26. When VDD remains in the range from 1.71 V to 1.9 V for more than 50 µs, the slew rate when moving from the 1.71 V to 1.9 V range to greater than 2 V must be
slower than 1 V/500 µs to avoid triggering POR. The only other restriction on slew rates for any other voltage range or transition is the SRPOWER_UP parameter.
27. If powering down in standby sleep mode, to properly detect and recover from a VDD brown out condition any of the following actions must be taken:
a. Bring the device out of sleep before powering down.
b. Assure that VDD falls below 100 mV before powering back up.
c. Set the No Buzz bit in the OSC_CR0 register to keep the voltage monitoring circuit powered during sleep.
d. Increase the buzz rate to assure that the falling edge of VDD is captured. The rate is configured through the PSSDC bits in the SLP_CFG register. For the referenced
registers, refer to the Technical Reference Manual. In deep sleep/standby sleep mode, additional low power voltage monitoring circuitry allows VDD brown out
conditions to be detected and resets the device when VDD goes lower than 1.1 V at edge rates slower than 1 V/ms.
28. For proper CapSense block functionality, if the drop in VDD exceeds 5% of the base VDD, the rate at which VDD drops should not exceed 200 mV/s. Base VDD can
be between 1.8 V and 5.5 V.
Document Number: 001-69257 Rev. *I
Page 14 of 43
CY8C20xx7/S
DC GPIO Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 3.0 V to 5.5 V and
–40 °C T 85 °C, 2.4 V to 3.0 V and –40 °C T 85 °C, or 1.71 V to 2.4 V and –40 °C T 85 °C, respectively. Typical
A
A
A
parameters apply to 5 V and 3.3 V at 25 °C and are for design guidance only.
Table 10. 3.0 V to 5.5 V DC GPIO Specifications
Symbol
Description
Conditions
Min
Typ Max Units
R
Pull-up resistor
–
I
4
5.60
–
8
–
k
PU
V
V
V
High output voltage
Port 2 or 3 pins
< 10 A, maximum of 10 mA source
V
– 0.20
V
OH1
OH
DD
DD
DD
current in all I/Os
High output voltage
Port 2 or 3 Pins
I
= 1 mA, maximum of 20 mA source
OH
V
V
– 0.90
– 0.20
–
–
–
–
V
V
OH2
OH3
current in all I/Os
I < 10 A, maximum of 10 mA source
OH
High output voltage
Port 0 or 1 pins with LDO regulator Disabled current in all I/Os
for port 1
V
V
V
High output voltage
Port 0 or 1 pins with LDO regulator Disabled current in all I/Os
for port 1
I
= 5 mA, maximum of 20 mA source
V
– 0.90
–
–
V
V
V
OH4
OH5
OH6
OH
DD
High output voltage
Port 1 Pins with LDO Regulator Enabled for 4 I/Os all sourcing 5 mA
3 V out
I
< 10 A, V > 3.1 V, maximum of
2.85
3.00 3.30
OH
DD
High output voltage
Port 1 pins with LDO regulator enabled for source current in all I/Os
I
= 5 mA, V > 3.1 V, maximum of 20 mA
2.20
–
–
OH
DD
3 V out
V
V
V
V
V
High output voltage
Port 1 pins with LDO enabled for 2.5 V out source current in all I/Os
I
< 10 A, V > 2.7 V, maximum of 20 mA
2.35
1.90
1.60
1.20
–
2.50 2.75
V
V
V
V
V
OH7
OH8
OH9
OH10
OL
OH
DD
High output voltage = 2 mA, V > 2.7 V, maximum of 20 mA
Port 1 pins with LDO enabled for 2.5 V out source current in all I/Os
High output voltage < 10 A, V > 2.7 V, maximum of 20 mA
Port 1 pins with LDO enabled for 1.8 V out source current in all I/Os
High output voltage = 1 mA, V > 2.7 V, maximum of 20 mA
Port 1 pins with LDO enabled for 1.8 V out source current in all I/Os
I
–
–
OH
DD
I
1.80 2.10
OH
DD
I
–
–
–
OH
DD
Low output voltage
I
= 25 mA, V > 3.3 V, maximum of 60 mA
0.75
OL
DD
sink current on even port pins (for example,
P0[2] and P1[4]) and 60 mA sink current on
odd port pins (for example, P0[3] and P1[5])
V
V
V
I
Input low voltage
–
–
–
–
–
2.00
–
–
–
0.80
V
V
IL
IH
H
Input high voltage
–
–
1
Input hysteresis voltage
Input leakage (Absolute Value)
80
mV
A
–
0.00
1
IL
C
Pin capacitance
Package and pin dependent
Temp = 25 °C
0.50
0.8
1.4
0.8
1.7
1.70
7
–
–
–
–
pF
–
PIN
VILLVT3.3 Input Low Voltage with low threshold enable Bit3 of IO_CFG1 set to enable low threshold
set, Enable for Port1 voltage of Port1 input
V
VIHLVT3.3 Input High Voltage with low threshold enable Bit3 of IO_CFG1 set to enable low threshold
set, Enable for Port1 voltage of Port1 input
–
V
–
VILLVT5.5 Input Low Voltage with low threshold enable Bit3 of IO_CFG1 set to enable low threshold
set, Enable for Port1 voltage of Port1 input
V
VIHLVT5.5 Input High Voltage with low threshold enable Bit3 of IO_CFG1 set to enable low threshold
–
V
set, Enable for Port1
voltage of Port1 input
Document Number: 001-69257 Rev. *I
Page 15 of 43
CY8C20xx7/S
Table 11. 2.4 V to 3.0 V DC GPIO Specifications
Symbol Description
Pull-up resistor
Conditions
Min
Typ
5.60
–
Max
8
Units
k
R
–
I
4
PU
V
V
V
High output voltage
Port 2 or 3 pins
< 10 A, maximum of 10 mA source V - 0.20
current in all I/Os
–
V
OH1
OH
DD
High output voltage
Port 2 or 3 Pins
I
= 0.2 mA, maximum of 10 mA
V - 0.40
DD
–
–
–
–
V
V
OH2
OH3
OH
source current in all I/Os
I < 10 A, maximum of 10 mA source V - 0.20
OH
current in all I/Os
High output voltage
Port 0 or 1 pins with LDO regulator
DD
Disabled for port 1
V
V
V
V
High output voltage
Port 0 or 1 pins with LDO regulator
Disabled for Port 1
I
= 2 mA, maximum of 10 mA source V - 0.50
–
1.80
–
–
V
V
V
V
OH4
OH5A
OH6A
OL
OH
DD
current in all I/Os
High output voltage
Port 1 pins with LDO enabled for 1.8 V 20 mA source current in all I/Os
out
I
< 10 A, V > 2.4 V, maximum of
1.50
1.20
–
2.10
–
OH
DD
High output voltage
Port 1 pins with LDO enabled for 1.8 V 20 mA source current in all I/Os
out
I
= 1 mA, V > 2.4 V, maximum of
OH DD
Low output voltage
I
= 10 mA, maximum of 30 mA sink
–
0.75
OL
current on even port pins (for example,
P0[2] and P1[4]) and 30 mA sink
current on odd port pins (for example,
P0[3] and P1[5])
V
V
V
Input low voltage
–
–
–
–
–
1.40
–
–
–
0.72
V
V
IL
IH
H
Input high voltage
Input hysteresis voltage
Input leakage (absolute value)
Capacitive load on pins
80
1
–
1000
7
mV
nA
pF
I
–
IL
C
Package and pin dependent
0.50
1.70
PIN
Temp = 25 C
V
V
Input Low Voltage with low threshold
enable set, Enable for Port1
Bit3 of IO_CFG1 set to enable low
threshold voltage of Port1 input
0.7
1.2
V
–
–
ILLVT2.5
IHLVT2.5
Input High Voltage with low threshold Bit3 of IO_CFG1 set to enable low
enable set, Enable for Port1
V
threshold voltage of Port1 input
Table 12. 1.71 V to 2.4 V DC GPIO Specifications
Symbol Description
Pull-up resistor
Conditions
Min
Typ
5.60
–
Max
8
Units
k
R
–
4
PU
V
V
V
High output voltage
Port 2 or 3 pins
I
= 10 A, maximum of 10 mA V – 0.20
–
V
OH1
OH
DD
source current in all I/Os
High output voltage
Port 2 or 3 pins
I
= 0.5 mA, maximum of 10 mA V – 0.50
–
–
–
–
V
V
OH2
OH3
OH
DD
source current in all I/Os
I = 100 A, maximum of 10 mA V – 0.20
OH
source current in all I/Os
High output voltage
Port 0 or 1 pins with LDO regulator
Disabled for Port 1
DD
V
High output voltage
Port 0 or 1 Pins with LDO Regulator
I
= 2 mA, maximum of 10 mA source V – 0.50
–
–
V
OH4
OH
DD
current in all I/Os
Disabled for Port 1
Document Number: 001-69257 Rev. *I
Page 16 of 43
CY8C20xx7/S
Table 12. 1.71 V to 2.4 V DC GPIO Specifications (continued)
Symbol Description
Low output voltage
Conditions
Min
Typ
Max
Units
V
I
= 5 mA, maximum of 20 mA sink
OL
–
–
0.40
V
OL
current on even port pins (for example,
P0[2] and P1[4]) and 30 mA sink
current on odd port pins (for example,
P0[3] and P1[5])
V
V
V
Input low voltage
–
–
–
–
–
–
–
0.30 × V
V
V
IL
IH
H
DD
Input high voltage
0.65 × V
–
–
DD
Input hysteresis voltage
Input leakage (absolute value)
Capacitive load on pins
–
–
80
1
mV
nA
pF
I
1000
7
IL
C
Package and pin dependent
0.50
1.70
PIN
temp = 25 C
Table 13. GPIO Current Sink and Source Specifications
Supply
Voltage
Port 0/1 per I/O
(max)
Port 2/3/4 per Total Current Even Total Current Odd
Mode
Units
I/O (max)
Pins (max)
Pins (max)
1.71–2.4
2.4–3.0
3.0–5.0
Sink
Source
Sink
5
2
5
20
30
mA
mA
mA
mA
mA
mA
[29]
[29]
[29]
0.5
10
0.2
25
1
10
10
20
10
2
30
60
30
60
Source
Sink
25
5
Source
DC Analog Mux Bus Specifications
The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 14. DC Analog Mux Bus Specifications
Symbol
Description
Conditions
Min
Typ
Max
Units
R
Switch resistance to common analog
bus
–
–
–
–
800
SW
R
Resistance of initialization switch to
–
–
800
GND
V
SS
The maximum pin voltage for measuring RSW and RGND is 1.8 V
DC Low Power Comparator Specifications
The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 15. DC Comparator Specifications
Symbol
Description
Conditions
Min
Typ
Max
Units
V
Low power comparator (LPC) common Maximum voltage limited to V
mode
0.2
–
1.8
V
LPC
DD
I
LPC supply current
LPC voltage offset
–
–
–
–
10
80
30
A
LPC
V
2.5
mV
OSLPC
Note
29. Total current (odd + even ports)
Document Number: 001-69257 Rev. *I
Page 17 of 43
CY8C20xx7/S
Comparator User Module Electrical Specifications
The following table lists the guaranteed maximum and minimum specifications. Unless stated otherwise, the specifications are for the
entire device voltage and temperature operating range: –40 °C TA 85 °C, 1.71 V V 5.5 V.
DD
Table 16. Comparator User Module Electrical Specifications
Symbol
Description
Comparator response time 50 mV overdrive
Valid from 0.2 V to 1.5 V
Conditions
Min
–
Typ
70
Max
100
30
Units
ns
T
COMP
Offset
–
2.5
20
mV
µA
Current
Average DC current, 50 mV
overdrive
–
80
Supply voltage > 2 V
Supply voltage < 2 V
Power supply rejection ratio
–
–
80
40
–
–
dB
dB
V
PSRR
Power supply rejection ratio
–
Input range
0.2
1.5
ADC Electrical Specifications
Table 17. ADC User Module Electrical Specifications
Symbol
Description
Conditions
Min
Typ
Max
Units
Input
V
Input voltage range
Input capacitance
Input resistance
–
–
0
–
–
–
VREFADC
5
V
pF
IN
C
R
IIN
IN
Equivalent switched cap input 1/(500fF × 1/(400fF × 1/(300fF ×
resistance for 8-, 9-, or 10-bit data clock) data clock) data clock)
resolution
Reference
V
ADC reference voltage
Data clock
–
1.14
2.25
–
–
1.26
6
V
REFADC
Conversion Rate
F
Source is chip’s internal main
oscillator. See AC Chip-Level
Specifications on page 21 for
accuracy
MHz
CLK
S8
8-bit sample rate
10-bit sample rate
Data clock set to 6 MHz.
sample rate = 0.001/
(2^Resolution/Data Clock)
–
–
23.43
5.85
–
–
ksps
ksps
S10
Data clock set to 6 MHz.
sample rate = 0.001/
(2^resolution/data clock)
DC Accuracy
RES
Resolution
Can be set to 8, 9, or 10 bit
8
–1
–2
0
–
–
10
+2
bits
LSB
DNL
Differential nonlinearity
Integral nonlinearity
Offset error
–
INL
–
–
+2
LSB
E
8-bit resolution
10-bit resolution
For any resolution
3.20
12.80
–
19.20
76.80
+5
LSB
OFFSET
0
LSB
E
Gain error
–5
%FSR
GAIN
Power
I
Operating current
–
–
–
–
2.10
24
2.60
–
mA
dB
dB
ADC
PSRR
Power supply rejection ratio PSRR (V > 3.0 V)
DD
PSRR (V < 3.0 V)
30
–
DD
Document Number: 001-69257 Rev. *I
Page 18 of 43
CY8C20xx7/S
DC POR and LVD Specifications
The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 18. DC POR and LVD Specifications
Symbol
Description
Conditions
Min
1.61
–
Typ
1.66
2.36
2.60
2.82
2.45
2.71
2.92
3.02
3.13
1.90
1.80
4.73
Max
1.71
2.41
2.66
2.95
2.51
2.78
2.99
3.09
3.20
2.32
1.84
4.83
Units
V
V
V
V
V
V
V
V
V
V
V
V
1.66 V selected in PSoC Designer V must be greater thanor equal to 1.71 V
V
POR0
POR1
POR2
POR3
LVD0
LVD1
LVD2
LVD3
LVD4
LVD5
LVD6
LVD7
DD
during startup, reset from the XRES pin, or
reset from watchdog.
2.36 V selected in PSoC Designer
2.60 V selected in PSoC Designer
–
2.82 V selected in PSoC Designer
2.45 V selected in PSoC Designer –
2.71 V selected in PSoC Designer
2.92 V selected in PSoC Designer
3.02 V selected in PSoC Designer
3.13 V selected in PSoC Designer
1.90 V selected in PSoC Designer
1.80 V selected in PSoC Designer
4.73 V selected in PSoC Designer
–
2.40
V
[30]
2.64
2.85
2.95
[31]
[32]
3.06
1.84
[33]
1.75
4.62
DC Programming Specifications
The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 19. DC Programming Specifications
Symbol
Description
Conditions
Min
Typ
Max
Units
V
Supply voltage for flash write
operations
–
–
1.71
–
5.25
V
DDIWRITE
I
Supply current during
programming or verify
–
–
5
–
–
–
25
mA
V
DDP
V
Input low voltage during
programming or verify
See appropriate DC GPIO Specifications
on page 15
V
IL
ILP
V
Input high voltage during
programming or verify
See appropriate DC GPIO Specifications
on page 15
V
–
V
IHP
IH
I
I
Input current when Applying V
to P1[0] or P1[1] during
programming or verify
Driving internal pull-down resistor
–
0.2
mA
ILP
ILP
Input current when applying V
to P1[0] or P1[1] during
programming or verify
Driving internal pull-down resistor
–
–
1.5
mA
IHP
IHP
V
V
Output low voltage during
programming or verify
–
–
–
V
+ 0.75
V
V
OLP
SS
Output high voltage during
programming or verify
See appropriate DC GPIO Specifications
V
V
DD
OHP
OH
on page 15. For V > 3V use V
in
DD
OH4
Table 10 on page 15.
Flash
Flash
Flash write endurance
Flash data retention
Erase/write cycles per block
50,000
20
–
–
–
–
–
ENPB
Following maximum Flash write cycles;
ambient temperature of 55 °C
Years
DR
Notes
30. Always greater than 50 mV above VPPOR1 voltage for falling supply.
31. Always greater than 50 mV above VPPOR2 voltage for falling supply.
32. Always greater than 50 mV above VPPOR3 voltage for falling supply.
33. Always greater than 50 mV above VPPOR0 voltage for falling supply.
Document Number: 001-69257 Rev. *I
Page 19 of 43
CY8C20xx7/S
2
DC I C Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 3.0 V to 5.5 V and
–40 °C T 85 °C, 2.4 V to 3.0 V and –40 °C T 85 °C, or 1.71 V to 2.4 V and –40 °C T 85 °C, respectively. Typical
A
A
A
parameters apply to 5 V and 3.3 V at 25 °C and are for design guidance only.
[34]
Table 20. DC I2C Specifications
Symbol
Description
Input low level
Conditions
3.1 V ≤ V ≤ 5.5 V
Min
Typ
Max
Units
V
–
–
0.25 × V
V
ILI2C
DD
DD
DD
DD
2.5 V ≤ V ≤ 3.0 V
–
–
–
–
–
0.3 × V
0.3 × V
V
V
V
DD
1.71 V ≤ V ≤ 2.4 V
DD
V
Input high level
1.71 V ≤ V ≤ 5.5 V
0.65 × V
V
0.7 V
+
IHI2C
DD
DD
DD
[35]
Shield Driver DC Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 3.0 V to 5.5 V and
–40 °C T 85 °C, 2.4 V to 3.0 V and –40 °C T 85 °C, or 1.71 V to 2.4 V and –40 °C T 85 °C, respectively. Typical
A
A
A
parameters apply to 5 V and 3.3 V at 25 °C and are for design guidance only.
Table 21. Shield Driver DC Specifications
Symbol
Description
Conditions
1.7 V ≤ V ≤ 5.5 V
Min
Typ
Max
Units
V
V
Reference buffer output
0.942
–
1.106
V
Ref
DD
Reference buffer output
1.7 V ≤ V ≤ 5.5 V
1.104
–
1.296
V
RefHi
DD
DC IDAC Specifications
The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 22. DC IDAC Specifications (8-bit IDAC)
Symbol
IDAC_DNL
IDAC_DNL
Description
Differential nonlinearity
Integral nonlinearity
Min
–1
Typ
–
Max
1
Units
LSB
LSB
µA
Notes
–2
–
2
IDAC_Current Range = 4x
Range = 8x
138
138
–
169
169
DAC setting = 127 dec
DAC setting = 64 dec
–
µA
Table 23. DC IDAC Specifications (7-bit IDAC)
Symbol
IDAC_DNL
IDAC_DNL
Description
Differential nonlinearity
Integral nonlinearity
Min
–1
Typ
–
Max
1
Units
LSB
LSB
µA
Notes
–2
–
2
IDAC_Current Range = 4x
Range = 8x
137
138
–
168
169
DAC setting = 127 dec
DAC setting = 64 dec
–
µA
Notes
34. Pull-up resistors on I2C interface cannot be connected to a supply voltage that is more than 0.7 V higher than the CY8C20xx7/S/H/L power supply. See the CY8C20xx7
Silicon Errata document for more details.
35. Please refer to Item # 6 of the Silicon Errata for the CY8C20xx7/S Family
Document Number: 001-69257 Rev. *I
Page 20 of 43
CY8C20xx7/S
AC Chip-Level Specifications
The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 24. AC Chip-Level Specifications
Symbol
Description
IMO frequency at 24 MHz Setting
IMO frequency at 12 MHz setting
IMO frequency at 6 MHz setting
CPU frequency
Conditions
Min
22.8
11.4
5.7
0.75
15
13
40
40
–
Typ
24
12
6.0
–
Max
25.2
12.6
6.3
25.20
50
Units
MHz
MHz
MHz
MHz
kHz
kHz
%
F
F
F
F
F
F
–
–
–
–
–
–
–
–
V
IMO24
IMO12
IMO6
CPU
ILO frequency
32
32
50
50
–
32K1
ILO untrimmed frequency
Duty cycle of IMO
82
32K_U
DC
DC
SR
60
IMO
ILO duty cycle
60
%
ILO
Power supply slew rate
slew rate during power-up
DD
250
–
V/ms
ms
POWER_UP
t
t
t
External reset pulse width at power-up
External reset pulse width after power-up
6 MHz IMO cycle-to-cycle jitter (RMS)
After supply voltage is valid
1
–
XRST
[36]
Applies after part has booted
10
–
–
–
s
XRST2
[37]
–
–
0.7
4.3
6.7
29.3
ns
JIT_IMO
6 MHz IMO long term N cycle-to-cycle jitter
(RMS); N = 32
–
ns
6 MHz IMO period jitter (RMS)
–
–
–
–
–
0.7
0.5
2.3
3.3
5.2
5.6
ns
ns
ns
12 MHz IMO cycle-to-cycle jitter (RMS)
12 MHz IMO long term N cycle-to-cycle jitter
(RMS); N = 32
––
12 MHz IMO period jitter (RMS)
–
–
–
–
–
–
0.4
1.0
1.4
2.6
8.7
6.0
ns
ns
ns
24 MHz IMO cycle-to-cycle jitter (RMS)
24 MHz IMO long term N cycle-to-cycle jitter
(RMS); N = 32
24 MHz IMO period jitter (RMS)
–
–
0.6
4.0
ns
Note
36. The minimum required XRES pulse length is longer when programming the device (see Table 28 on page 23).
37. See the Cypress Jitter Specifications application note, Understanding Datasheet Jitter Specifications for Cypress Timing Products – AN5054 for more information.
Document Number: 001-69257 Rev. *I
Page 21 of 43
CY8C20xx7/S
AC General Purpose I/O Specifications
The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 25. AC GPIO Specifications
Symbol
Description
Conditions
Min
Typ
Max
6 MHz for
Units
F
GPIO operating frequency
Normal strong mode Port 0, 1
0
–
MHz
GPIO
1.71 V <V < 2.40 V
DD
0
–
–
–
–
–
–
–
12 MHz for
MHz
ns
2.40 V < V < 5.50 V
DD
t
t
t
t
t
t
Rise time, strong mode, Cload = 50 pF
Ports 2 or 3
V
V
V
= 3.0 to 3.6 V, 10% to 90%
= 1.71 to 3.0 V, 10% to 90%
= 3.0 to 3.6 V, 10% to 90%
15
15
10
10
10
10
80
80
50
80
50
70
RISE23
RISE23L
RISE01
RISE01L
FALL
DD
DD
DD
Rise time, strong mode low supply,
Cload = 50 pF, Ports 2 or 3
ns
Rise time, strong mode, Cload = 50 pF
Ports 0 or 1
ns
LDO enabled or disabled
Rise time, strong mode low supply,
Cload = 50 pF, Ports 0 or 1
V
= 1.71 to 3.0 V, 10% to 90%
ns
DD
LDO enabled or disabled
Fall time, strong mode, Cload = 50 pF
all ports
V
= 3.0 to 3.6 V, 10% to 90%
ns
DD
DD
Fall time, strong mode low supply,
Cload = 50 pF, all ports
V
= 1.71 to 3.0 V, 10% to 90%
ns
FALLL
Figure 9. GPIO Timing Diagram
90%
GPIO Pin
Output
Voltage
10%
TRise23
TRise01
TRise23L
TRise01L
TFall
TFallL
AC Comparator Specifications
The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 26. AC Low Power Comparator Specifications
Symbol
Description
Conditions
Min
Typ
Max
Units
t
Comparator response time,
50 mV overdrive
50 mV overdrive does not include
offset voltage.
–
–
100
ns
LPC
AC External Clock Specifications
The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 27. AC External Clock Specifications
Symbol
Description
Conditions
Min
Typ
Max
Units
F
Frequency (external oscillator
frequency)
–
0.75
–
25.20
MHz
OSCEXT
High period
–
–
–
20.60
20.60
150
–
–
–
5300
ns
ns
s
Low period
–
–
Power-up IMO to switch
Document Number: 001-69257 Rev. *I
Page 22 of 43
CY8C20xx7/S
AC Programming Specifications
Figure 10. AC Waveform
SCLK (P1[1])
TRSCLK
TFSCLK
SDATA (P1[0])
TSSCLK
THSCLK
TDSCLK
The following table lists the guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 28. AC Programming Specifications
Symbol
Description
Rise time of SCLK
Conditions
Min
1
Typ
–
Max
20
20
–
Units
ns
t
t
t
t
–
–
–
–
–
–
–
RSCLK
Fall time of SCLK
1
–
ns
FSCLK
SSCLK
HSCLK
Data setup time to falling edge of SCLK
Data hold time from falling edge of SCLK
Frequency of SCLK
40
40
0
–
ns
–
–
ns
F
–
8
MHz
ms
ms
ns
SCLK
t
t
t
t
t
t
Flash erase time (block)
–
–
18
25
60
85
130
–
ERASEB
WRITE
DSCLK
DSCLK3
DSCLK2
XRST3
Flash block write time
–
–
Data out delay from falling edge of SCLK 3.6 V
Data out delay from falling edge of SCLK 3.0 V 3.6
Data out delay from falling edge of SCLK 1.71 V 3.0
External reset pulse width after power-up Required to enter programming
mode when coming out of sleep
–
–
DD
–
–
ns
DD
–
–
ns
DD
300
–
s
t
t
t
t
t
XRES pulse length
–
–
–
–
–
300
0.1
–
–
–
–
–
–
1
s
ms
ms
ms
ms
XRES
[38]
[38]
V
V
stable to wait-and-poll hold off
stable to XRES assertion delay
VDDWAIT
DD
14.27
0.01
3.20
–
VDDXRES
DD
SDAT high pulse time
200
19.60
POLL
[38]
“Key window” time after a V ramp
acquire event, based on 256 ILO clocks.
ACQ
DD
[38]
t
“Key window” time after an XRES event,
based on 8 ILO clocks
–
98
–
615
s
XRESINI
Note
38. Valid from 5 to 50 °C. See the spec, CY8C20X66, CY8C20X46, CY8C20X36, CY7C643XX, CY7C604XX, CY8CTST2XX, CY8CTMG2XX, CY8C20X67,
CY8C20X47, CY8C20X37, Programming Spec for more details.
Document Number: 001-69257 Rev. *I
Page 23 of 43
CY8C20xx7/S
2
AC I C Specifications
The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 29. AC Characteristics of the I2C SDA and SCL Pins
Standard
Mode
Fast Mode
Symbol
Description
Units
Min
Max
100
–
Min
0
Max
f
t
SCL clock frequency
0
400 kHz
SCL
Hold time (repeated) START condition. After this period, the first clock pulse is
generated
4.0
0.6
–
µs
HD;STA
t
t
t
t
t
t
t
t
LOW period of the SCL clock
4.7
4.0
4.7
20
–
–
1.3
0.6
0.6
20
–
–
µs
µs
µs
µs
ns
µs
µs
ns
LOW
HIGH Period of the SCL clock
HIGH
Setup time for a repeated START condition
Data hold time
–
–
SU;STA
HD;DAT
SU;DAT
SU;STO
BUF
[39]
3.45
–
0.90
–
[40]
Data setup time
250
4.0
4.7
–
100
Setup time for STOP condition
–
0.6
1.3
0
–
Bus free time between a STOP and START condition
Pulse width of spikes are suppressed by the input filter
–
–
–
50
SP
Figure 11. Definition for Timing for Fast/Standard Mode on the I2C Bus
Notes
39. To wake up from sleep using I2C hardware address match event, I2C interface needs 20 ns hold time on SDA line with respect to falling edge of SCL. See the
CY8C20xx7 Silicon Errata document for more details.
40. A Fast-Mode I2C-bus device can be used in a standard mode I2C-bus system, but the requirement tSU;DAT 250 ns must then be met. This automatically be the
case if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit
to the SDA line trmax + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released.
Document Number: 001-69257 Rev. *I
Page 24 of 43
CY8C20xx7/S
Table 30. SPI Master AC Specifications
Symbol Description
Conditions
Min
Typ
Max
Units
F
SCLK clock frequency
V
V
2.4 V
–
–
–
–
6
3
MHz
MHz
SCLK
DD
DD
< 2.4 V
DC
t
SCLK duty cycle
–
–
50
–
%
MISO to SCLK setup time
V
V
2.4 V
< 2.4 V
60
100
–
–
–
–
ns
ns
SETUP
DD
DD
t
t
t
SCLK to MISO hold time
SCLK to MOSI valid time
MOSI high time
–
–
–
40
–
–
–
–
–
40
–
ns
ns
ns
HOLD
OUT_VAL
OUT_H
40
Figure 12. SPI Master Mode 0 and 2
SPI Master, modes 0 and 2
1/FSCLK
THIGH
TLOW
SCLK
(mode 0)
SCLK
(mode 2)
TSETUP
THOLD
MISO
(input)
LSB
MSB
TOUT_SU
TOUT_H
MOSI
(output)
Figure 13. SPI Master Mode 1 and 3
SPI Master, modes 1 and 3
1/FSCLK
THIGH
TLOW
SCLK
(mode 1)
SCLK
(mode 3)
TSETUP
THOLD
MISO
(input)
MSB
LSB
TOUT_SU
TOUT_H
MOSI
(output)
LSB
MSB
Document Number: 001-69257 Rev. *I
Page 25 of 43
CY8C20xx7/S
Table 31. SPI Slave AC Specifications
Symbol
Description
Conditions
Min
Typ
–
Max
4
Units
MHz
ns
F
SCLK clock frequency
SCLK low time
–
–
–
–
–
–
–
–
–
–
–
SCLK
t
t
t
t
t
t
t
t
t
42
–
–
LOW
SCLK high time
42
–
–
ns
HIGH
MOSI to SCLK setup time
SCLK to MOSI hold time
SS high to MISO valid
SCLK to MISO valid
SS high time
30
–
–
ns
SETUP
HOLD
50
–
–
ns
–
–
–
153
125
–
ns
SS_MISO
SCLK_MISO
SS_HIGH
SS_CLK
CLK_SS
–
ns
50
–
ns
Time from SS low to first SCLK
Time from last SCLK to SS high
2/SCLK
2/SCLK
–
–
ns
–
–
ns
Figure 14. SPI Slave Mode 0 and 2
SPI Slave, modes 0 and 2
TSS_HIGH
TCLK_SS
TSS_CLK
/SS
1/FSCLK
THIGH
TLOW
SCLK
(mode 0)
SCLK
(mode 2)
TOUT_H
TSS_MISO
MISO
(output)
TSETUP
THOLD
MOSI
(input)
LSB
MSB
Figure 15. SPI Slave Mode 1 and 3
SPI Slave, modes 1 and 3
TSS_CLK
TCLK_SS
/SS
1/FSCLK
THIGH
TLOW
SCLK
(mode 1)
SCLK
(mode 3)
TOUT_H
TSCLK_MISO
TSS_MISO
MISO
(output)
MSB
LSB
TSETUP
THOLD
MOSI
(input)
MSB
LSB
Document Number: 001-69257 Rev. *I
Page 26 of 43
CY8C20xx7/S
Packaging Information
This section illustrates the packaging specifications for the CY8C20x37/47/67 PSoC device, along with the thermal impedances for
each package.
Important Note Emulation tools may require a larger area on the target PCB than the chip’s footprint. For a detailed description of
the emulation tools’ dimensions, refer to the document titled PSoC Emulator Pod Dimensions at
http://www.cypress.com/design/MR10161.
Figure 16. 16-pin (150 Mil) SOIC
51-85068 *E
Figure 17. 16-pin QFN No Center Pad (3 x 3 x 0.6 mm) Package Outline (Sawn)
001-09116 *H
Document Number: 001-69257 Rev. *I
Page 27 of 43
CY8C20xx7/S
Figure 18. 24-Pin (4 × 4 × 0.6 mm) QFN
001-13937 *E
Figure 19. 32-Pin (5 × 5 × 0.6 mm) QFN
001-42168 *E
Document Number: 001-69257 Rev. *I
Page 28 of 43
CY8C20xx7/S
Figure 20. 48-Pin (6 × 6 × 0.6 mm) QFN
001-57280 *E
Important Notes
■ For information on the preferred dimensions for mounting QFN packages, see the following Application Note at
http://www.amkor.com/products/notes_papers/MLFAppNote.pdf.
■ Pinned vias for thermal conduction are not required for the low power PSoC device.
Document Number: 001-69257 Rev. *I
Page 29 of 43
CY8C20xx7/S
Thermal Impedances
Table 32. Thermal Impedances per Package
[41]
Package
16-Pin SOIC
16-Pin QFN
Typical JA
95 C/W
33 C/W
21 C/W
20 C/W
18 C/W
54 C/W
[42]
24-Pin QFN
32-Pin QFN
48-Pin QFN
[42]
[42]
30-Ball WLCSP
Capacitance on Crystal Pins
Table 33. Typical Package Capacitance on Crystal Pins
Package
32-Pin QFN
48-Pin QFN
Package Capacitance
3.2 pF
3.3 pF
Solder Reflow Peak Temperature
Table 34 shows the solder reflow temperature limits that must not be exceeded.
Table 34. Solder Reflow Peak Temperature
Package
16-pin SOIC
16-pin QFN
24-pin QFN
32-pin QFN
48-pin QFN
30-ball WLCSP
Maximum Time above TC – 5 C
Maximum Peak Temperature (TC)
260 C
260 C
260 C
260 C
260 C
260 C
30 seconds
30 seconds
30 seconds
30 seconds
30 seconds
30 seconds
Notes
41. TJ = TA + Power ×
.
JA
42. To achieve the thermal impedance specified for the QFN package, the center thermal pad must be soldered to the PCB ground plane.
Document Number: 001-69257 Rev. *I
Page 30 of 43
CY8C20xx7/S
Development Kits
Development Tool Selection
Software
All development kits are sold at the Cypress Online Store.
Evaluation Tools
PSoC Designer™
All evaluation tools are sold at the Cypress Online Store.
At the core of the PSoC development software suite is
PSoC Designer, used to generate PSoC firmware applications.
PSoC Designer is a Microsoft Windows-based, integrated
development environment for the Programmable System-on-
Chip (PSoC) devices. The PSoC Designer IDE and application
runs on Windows XP and Windows Vista.
CY3210-MiniProg1
®
The CY3210-MiniProg1 kit allows you to program PSoC devices
through the MiniProg1 programming unit. The MiniProg is a
small, compact prototyping programmer that connects to the PC
through a provided USB 2.0 cable. The kit includes:
This system provides design database management by project,
in-system programming support, and built-in support for third-
party assemblers and C compilers. PSoC Designer also
supports C language compilers developed specifically for the
devices in the PSoC family. PSoC Designer is available free of
charge at
■ MiniProg programming unit
■ MiniEval socket programming and evaluation board
■ 28-pin CY8C29466-24PXI PDIP PSoC device sample
■ 28-pin CY8C27443-24PXI PDIP PSoC device sample
■ PSoC Designer software CD
http://www.cypress.com/psocdesigner and includes a free C
compiler.
PSoC Designer Software Subsystems
■ Getting Started guide
You choose a base device to work with and then select different
onboard analog and digital components called user modules that
use the PSoC blocks. Examples of user modules are ADCs,
DACs, Amplifiers, and Filters. You configure the user modules
for your chosen application and connect them to each other and
to the proper pins. Then you generate your project. This
prepopulates your project with APIs and libraries that you can
use to program your application.
■ USB 2.0 cable
CY3210-PSoCEval1
The CY3210-PSoCEval1 kit features an evaluation board and
the MiniProg1 programming unit. The evaluation board includes
an LCD module, potentiometer, LEDs, and plenty of bread-
boarding space to meet all of your evaluation needs. The kit
includes:
The tool also supports easy development of multiple
configurations and dynamic reconfiguration. Dynamic
reconfiguration allows for changing configurations at run time.
Code Generation Tools PSoC Designer supports multiple third-
party C compilers and assemblers. The code generation tools
work seamlessly within the PSoC Designer interface and have
been tested with a full range of debugging tools. The choice is
yours.
■ Evaluation board with LCD module
■ MiniProg programming unit
■ Two 28-pin CY8C29466-24PXI PDIP PSoC device samples
■ PSoC Designer software CD
■ Getting Started guide
■ USB 2.0 cable
Assemblers. The assemblers allow assembly code to be
merged seamlessly with C code. Link libraries automatically use
absolute addressing or are compiled in relative mode, and linked
with other software modules to get absolute addressing.
Device Programmers
All device programmers are purchased from the Cypress Online
Store.
C Language Compilers. C language compilers are available
that support the PSoC family of devices. The products allow you
to create complete C programs for the PSoC family devices. The
optimizing C compilers provide all the features of C tailored to
the PSoC architecture. They come complete with embedded
libraries providing port and bus operations, standard keypad and
display support, and extended math functionality.
CY3216 Modular Programmer
The CY3216 Modular Programmer kit features a modular
programmer and the MiniProg1 programming unit. The modular
programmer includes three programming module cards and
supports multiple Cypress products. The kit includes:
■ Modular programmer base
■ Three programming module cards
■ MiniProg programming unit
■ PSoC Designer software CD
■ Getting Started guide
PSoC Programmer
PSoC Programmer is flexible enough and is used on the bench
in development and is also suitable for factory programming.
PSoC Programmer works either as a standalone programming
application or operates directly from PSoC Designer. PSoC
Programmer software is compatible with both PSoC ICE Cube
in-circuit Emulator and PSoC MiniProg. PSoC programmer is
available free of cost at
■ USB 2.0 cable
http://www.cypress.com/psocprogrammer.
Document Number: 001-69257 Rev. *I
Page 31 of 43
CY8C20xx7/S
CY3207ISSP In-System Serial Programmer (ISSP)
■ CY3207 programmer unit
■ PSoC ISSP software CD
The CY3207ISSP is a production programmer. It includes
protection circuitry and an industrial case that is more robust than
the MiniProg in a production-programming environment.
■ 110 ~ 240 V power supply, Euro-Plug adapter
■ USB 2.0 cable
Note CY3207ISSP needs special software and is not compatible
with PSoC Programmer. The kit includes:
Accessories (Emulation and Programming)
Table 35. Emulation and Programming Accessories
[43]
[44]
[45]
Part Number
CY8C20237-24LKXI
CY8C20247-24LKXI
CY8C20337-24LQXI
CY8C20347-24LQXI
CY8C20437-24LQXI
CY8C20447-24LQXI
CY8C20467-24LQXI
CY8C20637-24LQXI
CY8C20647-24LQXI
CY8C20667-24LQXI
Pin Package
16 QFN
Flex-Pod Kit
Foot Kit
Adapter
CY3250-20246QFN
CY3250-20246QFN
CY3250-20346QFN
CY3250-20346QFN
CY3250-20466QFN
CY3250-20466QFN
CY3250-20466QFN
CY3250-20666QFN
CY3250-20666QFN
CY3250-20666QFN
CY3250-20246QFN-POD
CY3250-20246QFN-POD
CY3250-20346QFN-POD
CY3250-20346QFN-POD
CY3250-20466QFN-POD
CY3250-20466QFN-POD
CY3250-20466QFN-POD
CY3250-20666QFN-POD
CY3250-20666QFN-POD
CY3250-20666QFN-POD
See note 42
See note 45
See note 42
See note 45
See note 42
See note 45
See note 45
See note 45
See note 45
See note 45
16 QFN
24 QFN
24 QFN
32 QFN
32 QFN
32 QFN
48 QFN
48 QFN
48 QFN
Third Party Tools
Several tools have been specially designed by the following third-party vendors to accompany PSoC devices during development and
production. Specific details for each of these tools can be found at http://www.cypress.com under Documentation > Evaluation Boards.
Build a PSoC Emulator into Your Board
For details on how to emulate your circuit before going to volume production using an on-chip debug (OCD) non-production PSoC
device, see the Application Note Debugging - Build a PSoC Emulator into Your Board – AN2323.
Notes
43. Flex-Pod kit includes a practice flex-pod and a practice PCB, in addition to two flex-pods.
44. Foot kit includes surface mount feet that can be soldered to the target PCB.
45. Programming adapter converts non-DIP package to DIP footprint. Specific details and ordering information for each of the adapters can be found at
http://www.emulation.com.
Document Number: 001-69257 Rev. *I
Page 32 of 43
CY8C20xx7/S
Ordering Information
The following table lists the CY8C20x37/47/67/S PSoC devices' key package features and ordering codes.
Table 36. PSoC Device Key Features and Ordering Information
Flash SRAM CapSense Digital I/O
XRES
Pin
Analog
Ordering Code
Package
ADC
[46]
(Bytes) (Bytes) Sensors
Pins
13
13
13
13
13
13
13
13
13
19
19
19
19
19
19
28
28
28
28
28
28
28
28
28
28
34
34
34
34
34
34
34
34
34
34
Inputs
13
13
13
13
13
13
13
13
13
19
19
19
19
19
19
28
28
28
28
28
28
28
28
28
28
34
34
34
34
34
34
34
34
34
34
CY8C20237-24SXI
16-pin SOIC
8 K
16 K
16 K
8 K
1 K
2 K
2 K
1 K
1 K
2 K
2 K
2 K
2 K
1 K
1 K
2 K
2 K
2 K
2 K
1 K
1 K
2 K
2 K
2 K
2 K
2 K
2 K
2 K
2 K
1 K
1 K
2 K
2 K
2 K
2 K
2 K
2 K
2 K
2 K
10
10
10
10
10
10
10
10
10
16
16
16
16
16
16
25
25
25
25
25
25
25
25
25
25
31
31
31
31
31
31
31
31
31
31
Yes Yes
Yes Yes
Yes Yes
Yes Yes
Yes Yes
Yes Yes
Yes Yes
Yes Yes
Yes Yes
Yes Yes
Yes Yes
Yes Yes
Yes Yes
Yes Yes
Yes Yes
Yes Yes
Yes Yes
Yes Yes
Yes Yes
Yes Yes
Yes Yes
Yes Yes
Yes Yes
Yes Yes
Yes Yes
Yes Yes
Yes Yes
Yes Yes
Yes Yes
Yes Yes
Yes Yes
Yes Yes
Yes Yes
Yes Yes
Yes Yes
CY8C20247/S-24SXI
CY8C20247S-24SXI
CY8C20237-24LKXI
CY8C20237-24LKXIT
CY8C20247/S-24LKXI
CY8C20247/S-24LKXIT
CY8C20247S-24LKXI
CY8C20247S-24LKXIT
CY8C20337-24LQXI
CY8C20337-24LQXIT
CY8C20347-24LQXI
CY8C20347-24LQXIT
CY8C20347S-24LQXI
CY8C20347S-24LQXIT
CY8C20437-24LQXI
CY8C20437-24LQXIT
CY8C20447-24LQXI
CY8C20447-24LQXIT
CY8C20447S-24LQXI
CY8C20447S-24LQXIT
CY8C20467-24LQXI
CY8C20467-24LQXIT
CY8C20467S-24LQXI
CY8C20467S-24LQXIT
CY8C20637-24LQXI
CY8C20637-24LQXIT
CY8C20647-24LQXI
CY8C20647-24LQXIT
CY8C20647S-24LQXI
CY8C20647S-24LQXIT
CY8C20667-24LQXI
CY8C20667-24LQXIT
CY8C20667S-24LQXI
CY8C20667S-24LQXIT
16-pin SOIC
16-pin SOIC
16-pin QFN
16-pin QFN (Tape and Reel)
16-pin QFN
8 K
16 K
16 K
16 K
16 K
8 K
16-pin QFN (Tape and Reel)
16-pin QFN
16-pin QFN (Tape and Reel)
24-pin QFN
24-pin QFN (Tape and Reel)
24-pin QFN
8 K
16 K
16 K
16 K
16 K
8 K
24-pin QFN (Tape and Reel)
24-pin QFN
24-pin QFN (Tape and Reel)
32-pin QFN
32-pin QFN (Tape and Reel)
32-pin QFN
8 K
16 K
16 K
16 K
16 K
32 K
32 K
32 K
32 K
8 K
32-pin QFN (Tape and Reel)
32-pin QFN
32-pin QFN (Tape and Reel)
32-pin QFN
32-pin QFN (Tape and Reel)
32-pin QFN
32-pin QFN (Tape and Reel)
48-pin QFN
48-pin QFN (Tape and Reel)
48-pin QFN
8 K
16 K
16 K
16 K
16 K
32 K
32 K
32 K
32 K
48-pin QFN (Tape and Reel)
48-pin QFN
48-pin QFN (Tape and Reel)
48-pin QFN
48-pin QFN (Tape and Reel)
48-pin QFN
48-pin QFN (Tape and Reel)
Note
46. Dual-function Digital I/O Pins also connect to the common analog mux.
Document Number: 001-69257 Rev. *I
Page 33 of 43
CY8C20xx7/S
Table 36. PSoC Device Key Features and Ordering Information (continued)
Flash SRAM CapSense Digital I/O
XRES
Pin
Analog
Inputs
Ordering Code
Package
30-pin WLCSP
ADC
[46]
(Bytes) (Bytes) Sensors
Pins
CY8C20747-24FDXC
CY8C20747-24FDXCT
CY8C20767-24FDXC
CY8C20767-24FDXCT
16 K
16 K
32 K
32 K
1 K
1 K
2 K
2 K
24
24
24
24
27
27
Yes Yes
Yes Yes
Yes Yes
Yes Yes
30-pin WLCSP (Tape and Reel)
30-pin WLCSP
27
27
27
27
30-pin WLCSP (Tape and Reel)
27
27
Ordering Code Definitions
-
CY 8 C 20 XX7 X 24 XX
(T)
X
X
Tape and reel
Temperature range: X = C or I
C = Commercial; I = Industrial
Pb-free
Package Types: XX = S, LK, LQ, or FD
S = 16-pin SOIC
LK = 16-pin QFN (no center pad)
LQ = 24-pin QFN, 32-pin QFN, 48-pin QFN
FD = 30-ball WLCSP
Speed grade = 24 MHz
S = SmartSense™ Auto-tuning Enabled
Part Number
Family Code
Technology Code: C = CMOS
Marketing Code: 8 = PSoC
Company ID: CY = Cypress
Document Number: 001-69257 Rev. *I
Page 34 of 43
CY8C20xx7/S
Acronyms
Reference Documents
The following table lists the acronyms that are used in this
document.
■ Technical reference manual for CY20xx7 devices
■ In-system Serial Programming (ISSP) protocol for 20xx7
■ Host Sourced Serial Programming for 20xx7 devices
Table 37. Acronyms Used in this Document
Acronym
AC
Description
alternating current
Document Conventions
ADC
API
CMOS
CPU
DAC
DC
analog-to-digital converter
application programming interface
complementary metal oxide semiconductor
central processing unit
digital-to-analog converter
direct current
Units of Measure
Table 38 lists all the abbreviations used to measure the PSoC
devices.
Table 38. Units of Measure
ESD
FSR
electrostatic discharge
full scale range
general purpose input/output
inter-integrated circuit
in-circuit emulator
internal low speed oscillator
internal main oscillator
input/output
in-system serial programming
liquid crystal display
low dropout (regulator)
light-emitting diode
low power comparator
least-significant bit
low voltage detect
micro-controller unit
million instructions per second
master in slave out
master out slave in
most-significant bit
on-chip debug
printed circuit board
power on reset
power supply rejection ratio
Symbol
°C
Unit of Measure
degree Celsius
decibel
kilohertz
GPIO
dB
kHz
ksps
k
MHz
A
s
mA
mm
ms
mV
nA
ns
2
I C
ICE
ILO
IMO
I/O
ISSP
LCD
LDO
LED
LPC
LSB
kilo samples per second
kilohm
megahertz
microampere
microsecond
milliampere
millimeter
millisecond
millivolt
nanoampere
nanosecond
ohm
LVD
MCU
MIPS
MISO
MOSI
MSB
OCD
PCB
POR
PSRR
%
pF
V
percent
picofarad
volt
W
watt
PWRSYS power system
PSoC
QFN
SCLK
SDA
programmable system-on-chip
quad flat no-lead
2
serial I C clock
2
serial I C data
SDATA
SOIC
SPI
SRAM
SS
serial ISSP data
small outline integrated circuit
serial peripheral interface
static random access memory
slave select
USB
universal serial bus
WLCSP
wafer level chip scale package
Document Number: 001-69257 Rev. *I
Page 35 of 43
CY8C20xx7/S
Numeric Naming
Hexadecimal numbers are represented with all letters in uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or ‘3Ah’).
Hexadecimal numbers may also be represented by a ‘0x’ prefix, the C coding convention. Binary numbers have an appended
lowercase ‘b’ (for example, 01010100b’ or ‘01000011b’). Numbers not indicated by an ‘h’, ‘b’, or 0x are decimal.
Glossary
Crosspoint connection
Differential non linearity
Connection between any GPIO combination via analog multiplexer bus.
Ideally, any two adjacent digital codes correspond to output analog voltages that are exactly
one LSB apart. Differential non-linearity is a measure of the worst case deviation from the
ideal 1 LSB step.
Hold time
Hold time is the time following a clock event during which the data input to a latch or flip-
flop must remain stable in order to guarantee that the latched data is correct.
2
I C
It is a serial multi-master bus used to connect low speed peripherals to MCU.
Integral nonlinearity
It is a term describing the maximum deviation between the ideal output of a DAC/ADC and
the actual output level.
Latch-up current
Current at which the latch-up test is conducted according to JESD78 standard (at 125
degree Celsius)
Power supply rejection ratio (PSRR)
The PSRR is defined as the ratio of the change in supply voltage to the corresponding
change in output voltage of the device.
Scan
The conversion of all sensor capacitances to digital values.
Setup time
Period required to prepare a device, machine, process, or system for it to be ready to
function.
Signal-to-noise ratio
SPI
The ratio between a capacitive finger signal and system noise.
Serial peripheral interface is a synchronous serial data link standard.
Document Number: 001-69257 Rev. *I
Page 36 of 43
CY8C20xx7/S
Appendix: Silicon Errata for the CY8C20xx7/S Family
This section describes the errata for the CY8C20xx7/S family. Details include errata trigger conditions, scope of impact, available
workarounds, and silicon revision applicability.
Contact your local Cypress Sales Representative if you have questions.
CY8C20xx7/S Qualification Status
Product Status: Production released.
CY8C20xx7/S Errata Summary
The following Errata items apply to the CY8C20xx7/S datasheet 001-69257.
1. DoubleTimer0 ISR
■ Problem Definition
When programmable timer 0 is used in “one-shot” mode by setting bit 1 of register 0,B0h (PT0_CFG), and the timer interrupt
is used to wake the device from sleep, the interrupt service routine (ISR) may be executed twice.
■ Parameters Affected
No datasheet parameters are affected.
■ Trigger Condition(S)
Triggered by enabling one-shot mode in the timer, and using the timer to wake from sleep mode.
■ Scope of Impact
The ISR may be executed twice.
■ Workaround
In the ISR, firmware should clear the one-shot bit with a statement such as “and reg[B0h], FDh”
■ Fix Status
Will not be fixed
■ Changes
None
2. Missed GPIO Interrupt
■ Problem Definition
When in sleep mode, if a GPIO interrupt happens simultaneously with a Timer0 or Sleep Timer interrupt, the GPIO interrupt
may be missed, and the corresponding GPIO ISR not run.
■ Parameters Affected
No datasheet parameters are affected.
■ Trigger Condition(S)
Triggered by enabling sleep mode, then having GPIO interrupt occur simultaneously with a Timer 0 or Sleep Timer interrupt.
■ Scope of Impact
The GPIO interrupt service routine will not be run.
■ Workaround
The system should be architected such that a missed GPIO interrupt may be detected. For example, if a GPIO is used to wake
the system to perform some function, the system should detect if the function is not performed, and re-issue the GPIO interrupt.
Alternatively, if a GPIO interrupt is required to wake the system, then firmware should disable the Sleep Timer and Timer0.
Alternatively, the ISR’s for Sleep Timer and Timer0 should manually check the state of the GPIO to determine if the host system
has attempted to generate a GPIO interrupt.
■ Fix Status
Will not be fixed
■ Changes
None
Document Number: 001-69257 Rev. *I
Page 37 of 43
CY8C20xx7/S
3. Missed Interrupt During Transition to Sleep
■ Problem Definition
If an interrupt is posted a short time (within 2.5 CPU cycles) before firmware commands the device to sleep, the interrupt will
be missed.
■ Parameters Affected
No datasheet parameters are affected.
■ Trigger Condition(S)
Triggered by enabling sleep mode just prior to an interrupt.
■ Scope of Impact
The relevant interrupt service routine will not be run.
■ Workaround
None.
■ Fix Status
Will not be fixed
■ Changes
None
4. Wakeup from sleep with analog interrupt
■ Problem Definition
Device wakes up from sleep when an analog interrupt is trigger
■ Parameters Affected
No datasheet parameters are affected.
■ Trigger Condition(S)
Triggered by enabling analog interrupt during sleep mode when device operating temperature is 50 °C or above
■ Scope of Impact
Device unexpectedly wakes up from sleep
■ Workaround
Disable the analog interrupt before entering sleep and turn it back on upon wake-up.
■ Fix Status
Will not be fixed
■ Changes
None
Document Number: 001-69257 Rev. *I
Page 38 of 43
CY8C20xx7/S
5. Wake-up from Sleep with Hardware I2C Address match on Pins P1[0], P1[1]
■ Problem Definition
I2C interface needs 20 ns hold time on SDA line with respect to falling edge of SCL, to wake-up from sleep using I2C hardware
address match event.
■ Parameters Affected
t
increased to 20 ns from 0 ns
HD;DAT
■ Trigger Condition(S)
This is an issue only when all these three conditions are met:
1) P1.0 and P1.1 are used as I2C pins,
2) Wakeup from sleep with hardware address match feature is enabled, and
3) I2C master does not provide 20 ns hold time on SDA with respect to falling edge of SCL.
■ Scope of Impact
These trigger conditions cause the device to never wake-up from sleep based on I2C address match event
■ Workaround
For a design that meets all of the trigger conditions, the following suggested circuit has to be implemented as a work-around.
The R and C values proposed are 100 ohm and 200 pF respectively.
■ Fix Status
Will not be fixed
■ Changes
None
Document Number: 001-69257 Rev. *I
Page 39 of 43
CY8C20xx7/S
6. I2C Port Pin Pull-up Supply Voltage
■ Problem Definition
Pull-up resistor on I2C interface cannot be connected to a supply voltage that is greater than 0.7 V of CY8C20xx7/S V
.
DD
■ Parameters Affected
None.
■ Trigger Condition(S)
This problem occurs only when the I2C master is powered at a higher voltage than CY8C20xx7/S.
■ Scope of Impact
This trigger condition will corrupt the I2C communication between the I2C host and the CY8C20xx7/S CapSense controller.
■ Workaround
I2C master cannot be powered at a supply voltage that is greater than 0.7 V compared to CY8C20xx7/S supply voltage.
■ Fix Status
Will not be fixed
■ Changes
None
7. Port1 Pin Voltage
■ Problem Definition
Pull-up resistor on port1 pins cannot be connected to a voltage that is greater than 0.7 V higher than CY8C20xx7/S V
.
DD
■ Parameters Affected
None.
■ Trigger Condition(S)
This problem occurs only when port1 pins are at voltage 0.7 V higher than V of CY8C20xx7/S.
DD
■ Scope of Impact
This trigger condition will not allow CY8C20xx7/S to drive the output signal on port1 pins, input path is unaffected by this
condition.
■ Workaround
Port1 should not be connected to a higher voltage than V of CY8C20xx7/S
DD
■ Fix Status
Will not be fixed
■ Changes
None
Document Number: 001-69257 Rev. *I
Page 40 of 43
CY8C20xx7/S
Document History Page
DocumentTitle:CY8C20xx7/S, 1.8VCapSense® ControllerwithSmartSense™Auto-tuning 31Buttons,6Sliders,Proximity
Sensors
Document Number: 001-69257
Orig. of
Change
Submission
Date
Revision
ECN
Description of Change
**
3276782
3327230
DST
DST
06/27/2011 New silicon and document
*A
07/28/2011 Changed 48-pin dimensions to 6 × 6 × 0.6 mm QFN
Updated pins name in Table 3 on page 9 and removed USB column and
updated dimensions for 48-pin parts in Table 36 on page 33
Updated Figure 20 on page 29
Removed ICE and Debugger sections.
Removed CY3215 Development Kit and CY3280-20x66 UCC sections.
Updated Ordering Information.
*B
*C
3403111
3473317
YVA
DST
10/12/2011 Moved status from Advance to Preliminary.
Updated Ordering Information
Removed the row named “48-Pin (6 × 6 mm) QFN (OCD)”.
Changed all 48-pin ordering code column from CY8C20XXX-24LTxx to
CY8C20XXX-24LQxx.
Updated 16-pin SOIC and 16-pin QFN package drawings.
12/23/2011 Updated Features.
Updated Pinouts (Removed PSoC in captions of Figure 2, Figure 3, Figure 4,
Figure 6, and Figure 7).
Updated DC Chip-Level Specifications under Electrical Specifications
(Updated typical value of I
parameter from 3.32 mA to 2.88 mA, updated
DD24
typical value of I
parameterfrom 1.86 mA to1.71mA, updated typical value
DD12
of I
parameter from 1.13 mA to 1.16 mA, updated maximum value of I
DD6
SB0
parameter from 0.50 µA to 1.1 µA, added I
parameter and its details).
SBI2C
Updated DC GPIO Specifications under Electrical Specifications (Added the
parameters namely VILLVT3.3, VIHLVT3.3, VILLVT5.5, VIHLVT5.5 and their details in
Table 10, added the parameters namely V
Table 11).
, V
and their details in
ILLVT2.5 IHLVT2.5
Added the following sections namely DC I2C Specifications, Shield Driver DC
Specifications, and DC IDAC Specifications under Electrical Specifications.
Updated AC Chip-Level Specifications (Added the parameter namely t
and its details).
JIT_IMO
Updated Ordering Information (updated Table 36).
*D
3510277
YVA/DST
02/16/2012 Added CY8C20x37/37S/47/47S/67/67S part numbers and changed title to “1.8
V CapSense® Controller with SmartSense™ Auto-tuning
31 Buttons, 6 Sliders”
Updated Features.
Modified comparator blocks in Logic Block Diagram.
Replaced SmartSense with SmartSense auto-tuning.
Added CY8C20xx7S part numbers in Pin Definitions.
Added footnote for Table 20.
Updated Table 21 and Table 22 and added Table 23.
Updated F
min value.
32K1
Updated data hold time min values.
Updated CY8C206x7 part information in Table 35.
Updated Ordering Information.
*E
3539259
DST
03/01/2012 Changed Datasheet status from Preliminary to Final.
Updated all Pinouts to include Driven Shield Output (optional) information.
Updated Min value for V
Table 15.
LPC
Updated Offset and Input range in Table 16.
Document Number: 001-69257 Rev. *I
Page 41 of 43
CY8C20xx7/S
Document History Page (continued)
DocumentTitle:CY8C20xx7/S, 1.8VCapSense® ControllerwithSmartSense™Auto-tuning 31Buttons,6Sliders,Proximity
Sensors
Document Number: 001-69257
Orig. of
Change
Submission
Date
Revision
ECN
Description of Change
*F
3645807
DST/BVI
07/03/2012 Updated F
page 26
parameter in the Table 31, “SPI Slave AC Specifications,” on
SCLK
Changed t
to t
in Table 30, “SPI Master AC Specifications,” on
OUT_H
OUT_HIGH
page 25
Updated Features section, “Programmable pin configurations” bullet:
■ Included the following sub-bullet point -
5 mA source current on port 0 and 1 and 1 mA on port 2,3 and 4
■ Changed the bullet point “High sink current of 25 mA for each GPIO” to “High
sink current of 25 mA for each GPIO. Total 120 mA maximum sink current
per chip”
®
■ Added “QuietZone™ Controller” bullet and updated “Low power CapSense
block with SmartSense™ auto-tuning” bullet.
Updated package diagrams 001-13937 to *D and 001-57280 to *C revisions.
*G
3800055
DST
11/23/2012 Changed document title.
Part named changed from CY8C20xx7 to CY8C20xx7/S
Table 20: Update to VIHI2C to match Item #6 in K2 Si Errata document (001-
75370)
Updated package diagrams:
51-85068 to *E
001-09116 to *G
001-13937 to *E
001-42168 to *E
001-57280 to *E
*H
*I
3881332
3993458
SRLI
DST
02/04/2013 Updated Features:
Added Note 1 and referred the same note in “24 Sensing Inputs – 30-pin
WLCSP”.
05/07/2013 Updated Electrical Specifications (Updated DC GPIO Specifications (Updated
heading of third column as “Port 0/1 per I/O (max)” for Table 13)).
Updated Packaging Information:
spec 001-09116 – Changed revision from *G to *H (Figure 17).
Added Appendix: Silicon Errata for the CY8C20xx7/S Family.
Document Number: 001-69257 Rev. *I
Page 42 of 43
CY8C20xx7/S
Sales, Solutions, and Legal Information
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© Cypress Semiconductor Corporation, 2011-2013. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
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the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-69257 Rev. *I
Revised May 7, 2013
Page 43 of 43
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相关型号：
CY8C20xx7S
1.8 V CapSense® Controller with SmartSense⢠Auto-tuning 31 Buttons, 6 Sliders, Proximity Sensors
CYPRESS
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