CY7C9689A_技术文档

CY7C9689A

TAXI™-compatible HOTLink Transceiver

encoders to improve its serial transmission characteristics.

These encoded characters are then serialized, converted to

NRZI, and output from two PECL-compatible differential trans-

mission line drivers at a bit-rate of either 10 or 20 times the

input reference clock in 8-bit (or 10-bit bypass) mode, or 12 or

24 times the reference clock in 10-bit (or 12-bit bypass) mode.

Features

• Second-generation HOTLink^®technology

• AMD™ AM7968/7969 TAXIchip™-compatible

• 8-bit 4B/5B or 10-bit 5B/6B NRZI encoded data transport

• 10-bit or 12-bit NRZI pre-encoded (bypass) data

transport

• Synchronous TTL parallel interface

• Embedded/bypassable 256-character Transmit and

Receive FIFOs

• 50- to 200-MBaud serial signaling rate

• Internal phase-locked loops (PLLs) with no external

PLL components

• Dual differential PECL-compatible serial inputs and

outputs

The receive section of the CY7C9689A HOTLink accepts a

serial bit-stream from one of two PECL compatible differential

line receivers and, using a completely integrated PLL Clock

Synchronizer, recovers the timing information necessary for

data reconstruction. The recovered bit stream is converted

from NRZI to NRZ, deserialized, framed into characters,

4B/5B or 5B/6B decoded, and checked for transmission

errors. The recovered 8- or 10-bit decoded characters are then

written to an internal Receive FIFO, and presented to the

destination host system.

• Compatiblewith fiber-optic modules and copper cables

• Built-In Self-Test (BIST) for link testing

• Link Quality Indicator

• Single +5.0V ±10%supply

• 100-pin TQFP

The integrated 4B/5B and 5B/6B encoder/decoder may be

bypassed (disabled) for systems that present externally

encoded or scrambled data at the parallel interface. With the

encoder bypassed, the pre-encoded parallel data stream is

converted to and from a serial NRZI stream. The embedded

FIFOs may also be bypassed (disabled) to create a

reference-locked serial transmission link. For those systems

requiring even greater FIFO storage capability, external FIFOs

may be directly coupled to the CY7C9689A through the

parallel interface without the need for additional glue-logic.

Functional Description

The CY7C9689A HOTLink Transceiver is a point-to-point

communications building block allowing the transfer of data

over high-speed serial links (optical fiber, balanced, and unbal-

anced copper transmission lines) at speeds ranging between

50 and 200 MBaud. The transmit section accepts parallel data

of selectable widths and converts it to serial data, while the

receiver section accepts serial data and converts it to parallel

data of selectable widths. Figure 1 illustrates typical connec-

tions between two independent host systems and corre-

sponding CY7C9689A parts. The CY7C9689A provides

enhanced technology, increased functionality, a higher level of

integration, higher data rates, and lower power dissipation

over the AMD AM7968/7969 TAXIchip products.

The TTL parallel I/O interface may be configured as either a

FIFO (configurable for depth expansion through external

FIFOs) or as a pipeline register extender. The FIFO configura-

tions are optimized for transport of time-independent

(asynchronous) 8- or 10-bit character-oriented data across a

link. A Built-In Self-Test (BIST) pattern generator and checker

allows for testing of the high-speed serial data paths in both

the transmit and receive sections, and across the intercon-

necting links.

HOTLink devices are ideal for a variety of applications where

parallel interfaces can be replaced with high-speed,

point-to-point serial links. Some applications include intercon-

necting workstations, backplanes, servers, mass storage, and

video transmission equipment.

The transmit section of the CY7C9689A HOTLink can be

configured to accept either 8- or 10-bit data characters on each

clock cycle, and stores the parallel data into an internal

synchronous Transmit FIFO. Data is read from the Transmit

FIFO and is encoded using embedded 4B/5B or 5B/6B

Transmit

Data

Receive

Serial Link

Control

Status

CY7C9689A

Status

Serial Link

Data

Transmit

Receive

Data

Figure 1. HOTLink System Connections

Cypress Semiconductor Corporation

Document #: 38-02020 Rev. *C

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Revised November 7, 2002

CY7C9689A

TAXI HOTLink Transceiver Logic Block Diagram

RXDATA/RXCMD

13

CONTROL

TXDATA/TXCMD

TXCLK

RX

STATUS

TX

STATUS

MODE

RXCLK

REFCLK

10

8

13

3

4

Mode

Control

Output Register

MUX

Input Register

Flags

Mode

Receive

FIFO

Flags

Transmit

FIFO

CONTROL

Transmit

PLL Clock

Multiplier

CE

TXEN

RXEN

TXHALT

MUX

TXRST

RXRST

RFEN

TXBISTEN

RXBISTEN

RESET

Pipeline Register

MUX

MODE

RANGESEL

SPDSEL

Pipeline Register

Receive

Control

State

RXMODE[1:0]

FIFOBYP

EXTFIFO

ENCBYP

BYTE8/10

TEST

BIST LFSR

4B/5B, 5B/6B Decoder

Machine

BIST LFSR

4B/5B, 5B/6B Encoder

Transmit

Control

State

Deserializer

Framer

Clock

Divider

RXSTATUS

LFI

RXEMPTY

RXHALF

RXFULL

Machine

MUX

Receive

Clock/Data

Recovery

Bit Clock

Serial Shifter

Bit Clock

TX STATUS

TXEMPTY

TXHALF

Routing Matrix

TXFULL

Signal

Validation

DLB

OUTA

CURSETA

INA

INB

A/B

OUTB

CURSETB

CARDET

Document #: 38-02020 Rev. *C

Page 2 of 46

CY7C9689A

Pin Configuration

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76

TEST

1

2

3

75

SPDSEL

RANGESEL

RFEN

A/B

74

73

72

LFI

TXFULL

V_SS

DLB

4

5

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

CE

VLTN

6

TXHALF

RXEN

TXBISTEN

RXCLK

7

8

TXCLK

RXRST

V_SS

TXHALT

RXFULL

V_SS

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

RXSC/D

V_DD

REFCLK

V_SS

CY7C9689A

V_DD

V_SS

RXDATA[0]

TXEMPTY

RXDATA[1]

TXCMD[1]

V_SS

TXRST

V_DD

TXEN

RXHALF

TXSC/D

RXEMPTY

TXDATA[0]

RXDATA[11]/RXCMD[1]

TXCMD[0]

V_DD

TXDATA[9]/TXCMD[2]

RXDATA[2]

V_SS

RXMODE[1]

RXMODE[0]

24

25

RESET

26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

Document #: 38-02020 Rev. *C

Page 3 of 46

CY7C9689A

(

Pin Descriptions

Transmit Path Signals

68 TXCLK

Name

I/O Characteristics

Signal Description

TTL clock input

Internal Pull-up

Transmit FIFO Clock.

Used to sample all Transmit FIFO and related interface signals.

44, 42, TXDATA[7:0] TTL input, sampled on Parallel Transmit DATA Input.

40, 36,

34, 32,

30, 22

TXCLK↑ or REFCLK↑ When selected (CE = LOW and TXEN = asserted), information on these inputs

Internal Pull-up

is processed as DATA when TXSC/D is LOW and ignored otherwise. When the

encoder is bypassed (ENCBYP is LOW), TXDATA[7:0] functions as the least

significant eight bits of the 10- or 12-bit pre-encoded transmit character.

When the Transmit FIFO is enabled (FIFOBYP is HIGH), these inputs are

sampled on the rising edge of TXCLK. When the Transmit FIFO is bypassed

(FIFOBYP is LOW) these inputs are captured on the rising edge of REFCLK.

54, 46 TXDATA[9:8]/ TTL input, sampled on Parallel Transmit DATA or COMMAND Input.

TXCMD[2:3]

TXCLK↑ or REFCLK↑ When selected, BYTE8/10 is HIGH, and the encoder is enabled (ENCBYP is

Internal Pull-up

HIGH), information on these inputs are processed as TXCMD[2:3] if TXSC/D is

HIGH and ignored otherwise.

When selected, BYTE8/10 is LOW, and the encoder is enabled (ENCBYP is

HIGH), information on these inputs are processed as TXDATA[9:8] if TXSC/D

is LOW and ignored otherwise.

When the encoder is bypassed (ENCBYP is LOW), TXDATA[9:8] functions as

the 9th and 10th bits of the 10- or 12-bit pre-encoded transmit character.

When the Transmit FIFO is enabled (FIFOBYP is HIGH), these inputs are

sampled on the rising edge of TXCLK. When the Transmit FIFO is bypassed

(FIFOBYP is LOW), these inputs are captured on the rising edge of REFCLK.

58, 56 TXCMD[1:0]

TTL input, sampled on Parallel Transmit COMMAND Input.

TXCLK↑ or REFCLK↑ When selected and the encoder is enabled (ENCBYP is HIGH), information on

Internal Pull-up

these inputs is processed as a COMMAND when TXSC/D is HIGH and ignored

otherwise.

When BYTE8/10 is HIGH and the encoder is bypassed (ENCBYP is LOW), the

TXCMD[1:0] inputs are ignored.

When BYTE8/10 is LOW and when the encoder is bypassed (ENCBYP is

LOW), the TXCMD[1:0] inputs function as the 11th and 12th (MSB) bits of the

12-bit pre-encoded transmit character.

When the Transmit FIFO is enabled (FIFOBYP is HIGH), these inputs are

sampled on the rising edge of TXCLK. When the Transmit FIFO is bypassed

(FIFOBYP is LOW), these inputs are sampled on the rising edge of REFCLK.

20

TXSC/D

TTL input, sampled on COMMAND or DATA input selector.

TXCLK↑ or REFCLK↑ When selected, BYTE8/10 is HIGH, and the encoder is enabled (ENCBYP is

Internal Pull-up

HIGH), this input selects if the DATA or COMMAND inputs are processed. If

TXSC/D is HIGH, the value on TXCMD[3:0] is captured as one of sixteen

possible COMMANDs, and the data on the TXDATA[7:0] bits are ignored. If

TXSC/D is LOW, the information on TXDATA[7:0] is captured as one of 256

possible 8-bit DATA values, and the information on the TXCMD[3:0] bus is

ignored.

When BYTE8/10 is LOW and the encoder is enabled (ENCBYP is HIGH) this

input selects if the DATA or COMMAND inputs are processed. If TXSC/D is

HIGH, the information on TXCMD[1:0] is captured as one of four possible

COMMANDs, and the information on the TXDATA[9:0] bits are ignored. If

TXSC/D is LOW, the information on TXDATA[9:0] is captured as one of 1024

possible 10-bit DATA values, and the information on the TXCMD[1:0] bus is

ignored.

When the encoder is bypassed (ENCBYP is LOW) TXSC/D is ignored

Document #: 38-02020 Rev. *C

Page 4 of 46

CY7C9689A

Pin Descriptions (continued)

18

Name

TXEN

I/O Characteristics

Signal Description

TTL input, sampled on Transmit Enable.

TXCLK↑ or REFCLK↑ TXEN is sampled on the rising edge of the TXCLK or REFCLK input and enables

Internal Pull-up

parallel data bus write operations (when selected). The device is selected when

TXEN is asserted during a clock cycle immediately following one in which CE

is sampled LOW.

Depending on the level on EXTFIFO, the asserted state for TXEN can be active

HIGH or active LOW. If EXTFIFO is LOW, then TXEN is active LOW and data

is captured on the same clock cycle where TXEN is sampled LOW. If EXTFIFO

is HIGH, then TXEN is active HIGH and data is captured on the clock cycle

following any clock edge when TXEN is sampled HIGH.

7

TXBISTEN

TXRST

TTL input,

asynchronous

Internal Pull-up

Transmitter BIST Enable.

When TXBISTEN is LOW, the transmitter generates a 511-character repeating

sequence that can be used to validate link integrity. This 4B/5B BIST sequence

is generated regardless of the state of other configuration inputs. The trans-

mitter returns to normal operation when TXBISTEN is HIGH. All Transmit FIFO

read operations are suspended when BIST is active.

16

TTL input, sampled on Reset Transmit FIFO.

TXCLK↑

When the Transmit FIFO is enabled (FIFOBYP is HIGH), TXEN is deasserted,

Internal Pull-up

CE is asserted (LOW), and TXRST is sampled LOW by TXCLK for seven cycles,

the Transmit FIFO begins its internal reset process. The Transmit FIFO TXFULL

flag is asserted and the host interface counter and address pointer are zeroed.

This reset propagates to the serial transmit side, any remaining counters and

pointers. The TXFULL flag is asserted until both sides of the Transmit FIFO

have reset. While TXRST remains asserted, the Transmit FIFO remains in reset

and the TXFULL output remains asserted.

When the Transmit FIFO is bypassed (FIFOBYP is LOW), TXRST is ignored.

9

TXHALT

TXFULL

TTL input, sampled on Transmitter Halt Control Input.

TXCLK↑

When TXHALT is asserted LOW, transmission of data is suspended and the

Internal Pull-up

HOTLink TAXI transmits SYNC characters. When TXHALT is deasserted HIGH,

normal data processing proceeds.

If the Transmit FIFO is enabled (FIFOBYP is HIGH), the interface is allowed to

continue loading data into the Transmit FIFO while TXHALT is asserted.

72

Three-state TTL

output, changes

Transmit FIFO Full Status Flag.

When the Transmit FIFO is enabled (FIFOBYP is HIGH) and its flags are driven

following TXCLK↑ or (CE is LOW), TXFULL is asserted when four or fewer characters can be written

REFCLK↑

to the HOTLink Transmit FIFO. If a Transmit FIFO reset has been initiated

(TXRST was sampled asserted for a minimum of seven TXCLK cycles),

TXFULL is asserted to enforce the full/unavailable status of the Transmit FIFO

during reset.

When the Transmit FIFO is bypassed (FIFOBYP is LOW), the TXFULL output

changes after the rising edge of REFCLK. TXFULL is asserted when the trans-

mitter is BUSY (not accepting a new data or command characters) and

deasserted when new characters can be accepted.

When the Transmit FIFO is bypassed and RANGESEL is HIGH or SPDSEL is

LOW, TXFULL toggles at the character rate to provide a character rate

reference control-indication since REFCLK is operating at twice of the data rate.

The asserted state of this output (HIGH or LOW) is determined by the state of

the EXTFIFO input. When EXTFIFO is LOW, TXFULL is active LOW. When

EXTFIFO is HIGH, TXFULL is active HIGH.

70

TXHALF

Three-state TTL

output, changes

following TXCLK↑

Transmit FIFO Half-full Status Flag.

When the Transmit FIFO is enabled (FIFOBYP is HIGH and CE is LOW)

TXHALF is asserted when the HOTLink Transmit FIFO is half full (128

characters is half full). If a Transmit FIFO reset has been initiated (TXRST was

sampled asserted for a minimum of seven TXCLK cycles), TXHALF is asserted

to enforce the full/unavailable status of the Transmit FIFO during reset.

When the Transmit FIFO is bypassed (FIFOBYP is LOW), TXHALF remains

deasserted, having no logical function.

TXHALF is forced to the High-Z state only during a “full-chip” reset (i.e., while

RESET is LOW).

Document #: 38-02020 Rev. *C

Page 5 of 46

CY7C9689A

Pin Descriptions (continued)

60

Name

I/O Characteristics

Signal Description

Transmit FIFO Empty Status Flag.

When the Transmit FIFO is enabled (FIFOBYP is HIGH and CE is LOW),

TXEMPTY

Three-state TTL

output, changes

following TXCLK↑ or TXEMPTY is asserted when the HOTLink Transmit FIFO has no data to forward

REFCLK↑

to the encoder. If a Transmit FIFO reset has been initiated (TXRST was sampled

asserted for a minimum of seven TXCLK cycles), TXEMPTY is deasserted and

remains deasserted until the Transmit FIFO reset operation is complete.

When the Transmit FIFO is bypassed (FIFOBYP is LOW), TXEMPTY is

asserted to indicate that the transmitter can accept data. TXEMPTYis also used

as a BIST progress indicator when TXBISTEN is asserted.

When TXBISTEN is asserted LOW, TXEMPTY becomes the transmit BIST-loop

counter indicator (regardless of the logic state of FIFOBYP). In this mode

TXEMPTY is asserted for one TXCLK or REFCLK period at the end of each

transmitted BIST sequence.

Note: During BIST operations, when the Transmit FIFO is enabled (FIFOBYP

is HIGH), it is necessary to keep TXCLK operating, even though no data is

loaded into the Transmit FIFO and TXEN is never asserted, to allow the

TXEMPTY flag to respond to the BIST state changes.

The asserted state of this output (HIGH or LOW) is determined by the state of

the EXTFIFO input. When EXTFIFO is LOW, TXEMPTY is active LOW. When

EXTFIFO is HIGH, TXEMPTY is active HIGH.

If CE is sampled asserted (LOW), TXEMPTY is driven to an active state. If CE

is sampled deasserted (HIGH), TXEMPTY is placed into a High-Z state.

Receive Path Signals

RXCLK

8

Bidirectional TTL clock Receive Clock.

Internal Pull-up When the Receive FIFO is enabled (FIFOBYP is HIGH), this clock is the

Receive interface input clock and is used to control Receive FIFO read and

reset, operations. When the Receive FIFO is bypassed (FIFOBYP is LOW), this

clock becomes the recovered Receive PLL character clock output which runs

continuously at the character rate.

41, 43, RXDATA[7:0] Three-state TTL

Parallel Receive DATA Outputs.

45, 47,

48, 53,

59,61

output, changes

following RXCLK↑

When the decoder is enabled (ENCBYP is HIGH), the low-order eight bits of

the decoded DATA character are presented on the RXDATA[7:0] outputs.

COMMAND characters, when they are received, do not disturb these outputs.

When the decoder is bypassed, the low order eight bits of the non-decoded

character are presented on the RXDATA[7:0] outputs.

When the Receive FIFO is disabled (FIFOBYP is LOW), these outputs change

on the rising edge of the RXCLK output. When the Receive FIFO is enabled

(FIFOBYP is HIGH), these outputs change on the rising edge of RXCLK input.

RXEN is the three-state control for RXDATA[7:0].

31, 33 RXDATA[9:8]/ Three-state TTL

Parallel Receive DATA or COMMAND Output.

RXCMD[2:3]

output, changes

following RXCLK↑

When BYTE8/10 is HIGH and the decoder is enabled (ENCBYP is HIGH) these

outputs reflects the value for the most recently received RXCMD[2:3].

When BYTE8/10 is LOW and the decoder is enabled (ENCBYP is HIGH) these

outputs reflects the value for the most recently received RXDATA[9:8].

When the decoder is bypassed (ENCBYP is LOW), RXDATA[9:8] functions as

the 9th and 10th bits of the 10- or 12-bit non-decoded receive character.

When the Receive FIFO is disabled (FIFOBYP is LOW), these outputs change

on the rising edge of the RXCLK output. When the Receive FIFO is enabled

(FIFOBYP is HIGH), these outputs change on the rising edge of the RXCLK

input.

RXEN is a three-state control for RXDATA[9:8]/RXCMD[2:3].

Document #: 38-02020 Rev. *C

Page 6 of 46

CY7C9689A

Pin Descriptions (continued)

Name

I/O Characteristics

Signal Description

Parallel Receive COMMAND Outputs.

When the decoder is enabled (ENCBYP is HIGH) these outputs reflect the value

for the most recently received RXCMD[1:0].

23, 29 RXDATA[11:10 Three-state TTL

]/RXCMD[1:0]

output, changes

following RXCLK↑

When BYTE8/10 is HIGH and the decoder is bypassed (ENCBYP is LOW),

these outputs have no meaning and are driven LOW.

When BYTE8/10 is LOW and the decoder is bypassed (ENCBYP is LOW),

RXCMD[1:0] functions as the 11th and 12th (MSB) bits of the 12-bit

non-decoded receive character.

When the Receive FIFO is disabled (FIFOBYP is LOW), this output changes

on the rising edge of the RXCLK output. When the Receive FIFO is enabled

(FIFOBYP is HIGH), these outputs change on the rising edge of the RXCLK

input.

RXEN is a three-state control for RXCMD[1:0].

69

RXEN

TTL input, sampled

on RXCLK↑

Internal Pull-up

Receive Enable Input.

RXEN is a three-state control for the parallel data bus read operations. RXEN

is sampled on the rising edge of the RXCLK input (or output) and enables

parallel data bus read operations (when selected). The device is selected when

RXEN is asserted during an RXCLK cycle immediately following one in which

CE is sampled LOW. The parallel data pins are driven to active levels after the

rising edge of RXCLK. When RXEN is de-asserted (ending the selection) the

parallel data pins are High-Z after the rising edge of RXCLK.

Depending on the level on EXTFIFO, this signal can be active HIGH or active

LOW. If EXTFIFO is LOW, then RXEN is active LOW. If EXTFIFO is HIGH, then

RXEN is active HIGH. Data is delivered on the clock cycle following any clock

edge when RXEN is active.

65

RXSC/D

Three-state TTL

output, changes

following RXCLK↑

COMMAND or DATA Output Indicator.

When BYTE8/10 is HIGH and the decoder is enabled (ENCBYP is HIGH), this

output indicates which group of outputs have been updated. If RXSC/D is HIGH,

RXCMD[3:0] contains a new COMMAND. The DATA on the RXDATA[7:0] pins

remain unchanged. If RXSC/D is LOW, RXDATA[7:0] contains a new DATA

character. The COMMAND output on RXCMD[3:0] remain unchanged.

When BYTE8/10 is LOW and the decoder is enabled (ENCBYP is HIGH), this

output indicates which group of outputs have been updated. If RXSC/D is HIGH,

RXCMD[1:0] contains a new COMMAND and the DATA on the RXDATA[9:0]

remain unchanged. If RXSC/D is LOW, RXDATA[9:0] contains a new DATA

character and the COMMAND output on RXCMD[1:0] remain unchanged.

When the decoder is bypassed (ENCBYP is LOW) RXSC/D is not used and

may be left unconnected.

RXEN is a three-state control for RXSC/D.

6

VLTN

Three-state TTL

output, changes

following RXCLK↑

Internal Pull-down

Code Rule Violation Detected.

VLTN is asserted in response to detection of a 4B/5B or 5B/6B character that

does not meet the coding rules of these characters. When VLTN is asserted,

the values on the output DATA and COMMAND buses remain unchanged.

VLTN remains asserted for one RXCLK period.

VLTN is used to report character mismatches when RXBISTEN is driven LOW.

VLTN is driven LOW when the decoder is bypassed (ENCBYP is LOW).

RXEN is a three-state control for VLTN.

67

RXRST

TTL input, sampled on Receive FIFO Reset. Active LOW.

RXCLK↑

Internal Pull-up

When the Receive FIFO is enabled (FIFOBYP is HIGH), RXEN is deasserted,

CE is asserted (LOW), and RXRSTis sampled while asserted (LOW) by RXCLK

for seven cycles, the Receive FIFO begins its internal reset process.

Once the reset operation is started, the RXEMPTY flag is asserted and the

interface counters and address pointer are zeroed. The reset operation

proceeds to clear out the internal write pointers and counters. The RXEMPTY

output remains asserted through the reset operation and remains asserted until

new data is written to the Receive FIFO. While RXRST remains asserted, the

Receive FIFO remains in reset and cannot accept received characters.

When the Receive FIFO is bypassed (FIFOBYP is LOW), RXRST is ignored.

Document #: 38-02020 Rev. *C

Page 7 of 46

CY7C9689A

Pin Descriptions (continued)

Name

I/O Characteristics

Signal Description

Receiver Discard Policy Mode Select.

00b—allows all characters to be written into the Receive FIFO or output to the

24, 25 RXMODE[1:0] Static control input

TTL levels

Normally wired HIGH Receive data bus

or LOW

01b—discards all JK or LM sync characters except the “last” one of a string of

sync characters. Single sync characters in a data stream are included in the

data written into the Receive FIFO.

1Xb—discards all JK or LM sync characters. The data stream written into the

Receive FIFO does not include sync characters.

77

73

RXBISTEN

TTL input,

asynchronous

Internal Pull-up

Receiver BIST Enable. Active LOW.

When LOW, the receiver is configured to perform a character-for-character

match of the incoming data stream with a 511-character BIST sequence. The

result of character mismatches are indicated on the VLTN pin. Completion of

each 511-character BIST loop is accompanied by an assertion pulse on the

RXFULL flag.

The state of ENCBYP, FIFOBYP, and BYTE8/10 have no effect on BIST

operation.

RFEN

TTL input,

asynchronous

Internal Pull-up

Reframe Enable.

Used to control when the framer is allowed to adjust the character boundaries

based on detection of one or more framing characters in the data stream.

When framing is enabled (RFEN is HIGH) the receive framer realigns the serial

stream to the incoming 10-bit JK sync character (if BYTE8/10 is HIGH) or the

12-bit LM sync character (if BYTE8/10 is LOW). Framing is disabled when

RFEN is LOW. The deassertion of RFEN freezes the character boundary

relationship between the serial stream and character clock. RFEN is an

asynchronous input, sampled by the internal Receive PLL character clock.

10

RXFULL

Three-state TTL

output, changes

following RXCLK↑

Receive FIFO Full Flag.

When the Receive FIFO is enabled (FIFOBYP is HIGH) and its flags are driven

(CE is LOW), RXFULL is asserted when space is available for four or fewer

characters to be written to the HOTLink Receive FIFO. If the RXCLK input is

not continuous or the FIFO is accessed at a rate slower than data is being

received, RXFULL may also indicate that some data has been lost because of

FIFO overflow.

When the Receive FIFO is bypassed (FIFOBYP is LOW), RXFULL is

deasserted to indicate that valid data may be present. RXFULL is also used as

a BIST progress indicator, and pulses once every pass through the 511

character BIST loop.

When RXBISTEN is asserted (LOW), RXFULL becomes the receive BIST loop

progress indicator (regardless of the logic state of FIFOBYP). While RXBISTEN

is asserted, RXFULL is asserted until the receiver detects the start of the BIST

pattern. Then RXFULL is deasserted for the duration of the BIST pattern,

pulsing asserted for one RXCLK period on the last symbol of each BIST loop.

If 14 of 28 consecutive symbols are received in error, RXFULL returns to the

asserted state until the start of a BIST pattern is again detected.

The asserted state of this output (HIGH or LOW) is determined by the state of

the EXTFIFO input. When EXTFIFO is LOW, RXFULL is active LOW. When

EXTFIFO is HIGH, RXFULL is active HIGH.

19

RXHALF

Three-state TTL

output, changes

following RXCLK↑

Receive FIFO Half-full Flag.

When the Receive FIFO is enabled (FIFOBYP is HIGH and CE is LOW)

RXHALF is asserted when the HOTLink Receive FIFO is half full (128

characters is half full). If a Receive FIFO reset has been initiated (RXRST was

sampled asserted for a minimum of seven RXCLK cycles), RXHALF is

deasserted to enforce the empty/unavailable status of the Receive FIFO during

reset. If FIFOBYP is LOW, RXHALF remains deasserted having no logical

function.

RXHALF is forced to the High-Z state only during a “full-chip” reset (i.e., while

RESET is LOW).

Document #: 38-02020 Rev. *C

Page 8 of 46

CY7C9689A

Pin Descriptions (continued)

21

Name

I/O Characteristics

Signal Description

RXEMPTY

Three-state TTL

output, changes

following RXCLK↑

Receive FIFO Empty Flag.

When the Receive FIFO is enabled (FIFOBYP is HIGH) and its flags are driven

(CE is LOW), RXEMPTY is asserted when the HOTLink Receive FIFO has no

data to forward to the parallel interface. If a Receive FIFO reset has been

initiated (RXRST was sampled asserted for a minimum of seven RXCLK

cycles), RXEMPTY is asserted to enforce the empty/unavailable status of the

Receive FIFO during reset.

Any read operation occurring when RXEMPTY is asserted results in no change

in the FIFO status, and the data from the last valid read remains on the RXDATA

bus. When the Receive FIFO is bypassed but the decoder is enabled,

RXEMPTY is used as a valid data indicator. When deasserted it indicates that

valid data is present at the RXDATA or RXCMD outputs as indicated by

RXSC/D. When asserted it indicates that a SYNC character (JK or LM) is

present on the RXCMD output pins. When the Receive FIFO is bypassed

(FIFOBYP is LOW), RXEMPTY is deasserted whenever data is ready.

The asserted state of this output (HIGH or LOW) is determined by the state of

the EXTFIFO input. When EXTFIFO is LOW, RXEMPTY is active LOW. When

EXTFIFO is HIGH, RXEMPTY is active HIGH.

Control Signals

71

CE

TTL input sampled on Chip Enable Input. Active LOW.

TXCLK↑, RXCLK↑, or When CE is asserted and sampled LOW by RXCLK, the Receive FIFO status

REFCLK↑

flags are driven to their active states. When this input is deasserted and sampled

by RXCLK, the Receive FIFO status flags are placed in a High-Z state.

When CE has been sampled LOW and RXEN changes from deasserted to

asserted and is sampled by RXCLK, the RXSC/D, RXDATA[7:0], RXDATA[9:8]/

RXCMD[2:3] and VLTN output drivers are enabled and go to their driven levels.

These pins remain driven until RXEN is sampled deasserted.

When the Transmit FIFO is enabled (FIFOBYP is HIGH), and CE is asserted

and sampled by TXCLK, the Transmit FIFO status flags are driven to their active

states. When this input is deasserted and sampled by TXCLK, the Transmit

FIFO status flags are placed in a High-Z state.

When the Transmit FIFO is bypassed (FIFOBYP is LOW), and CE is asserted

and sampled by REFCLK, the Transmit FIFO status flags are driven to their

active states. When this input is deasserted and sampled by REFCLK, the

Transmit FIFO status flags are placed in a High-Z state.

When the Transmit FIFO is enabled (FIFOBYP is HIGH), CE has been sampled

LOW, and TXEN changes from deasserted to asserted and is sampled by

TXCLK, the TXSC/D, TXDATA[7:0], TXDATA[9:8]/RXCMD[2:3], and

TXCMD[1:0] inputs are sampled and passed to the Transmit FIFO. These inputs

are sampled on all consecutive TXCLK cycles until TXEN is sampled

deasserted.

When the Transmit FIFO is bypassed (FIFOBYP is LOW), CE has been

sampled LOW, and TXEN changes from deasserted to asserted and is sampled

by REFCLK, the TXSC/D, TXDATA[7:0], TXDATA[9:8]/RXCMD[2:3], and

TXCMD[1:0] inputs are sampled and passed to the encoder or serializer as

directed by other control inputs. These inputs are sampled on all consecutive

REFCLK cycles until TXEN is sampled deasserted.

12

75

REFCLK

SPDSEL

TTL clock input

PLL Frequency Reference Clock.

This clock input is used as the timing reference for the transmit and receive

PLLs. When the Transmit FIFO is bypassed (FIFOBYP is HIGH), REFCLK is

also used as the clock for the parallel transmit interface.

Static control input

TTL levels

Speed Select.

Used to select from one of two operating serial rates for the CY7C9689A. When

Normally wired HIGH SPDSEL is HIGH, the signaling rate is between 100 and 200 MBaud. When

or LOW

LOW, the signaling rate is between 50 and 100 MBaud. Used in combination

with RANGESEL and BYTE8/10 to configure the VCO multipliers and dividers.

Document #: 38-02020 Rev. *C

Page 9 of 46

CY7C9689A

Pin Descriptions (continued)

74

Name

I/O Characteristics

Signal Description

RANGESEL

Static control input

TTL levels

Range Select.

Selects the proper prescaler for the REFCLK input. If RANGESEL is LOW, the

Normally wired HIGH REFCLK input is passed directly to the Transmit PLL clock multiplier. If

or LOW

RANGESEL is HIGH, REFLCK is divided by two before being sent to the

Transmit PLL multiplier.

When the Transmit FIFO is bypassed (FIFOBYP is LOW), with RANGESEL

HIGH or SPDSEL LOW, TXFULL toggles at half the REFCLK rate to provide a

character rate indication, and to show when data can be accepted.

51

28

RESET

Asynchronous

TTL input

Master Reset for Internal Logic.

Pulsed LOW for one or more REFCLK cycles.

FIFOBYP

Static control input

TTL levels

FIFO Bypass Enable.

When asserted, the Transmit and Receive FIFOs are bypassed. In this mode

Normally wired HIGH TXCLK is not used. Instead all transmit data must be synchronous to REFCLK.

or LOW

Transmit FIFO status flags are synchronized to REFCLK. All received data is

synchronous to RXCLK output. Receive FIFO status flags are synchronized to

RXCLK (the recovered Receive PLL character clock).

When not asserted, the Transmit and Receive FIFOs are enabled. In this mode

all Transmit FIFO writes are synchronized to TXCLK, and all Receive FIFO

reads are synchronous to the RXCLK input.

50

BYTE8/10

Static control input

TTL levels

8/10-bit Parallel Data Size Select.

When set for 8-bit data (BYTE8/10 is HIGH) and the encoder is enabled

Normally wired HIGH (ENCBYP is HIGH), 8-bit DATA characters and 4-bit COMMAND characters are

or LOW

captured at the TXDATA[7:0] or TXCMD[3:0] inputs (selected by the TXSC/D

input) and passed to the Transmit FIFO (if enabled) and encoder. Received

characters are decoded, passed through the Receive FIFO (if enabled) and

presented at either the RXDATA[7:0] or RXCMD[3:0] outputs and indicated by

the RXSC/D output.

When set for 8-bit data (BYTE8/10 is HIGH) and the encoder is bypassed

(ENCBYP is LOW), the internal data paths are set for 10-bit characters. Each

received character is presented to the Receive FIFO (if enabled) and is passed

to the RXDATA[9:0] outputs.

When set for 10-bit data (BYTE8/10 is LOW) and the encoder is enabled

(ENCBYP is HIGH), 10-bit DATA characters and 2-bit COMMAND characters

are captured at the TXDATA[9:0] or TXCMD[1:0] inputs (selected by the

TXSC/D input) and passed to the Transmit FIFO (if enabled) and encoder.

Received characters are decoded, passed through the Receive FIFO (if

enabled) and presented at either the RXDATA[9:0] or RXCMD[1:0] outputs and

indicated by the RXSC/D output.

When set for 10-bit data (BYTE8/10 is LOW) and the encoder is bypassed

(ENCBYP is LOW), the internal clock data paths are set for 12-bit characters.

Each received character is presented to the Receive FIFO (if enabled) and is

passed to the RXDATA[9:0] and the RXCMD[1:0] outputs.

49

EXTFIFO

Static control input

TTL levels

External FIFO Mode.

EXTFIFO modifies the active state of the RXEN and TXEN inputs and the timing

Normally wired HIGH of the Transmitter and Receiver data buses. When configured for external

or LOW

FIFOs (EXTFIFO is HIGH), TXEN is assumed to be driven by the empty flag of

an attached CY7C42X5 FIFO, and RXEN is assumed to be driven by the almost

full flag of an attached CY7C42X5 FIFO. In this mode the active data transition

is in the clock following the clock edge that “enables” the data bus.

When not configured for external FIFOs (EXTFIFO is LOW), TXEN is assumed

to be driven as a pipeline register and RXEN is assumed to be driven by a

controller for a pipeline register. In this mode the active data transition is within

the same clock as the clock edge that “enables” the data bus.

EXTFIFO also modifies the output state of the Receive and Transmit FIFO flags.

When configured for external FIFOs (EXTFIFO is HIGH), the Full and Empty

FIFO flags are active HIGH (the Half full flag is always active LOW). When not

configured for external FIFOs (EXTFIFO is LOW), all of the FIFO flags are active

LOW.

Document #: 38-02020 Rev. *C

Page 10 of 46

CY7C9689A

Pin Descriptions (continued)

27

Name

I/O Characteristics

Signal Description

Enable Encoder Bypass Mode.

When asserted, both the encoder and decoder are bypassed. Data is trans-

ENCBYP

Static control input

TTL levels

Normally wired HIGH mitted without 4B/5B or 5B/6B encoding (but with NRZI encoding), LSB first.

or LOW

Received data are presented as parallel characters to the parallel interface

without decoding.

When deasserted, data is passed through both the encoder in the Transmit path

and the decoder in the Receive path.

Analog I/O and Control

89, 90, OUTA± PECL compatible

Differential Serial Data Outputs.

81, 82

OUTB±

differential output

These PECL-compatible differential outputs are capable of driving terminated

transmission lines or commercial fiber-optic transmitter modules. To minimize

the power dissipation of unused outputs, the outputs should be left unconnected

and the associated CURSETA or CURSETB should be connected to V_DD

.

94, 93, INA±

PECL compatible

differential input

Differential Serial Data Inputs.

86, 85

INB±

These inputs accept the serial data stream for deserialization and decoding.

Only one serial stream at a time may be fed to the receive PLL to extract the

data content. This stream is selected using the A/B input.

97

CURSETA

CURSETB

CARDET

Analog

Current-set Resistor Input for OUTA±.

A precision resistor is connected between this input and a clean ground to set

the output differential amplitude and currents for the OUTA± differential driver.

78

Current-set Resistor Input for OUTB±.

A precision resistor is connected between this input and a clean ground to set

the output differential amplitude and currents for the OUTB± differential driver.

100

PECL input,

Carrier Detect Input.

asynchronous

Used to allow an external device to signify a valid signal is being presented to

the high-speed PECL input buffers, as is typical on an Optical Module. When

CARDET is deasserted LOW, the LFI indicator asserts LOW signifying a Link

Fault. This input can be tied HIGH for copper media applications.

2

3

A/B

LFI

Asynchronous TTL

input

Input A or Input B Selector.

When HIGH, input INA± is selected, when LOW, INB± is selected.

TTL output, changes Link Fault Indication Output. Active LOW.

following RXCLK↑

LFI changes synchronous with RXCLK. This output is driven LOW when the

serial link currently selected by A/B is not suitable for data recovery. This could

be because:

Serial Data Amplitude is below acceptable levels

Input transition density is not sufficient for PLL clock recovery

Input Data stream is outside an acceptable frequency range of operation

CARDET is LOW

5

DLB

Asynchronous TTL

input

Diagnostic Loop Back Selector.

When DLB is LOW, LOOP Mode is OFF. Output of the transmitter shifter is

routed to both OUTA± and OUTB± and the serial input selected by A/B is routed

to the receive PLL for data recovery.

When DLB is HIGH, Diagnostic Loopback is Enabled. Output of the transmitter

serial data is routed to the receive PLL for data recovery. Primarily used for

System Diagnostic test. The serial inputs are ignored and OUTA± and OUTB±

are both active.

1

TEST

Asynchronous TTL

input normally wired

HIGH

Test Mode Select.

Used to force the part into a diagnostic test mode used for factory ATE test. This

input must be tied HIGH during normal operation.

Power

80, 87, V_DDA

88, 95,

Power for PECL-compatible I/O signals and internal circuits.

96, 98

Document #: 38-02020 Rev. *C

Page 11 of 46

CY7C9689A

Pin Descriptions (continued)

Name

I/O Characteristics

Signal Description

76, 79, V_SSA

83, 84,

91, 92,

99

Ground for PECL-compatible I/O signals and internal circuits.

14, 17, V_DD

35, 55,

62, 64

Power for TTL I/O signals and internal circuits.

Ground for TTL I/O signals and internal circuits.

4,11, V_SS

13, 15,

26, 37,

38, 39,

52, 57,

63, 66

When configured for synchronous operation, the transmit

CY7C9689A HOTLink Operation

interface is clocked by REFCLK and operates synchronous to

the internal character and bit-stream clocks. The input register

can be written at either 1/10 or 1/12 the serial bit rate. This

interface can be clocked at up to 40 MHz when configured for

8-bit data width, and up to 33 MHz when configured for 10-bit

data bus width. Actual clock rate depends on data rate as well

as RANGESEL and SPDSEL logic levels.

Overview

The CY7C9689A is designed to move parallel data across

both short and long distances with minimal overhead or host

system intervention. This is accomplished by converting the

parallel characters into a serial bit-stream, transmitting these

serial bits at high speed, and converting the received serial bits

back into the original parallel data format.

Both asynchronous and synchronous interface operations

support user control over the logical sense of the FIFO status

flags. Full and empty flags on both the transmitter and receiver

can be active HIGH or active LOW. This facilitates interfacing

with existing control logic or external FIFOs with minimal or no

external glue logic.

The CY7C9689A offers a large feature set, allowing it to be

used in a wide range of host systems. Some of the configu-

ration options are

• AMD TAXIchip 4B/5B- and 5B/6B-compatible

encoder/decoder

• AMD TAXIchip-compatible serial link

Encoder

• AMD TAXIchip parallel COMMAND and DATA I/O bus

Data from the host interface or Transmit FIFO is next passed

to an Encoder block. The CY7C9689A contains both 4B/5B

and 5B/6B encoders that are used to improve the serial

transport characteristics of the data. For those systems that

contain their own encoder or scrambler, this Encoder may be

bypassed.

architecture

• 8-bit or 10-bit character size

• User-definable data packet or frame structure

• Two-octave data rate range

• Asynchronous (FIFOed) or synchronous data interface

• Embedded or bypassable FIFO data storage

• Encoded or non-encoded

Serializer/Line Driver

The data from the Encoder is passed to a Serializer. This

Serializer operates at 10 or 12 times the character rate. With

the internal FIFOs enabled, REFCLK can run at 1x, 2x, or 4x

the character rate. With the FIFOs bypassed, REFCLK can

operate at 1x or 2x the character rate. The serialized data is

output in NRZI format from two PECL-compatible differential

line drivers configured to drive transmission lines or optical

modules.

• Multi-PHY capability

This flexibility allows the CY7C9689A to meet the data

transport needs of almost any system.

Transmit Data Path

Transmit Data Interface/Transmit Data FIFO

The transmit data interface to the host system is configurable

as either an asynchronous buffered (FIFOed) parallel interface

or as a synchronous pipeline register. The bus itself can be

configured for operation with either 8-bit or 10-bit character

widths.

Receive Data Interface

Line Receiver/Deserializer/Framer

Serial data is received at one of two PECL-compatible differ-

ential line receivers. The data is passed to both a Clock and

Data Recovery PLL and to a Deserializer that converts NRZI

serial data into NRZ parallel characters. The Framer adjusts

the boundaries of these characters to match those of the

original transmitted characters.

When configured for asynchronous operation (where the

host-bus interface clock operates asynchronous to the serial

character and bit stream clocks), the host interface becomes

that of a synchronous FIFO clocked by TXCLK. In this config-

uration an internal 256-character Transmit FIFO is enabled

that allows the host interface to be written at any rate from DC

to 50 MHz.

Decoder

The parallel characters are passed through a pair of 5B/4B or

6B/5B decoders and returned to their original form. For

Document #: 38-02020 Rev. *C

Page 12 of 46

CY7C9689A

systems that make use of external decoding or descrambling,

the decoder may be bypassed.

made compatible with asynchronous or synchronous host

system buses. These buses can take the form of external

FIFOs, state machines, or other control structures. Data and

command present on the TXDATA[9:0] and TXSC/D inputs are

captured at the rising edge of the selected sample clock. The

transmit data bus bit-assignments vary depending on the data

encoding and bus-width selected. These bus bit-assignments

are shown in Table 1, and list the functional names of these

different signals. Note that the function of several of these

signals changes in different operating modes. The logical

sense of the enable and FIFO flag signals depends on the

intended interface convention and is set by the EXTFIFO pin.

Receive Data Interface/Receive Data FIFO

Data from the decoder is passed either to a synchronous

Receive FIFO or is passed directly to the output register. The

output register can be configured for either 8-bit character or

10-bit character operation.

When configured for an asynchronous buffered (FIFOed)

interface, the data is passed through a 256-character Receive

FIFO that allows data to be read at any rate from DC to 50

MHz. When configured for synchronous operation (Receive

FIFO is bypassed) data is clocked out of the Receive Output

register at up to 20 MHz when configured for 8-bit characters,

or 16.67 MHz when configured for 10-bit characters. The

receive interface is also configurable for FIFO flags with either

HIGH or LOW status indication

The transmit interface supports both synchronous and

asynchronous clocking modes, each supporting both UTOPIA

and Cascade timing models. The selection of the specific

clocking mode is determined by the RANGESEL and SPDSEL

inputs and the FIFO Bypass (FIFOBYP) signal.

TXDATA[7:0]

REFCLK

TXCMD[3:0]

Oscillator Speed Selection

TXEN

TXCLK

TXSC/D

CE

The CY7C9689A is designed to operate over a two-octave

range of serial signaling rates, covering the 50- to 200-MBaud

range. To cover this wide range, the PLLs are configured into

various sub-regions using the SPDSEL and RANGESEL

inputs, and to a limited extent the BYTE8/10 input. These

inputs are used to configure the various prescalers and clock

dividers used with the transmit and receive PLLs.

12

Transmit Input Register

14

CY7C9689A TAXI HOTLink Transceiver

Block Diagram Description

Transmit Input/Output Register

Transmit FIFO

The CY7C9689A provides a synchronous interface for data

and command inputs, instead of the TAXI’s asynchronous

strobed interface. The Transmit Input Register, shown in

Figure 2, captures the data and command to be processed by

the HOTLink Transmitter, and allows the input timing to be

Table 1. Transmit Input Bus Signal Map

To Encoder

Block

Figure 2. Transmit Input Register

Transmit Encoder Mode^[1]

Encoded 8-bit

Pre-encoded 10-bit

Character Stream

Encoded 10-bit

Pre-encoded 12-bit

Character Stream

TXDATA Bus Input Bit

TXSC/D

Character Stream^[2]

Character Stream^[3]

TXSC/D

TXDATA[0]

TXDATA[1]

TXDATA[2]

TXDATA[3]

TXDATA[4]

TXDATA[5]

TXDATA[6]

TXDATA[7]

TXCMD[3]

TXCMD[2]

TXCMD[1]

TXCMD[0]

TXD[0]^[4]

TXD[1]

TXD[2]

TXD[3]

TXD[4]

TXD[5]

TXD[6]

TXD[7]

TXD[8]

TXD[9]

TXDATA[0]

TXDATA[1]

TXDATA[2]

TXDATA[3]

TXDATA[4]

TXDATA[5]

TXDATA[6]

TXDATA[7]

TXDATA[8]

TXDATA[9]^[3]

TXCMD[1]

TXD[0]^[5]

TXD[1]

TXD[2]

TXD[3]

TXD[4]

TXD[5]

TXD[6]

TXD[7]

TXD[8]

TXD[9]

TXD[10]^[5]

TXD[11]

TXDATA[1]

TXDATA[2]

TXDATA[3]

TXDATA[4]

TXDATA[5]

TXDATA[6]

TXDATA[7]

TXDATA[8]/TXCMD[3]

TXDATA[9]/TXCMD[2]

TXCMD[1]

TXCMD[0]

Notes:

1. All open cells are ignored.

2. When ENCBYP is HIGH and BYTE8/10 is HIGH, transmitted bit order is the encoded form (MSB to LSB) of TXDATA[7,6,5,4] and TXDATA[3,2,1,0] or

TXCMD[3,2,1,0] as selected by TXSC/D.

3. When ENCBYP is HIGH and BYTE8/10 is LOW, transmitted bit order is the encoded form (MSB to LSB) of TXDATA[8,7,6,5,4] and TXDATA[9,3,2,1,0] or

TXCMD[1,0] as selected by TXSC/D.

4. When ENCBYP is LOW and BYTE8/10 is HIGH, the transmitted bit order is (LSB to MSB) TXD[0,1,2,3,4,5,6,7,8,9].

5. When ENCBYP is LOW and BYTE8/10 is LOW, the transmitted bit order is (LSB to MSB) TXD[0,1,2,3,4,5,6,7,8,9,11,10].

Document #: 38-02020 Rev. *C

Page 13 of 46

CY7C9689A

Synchronous Interface

write is enabled (the device is selected and TXEN is sampled

asserted), data is captured in the transmit input register and

stored into the Transmit FIFO. All Transmit FIFO write opera-

tions are clocked by TXCLK.

Synchronous interface clocking operates the entire transmit

data path synchronous to REFCLK. It is enabled by

connecting FIFOBYP LOW to disable the internal FIFOs.

The Transmit FIFO presents Full, Half-Full, and Empty FIFO

flags. These flags are provided synchronous to TXCLK. When

the Transmit FIFO is enabled, it allows operation with a

Moore-type external controlling state machine. When

configured for Cascade timing, the timing and active levels of

these signals are also designed to support direct expansion to

Cypress CY7C42x5 synchronous FIFOs.

Asynchronous Interface

Asynchronous interface clocking controls the writing of host

bus data into the Transmit FIFO. It is enabled by setting

FIFOBYP HIGH to enable the internal FIFOs. In these config-

urations, all writes to the Transmit Input Register, and

associated transfers to the Transmit FIFO, are controlled by

TXCLK. The remainder of the transmit data path is clocked by

REFCLK or synthesized derivatives of REFCLK.

Regardless of bus width (8- or 10-bit characters) the Transmit

FIFO can be clocked at any rate from DC to 50 MHz. This

gives the Transmit FIFO a maximum bandwidth of 50 million

characters per second. Since the serial outputs can only move

20 million characters per second at their fastest operating rate,

there is ample time to service multiple CY7C9689A HOTLinks

with a single controller.

Shared Bus Timing Model

The Shared Bus Timing Model allows multiple CY7C9689A

transmitters to be accessed from a common host bus. It is

enabled by setting EXTFIFO LOW. In shared bus timing, the

TXEMPTY and TXFULL outputs and TXEN input are all active

LOW signals. If the CY7C9689A is addressed by asserting CE

LOW, it becomes “selected” when TXEN is asserted LOW.

Following selection, data or command is written into the

Transmit FIFO on every clock cycle where TXEN remains

LOW.

The read port of the Transmit FIFO is connected to a logic

block that performs data formatting and validation. All data

read operations from the Transmit FIFO are controlled by a

Transmit Control State Machine that operates synchronous to

REFCLK.

Encoder Block

Cascade Timing Model

The Encoder logic block performs two primary functions:

encoding the data for serial transmission and generating BIST

patterns to allow at-speed link and device testing.

The Cascade timing model is a variation of the shared bus

timing model. Here the TXEMPTY and TXFULL outputs, and

TXEN input, are all active HIGH signals. Cascade timing

makes use of the same selection sequences as shared bus

timing, but write data accesses use a delayed write. This

delayed write is necessary to allow direct coupling to external

FIFOs, or to state machines that initiate a write operation one

clock cycle before the data is available on the bus.

BIST LFSR

The Encoder logic block operates on data stored in a register.

This register accepts information directly from the Transmit

FIFO, the Transmit Input Register or from the Transmit Control

State Machine when it inserts special characters into the data

stream.

Cascade timing is enabled by setting EXTFIFO HIGH.

When used for FIFO depth expansion, Cascade timing allows

the size of the internal Transmit FIFO to be expanded to an

almost unlimited depth. It allows a CY7C42x5 series

synchronous FIFO to be attached to the transmit interface

without any extra logic, as shown in Figure 3.

This same register is converted into a Linear Feedback Shift

Register (LFSR) when the BIST pattern generator is enabled

(TXBISTEN is LOW). When enabled, this LFSR generates a

511-character sequence that includes all Data and Special

Character codes, including the explicit violation symbols. This

provides a predictable but pseudo-random sequence that can

be matched to an identical LFSR in the Receiver.

CY7C42x5 FIFO

FF* EF*

WEN* REN*

CY7C9689A

FF*

TXEN

Encoder

WEN*

TXFULL

The data passed through the Transmit FIFO and pipeline

register, or as received directly from the Transmit Input

Register, is seldom in a form suitable for transmission across

a serial link. The characters must usually be processed or

transformed to guarantee:

D

Q

TXDATA

TXSC/D

TXCLK

WCLK RCLK

TXCLK

•a minimum transition density (to allow the serial receiver PLL

to extract a clock from the data stream)

•some way to allow the remote receiver to determine the

correct character boundaries (framing).

“1”

EXTFIFO

The CY7C9689A contains an integrated 4B/5B encoder that

accepts 8-bit data characters and converts these into 10-bit

transmission characters that have been optimized for

transport on serial communications links. This 4B/5B encoding

scheme is compliant with the ANSI X3T9.5 (FDDI)

committee’s 4B/5B code. The CY7C9689A also contains a

5B/6B encoder that accepts 10-bit data characters and

converts these into 12-bit transmission characters.

Figure 3. External FIFO Depth Expansion of the

CY7C9689A Transmit Data Path

Transmit FIFO

The Transmit FIFO is used to buffer data and command

captured in the input register for later processing and trans-

mission. This FIFO is sized to hold 256 14-bit characters.

When the Transmit FIFO is enabled, and a Transmit FIFO

Document #: 38-02020 Rev. *C

Page 14 of 46

CY7C9689A

The 4B/5B, 5B/6B encoder can be bypassed for those

systems that operate with external 4B/5B or 5B/6B encoders

or use alternate forms of encoding or scrambling to ensure

good transmission characteristics. The complete encoding

tables are listed in Table 7 and Table 8.

OUTA± receives its data directly from the transmit shifter, while

OUTB± receives its data from the Routing Matrix. These two

outputs (OUTA± and OUTB±) are capable of direct connection

to +5V optical modules, and can also directly drive DC- or

AC-coupled transmission lines.

When the Encoder is enabled, the transmit data characters (as

passed through the Transmit FIFO and pipeline register) are

converted to either a 10-bit or 12-bit Data symbol or a 10-bit or 12-bit

Command Character, depending upon the state of the TXSC/D

input. If TXSC/D is HIGH, the data on the command inputs are

encoded into Command Character as shown in Table 8. If TXSC/D

is LOW, the data inputs are encoded using the Data Character

encoding in Table 7.

The PECL-compatible Output Drivers can be viewed as

programmable current sources. The output voltage is deter-

mined by the output current and the load impedance Z_LOAD

.

The desired output voltage swing is therefore controlled by the

current-set resistor R_CURSETassociated with that driver.

Different R_CURSETvalues are required for different line

impedance/amplitude combinations. The output swing is

designed to center around V_DD–1.33V. Each output must be

externally biased to V_DD–1.33V.

The 4B/5B, 5B/6B coding function of the Encoder can be

bypassed for systems that include an external coder or

scrambler function as part of the controller or host system. This

is performed by setting ENCBYP LOW. With the encoder

bypassed, each 10-bit or 12-bit character (as captured in the

Transmit Input Register) is passed directly to the Transmit

Shifter (or Transmit FIFO) without modification.

This differential output-swing can be specified two ways: either

as a peak-to-peak voltage into a single-end load, or as an

absolute differential voltage into a differential load.

When specified into a single-ended load (one of the outputs

switching into a load), the single output will both source and

sink current as it changes between its HIGH and LOW levels.

The voltage difference between this HIGH level and LOW level

determine the peak-to-peak signal-swing of the output. This

amplitude relationship is controlled by the load impedance on

the driver, and by the resistance of the R_CURSETresistor for

that driver, as listed in Eq. 1

Transmit Shifter

The Transmit Shifter accepts 10-bit (BYTE8/10 = HIGH) or

12-bit (BYTE8/10 = LOW) parallel data from the Encoder block

once each character time, and shifts it out the serial interface

output buffers using a PLL-multiplied bit-clock with NRZI

encoding. This bit-clock runs at 2.5, 5, or 10 times the REFCLK

rate (3, 6, or 12 times when BYTE8/10 is LOW) as selected by

RANGESEL and SPDSEL (see Table 3). Timing for the

parallel transfer is controlled by the counter and dividers in the

Clock Multiplier PLL and is not affected by signal levels or

timing at the input pins. Bits in each character are shifted out

LSB first.

180 × Z_LOAD

R_CURSET= ---------------------------------

Eq. 1

V_OPP

In Eq. 1, V_OPPis the difference in voltage levels at one output

of the differential driver when that output is driving HIGH and

LOW, Z_LOADis that load seen by the one output when it is

sourcing and sinking current. With a known load impedance

and a desired signal swing, it is possible to calculate the value

of the associated CURSETA or CURSETB resistor that sets

this current.

Routing Matrix

The Routing Matrix is a precision multiplexor that allows local

diagnostic loopback. The signal routing for the transmit serial

outputs is controlled by the DLB input as listed in Table 2.

Unused differential output drivers should be left open, and can

reduce their power dissipation by connecting their respective

Table 2. Transmit Data Routing Matrix

CURSETx input to V_DD

.

DLB[0]

Data Connections

Transmit PLL Clock Multiplier

The Transmit PLL Clock Multiplier accepts an external clock at

the REFCLK input, and multiples that clock by 2.5, 5, or 10 (3,

6, or 12 when BYTE8/10 is LOW and the encoder is disabled)

to generate a bit-rate clock for use by the transmit shifter. It

also provides a character-rate clock used by the Transmit

Controller state machine.

0

TRANSMIT

OUTA

OUTB

SHIFTER

A/B

INB

INA

RECEIVE

PLL

The clock multiplier PLL can accept a REFCLK input between

8 MHz and 40 MHz, however, this clock range is limited by the

operation mode of the CY7C9689A as selected by the

SPDSEL and RANGESEL inputs, and to a limited extent, by

the BYTE8/10 and FIFOBYP signals. The operating serial

signalling rate and allowable range of REFCLK frequencies is

listed in Table 3.

1

TRANSMIT

SHIFTER

OUTA

OUTB

A/B

INB

INA

RECEIVE

PLL

Transmit Control State Machine

The Transmit Control State Machine responds to multiple

inputs to control the data stream passed to the encoder. It

operates in response to:

Serial Line Drivers

The serial interface PECL Output Drivers (ECL referenced to

+5V) are the transmission line drivers for the serial media.

Document #: 38-02020 Rev. *C

Page 15 of 46

CY7C9689A

Table 3. Speed Select and Range Select Settings

generally used only for local diagnostic loopback purposes. The

serial line receiver inputs are all differential, and will accommodate

wire interconnect with filtering losses or transmission line attenu-

ation greater than 9 dB (V_DIF> 200 mV, or 400 mV peak-to-peak

differential) or can be directly connected to +5V fiber-optic interface

modules (any ECL logic family, not limited to ECL 100K). The

common-mode tolerance of these line receivers accommodates a

wide range of signal termination voltages.

Serial

Data Rate

(MBaud)

REFCLK^[7]

Frequency

(MHz)

SPDSEL

LOW

RANGESEL

LOW

50–100

10–20

20–40

10–20

20–40

LOW

HIGH^[6]

As can be seen in Table 2, these inputs are configured to allow

single-pin control for most applications. For those systems

requiring selection of only INA± or INB±, the DLB signals can be

tied LOW, and the A/B selection can be performed using only

A/B. For those systems requiring only a single input and a local

loopback, the A/B can be tied HIGH or LOW, and DLB can be

used for loopback control.

HIGH

LOW

100–200

HIGH

•the state of the FIFOBYP input

•the presence of data in the Transmit FIFO

•the contents of the Transmit FIFO

Signal Detect

•the state of the transmitter BIST enable (TXBISTEN)

•the state of external halt signal (TXHALT).

The selected Line Receiver (that routed to the clock and data

recovery PLL) is simultaneously monitored for:

These signals are used by the Transmit Control State Machine

to control the data formatter, read access to the Transmit FIFO

and BIST. They determine the content of the characters

passed to the Encoder and Transmit Shifter.

•analog amplitude (> 400 mV pk-pk)

•transition density

•received data stream outside normal frequency range

(±400 ppm)

When the Transmit FIFO is bypassed, the Transmit Control

State Machine operates synchronous to REFCLK. In this

mode, data from the TXDATA bus is passed directly from the

Input Register to the Pipeline Register. If no data is enabled

into the Input register (TXEN is deasserted or TXFULL is

asserted) then the Transmit Control State Machine presents a

JK or LM (when BYTE8/10 = LOW) Command Character code

to the Encoder to maintain link synchronization.

•carrierdetected.

All of these conditions must be valid for the Signal Detect block

to indicate a valid signal is present. This status is presented on

the LFI (Link Fault Indicator) output, which changes

synchronous to RXCLK. While link status is monitored inter-

nally at all times, it is necessary to have transitions on RXCLK

to allow this signal to change externally.

If both the Encoder and Transmit FIFO are bypassed and no

data is enabled into the Input Register, the Transmit Control

State Machine injects JK or LM (when BYTE8/10 = LOW) into

the Serial Shifter Register at this time slot. This also occurs if

the Encoder is bypassed, the Transmit FIFO is enabled, and

the Transmit FIFO is empty.

Clock/Data Recovery

The extraction of a bit-rate clock and recovery of data bits from

the received serial stream is performed within the Clock/Data

Recovery (CDR) block. The clock extraction function is

performed by a high-performance embedded PLL that tracks

the frequency of the incoming bit stream and aligns the phase

of its internal bit-rate clock to the transitions in the serial data

stream.

External Control of Data Flow

The Transmit Control State Machine supports halting of data

transmission by the TXHALT input. This control signal input is

only interpreted when the Transmit FIFO is enabled. TXHALT

is brought directly to the state machine without going through

the Transmit FIFO.

The CDR makes use of the clock present at the REFCLK input.

It is used to ensure that the VCO (within the CDR) is operating

at the correct frequency (rather than some harmonic of the bit

rate), to improve PLL acquisition time, and to limit unlocked

frequency excursions of the CDR VCO when no data is

present at the serial inputs.

The assertion of TXHALT causes character processing to stop

at the next FIFO character location. No additional data is read

from the Transmit FIFO until TXHALT is deasserted.

Regardless of the type of signal present, the CDR will attempt

to recover a data stream from it. If the frequency of the

recovered data stream is outside the limits for the range

controls, the CDR PLL will track REFCLK instead of the data

stream. When the frequency of the selected data stream

returns to a valid frequency, the CDR PLL is allowed to track

the received data stream. The frequency of REFCLK is

required to be within ±400 ppm of the frequency of the clock

that drives the REFCLK signal at the remote transmitter to

ensure a lock to the incoming data stream.

TXHALT may be used to prevent a remote FIFO overflow,

which would result in lost data. This back-pressure mechanism

can significantly improve data integrity in systems that cannot

guarantee the full bandwidth of the host system at all times.

Serial Line Receivers

Two differential line receivers, INA± and INB±, are available for

accepting serial data streams, with the active input selected

using the A/B input. The DLB input allow the transmit Serializer

output to be selected as a third input serial stream, but this path is

Notes:

6. When SPDSEL is LOW and the FIFOs are bypassed (FIFOBYP is LOW), the RANGESEL input is ignored and is internally mapped to the LOW setting.

7. When configured for 12-bit preencoded data (BYTE8/10 and ENCBYP are both LOW) the allowable REFCLK ranges are 8.33 to 16.67 MHz and 16.67 to

33.33 MHz.

Document #: 38-02020 Rev. *C

Page 16 of 46

CY7C9689A

For systems using multiple or redundant connections, the LFI

output can be used to select an alternate data stream. When

an LFI indication is detected, external logic can toggle

selection of the INA± and INB± inputs through the A/B input.

When a port switch takes place, it is necessary for the PLL to

reacquire the new serial stream and frame to the incoming

characters.

BIST LFSR

The output register of the Decoder block is normally used to

accumulate received characters for delivery to the Receive

Formatter block. When configured for BIST mode (RXBISTEN

is LOW), this register becomes a signature pattern generator

and checker by logically converting to a Linear Feedback Shift

Register (LFSR). When enabled, this LFSR generates a

511-character sequence that includes all Data and Command

Character codes, including the explicit violation symbols. This

provides a predictable but pseudo-random sequence that can

be matched to an identical LFSR in the Transmitter. When

synchronized with the received data stream, it checks each

character in the Decoder with each character generated by the

LFSR and indicates compare errors at the VLTN output of the

Receive Output Register.

Clock Divider

This block contains the clock division logic, used to transfer the

data from the Deserializer/Framer to the Decoder once every

character (once every ten or twelve bits) clock. This counter is

free running and generates outputs at the bit-rate divided by

10 (12 when the BYTE8/10 is LOW). When the Receive FIFO

is bypassed, one of these generated clocks is driven out the

RXCLK pin.

The LFSR is initialized by the BIST hardware to the BIST loop

start code of HEX data 00 (00 is sent only once per BIST loop).

Once the start of the BIST loop has been detected by the

receiver, RXRVS is asserted for pattern mismatches between

the received characters and the internally generated character

sequence. Code rule violations or running disparity errors that

occur as part of the BIST loop do not cause an error indication.

RXFULL pulses asserted for one RXCLK cycle per BIST loop and

can be used to check test pattern progress.

Deserializer/Framer

The CDR circuit extracts bits from the serial data stream and

clocks these bits into the Shifter/Framer at the bit-clock rate.

When enabled, the Framer examines the data stream looking

for JK or LM (when BYTE8/10 is LOW) characters at all

possible bit positions. The location of this character in the data

stream is used to determine the character boundaries of all

following characters.

The specific patterns checked by the receiver are described in

Table 4.

The framer operates in two different modes, as selected by the

RFEN input. When RFEN is asserted (HIGH), the framer is

allowed to reset the internal character boundaries on any

detected JK or LM (when BYTE8/10 is LOW) character.

If a large number of errors are detected, the receive BIST state

machine aborts the compare operations and resets the LFSR

to the D0.0 state to look for the start of the BIST sequence

again.

If RFEN is LOW, the framer is disabled and no changes are

made to character boundaries.

Receive Control State Machine

The framer in the CY7C9689A operates by shifting the internal

character position to align with the character clock. This

ensures that the recovered clock does not contain any signif-

icant phase changes/hops during normal operation or framing,

and allows the recovered clock to be replicated and distributed

to other circuits using PLL-based logic elements.

The Receive Control State Machine responds to multiple input

conditions to control the routing and handling of received

characters. It controls the staging of characters across various

registers and the Receive FIFO. It controls the various discard

policies and error control within the receiver, and operates in

response to:

Decoder Block

•the received character stream

The decoder logic block performs two primary functions:

decoding the received transmission characters back into Data

and Command Character codes, and comparing generated

BIST patterns with received characters to permit at-speed link

and device testing.

•the room for additional data in the Receive FIFO

•the state of the receiver BIST enable (RXBISTEN)

•the state of FIFOBYP.

These signals and conditions are used by the Receive Control

State Machine to control the Receive Formatter, write access

to the Receive FIFO, the Receive Output register, and BIST.

They determine the content of the characters passed to each

of these destinations.

5B/4B, 6B/5B Decoder

The framed parallel output of the Deserializer is passed to the

5B/4B, 6B/5B Decoder. If the Decoder is enabled, it is trans-

formed from a 10-bit or 12-bit transmission character back to

the original Data and Command Character codes. This block

uses the standard decoder patterns in Table 7 and Table 8 of

this data sheet. Data Patterns on the data bus are indicated by

a LOW on RXSC/D, and Command Character codes on the

command bus are indicated by a HIGH. Invalid patterns or disparity

errors are signaled as errors by a HIGH on VLTN.

The Receive Control State Machine always operates

synchronous to the recovered character clock (bit-clock/10 or

bit-clock/12). When the Receive FIFO is bypassed, RXCLK

becomes an output that changes synchronous to the internal

character clock. RXCLK operates at the same frequency as

the internal character clock.

Discard Policies

If the Decoder is bypassed and BYTE8/10 is HIGH, the ten

(10) data bits of each transmission character are passed

unchanged from the framer to the Pipeline Register.

When the Receive FIFO is enabled, the Receive Control State

Machine has the ability to selectively discard specific

characters from the data stream that are determined by the

present configuration as being unnecessary. When discarding

is enabled, it reduces the host system overhead necessary to

keep the Receive FIFO from overflowing and losing data.

When the Decoder is bypassed and BYTE8/10 is LOW, the

twelve (12) data bits of each transmission character are

passed unchanged from the framer to the Pipeline Register.

Document #: 38-02020 Rev. *C

Page 17 of 46

CY7C9689A

able 4. CY7C9689A TAXI HOTLink BIST Sequence

D.00 C.JK C.IH C.SR C.SS C.QQ D.FB D.77

C.JK C.IH C.QI D.EE C.RR D.B3 D.55 D.2C

C.TR C.SR C.SS C.QQ D.F8 C.TS C.QH D.D2

D.89 D.42 C.HI D.94 C.TT C.TR C.QI D.EB

D.3D D.1E C.HH D.8F D.4B D.23 D.11 D.04

C.JK C.RS D.C5 D.68 C.II

C.RS D.C0 C.TS

C.RR D.BC C.TT C.QH D.D7 D.6D D.3A C.HH

D.73 D.35 D.1C C.JK C.RS D.CF D.6B D.33

D.15 D.0C C.JK C.RS D.CD D.6A C.HI D.91

D.A8 C.TT C.QH D.D4 C.TS C.TR C.QI D.E3

D.99 D.46 C.HI D.96 C.HQ D.AE C.HQ D.A3

D.44 C.II

C.IH C.QI D.E6 C.RR D.B2 C.HQ

D.71 D.34 C.JK C.IH C.QI D.ED D.7A C.HI

D.51 D.24 C.JK C.IH C.QI D.EC C.TS C.QH

C.QI D.E0 C.TS C.TR C.SR C.SS C.SS C.SS

D.D1 D.64 C.II

C.IH C.QI D.E4 C.RR C.TR

C.SS C.QQ D.F0 C.TS C.TR C.SR C.QQ D.F4

C.QQ D.FC C.TS C.QH D.D3 D.65 D.38 C.JK

C.TS C.TR C.QI D.E1 D.70 C.II

C.IH C.SR

C.RS D.C6 C.RR D.B6 C.HQ D.AA C.HQ D.A1

D.9B D.47 D.29 D.12 C.HH D.8C C.TT C.QH

D.C4 C.TS C.TR C.QI D.E2 C.RR D.B0 C.TT

D.50 C.II

C.IH C.SR C.QQ D.FD D.7E C.HI

D.DD D.6E C.HI D.93 D.45 D.28 C.JK C.RS

C.TR C.SR C.QQ D.F6 C.RR D.BA C.HQ D.A9

D.52 C.HI D.9C C.TT C.QH D.DF D.6F D.3B

D.C8 C.TS C.QH D.D8 C.TS C.QH D.DA C.RR

D.08 C.JK C.RS D.CC C.TS C.QH D.D9 D.66

D.17 D.0D D.0A C.HH D.85 D.48 C.II

C.RS

D.BD D.5E C.HI D.9F D.4F D.2B D.13 D.05

C.HI D.92 C.HQ D.AC C.TT C.QH D.D5 D.6C

C.II

C.RS D.C1 D.60 C.II

C.IH C.SR C.SS

C.SS C.SS C.QQ D.F1 D.74 C.II

C.IH C.QI

D.E5 D.78 C.II

C.RS D.C2 C.RR D.B4 C.TT

C.TR C.QI D.E9 D.72 C.HI D.98 C.TT C.QH

D.02 C.HH D.84 C.TT C.TR C.QI D.EA C.RR

D.DE C.RR D.BF D.5F D.2F D.1B D.07 D.09

D.B1 D.54 C.II C.IH C.QI D.E7 D.79 D.36

C.RR D.B5 D.5C C.II C.RS D.CB D.63 D.31

C.HH D.8A C.HQ D.A5 D.58 C.II

C.RS D.CA

D.14 C.JK C.IH C.QI D.EF D.7B D.37 D.1D

C.TR C.SR C.SS C.QQ D.F9 D.76 C.HI D.9A

D.0E C.HH D.87 D.49 D.22 C.HH D.80 C.TT

C.HQ D.AD D.5A C.HI D.9D D.4E C.HI D.97

C.SS C.QQ D.FA C.RR D.B9 D.56 C.HI D.9E

C.HQ D.A6 C.HQ D.A2 C.HQ D.AO C.TT C.TR

D.4D D.2A C.HH D.81 D.40 C.II

C.IH C.SR

C.HQ D.AF D.5B D.27 D.19 D.06 C.HH D.86

C.SR C.SS C.SS C.QQ D.F2 C.RR D.B8 C.TT

D.18 C.JK C.RS D.CE C.RR D.B7 D.5D D.2E

C.SS C.QQ D.F3 D.75 D.3C C.JK C.RS D.C7

C.QH D.DB D.67 D.39 D.16 C.HH D.8E C.HQ

C.QH D.D6 C.RR D.BE C.HQ D.AB D.53 D.25

C.HH D.83 D.41 D.20 C.JK C.IH C.SR C.SS

D.69 D.32 C.HH D.88 C.TT C.QH D.DC C.TS

D.A7 D.59 D.26 C.HH D.82 C.HQ D.A4 C.TT

C.TR C.QI D.E8 C.TS C.QH D.D0 C.TS C.TR

D.30 C.JK C.IH C.SR C.QQ D.FE C.RR D.BB

C.SR C.QQ D.F5 D.7C C.II

C.RS D.C3 D.61

D.57 D.2D D.1A C.HH D.8D D.4A C.HI D.95

C.TR C.SR C.QQ D.F7 D.7D D.3E C.HH D.8B

D.4C C.II

C.RS D.C9 D.62 C.HI D.90 C.TT

D.43 D.21 D.10 C.JK C.IH C.SR C.QQ D.FF

D.7F D.3F D.1F D.0F D.0B D.03 D.01 GOTO

Start

The discard policy is configured as part of the operating mode

and is set using the RXMODE[1:0] inputs. The four discard

policies are listed in Table 5.

Table 5. Receiver Discard Policies

Policy # Policy Description

Policy 0 is the simplest and also applies for all conditions

where the Receive FIFO is bypassed. In this mode, every

character that is received is placed into the Receive FIFO

(when enabled) or into the Receive Output Register.

0 (00)

1 (01)

Keep all received characters

Process Commands, discard all but the last JK or

LM SYNC character

2 (1X) Process Commands, discard all C5.0 characters

Document #: 38-02020 Rev. *C

Page 18 of 46

CY7C9689A

In discard policy 1, the JK or LM SYNC character, which is

automatically transmitted when no data is present in the

Transmit FIFO, is treated differently here. In this mode,

whenever two or more adjacent JK or LM characters are

received, all of them are discarded except the last one

received before any other character type. This allows these fill

characters to be removed from the data stream, but the last

SYNC character which can be used as a delimiter.

CY7C42x5 FIFO

EF* FF*

REN* WEN*

CY7C9689A

EF*

RXEN

REN*

RXEMPTY

Q

D

RXDATA

RXSC/D

Policy 2 is identical to policy 1 except that all C5.0 characters

are removed from the data stream.

RXCLK

When the FIFOs are bypassed (FIFOBYP LOW), no

characters are actually discarded, but the receiver discard

policy can be used to control external filtering of the data. The

RXEMPTY FIFO flag is used to indicate if the character on the

output bus is valid or not. In discard policy 0, the RXEMPTY

flag is always deasserted to indicate that valid data is always

present. In discard policy 1, the RXEMPTY flag indicates an

empty condition for all but the last JK or LM character before

any other character is presented. In discard policy 2, the

RXEMPTY flag indicates an empty condition for all JK or LM

SYNC characters. When any other character is present, this

flag indicates that valid or “interesting” Data or Special

Characters are present.

RCLK WCLK

RXCLK

“1”

EXTFIFO

Figure 4. External FIFO Depth Expansion of the

CY7C9689A Receive Data Path

Receive Input Register

The input register is clocked by the rising edge of RXCLK. It

samples numerous signals that control the reading of the

Receive FIFO and operation of the Receive Control State

Machine.

Receive FIFO

The Receive FIFO is used to buffer data captured from the

selected serial stream for later processing by the host system.

This FIFO is sized to hold 256 14-bit characters. When the

FIFO is enabled, it is written to by the Receive Control State

Machine. When data is present in the Receive FIFO (as

indicated by the RXFULL, RXHALF, and RXEMPTY Receive

FIFO status flags), it can be read from the Output Register by

asserting CE and RXEN.

Receive Output Register

The Receive Output Register changes in response to the

rising edge of RXCLK. The Receive FIFO status flag outputs

of this register are placed in a High-Z state when the

CY7C9689A is not addressed (CE is sampled HIGH). The

RXDATA bus output drivers are enabled when the device is

selected by RXEN being asserted in the RXCLK cycle immedi-

ately following that in which the device was addressed (CE is

sampled LOW), and RXEN being sampled by RXCLK. This

initiates a Receive FIFO read cycle.

The read port on the Receive FIFO may be configured for the

same two timing models as the transmit interface: UTOPIA

and Cascade. Both are forms of a FIFO interface. The UTOPIA

timing model has active LOW RXEMPTY and RXFULL status

flags, and an active LOW RXEN enable. When configured for

Cascade operation, these same signals are all active HIGH.

Either timing model supports connection to various host bus

interfaces, state machines, or external FIFOs for depth

expansion (see Figure 4).

Just as with the TXDATA bus on the Transmit Input Register,

the receive outputs are also mapped by the specific decoding

and bus-width selected by the ENCBYP, BYTE8/10 and

FIFOBYP inputs. These assignments are shown in Table 6.

If the Receive FIFO and Decoder are bypassed, all received

characters are passed directly to the Receive Output Register.

If framing is enabled, and JK or LM sync characters have been

detected meeting the present framing requirements, the

output characters will appear on proper character boundaries.

If framing is disabled (RFEN is LOW) or sync characters have

not been detected in the data stream, the received characters

may not be output on their proper 10-bit boundaries. In this

mode, some form of external framing and decoding/descram-

bling must be used to recover the original source data.

The Receive FIFO presents Full, Half-Full, and Empty FIFO

status flags. These flags are provided synchronous to RXCLK

to allow operation with a Moore-type external controlling state

machine. When configured with the Receive FIFO enabled,

RXCLK is an input. When the Receive FIFO is bypassed

(FIFOBYP is LOW), RXCLK is an output operating at the

received character rate.

Document #: 38-02020 Rev. *C

Page 19 of 46

CY7C9689A

Table 6. Receiver Output Bus Signal Map

Receiver Decoder Mode^[1]

Encoded 8-bit

Pre-encoded 10-bit

Character Stream

Encoded 10-bit

Pre-encoded 12-bit

Character Stream

RXDATA Bus Output Bit Character Stream^[8]

Character Stream^[9]

RXSC/D

RXDATA[0]

RXSC/D

RXDATA[0]

RXDATA[1]

RXDATA[2]

RXDATA[3]

RXDATA[4]

RXDATA[5]

RXDATA[6]

RXDATA[7]

RXCMD[3]

RXCMD[2]

RXCMD[1]

RXCMD[0]

VLTN

RXSC/D

RXDATA[0]

RXDATA[1]

RXDATA[2]

RXDATA[3]

RXDATA[4]

RXDATA[5]

RXDATA[6]

RXDATA[7]

RXDATA[8]

RXDATA[9]^[9]

RXCMD[1]

RXCMD[0]

VLTN

RXD[0]^{[10, 11]}

RXD[1]

RXD[2]

RXD[3]

RXD[4]

RXD[5]

RXD[6]

RXD[7]

RXD[8]

RXD[9]

RXD[0]^{[10, 12]}

RXD[1]

RXDATA[1]

RXDATA[2]

RXD[2]

RXDATA[3]

RXD[3]

RXDATA[4]

RXD[4]

RXDATA[5]

RXD[5]

RXDATA[6]

RXD[6]

RXDATA[7]

RXD[7]

RXDATA[8]/RXCMD[3]

RXDATA[9]/RXCMD[2]

RXCMD[1]

RXD[8]

RXD[9]

RXD[10]^[12]

RXCMD[0]

RXD[11]

VLTN

Notes:

8. When BYTE8/10 is HIGH, received bit order is decoded form the serial stream and presented (MSB to LSB) at RXDATA[7,6,5,4] and RXDATA[3,2,1,0] or

RXCMD[3,2,1,0] as indicated by RXSC/D.

9. When BYTE8/10 is LOW, received bit order is decoded form the serial stream and presented (MSB to LSB) at RXDATA[8,7,6,5,4] and RXDATA[9,3,2,1,0]

or RXCMD[1,0] as indicated by RXSC/D.

10. First bit shifted into the receiver.

11. When ENCBYP is LOW and BYTE8/10 is HIGH, the received bit order is (LSB to MSB) RXD[0,1,2,3,4,5,6,7,8,9].

12. When ENCBYP is LOW and BYTE8/10 is LOW, the received bit order is (LSB to MSB) RXD[0,1,2,3,4,5,6,7,8,9,11,10].

Document #: 38-02020 Rev. *C

Page 20 of 46

CY7C9689A

DC Input Voltage ................................... –0.5V to V_DD+ 0.5V

Maximum Ratings

Static Discharge Voltage...........................................> 2001V

(per MIL-STD-883, Method 3015)

(Above which the useful life may be impaired. For user guide-

lines, not tested.)

Latch-up Current.....................................................> 200 mA

Operating Range

Storage Temperature .................................–65°C to +150°C

Ambient Temperature with (Power Applied)–55°C to +125°C

Supply Voltage to Ground Potential............... –0.5V to +6.5V

DC Voltage Applied to Outputs ..............–0.5V to V_DD+ 0.5V

Output Current into TTL Outputs (LOW)......................30 mA

Range

Commercial

Industrial

Ambient Temperature

0°C to +70°C

V_DD

5.0V ± 10%

–40°C to +85°C

CY7C9689A DC Electrical Characteristics Over the Operating Range

Parameter

Description

Test Conditions

Min.

Max.

Unit

TTL Outputs

V_OHT

V_OLT

I_OST

Output HIGH Voltage

Output LOW Voltage

I_OH= −2 mA, V_DD= Min.

I_OL= 8 mA, V_DD= Min.

V_OUT= 0V^[13]

2.4

V

0.4

−80

20

Output Short Circuit Current

–30

–20

mA

I_OZL

High-Z Output Leakage Current

TTL Inputs

V_IHT

V_ILT

Input HIGH Voltage

2.0

V_CC

0.8

V

Input LOW Voltage

–0.5

V

I_IHT

Input HIGH Current

V_IN= V_DD

V_IN= 0.0V

V_IN= V_CC

V_IN= 0.0V

±40

−40

+300

µA

I_ILT

Input LOW Current

I_ILPDT

I_ILPUT

Input HIGH Current with Internal Pull-down

Input LOW Current with Internal Pull-up

–300

Transmitter PECL-Compatible Output Pins: OUTA+, OUTA−, OUTB+, OUTB−

V_OHE

V_OLE

V_ODIF

Output HIGH Voltage (V_DDreferenced)

Load = 50Ω to V_DD− 1.33V;

R_CURSET= 10k

V

_DD− 1.03 V_DD− 0.83

V

Output LOW Voltage (V_DDreferenced)

Load = 50Ω to V_DD− 1.33V;

R_CURSET= 10k

V

_DD− 2.0

V

_DD− 1.62

Output Differential Voltage |(OUT+) − (OUT−)| Load = 50Ω to V_DD− 1.33V;

600

1100

mV

R_CURSET= 10k

Receiver Single-ended PECL-Compatible Input Pin: CARDET

V_IHE

V_ILE

I_IHE

I_ILE

Input HIGH Voltage (V_DDreferenced)

Input LOW Voltage (V_DDreferenced)

Input HIGH Current

V

_DD− 1.165

V_DD

_DD− 1.475

V

2.5

V

V_IN= V_IHE(min.)

V_IN= V_ILE(max.)

+40

µA

Input LOW Current

–40

200

2.5

Receiver Differential Line Receiver Input Pins: INA+, INA−, INB+, INB−

V_DIFF

V_IHH

V_ILL

Input Differential Voltage |(IN+) − (IN−)|

Highest Input HIGH Voltage

Lowest Input LOW Voltage

Input HIGH Current

2500

V_DD

mV

V

I_IHH

V_IN= V_IHHMax.

V_IN= V_ILLMin.

750

µA

[14]

I_ILL

Input LOW Current

−200

Typ.

170

Miscellaneous

Max.

[15]

I_DD

Power Supply Current

Freq. = Max.

Commercial

250

mA

Capacitance^[16]

Parameter

C_INTTL

C_INPECL

Notes:

Description

TTL Input Capacitance

PECL input Capacitance

Test Conditions

T_A= 25°C, f₀= 1 MHz, V_DD= 5.0V

Max.

7

4

Unit

pF

13. Tested one output at a time, output shorted for less than one second, less than 10% duty cycle.

14. To guarantee positive currents for all PECL voltages, an external pull-down resistor must be present.

15. Maximum I_CCis measured with V_DD= MAX, RFEN = LOW, and outputs unloaded. Typical I_DDis measured with V_DD= 5.0V, T_A= 25°C, RFEN = LOW, and

outputs unloaded.

16. Tested initially and after any design or process changes that may affect these parameters, but not 100% tested.

Document #: 38-02020 Rev. *C

Page 21 of 46

CY7C9689A

AC Test Loads and Waveforms

5.0V

R1

R2

OUTPUT

V_DD– 1.3

R1=500Ω

R =50Ω

L

C

L

R

L

C

R2=333Ω

C < 5 pF

L

C ≤ 10 pF

(Includes fixture and

probe capacitance)

L

(Includes fixture and

probe capacitance)

(a) TTL AC Test Load^[17]

(b) PECL AC Test Load ^[17]

V

IHE

3.0V

2.0V

V

3.0V

V =1.5V

IHE

2.0V

0.8V

80%

V =1.5V

th

20%

≤ 250 ps

20%

≤ 250 ps

0.8V

V

ILE

0.0V

< 1 ns

V

ILE

< 1 ns

(c) TTL Input Test Waveform

(d) PECL Input Test Waveform

CY7C9689A Transmitter TTL Switching Characteristics, FIFO Enabled Over the Operating Range

Parameter

f_TS

Description

TXCLK Clock Cycle Frequency With Transmit FIFO Enabled

TXCLK Period

Min.

Max.

Unit

MHz

ns

50

t_TXCLK

20

6.5

0.7

2

t_TXCPWH

t_TXCPWL

TXCLK HIGH Time

TXCLK LOW Time

TXCLK Rise Time^[18]

TXCLK Fall Time^[18]

[16]

t_TXCLKR

5

[16]

t_TXCLKF

t_TXA

Flag Access Time From TXCLK↑ to Output

Transmit Data Set-up Time to TXCLK↑

Transmit Data Hold Time from TXCLK↑

Transmit Enable Set-up Time to TXCLK↑

Transmit Enable Hold Time from TXCLK↑

Transmit FIFO Reset (TXRST) Set-up Time to TXCLK↑

Transmit FIFO Reset (TXRST Hold Time from TXCLK↑

Transmit Chip Enable (CE) Set-up Time to TXCLK↑

Transmit Chip Enable (CE) Hold Time from TXCLK↑

Sample of CE LOW by TXCLK↑, Output High-Z to Active HIGH or LOW

Sample of CE LOW by TXCLK↑ to Output Valid

Sample of CE HIGH by TXCLK↑ to Output in High-Z

15

t_TXDS

4

t_TXDH

1

t_TXENS

t_TXENH

t_TXRSS

t_TXRSH

t_TXCES

t_TXCEH

t_TXZA

4

1

4

1

4

1

0

t_TXOE

1.5

20

t_TXAZ

Notes:

17. Cypress uses constant current (ATE) load configurations and forcing functions. This figure is for reference only.

18. Input/output rise and fall time is measured between 0.8V and 2.0V

Document #: 38-02020 Rev. *C

Page 22 of 46

CY7C9689A

CY7C9689A Receiver TTL Switching Characteristics, FIFO Enabled Over the Operating Range

Parameter

f_RIS

Description

RXCLK Clock Cycle Frequency With Receive FIFO Enabled

RXCLK Input Period

Min.

Max.

Unit

MHz

ns

50

t_RXCLKIP

t_RXCPWH

t_RXCPWL

20

6.5

0.7

4

RXCLK Input HIGH Time

ns

RXCLK Input LOW Time

RXCLK Input Rise Time^[18]

RXCLK Input Fall Time^[18]

ns

[16]

t_RXCLKIR

5

ns

[16]

t_RXCLKIF

t_RXENS

t_RXENH

t_RXRSS

t_RXRSH

t_RXCES

t_RXCEH

t_RXA

ns

Receive Enable Set-up Time to RXCLK↑

Receive Enable Hold Time from RXCLK↑

Receive FIFO Reset (RXRXT) Set-up Time to RXCLK↑

Receive FIFO Reset (RXRXT) Hold Time from RXCLK↑

Receive Chip Enable (CE) Set-up Time to RXCLK↑

Receive Chip Enable (CE) Hold Time from RXCLK↑

Flag and Data Access Time From RXCLK↑ to Output

Sample of CE LOW by RXCLK↑, Output High-Z to Active HIGH or LOW,^[19]

or Sample of RXEN Asserted by RXCLK↑, Output High-Z to Active HIGH or LOW

Sample of CE LOW by RXCLK↑ to Output Valid,^[19]

ns

1

ns

4

ns

1

ns

4

ns

1

ns

1.5

0

15

ns

t_RXZA

ns

t_RXOE

t_RXZA

1.5

20

ns

or Sample of RXEN Asserted by RXCLK↑ to RXDATA Outputs Valid

Sample of CE HIGH by RXCLK↑ to Output in High-Z,^[19]

or Sample of RXEN Asserted by RXCLK↑ to RXDATA Outputs in High-Z

CY7C9689A Transmitter TTL Switching Characteristics, FIFO Bypassed Over the Operating Range

Parameter

t_TRA

Description

Min.

2

Max.

Unit

ns

Flag Access Time From REFCLK↑ to Output

Write Data Set-up Time to REFCLK↑

15

t_REFDS

4

t_REFDH

Write Data Hold Time from REFCLK↑

2

t_REFENS

t_REFENH

t_REFCES

t_REFCEH

t_REFZA

Transmit Enable Set-up Time to REFCLK↑

4

Transmit Enable Hold Time from REFCLK↑

2

Transmit Chip Enable (CE) Set-up Time to REFCLK↑

Transmit Chip Enable (CE) Hold Time from REFCLK↑

Sample of CE LOW by REFCLK↑, Output High-Z to Active HIGH or LOW

Sample of CE LOW by REFCLK↑ to Flag Output Valid

Sample of CE HIGH by REFCLK↑ to Flag Output High-Z

4

2

0

t_REFOE

t_REFAZ

1.5

20

CY7C9689A Receiver TTL Switching Characteristics, FIFO Bypassed Over the Operating Range

Parameter

Description

Min.

Max.

Unit

[20]

f_ROS

RXCLK Clock Output Frequency—100 to 200 MBaud 8-bit Operation

10

20

MHz

(SPDSEL is HIGH and BYTE8/10 is HIGH)

RXCLK Clock Output Frequency—50 to 100 MBaud 8-bit Operation

(SPDSEL is LOW and BYTE8/10 is HIGH)

5

10

MHz

RXCLK Clock Output Frequency—100 to 200 MBaud 10-bit Operation

(SPDSEL is HIGH and BYTE8/10 is LOW)

8.33

4.16

16.67

8.33

RXCLK Clock Output Frequency—50 to 100 MBaud 10-bit Operation

(SPDSEL is LOW and BYTE8/10 is LOW)

t_RXCLKOP

t_RXCLKOD

RXCLK Output Period

25

40

240

60

2

ns

%

RXCLK Output Duty Cycle

RXCLK Output Rise Time^[18]

RXCLK Output Fall Time^[18]

Receive Enable Set-up Time to RXCLK↑

[16]

t_RXCLKOR

0.25

4

ns

[16]

t_RXCLKOF

2

t_RXENS

Note:

19. Parallel data output specifications are only valid if all outputs are loaded with similar DC and AC loads.

20. The period of t_ROSwill match the period of the transmitter PLL reference (REFCLK) when receiving serial data. When data is interrupted, RXCLK may drift to REFCLK +0.2%.

Document #: 38-02020 Rev. *C

Page 23 of 46

CY7C9689A

CY7C9689A Receiver TTL Switching Characteristics, FIFO Bypassed Over the Operating Range (continued)

Parameter

t_RXENH

Description

Min.

Max.

Unit

ns

Receive Enable Hold Time from RXCLK↑

1

0

t_RXZA

t_RXOE

t_RXAZ

Sample of CE LOW by RXCLK↑, Outputs High-Z to Active

Sample of RXEN Asserted by RXCLK↑ to RXDATA Outputs High-Z to Active

ns

Sample of CE LOW by RXCLK↑ to Flag Output Valid

Sample of RXEN Asserted by RXCLK↑ to RXDATA Output Low-Z

1.5

20

ns

Sample of CE HIGH by RXCLK↑ to Flag Output High-Z

Sample of RXEN Deasserted by RXCLK↑ to RXDATA Output High-Z

CY7C9689A REFCLK Input Switching Characteristics Over the Operating Range

Conditions

Parameter

Description

SPDSEL RANGESEL BYTE8/10 Min.

Max. Unit

f_REF

REFCLK Clock Frequency—50 to 100 MBaud,

10-bit Mode, REFCLK = 2x Character Rate

0

1

0

1

0

1

0

1

0

1

8.33

16.67 MHz

REFCLK Clock Frequency—50 to 100 MBaud,

8-bit Mode, REFCLK = 2x Character Rate

0

10

20

33.3

40

MHz

REFCLK Clock Frequency—50 to 100 MBaud,

10-bit Mode, REFCLK = 4x Character Rate

1^[21]

0

16.67

20

REFCLK Clock Frequency—50 to 100 MBaud,

8-bit Mode, REFCLK = 4x Character Rate

REFCLK Clock Frequency—100 to 200 MBaud,

10-bit Mode, REFCLK = Character Rate

8.33

10

16.67 MHz

REFCLK Clock Frequency—100 to 200 MBaud,

8-bit Mode, REFCLK = Character Rate

0

20

33.3

40

MHz

REFCLK Clock Frequency—100 to 200 MBaud,

10-bit Mode, REFCLK = 2x Character Rate

1

16.67

20

REFCLK Clock Frequency—100 to 200 MBaud,

1

8-bit Mode, REFCLK = 2x Character Rate

t_REFCLK

t_REFH

REFCLK Period

25

6.5

120

ns

%

REFCLK HIGH Time

REFCLK LOW Time

REFCLK Frequency Referenced to Received Clock Period^[22]

t_REFL

6.5

t_REFRX

−0.04

+0.04

CY7C9689A Receiver Switching Characteristics Over the Operating Range

Parameter

[23]

Description

Min.

Max.

Unit

ns

t_B

Bit Time

20.0

5.0

t_SA

Static Alignment^{[16, 24]}

Error Free Window^{[16, 25, 26]}

600

ps

t_EFW

0.65

UI

t_{IN_J}

IN± Peak-to-Peak Input Jitter Tolerance^{[16, 25, 27, 28]}

0.5

UI

Notes:

21. When configured for synchronous operation with the FIFOs bypassed (FIFOBYP is LOW), if RANGESEL is HIGH the SPDSEL input is ignored and operation

is forced to the 100–200 MBaud range.

22. REFCLK has no phase or frequency relationship with RXCLK and only acts as a centering reference to reduce clock synchronization time. REFCLK must be

within ±0.04% of the transmitter PLL reference (REFCLK) frequency, necessitating a ±200-PPM crystal.

23. The PECL switching threshold is the midpoint between the PECL− V_OH, and V_OLspecification (approximately V_DD− 1.33V).

24. Static alignment is a measure of the alignment of the Receiver sampling point to the center of a bit. Static alignment is measured by the absolute difference

of the left and right edge shifts (|t_{SH_L}– t_{SH_R}|) of one bit until a character error occurs.

25. Receiver UI (Unit Interval) is calculated as 1/(f_REF*N) when operated in 8-bit mode (N = 10) and 10-bit mode (N = 12) if no data is being received, or 1/(f_REF*N)

of the remote transmitter if data is being received. In an operating link this is equivalent to N * t_Bwhen REFCLK = 1X the character rate. An alternate multiply

ratios (2X or 4X, as selected by SPDSEL and RANGESEL), the numerator is multiplied by 2 or 4 respectively.

26. Error Free Window is a measure of the time window between bit centers where a transition may occur without causing a bit sampling error. EFW is measured

over the operating range, input jitter < 50% Dj.

27. The specification is sum of 25% Duty Cycle Distortion (DCD), 10% Data Dependant Jitter (DDJ), 15% Random Jitter (RJ).

28. Parallel data output specifications are only valid if all outputs are loaded with similar DC and AC loads.

Document #: 38-02020 Rev. *C

Page 24 of 46

CY7C9689A

CY7C9689A Transmitter Switching Characteristics Over the Operating Range

Parameter

Description

Min.

20.0

200

Max.

5.0

Unit

ns

[23]

t_B

Bit Time

t_RISE

t_FALL

t_DJ

PECL Output Rise Time 20−80% (PECL Test Load)^[16]

PECL Output Fall Time 80−20% (PECL Test Load)^[16]

Deterministic Jitter (peak-peak)^{[16, 29]}

1700

0.02

0.008

0.08

ps

UI

t_RJ

Random Jitter (σ)^{[16, 30]}

UI

t_JT

Transmitter Total Output Jitter (peak-peak)^[16]

UI

CY7C9689A HOTLink Transmitter Switching Waveforms

Write Cycle

Asynchronous (FIFO) Interface

EXTFIFO = HIGH

t_TXCLK

FIFOBYP = HIGH

t_TXCPWH

t_TXCPWL

TXCLK

t_TXDS

t_TXDH

TXHALT

TXSC/D

TXDATA[7:0]

Note 31

TXDATA[9:8]/TXCMD[2:3]

TXCMD[1:0]

t_TXENH

NO OPERATION

TXEN

t_TXENS

t

TXA

t

TXA

TXFULL

TXHALF

TXEMPTY

Write Cycle

Asynchronous (FIFO) Interface

EXTFIFO = LOW

FIFOBYP = HIGH

TXCLK

t_TXDS

t_TXDH

TXHALT

TXSC/D

TXDATA[7:0]

Note 32

TXDATA[9:8]/TXCMD[2:3]

TXCMD[1:0]

t_TXENH

t_TXENS

TXEN

NO OPERATION

t

TXA

TXFULL

TXHALF

TXEMPTY

t_TXA

Notes:

29. While sending continuous JK, outputs loaded to 50Ω to V_DD− 1.3V, over the operating range.

30. While sending continuous HH, after 100,000 samples measured at the cross point of differential outputs, time referenced to REFCLK input, over the operating range.

31. When EXTFIFO is HIGH, the write data is captured on the clock cycle following TXEN = HIGH.

32. When EXTFIFO is LOW, the write data is captured on the same clock cycle as the TXEN = LOW.

Document #: 38-02020 Rev. *C

Page 25 of 46

CY7C9689A

CY7C9689A HOTLink Transmitter Switching Waveforms (continued)

OUTPUT ENABLE Timing

Asynchronous (FIFO) Interface

EXTFIFO = HIGH

FIFOBYP = HIGH

TXCLK

TXHALT

TXSC/D

TXDATA[7:0]

TXDATA[9:8]/TXCMD[2:3]

TXCMD[1:0]

NO OPERATION

TXEN

Note 33

t_TXRSS

t_TXRSH

TXRST

CE

t_TXCES

t_TXCEH

t_TXOAZ

t_TXOE

TXFULL

TXHALF

TXEMPTY

t_TXOZA

OUTPUT ENABLE Timing

Asynchronous (FIFO) Interface

EXTFIFO = LOW

FIFOBYP = HIGH

TXCLK

TXHALT

TXSC/D

TXDATA[7:0]

XDATA[9:8]/TXCMD[2:3]

TXCMD[1:0]

TXEN

NO OPERATION

t_TXRSH

t_TXRSS

Note 33

CE

TXRST

t_TXCES

t_TXCEH

CE

TXRST

t_TXOAZ

t_TXOE

TXFULL

TXHALF

TXEMPTY

t_TXOZA

Note:

33. Illustrates timing only. TXEN and TXRST not usually active in same time period.

Document #: 38-02020 Rev. *C

Page 26 of 46

CY7C9689A

CY7C9689A HOTLink Transmitter Switching Waveforms (continued)

Write Cycle

Synchronous Interface

t_REFCLK

EXTFIFO = HIGH

t_REFH

t_REFL

FIFOBYP = LOW

REFCLK

TXHALT

t_REFDS

t_REFDH

TXSC/D

TXDATA[7:0]

Note 34

XDATA[9:8]/TXCMD[2:3]

TXCMD[1:0]

t_REFENH

NO OPERATION

TXEN

t_REFENS

t_TRA

TXFULL

TXHALF

TXEMPTY

Write Cycle

Synchronous Interface

EXTFIFO = LOW

FIFOBYP = LOW

REFCLK

t_REFDS

t_REFDH

TXHALT

TXSC/D

Note 35

TXDATA[7:0]

DATA[9:8]/TXCMD[2:3]

TXCMD[1:0]

t_REFENH

t_REFENS

TXEN

NO OPERATION

TXFULL

TXHALF

TXEMPTY

Notes:

34. When transferring data to the Transmitter input from a depth expanded external FIFO, the data is captured from the external FIFO one clock cycle following the

actual enable (TXEN = HIGH).

35. When transferring data to the Transmitter input from a synchronous external controller, the data is captured in the same clock cycle as the actual enable (TXEN

= LOW).

Document #: 38-02020 Rev. *C

Page 27 of 46

CY7C9689A

CY7C9689A HOTLink Transmitter Switching Waveforms (continued)

OUTPUT ENABLE Timing

Synchronous Interface

EXTFIFO = HIGH

FIFOBYP = LOW

REFCLK

TXHALT

TXSC/D

TXDATA[7:0]

TXDATA[9:8]/TXCMD[2:3]

t_REFENH

TXCMD[1:0]

NO OPERATION

TXEN

t_REFENS

t_REFCEH

t_REFCES

CE

t_REFAZ

t_REFOE

TXFULL

TXEMPTY

t_REFZA

OUTPUT ENABLE Timing

Synchronous Interface

EXTFIFO = LOW

FIFOBYP = LOW

REFCLK

TXHALT

TXSC/D

TXDATA[7:0]

TXDATA[9:8]/TXCMD[2:3]

TXCMD[1:0]

NO OPERATION

TXEN

CE

TXFULL

TXEMPTY

Document #: 38-02020 Rev. *C

Page 28 of 46

CY7C9689A

CY7C9689A HOTLink Receiver Switching Waveforms

Read Cycle

Asynchronous (FIFO) Interface

EXTFIFO = HIGH

t_RXCLKOP

t_RXCLKIP

FIFOBYP = HIGH

t_RXCLKOD

t_RXCPWH

t_RXCLKOD

t_RXCPWL

RXCLK

t_RXENS

t_RXENH

RXEN

NO OPERATION

READ

t_RXA

Note 36

RXEMPTY

RXFULL

FIFO EMPTY

RXHALF

RXDATA[7:0]

VALID DATA

Note 37

RXDATA[9:8/RXCMD[2:3]

RXCMD[1:0]

CE

Read Cycle

Asynchronous (FIFO) Interface

EXTFIFO = LOW

FIFOBYP = HIGH

RXCLK

t_RXENS

t_RXENH

READ

RXEN

t_RXA

FIFO EMPTY

RXEMPTY

RXFULL

RXHALF

VALID DATA

Note 38

RXDATA[7:0]

RXDATA[9:8/RXCMD[2:3]

RXCMD[1:0]

CE

Notes:

36. When transferring data from the Receive FIFO to a depth expanded external FIFO, the data is sent to the external FIFO on the same clock cycle that RXEN =

HIGH. RXEMPTY = LOW indicates that data is available.

37. On inhibited reads, or if the Receive FIFO goes empty, the data outputs do not change.

38. When reading data from synchronous data interface, the data is captured on any clock cycle that RXEN = LOW. RXEMPTY = HIGH indicates data is available.

RXEMPTY = LOW indicates that the FIFO is empty.

Document #: 38-02020 Rev. *C

Page 29 of 46

CY7C9689A

CY7C9689A HOTLink Receiver Switching Waveforms (continued)

Output Enable Timing

RXCLK

t_RXENH

t_RXENS

RXEN

NO OPERATION

Note 39

t_RXRSS

t_RXRSH

RXRST

CE

t_RXCES

t_RXCEH

t_RXAZ

Note 40

t_RXOE

RXFULL

RXDATA[7:0]

OLD DATA

RXDATA[9:8/RXCMD[2:3]

RXCMD[1:0]

t_RXZA

t

REFCLK

t

REFL

t

REFH

REFCLK

Static Alignment

Error-Free Window

t /2− t

B

SA

t /2− t

B

SA

t

EFW

INA±

INB±

INA±

INB±

t

B

BIT CENTER

SAMPLE WINDOW

Table 7. HOTLink TAXI-compatible Encoder Patterns

4B/5B Encoder

5B/6B Encoder

5-bit Binary

HEX

Data

4-bit Binary

Data^[41]

5-bit Encoded

Symbol^{[42, 43]}

HEX

Data

6-bit Encoded

Symbol^{[42, 43]}

Data^[41]

00000

00001

00010

00011

00100

00101

0

1

2

3

4

5

0000

0001

0010

0011

0100

0101

11110

01001

10100

10101

01010

01011

00

01

02

03

04

05

110110

010001

100100

100101

010010

010011

Notes:

39. Illustrates timing only. RXEN and RXRST not usually active in same time period.

40. Receive FIFO Reads are inhibited while the outputs are High-Z.

41. Binary Input Data is the parallel input data which is input to the Transmitter and output from the Receiver. Binary bits are listed from left to right in the following

order: 8-Bit mode (BYTE8/10 is HIGH and TXSC/D or RXSC/D is LOW)—TXDATA/RXDATA[7], [6], [5], [4], and TXDATA/RXDATA[3], [2], [1], [0]; 10-Bit mode

(BYTE8/10 is LOW and TXSC/D or RXSC/D is LOW)—TXDATA/RXDATA[8], [7], [6], [5], [4], and TXDATA/RXDATA[9], [3], [2], [1], [0].

42. The ENCODED Symbols are shown here as “ones and zeros”, but are converted to and from an NRZI stream at the transmitter output and receiver input.

NRZI represents a “one” as a state transition (either LOW-to-HIGH or HIGH-to-LOW) and a “zero” as no transition within the bit interval.

43. Encoded Serial Symbol bits are shifted out with the most significant bit (Left-most) of the most significant nibble coming out first.

Document #: 38-02020 Rev. *C

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CY7C9689A

Table 7. HOTLink TAXI-compatible Encoder Patterns (continued)

4B/5B Encoder

5B/6B Encoder

5-bit Binary

HEX

Data

4-bit Binary

Data^[41]

5-bit Encoded

Symbol^{[42, 43]}

HEX

Data

6-bit Encoded

Symbol^{[42, 43]}

Data^[41]

00110

00111

01000

01001

01010

01011

01100

01101

01110

01111

10000

10001

10010

10011

10100

10101

10110

10111

10001

11001

11010

11011

11100

11101

11110

11111

6

7

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

01110

01111

10010

10011

10110

10111

11010

11011

11100

11101

06

07

08

09

0A

0B

0C

0D

0E

0F

10

11

010110

010111

100010

110001

110111

100111

110010

110011

110100

110101

111110

011001

101001

101101

011010

011011

011110

011111

101010

101011

101110

101111

111010

111011

111100

111101

8

9

A

B

C

D

E

F

12

13

14

15

16

17

18

19

1A

1B

1C

1D

1E

1F

Table 8. HOTLink TAXI Compatible Command Symbols

CY7C9689A (Transmitter)

CY7C9689A (Receiver)

Command Input

TXCMD[3:0]

Command Output

RXCMD[3:0]

Encoded

HEX

8-bit mode (BYTE8/10 is HIGH)

Binary CMD^[44]

Symbol^{[42, 43]}

Mnemonic

HEX

Binary CMD^[44]

0

1

2

3

4

5

6

7

0000

0001

0010

0011

0100

0101

0110

0111

11000 10001

11111 11111

01101 01101

01101 11001

11111 00100

01101 00111

11001 00111

11001 11001

JK (8-bit SYNC)

0

1

2

3

4

5

6

7

0000

0001

0010

0011

0100

0101

0110

0111

II

TT

TS

IH

TR

SR

SS

Note:

44. Binary CMD is the parallel input data which is input to the Transmitter and output from the Receiver. Binary bits are listed from left to right in the following order:

8-Bit mode (BYTE8/10 is HIGH and TXSC/D or RXSC/D is HIGH)—TXCMD/RXCMD[3], [2], [1], [0]; 10-Bit mode (BYTE8/10 is LOW and TXSC/D or RXSC/D

is HIGH)—TXCMD/RXCMD[1], [0].

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CY7C9689A

Table 8. HOTLink TAXI Compatible Command Symbols (continued)

CY7C9689A (Transmitter)

CY7C9689A (Receiver)

Command Input

TXCMD[3:0]

Command Output

RXCMD[3:0]

8^[45]

9^[45]

A^[45]

B

1000

1001

1010

1011

1100

1101

1110

1111

00100 00100

00100 11111

00100 00000

00111 00111

00111 11001

00000 00100

00000 11111

00000 00000

HH

HI

8

9

1000

1001

1010

1011

1100

1101

1110

1111

HQ

RR

RS

QH

QI

A

B

C

D

E

F

C

D^[45]

E^[45]

F^[45]

QQ

10-bit mode (BYTE8/10 is LOW)

0

1

2

3

00

01

10

11

011000 100011

111111 111111

011101 011101

011101 111001

LM (10-bit SYNC)

0

1

2

3

00

01

10

11

I’I’

T’T’

T’S’

• 8-bit characters

• 10-bit characters

• 10-bit pre-encoded characters (pre-scrambled or

pre-encoded)

• 12-bit pre-encoded characters (pre-scrambled or

pre-encoded).

Functional Description

The interconnection of two or more CY7C9689A Transceivers

forms a general-purpose communications subsystem capable

of transporting user data at up to 20 MBytes per second over

several types of serial interface media. The CY7C9689A is

highly configurable with multiple modes of operation.

The bit numbering and content of the parallel transmit interface

is shown in Table 1. When operated with the 4B/5B, 5B/6B

Encoder bypassed, the TXSC/D and RXSC/D bits are ignored.

In the transmit section of the CY7C9689A, data moves from

the input register, through the Transmit FIFO, to the 4B/5B

Encoder. The encoded data is then shifted serially out the

OUTx± differential PECL compatible drivers. The bit-rate clock

is generated internally from a 2.5x, 5x, or 10x PLL clock multi-

plier. A more complete description is found in the section

CY7C9689A HOTLink Transmit-Path Operating Mode

Description.

The HOTLink Transceiver serial interface provides a seamless

interface to various types of media. A minimal number of

external passive components are required to properly

terminate transmission lines and provide LVPECL loads. For

power supply decoupling, a single capacitor (in the range of

0.02 µF to 0.1 µF) is required per power/ground pair. Additional

information on interfacing these components to various media

can be found in the HOTLink Design Considerations appli-

cation note.

In the receive section of the CY7C9689A, serial data is

sampled by the receiver on one of the INx± differential line

receiver inputs. The receiver clock and data recovery PLL

locks onto the selected serial bit stream and generates an

internal bit-rate sample clock. The bit stream is deserialized,

decoded, and presented to the Receive FIFO, along with a

character clock. The data in the FIFO can then be read either

slower or faster than the incoming character rate. A more

complete description is found in the section CY7C9689A

HOTLink Receive-Path Operating Mode Description.

CY7C9689A TAXI HOTLink Transmit-Path

Operating Mode Descriptions

The TAXI HOTLink Transmitter can be configured into several

operating modes, each providing different capabilities and

fitting different transmission needs. These modes are selected

using the FIFOBYP, ENCBYP and BYTE8/10 inputs on the

CY7C9689A Transceiver. These modes can be reduced to five

primary classes:

The Transmitter and Receiver parallel interface timing and

functionality can be configured to Cascade directly to external

FIFOs for depth expansion, couple directly to registers, or

couple directly to state machines. These interfaces can accept

or output either:

• Synchronous Encoded

• Synchronous Pre-encoded

• Asynchronous Encoded

• Asynchronous Pre-encoded.

Note:

45. While these Commands are legal data and will not disrupt normal operation if used occasionally, they may cause data errors if grouped into recurrent fields.

Normal PLL operation cannot be guaranteed if one or more of these commands is continuously repeated.

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CY7C9689A

Synchronous Encoded

FIFO and Encoder are enabled, the input FIFO may be loaded

at any rate supported by the FIFO (up to 50 MHz), without

generating any decoder errors at the receive end of the link.

In this mode, the Transmit FIFO is bypassed, while the 4B/5B,

5B/6B encoder is enabled. One character is accepted at the

Transmit Input Register at the rising edge of REFCLK, and

passed to the Encoder where it is encoded for serial trans-

mission. The Serializer operates synchronous to REFCLK,

which is multiplied by 10 or 5 to generate the serial data

bit-clock. In this mode the TXRST and TXHALT inputs are not

interpreted and may be tied either HIGH or LOW. To place the

CY7C9689A into synchronous modes, FIFOBYP must be

LOW.

CY7C9689A TAXI HOTLink Receive-Path

Operating Mode Descriptions

The HOTLink Receiver can be configured into several

operating modes, each providing different capabilities and

fitting different reception needs. These modes are selected

using the FIFOBYP, ENCBYP, BYTE8/10 inputs on the

CY7C9689A Transceiver. These modes can be reduced to

four primary classes:

This mode is usually used for products that must meet specific

predefined protocol requirements, and cannot tolerate the

uncontrolled insertion of SYNC fill characters. The host

system is required to provide new data at every rising edge of

REFCLK (along with TXEN) to maintain the data stream. If

TXEN is not asserted, the Encoder is loaded with JK or LM

sync characters.

• Synchronous Decoded

• Synchronous Undecoded

• Asynchronous Decoded

• Asynchronous Undecoded.

In all these modes, serial data is received at one of the differ-

ential line receiver inputs and routed to the Deserializer and

Framer. The PLL in the clock and data recovery block is used

to extract a bit-rate clock from the transitions in the data

stream, and uses that clock to capture bits from the serial

stream. These bits are passed to the Deserializer where they

are formed into 10- or 12-bit characters.

Input Register Mapping

In Encoded modes, the bits of the TXDATA input bus are

mapped into characters (as shown in Table 1), including a

TXSVS bit, eight bits of data, and a TXSC/D bit to select either

Special Character codes or Data characters.

To align the incoming bit stream to the proper character bound-

aries, the Framer must be enabled by asserting RFEN HIGH.

The Framer logic-block checks the incoming bit stream for the

unique pattern that defines the character boundaries. This

logic filter looks for the JK or LM (when BYTE8/10 is LOW)

sync character. Once a sync character is found, the Framer

captures the offset of the data stream from the present

character boundaries, and resets the boundary to reflect this

new offset, thus framing the data to the correct character

boundaries.

The TXSC/D bit controls the encoding of the TXDATA[7:0] or

TXDATA[9:0] bits of each character. It is used to identify if the

input character represents a Data Character or a Special

Character code. If TXSC/D is LOW, the character appeared on

the TXDATA bus is encoded using the Data Character codes

listed in Table 7. If TXSC/D is HIGH, the character on the

TXCMD bus is encoded using the Special Character codes

listed in Table 8.

Synchronous Pre-encoded

In synchronous pre-encoded mode, both the Transmit FIFO

and the 4B/5B encoder are bypassed, and data passes directly

from the Transmit Input Register to the Serializer. The

Serializer operates synchronous to REFCLK, which is multi-

plied by 10 or 5 when BYTE8/10 is HIGH (as selected by the

SPDSEL and RANGESEL inputs) to generate the serial data

bit-clock. In this mode, part of the TXCMD bus inputs are used

as part of the data input bus. To place the CY7C9689A into

synchronous modes, FIFOBYP must be LOW.

Since noise induced errors can cause the incoming data to be

corrupted, and since many combinations of corrupt and legal

data can create an aliased sync character, the framer may also

be disabled by deasserting RFEN LOW.

Synchronous Decoded

In these modes, the Receive FIFO is bypassed, while the

5B/4B, 6B/5B Decoder is enabled. Framed characters output

from the Deserializer are decoded, and passed directly to the

Receive Output Register. The Deserializer operates

synchronous to the recovered bit-clock, which is divided by 10,

generate the output RXCLK clock. In this mode the RXRST

input is not interpreted and may be biased either HIGH or

LOW.

This mode is usually used for products containing external

encoders or scramblers, that must meet specific protocol

requirements. The host system is required to provide new data

at every rising edge of the REFCLK (along with TXEN) to

maintain the data stream. If TXEN is not asserted, the

Serializer is loaded with JK or LM sync characters.

These modes are usually used for products that must meet

specific protocol requirements. New decoded characters are

provided at the RXDATA outputs once every rising edge of

RXCLK. If RXEMPTY is asserted LOW, the characters on the

RXCMD output register is a JK or LM sync character, and the

discard policy is set to non-0. Because the decoder is now

enabled, all received characters are checked for compliance

to the 4B/5B decoding rules.

In this mode the LSB of each input character (TXDATA[0]) is

shifted out first, followed sequentially by TXDATA[1] through

TXDATA[9] (TXDATA[11] when BYTE8/10 is LOW).

Asynchronous Encoded

In Asynchronous Encoded mode, both the Transmit FIFO and

the Encoder are enabled. This provides 256 characters of data

buffering. The Serializer operates synchronous to REFCLK,

which is multiplied by 2.5, 5, or 10 to generate the serial data

bit-clock (as selected by SPDSEL and RANGESEL). In this

mode the TXRST and TXHALT inputs are interpreted.

Output Register Mapping

The RXDATA[11:0] output bus is mapped into a character

consisting of eight bits of data and four bits of command, or ten

bits of data and two bits of command. An accompanying

RXSC/D bit identifies the character as either command or

data.

This mode supports the same Input Register mapping as

Synchronous Encoded mode. Because both the Transmit

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CY7C9689A

The Violation (VLTN) output indicates a code violation has

occured. When the VLTN output is asserted HIGH, this

indicates a transmission error is detected in the character at

the current transfer clock cycle.

serial interface are written to the Receive FIFO before being

passed to the output register. The Deserializer operates

synchronous to the recovered bit-clock, which is divided by 10

(or 12) to generate the Receive FIFO write clock. Data is read

from the Receive FIFO, using the RXCLK input clock, when

addressed by CE and selected by RXEN.

Synchronous Undecoded

In this mode, both the Receive FIFO and the 5B/4B, 6B/5B

Decoder are bypassed, and data passes directly from the

Deserializer to the output register. The Deserializer operates

synchronous to the recovered bit-clock, which is divided by 10

to generate the output RXCLK clock. In this mode the RXRST

input is not interpreted and may be biased either HIGH or

LOW.

These modes are usually used for products containing

external decoders or descramblers, that must meet specific

protocol requirements. New data may be read from the

Receive FIFO any time that the FIFO status flags indicate a

non-empty condition (RXEMPTY is deasserted). To ensure

that data is not lost, the Receive FIFO must be read faster than

data is loaded into the Receive FIFO.

This mode is usually used for products containing external

decoders or descramblers that must meet specific protocol

requirements. New data is provided at the RXDATA outputs

once every rising edge of RXCLK. Received characters are

not checked for any specific coding requirements and no

decoding errors are reported.

If the receiver is to provide framed characters, it is necessary

for the transmit end to include JK or LM sync characters in the

data stream. This can be done by:

• operating the transmitter in encoded mode and writing JK

or LM characters into the data stream

• operating the transmitter in pre-encoded mode and writing

the 10-bit value for an encoded JK (1100010001) or LM

(011000100011) character to the data stream

Asynchronous Decoded

In Asynchronous Decoded mode, both the Receive FIFO and

the Decoder of the CY7C9689A are enabled. The deserializer

operates synchronous to the recovered bit-clock, which is

divided by 10 to generate the Receive FIFO write clock.

Characters are read from the Receive FIFO, using the external

RXCLK input, when addressed by CE and selected by RXEN.

In this mode the RXRST input is interpreted.

• not enabling the transmitter when it is operated in

synchronous mode, or by allowing the transit FIFO to go

empty when it is operated in asynchronous mode.

BIST Operation and Reporting

The CY7C9689ADX HOTLink Transceiver incorporates the

same Built-In Self-Test (BIST) capability. This link diagnostic

uses a Linear Feedback Shift Register (LFSR) to generate a

511-character repeating sequence that is compared,

character-for-character, at the receiver.

Asynchronous Decoded mode supports the same Output

Register mapping as the Synchronous Decoded mode.

Because both the Receive FIFO and Decoder are enabled, the

output FIFO may be read at any rate supported by the FIFO,

however, if the Receive FIFO ever indicates a full condition

(RXFULL is asserted), data may be lost.

BIST mode is intended to check the entire high-speed serial

link at full link-speed, without the use of specialized and

expensive test equipment. The complete sequence of

characters used in BIST are documented in Table 4.

Asynchronous Undecoded

In Asynchronous Undecoded modes, the Receive FIFO is

enabled. This means that all characters received from the

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CY7C9689A

TXCLK

Enable TX BIST

Start of TX BIST

TXBISTEN

TXEMPTY

TXHALF

BIST

LOOP

OUTA±

OUTB±

TXFULL

TXCMD[1:0]

TXSC/D

Don’t Care

TXDATA[9:0]

TXEN

REFCLK

LOW to enable FIFO Flags CE

LOW to enable VLTN reads

RXEN

RXDATA[9:0]

Ignore these outputs

ERROR

RXSC/D

RXCMD[1:0]

VLTN

INA±

INB±

RXEMPTY

RXHALF

RXFULL

Forced to indicate EMPTY by BIST

Start of RX

BIST match

Start of RX

BIST Wait

BIST

LOOP

Enable RX BIST

RXBISTEN

RXCLK

A/B

HIGH to select A

Figure 5. Built-In Self-Test Illustration

BIST Enable Inputs

as documented, with the exception of the information

presented on the TXEMPTY FIFO status flag. Since this flag

is used to present BIST loop status, it continues to reflect the

state of the transmit BIST loop status until TXBISTEN is no

longer recognized internally. The completion of the reset

operation may still be monitored through the TXFULL FIFO

status flag.

There are separate BIST enable inputs for the transmit and

receive paths of the CY7C9689A. These inputs are both active

LOW; i.e., BIST is enabled in its respective section of the

device when the BIST enable input is determined to be at a

logic-0 level. Both BIST enable inputs are asynchronous; i.e.,

they are synchronized inside the CY7C9689A to the internal

state machines.

The TXEMPTY flag, when used for transmit BIST progress

indication, continues to reflect the active HIGH or active LOW

settings determined by the UTOPIA or Cascade timing model

selected by EXTFIFO; i.e., when configured for the Cascade

timing model, the TXEMPTY and TXFULL FIFO flags are

active HIGH, when configured for the UTOPIA timing model

the TXEMPTY and TXFULL FIFO flags are active LOW. The

illustration in Figure 5 uses the UTOPIA conventions.

BIST Transmit Path

The transmit path operation with BIST is controlled by the

TXBISTEN input and overrides most other inputs (see

Figure 5). When the Transmit FIFO is enabled (not bypassed)

and TXBISTEN is recognized internally, all reads from the

Transmit FIFO are suspended and the BIST generator is

enabled to sequence out the 511 character repeating BIST

sequence. If the recognition occurs in the middle of a data

field, the following data is not transmitted at that time, but

remains in the Transmit FIFO. Once the TXBISTEN signal is

removed, the data in the Transmit FIFO is again available for

transmission. To ensure proper data handling at the desti-

nation, the transmit host controller should either use TXHALT

to prevent transmission of data at specific boundaries, or allow

the Transmit FIFO to completely empty before enabling BIST.

When TXBISTEN is first recognized, the TXEMPTY flag is

clocked to a reset state, regardless of the addressed state of

the Transmit FIFO (if CE is LOW or not), but is not driven out

of the part unless CE has been sampled asserted (LOW).

Following this, on each completed pass through the BIST loop,

the TXEMPTY flag is set for one interface clock period (TXCLK

or REFCLK).

The TXEMPTY flag remains set until the interface is

addressed and the state of TXEMPTY has been observed. If

the device is not addressed (CE is not sampled LOW), the flag

remains set internally regardless of the number of TXCLK

clock cycles that are processed. If the device status is not

polled on a sufficiently regular basis, it is possible for the host

system to miss one or more of these BIST loop indications.

With transmit BIST enabled, the Transmit FIFO remains

available for loading of data. It may be written up to its normal

maximum limit while the BIST operation takes place. To allow

removal of stale data from the Transmit FIFO, it may also be

reset during a BIST operation. The reset operation proceeds

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CY7C9689A

A pass through the loop is defined as that condition where the

Encoder generates the 0x00 (where 0x denotes Hex number,

e.g. 0x00 denotes HEX00) state. Depending on the initial state

of the BIST LFSR, the first pass through the loop may occur at

substantially less than 511 character periods. Following the

first pass, as long as TXBISTEN remains LOW, all remaining

passes are exactly 511 characters in length.

same as the RXFULL flag, with respect to preserving the

detection state of an error until it is read.

Unlike the RXFULL flag, which only needs the CY7C9689A to

be addressed (CE sampled LOW by RXCLK) to enable the

RXFULL three-state driver, and an RXCLK to “read” the flag,

the VLTN output requires a selection (assertion of RXEN while

addressed) to enable the RXDATA bus three-state drivers.

The selection process is necessary to ensure that a multi-PHY

implementation does not enable multiple VLTN drivers at the

same time.

When the Transmit FIFO is bypassed, the interface is clocked

by the REFCLK signal instead of TXCLK. While the active or

asserted state of the TXEMPTY signal is still controlled by the

EXTFIFO, the state of any completed BIST loops is no longer

preserved. Instead, the TXEMPTY flag reflects the dynamic

state of the BIST loop progress, and is asserted only once

every 511 character periods. If the interface is not addressed

at the time that this occurs, then the FIFO status flags remain

in a high-Z state and the loop event is lost.

When the Receive FIFO is bypassed, the interface is clocked

by the RXCLK output signal. While the active or asserted state

of the RXFULL signal is still controlled by the EXTFIFO input,

the state of any completed BIST loops or detected errors are

no longer preserved. Instead, the RXFULL flag reflects the

dynamic state of the BIST loop progress, and is asserted only

once every 511 character periods. If the interface is not

addressed at the time that this occurs, then the FIFO status

flags remain in a high-Z state and the loop event is lost. This

is also true of the VLTN output, such that if the CY7C9689A

receive path is not selected to enable the RXDATA bus

three-state drivers, the detection of a BIST miscompare is lost.

BIST Receive Path

The receive path operation in BIST is similar to that of the

transmit path. While the Receive FIFO is enabled (not

bypassed) and RXBISTEN is recognized internally, all writes

to the Receive FIFO are suspended.

Any data present in the Receive FIFO when RXBISTEN is

recognized remains in the FIFO and cannot be read until the

BIST operation is complete. The data in the Receive FIFO

remains valid, but is NOT available for reading through the

host parallel interface. This is because the error output

indicator for receive BIST operations is the VLTN signal, which

is normally part of the RXDATA bus. To prevent read opera-

tions while BIST is in operation, the RXEMPTY and RXHALF

flags are forced to indicate an Empty condition. Once

RXBISTEN has been removed and recognized internally, the

Receive FIFO status flags are updated to reflect the current

content status of the Receive FIFO.

BIST Three-state Control

When BIST is enabled on either the transmitter or the receiver,

the three-state enable signals for the BIST status flags and

error indicators work the same as for normal data processing.

The output drivers for the BIST status that is presented on

FIFO status flags are only enabled when CE has been

sampled asserted (LOW) by the respective clock (TXCLK,

RXCLK, or REFCLK).

To access the BIST error information, it is necessary to

perform a read cycle of the addressed receiver. This means

that CE must be LOW to enable the receiver (Rx_Match), and

RXEN must be asserted from HIGH to LOW to select the

device. Because the part is in BIST, no data is read from the

FIFO, but the data bus is driven. This allows the VLTN indicator

to be driven onto the RXDATA bus. So long as RXEN remains

asserted, the receiver stays selected, the data bus remains

driven, and VLTN has meaning.

To allow removal of stale data from the Receive FIFO, it may

be reset during a BIST operation. The reset operation

proceeds as documented, with the exception that the

RXEMPTY and RXHALF status flags already indicate an

empty condition. The RXFULL flag is used to present BIST

progress. The active (asserted) state on RXFULL (and

RXEMPTY) remain controlled by the present operating mode

and interface timing model (UTOPIA or Cascade).

Bus Interfacing

When RXBISTEN has been recognized, RXFULL becomes

the receive BIST loop indicator (regardless of the logic state of

FIFOBYP). When RXBISTEN is first recognized, the RXFULL

flag is clocked to a set state, regardless of the addressed state

of the Receive FIFO (if CE is sampled LOW or not). Following

this, RXFULL remains set until the receiver detects the start of

the BIST pattern. Then RXFULL is deasserted for the duration

of the BIST pattern, pulsing asserted for one RXCLK period on

the last symbol of each BIST loop. If 14 of 28 consecutive

characters are received in error, RXFULL returns to the set

state until the start of a BIST sequence is again detected.

The parallel transmit and receive host interfaces to the

CY7C9689A are configurable for either synchronous or

asynchronous operation. Each of these configurations

supports two selectable timing and control models of Shared

Bus or Cascade.

All asynchronous bus configurations have the internal

Transmit and Receive FIFOs enabled. This allows data to be

written or read from these FIFOs at any rate up to the

maximum 50-MHz clock rate of the FIFOs. All internal opera-

tions of the CY7C9689A do not use the external TXCLK or

RXCLK, but instead make use of synthesized derivatives of

REFCLK for transmit path operations and a recovered

character clock for receive path operations.

Just like the BIST status flag on the transmit data path, the

RXFULL flag captures the asserted states, and keeps them

until they are read. This means that if the status flag is not read

on a regular basis, events may be lost.

All synchronous bus configurations require the bus interface

operations to be synchronous to REFCLK on the transmit path

and the recovered clock (output as RXCLK) on the receive

path. The internal FIFOs are bypassed in all synchronous

modes.

The detection of errors is presented on the VLTN output.

Unlike the RXFULL FIFO status flag, the active state of this

output is not controlled by the EXTFIFO input. With the

Receive FIFO enabled, these outputs should operate the

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CY7C9689A

The two supported timing and control models are Shared Bus

and Cascade. The Shared Bus is based on the timing model

of a FIFO with active LOW FIFO status flags and read/write

enables.

accesses to Slaves which have room in the TXFIFOs. While

data is being transferred on the data/command bus, the bus

Master can continue to poll each Slave device independently.

Device Selection

The Cascade timing model is a modification of the Shared Bus

model that changes the flags and FIFO read/write enables to

active HIGH. This model is present primarily to allow depth

expansion of the internal FIFO by direct coupling to external

CY7C42x5 synchronous FIFOs. To allow this direct coupling,

the cycle-to-cycle timing between the transmit and receive

enables (TXEN and RXEN) are also modified to ensure correct

data transfer.

All actions on the Shared Bus interface are controlled by the

Chip Enable and selection states of the interface. These states

control the read and write access to the Receive and Transmit

FIFOs, access to the FIFO status flags, reset of the Transmit

and Receive FIFOs, and read and write access to the Serial

Address Register. The CY7C9689A supports the concept of

an “address match” through a single Chip Enable (CE) input.

These four configurations of bus operation and timing/control

can all be used with or without external FIFOs. Depending on

the specific mode selected, the amount of external hardware

necessary to properly couple the CY7C9689A to state

machines or external FIFOs is minimal in all cases, and may

be zero if the proper configuration is selected.

Address Match and FIFO Flag Access

The CY7C9689A makes use of a single active-LOW Chip

Enable (CE) to generate address-match conditions. This

allows multiple CY7C9689A devices to share a common bus,

with device output three-state controls being managed by

either an address match condition (CE sampled LOW), or by

a selection state.

With only minor exceptions, all configurations of the

CY7C9689A in the Shared Bus mode borrowed concepts from

the ATM Forum’s UTOPIA Bus operation. concepts of

addressing and selection to control the enabled/disabled state

of the output drivers, and when data can be written to or read

from the part.

The Transmit and Receive FIFO flag output drivers are

enabled in any TXCLK, REFCLK, or RXCLK cycle following

CE being sampled asserted (LOW) by the rising edge of the

respective clock. The CE input is sampled separately by the

clocks for the transmit and receive interfaces, which allows

these clocks to be both asynchronous to each other, and to

operate at different clock rates. An example of both Transmit

and Receive FIFO flag access is shown in Figure 7.

Shared Bus Interface Concept

The CY7C9689A Parallel Interface is designed for interfacing

to a Shared Bus. The maximum TXCLK and RXCLK frequency

is 50 MHz, which provides a total bandwidth of 50Million

characters per second in each direction. More than two

CY7C9689A can be serviced on the same bus at full serial line

speed.

TXCLK

CE

The CY7C9689A is designed to be the Slave in Master-Slave

type of shared bus architecture. Generally, the bus Master (a

Medium Access Device, MAC) is a higher layer device that

sources out going data/command and sinks incoming

data/command to/from Slaves (CY7C9689A) on the shared

bus (see Figure 6).

TXFULL

Valid

Transmit Port Addressing

Bus

Master

RXCLK

CE

CEn

CE1

CE2

TXDATA/TXCMD

RXDATA/RXCMD

Valid

Status, Control

RXEMPTY

Receive Port Addressing

Figure 7. FIFO Flag Driver Enables

............

CY7C9689A

Figure 6. Shared Bus Architecture

When the Transmit FIFO is enabled (FIFOBYP is HIGH) and

CE is sampled LOW by the rising edge of TXCLK, the output

drivers for the TXFULL and TXEMPTY FIFO flags are

enabled. When CE is sampled HIGH by the rising edge of

TXCLK, these same output drivers are disabled.

The data bus (TXDATA, RXDATA), command bus (TXCMD,

RXCMD) and FIFO status flags (TXFULL, RXEMPTY, etc.) of

each CY7C9689A on the shared bus can be connected

together respectively. Each Slave can be assigned an

address. The address of each Slave can be decoded by a

decoder which drives the CE input of each Slave. The bus

Master will poll each Slave by selecting (or “Addressing”) the

device, and sample the FIFO flags. Depending on the FIFOs

status on each Slave device, the Master can schedule read

accesses to Slaves which have data in the RXFIFOs, and write

When the Transmit FIFO is bypassed (FIFOBYP is LOW and

not in byte-packed mode) and CE is sampled LOW by the

rising edge of REFCLK, the output drivers for the TXFULL and

TXEMPTY FIFO flags are enabled. When CE is sampled

HIGH by the rising edge of REFCLK, the FIFO flag output

drivers are disabled.

Document #: 38-02020 Rev. *C

Page 37 of 46

CY7C9689A

When CE is sampled LOW by the rising edge of RXCLK (input

or output), the output drivers for the RXFULL and RXEMPTY

FIFO flags are enabled. When CE is sampled HIGH by the

rising edge of RXCLK, the FIFO flag output drivers are

disabled.

Transmit Data Selection

Asynchronous With Shared Bus Timing and Control

(Transmit FIFO Enabled)

When CE is sampled LOW and TXRST is sampled HIGH by

the rising edge of TXCLK, a Tx_Match condition is generated.

This Tx_Match condition continues until CE is sampled HIGH

or TXRST is sampled LOW at the rising edge of TXCLK. When

a Tx_Match (or Tx_RstMatch) condition is present, the

TXEMPTY and TXFULL output drivers are enabled. When a

Tx_Match (or Tx_RstMatch) condition is not present, these

same drivers are disabled (High-Z).

Device Selection

The concept of selection is used to control the access to the

transmit and receive parallel-data ports of the device. There

are three primary types of selection:

• Transmit data selection (with and without internal Transmit

FIFO)

• Receive data selection (with and without internal Receive

The selection state of the Transmit FIFO is entered when a

Tx_Match condition is present, and TXEN transitions from

HIGH to LOW. Once selected, the Transmit FIFO remains

selected until TXEN is sampled HIGH by the rising edge of

TXCLK. In the selected state, data present on the TXDATA

inputs is captured and stored in the Transmit FIFO. This

transmit interface selection process is shown in Figure 8.

FIFO)

• Continuousselection(foreitherorbothtransmitandreceive

interfaces).

In addition to these normal selection types, there are two

additional sequences that are used to control the internal

Transmit and Receive FIFOs reset operations, and to control

read/write access to the Serial Address Register:

Synchronous With Shared Bus Timing and Control

(Transmit FIFO Bypassed)

• Transmit reset sequence

• Receive reset sequence.

When the Transmit FIFO is bypassed (FIFOBYP is LOW and

not in byte-packed mode), the CY7C9689A must still be

selected to write data into the Transmit Input Register.

Of these operations, the transmit data selection and transmit

reset sequence are mutually exclusive and cannot exist at the

same time. The receive data selection and receive reset

sequence are also mutually exclusive and cannot exist at the

same time. Either transmit operation can exist at the same

time as either receive operation.

When CE is sampled LOW and TXRST is sampled HIGH by

the rising edge of REFCLK, a Tx_Match condition is

generated. This Tx_Match condition continues until CE is

sampled HIGH or TXRST is sampled LOW at the rising edge

of REFCLK. When a Tx_Match (or Tx_RstMatch) condition is

present, the TXEMPTY and TXFULL output drivers are

enabled (with the Transmit FIFO bypassed, the status flags

normally indicate an Empty condition). When a Tx_Match (or

Tx_RstMatch) condition is not present, these same drivers are

disabled (High-Z).

All normal forms of selection require that an Chip Enable must

be asserted (CE sampled LOW) either at the same time as the

selection control signal being sampled asserted, or one or

more clock cycles prior to the selection control signal being

sampled asserted.

TXCLK

TXRST

CE

[46]

Tx_Match

Note 47

TXEN

[46]

Tx_Selected

TXDATA/TXCMD

D1

D2

D1

D3

D2

(Shared Bus Timing)

TXDATA/TXCMD

D3

(Cascade Timing)

TXFULL

Not Full

Note 47

Not Full

Figure 8. Transmit Selection with Transmit FIFO Enabled

Document #: 38-02020 Rev. *C

Page 38 of 46

CY7C9689A

The selection state of the Transmit Input Register is entered

when a Tx_Match condition is present, and TXEN transitions

from HIGH to LOW. Once selected, the transmit input register

remains selected until TXEN is sampled HIGH by the rising

edge of REFCLK. In the selected state, data present on the

TXDATA inputs is captured in the Transmit Input Register and

passed to the Serializer or Encoder (as selected by the

ENCBYP input). This transmit interface selection process is

shown in Figure 9.

Receive Data Selection

Asynchronous With Shared Bus Timing and Control

(Receive FIFO Enabled)

When CE is sampled LOW and RXRST is sampled HIGH by

the rising edge of RXCLK input, an Rx_Match condition is

generated. This Rx_Match condition continues until CE is

sampled HIGH or RXRST is sampled LOW at the rising edge

of RXCLK input. When an Rx_Match (or Rx_RstMatch)

condition is present, the RXEMPTY and RXFULL output

drivers are enabled.

When the 4B/5B Encoder is enabled and data is not written to

the Transmit Input Register, the data stream is automatically

padded with JK or LM SYNC characters. When the 4B/5B,

5B/6B Encoder is disabled and no data is written to the

Transmit Input Register, JK or LM SYNC characters are also

automatically padded with SYNC characters.

When an Rx_Match (or Rx_RstMatch) condition is not

present, these same drivers are disabled (High-Z).

The selection state of the Receive FIFO is entered when an

Rx_Match condition is present, and RXEN transitions from

HIGH to LOW. Once selected, the Receive FIFO remains

selected until RXEN is sampled HIGH by the rising edge of

RXCLK input. The selected state initiates a read cycle from the

Receive FIFO and enables the Receive FIFO data onto the

RXDATA bus. This receive interface selection process is

shown in Figure 10.

REFCLK

TXRST

CE

[46]

Tx_Match

Note 47

TXEN

[46]

Tx_Selected

TXDATA/TXCMD

D1

D2

D1

D3

D2

(Shared Bus Timing)

TXDATA/TXCMD

D3

(Cascade Timing)

TXFULL

Not Full

Note 47

Not Full

Figure 9. Transmit Selection with Transmit FIFO Bypassed

Notes:

46. Signals labeled in italics are internal to the CY7C9689A.

47. Signals shown as dotted lines represent the differences in timing and active state of signals when operated in Cascade Timing.

Document #: 38-02020 Rev. *C

Page 39 of 46

CY7C9689A

Synchronous With UTOPIA Timing and Control

(Receive FIFO Bypassed)

the Receive FIFO bypassed, these flags normally indicate a

non-empty condition but may indicate empty if a JK or LM

SYNC character is present in the output register and the

receiver discard policy is non-0. When an Rx_Match (or

Rx_RstMatch) condition is not present, these same drivers are

disabled (High-Z).

When the Receive FIFO is bypassed (FIFOBYP is LOW), the

CY7C9689A must still be selected to enable the output drivers

for the RXDATA bus. With the Receive FIFO bypassed,

RXCLK becomes a synchronous output clock operating at the

character rate.

The selection state of the Receive Output Register is entered

when an Rx_Match condition is present, and RXEN transitions

from HIGH to LOW. Once selected, the Receive Output

Register remains selected until RXEN is sampled HIGH by the

rising edge of RXCLK output. In the selected state, the output

drivers for the RXDATA outputs are enabled, and new data is

presented to the RXDATA bus on every clock cycle.

When CE is sampled LOW and RXRST is sampled HIGH by

the rising edge of RXCLK output, an Rx_Match condition is

generated. This Rx_Match condition continues until CE is

sampled HIGH or RXRST is sampled LOW at the rising edge

of RXCLK.

When an Rx_Match (or Rx_RstMatch) condition is present,

the RXEMPTY and RXFULL output drivers are enabled. With

RXCLK

RXRST

CE

[46]

Rx_Match

Note 47

RXEN

Rx_Selected

[46]

RXDATA/RXCMD

RXEMPTY

D1

D2

D3

Not Empty

Note 47

Not Empty

Figure 10. Receive Selection with Receive FIFO Enabled

enabled (just as in a normal Tx_Match condition). When a

Continuous Selection

Tx_RstMatch (or Tx_Match) condition is not present, these

same drivers are disabled (High-Z). The Transmit FIFO reset

Address Match is shown in Figure 11. Note that although

TXRST remains LOW for more than one clock cycle, the

Tx_RstMatch does not because the CE signal is no longer

asserted (LOW).

Continuous Selection is a specialized form of selection which

does not require sequenced assertion of CE and TXEN or

RXEN to select the device for data transfers. In this

Continuous Selection mode, the CE and associated TXEN or

RXEN enable signal must be asserted when the device is

powered up or during assertion of RESET. So long as these

signals remain asserted, the device remains selected and data

is accepted and presented on every clock cycle. Note: The

use of continuous selection makes it impossible to reset the

respective internal FIFOs, or to access the Serial Address

Register.

When CE and RXRST are both LOW, and this condition is

sampled by the rising edge of RXCLK, an Rx_RstMatch

condition is generated. This Rx_RstMatch condition continues

until CE or RXRST is sampled HIGH, at the rising edge of

RXCLK. When an Rx_RstMatch (or Rx_Match) condition is

present, the RXEMPTY and RXFULL output drivers are

enabled. When an Rx_RstMatch (or Rx_Match) condition is

not present, these same drivers are disabled (High-Z). The

Receive FIFO reset Address Match is shown in Figure 12.

Note that while the FIFO flags remain asserted for more than

one clock cycle, this is due to an Rx_Match condition, not a

continuation of the Rx_RstMatch.

FIFO Reset Address Match

When CE and TXRST are both LOW, and this condition is

sampled by the rising edge of TXCLK, a Tx_RstMatch

condition is generated. This Tx_RstMatch condition continues

until CE or TXRST is sampled HIGH by the rising edge of

TXCLK. When a Tx_RstMatch (or Tx_Match) condition is

present, the TXEMPTY and TXFULL output drivers are

Document #: 38-02020 Rev. *C

Page 40 of 46

CY7C9689A

Transmit FIFO Reset Sequence

TXCLK

TXRST

The Transmit FIFO reset sequence (see Figure 15) is started

when TXRST and CE are first sampled LOW by the rising edge

of TXCLK. Because a Tx_RstMatch condition is present, the

Transmit FIFO flags are asserted and can be used to track the

status of any Transmit FIFO reset in progress. Once the reset

sequence has reached its maximum count (eight TXCLK

cycles), the Transmit FIFO flags are asserted to indicate a

FULL condition (TXEMPTY is deasserted, and both TXHALF

and TXFULL are asserted). This indicates that the Transmit

FIFO reset has been recognized by the Transmit Control State

Machine and that a reset has been started. However, if the

TXEN is asserted prior to or during the assertion and sampling

of TXRST, the reset sequence is inhibited until TXEN is

removed. Note: The FIFO FULL state forced by the reset

operation is different from a FULL state caused by normal

FIFO data writes. For normal FIFO write operations, when

FULL is first asserted, the Transmit FIFO must still accept up

to four additional writes of data. When a FULL state is asserted

due to a Transmit FIFO reset operation, the FIFO will not

accept any additional data.

CE

[46]

Tx_RstMatch

Tx_Match

TXFULL

Valid

Figure 11. Transmit FIFO Reset Address Match

RXCLK

The Transmit FIFO reset does not complete until the external

reset condition is removed. This can be removed by

deassertion of either TXRST or CE. If CE is deasserted (HIGH)

to remove the reset condition, the Transmit FIFO flag’s drivers

are disabled, and the Transmit FIFO must be addressed at a

later time to validate completion of the Transmit FIFO reset. If

TXRST is deasserted (HIGH) to remove the reset condition,

the Tx_RstMatch is changed to a Tx_Match, and the Transmit

FIFO status flags remain driven. The Transmit FIFO reset

operation is complete when the Transmit FIFO flags indicate

an EMPTY state (TXEMPTY is asserted and both TXHALF

and TXFULL are deasserted). A valid Transmit FIFO reset

sequence is shown in Figure 15.

RXRST

CE

[46]

Rx_RstMatch

[46]

Rx_Match

RXEMPTY

Valid Valid

Figure 12. Receive FIFO Reset Address Match

Here the TXRST and CE are asserted (LOW) at the same

time. When these signals are both sampled LOW by TXCLK,

a Tx_RstMatch condition is present. With TXEN deasserted

(HIGH), the Transmit FIFO is not selected for data transfers.

This Tx_RstMatch condition must remain for eight TXCLK

cycles to initiate the Tx_FIFO_Reset. Following this the

TXFULL FIFO status flag is asserted to indicate that the

Transmit FIFO reset sequence has completed and that a

Transmit FIFO reset is in progress.

FIFO Reset Sequence

On power-up, the Transmitter and Receiver FIFOs are cleared

automatically. If the usage of the FIFOs in specific operating

modes results in stale or unwanted data, this data can be

cleared by resetting the respective FIFO. Data in the Transmit

FIFO will empty automatically if it is enabled to read the FIFO

(assuming TXHALT is not LOW). Stale received data can be

“flushed” by reading it, or the Receive FIFO can be reset to

remove the unwanted data.

When the TXRST signal is deasserted (HIGH), CE remains

LOW to allow the FIFO status flags to be driven. This allows

the completion of the reset operation to be monitored. To allow

better multi-tasking on multi-PHY implementations, it is

possible to deassert CE (HIGH) as soon as the FULL state is

indicated. The FIFO reset operation will complete and the

EMPTY state (indicating completion of the reset operation)

can be detected during a separate polling operation.

The Transmit and Receive FIFOs are reset when the

Tx_RstMatch or Rx_RstMatch condition remains present for

eight consecutive clock cycles. Any disruption of the reset

sequence prior to reaching the eight cycle count, either by

removal of CE or the respective TXRST or RXRST, or

assertion of the associated TXEN or RXEN, terminates the

sequence and does not reset the FIFO. Because CE must

remain asserted during the reset sequence, the addressed

FIFO flags remain driven during the entire sequence.

For those links implemented with a single PHY, it is possible

to hardwire CE LOW and still perform normal accesses and

reset operations. This is shown in Figure 13. In a single-PHY

implementation, a Transmit FIFO reset can never be initiated

with TXEN asserted at the same time as TXRST. Since CE is

always LOW, any assertion of TXEN causes the Transmit

FIFO to be selected, clearing the reset counter.

Document #: 38-02020 Rev. *C

Page 41 of 46

CY7C9689A

TXCLK

TXRST

Note 48

TXEN

CE

Tx_RstMatch^[49]

[49]

Tx_Match

Tx_FIFO_Reset^[49]

TXFULL

Note 48

Not Full

Full

Figure 13. Transmit FIFO Reset Sequence with Constant CE

TXCLK

TXRST

TXEN

CE

Note 48

[49]

Tx_RstMatch

Tx_Match^[49]

Tx_FIFO_Reset^[49]

TXFULL

Note 48

Not Full

Figure 14. Invalid Transmit FIFO Reset Sequence with TXEN Asserted

Notes:

48. Signals shown as dotted lines indicate timing and levels when configured for external FIFOs (EXTFIFO is HIGH).

49. Signal names listed in italics are internal signals, shown for reference only.

Document #: 38-02020 Rev. *C

Page 42 of 46

CY7C9689A

TXCLK

TXRST

TXEN

CE

Note 48

Tx_RstMatch^[49]

Tx_Match^[49]

[49]

Tx_FIFO_Reset

TXFULL

Note 48

Not Full

Full

Figure 15. Transmit FIFO Reset Sequence

Figure 14 shows a sequence of input signals which will not

produce a FIFO reset. In this case TXEN was asserted to

select a Transmit FIFO for data transfers. Because TXEN

remains active, the assertion of CE and TXRST does not

initiate a reset operation. This is shown by the TXFULL flag

remaining HIGH (deasserted) following what would be the

normal expiration of the seven-state reset counter.

selection of the interface. A sample Receive FIFO reset

sequence is shown in Figure 16. Upon recognition of a

Receive FIFO reset, the Receive FIFO flags are forced to

indicate an EMPTY state to prohibit additional reads from the

FIFO. Unlike the Transmit FIFO, where the internal completion

of the reset operation is shown by first going FULL and later

going EMPTY when the internal reset is complete, there is no

secondary indication of the completion of the internal reset of

the Receive FIFO. The Receive FIFO is usable as soon as

new data is placed into it by the Receive Control State

Machine.

Receive FIFO Reset Sequence

The Receive FIFO reset sequence operates (for the most part)

the same as the Transmit FIFO reset sequence. The same

requirements exist for the assertion state of RXRST and

RXCLK

RXRST

RXEN

CE

Note 48

Rx_RstMatch^[49]

Rx_Match^[49]

Rx_FIFO_Reset ^[49]

RXEMPTY

Note 48

Empty

Not Empty

Figure 16. Receive FIFO Reset Sequence

Document #: 38-02020 Rev. *C

Page 43 of 46

CY7C9689A

Printed Circuit Board Layout Suggestions

OUTA±

OUTB±

INA±

INB±

Power Supply Bypass

0.01-µF MLC X7R

1206 Chip Cap (4 sites)

Power Supply Bypass

0.01-µF MLC X7R

CURSETB

Resistor

CURSETA

Resistor

Power Supply Bypass

0.01-µF MLC X7R

1206 Chip Cap (2 sites)

RXSC/D

REFCLK

CY7CCY79C6986899AA--AACC

Power Supply Bypass

0.01-µF MLC X7R

RESET

Power Supply Bypass

0.01-µF MLC X7R

Via to V_DDplane

Via to V_SSplane

This is a typical printed circuit board layout showing example

placement of power supply bypass components and other

components mounted on the same side as the CY7C9689A.

Other layouts, including cases with components mounted on

the reverse side would work as well.

Ordering Information

Ordering Code

CY7C9689A-AC

CY7C9689A-AI

Package Name

A100

Package Type

Operating Range

Commercial

Industrial

100-lead Thin Quad Flat Pack

A100

Document #: 38-02020 Rev. *C

Page 44 of 46

CY7C9689A

Package Diagram

100-pin Thin Plastic Quad Flat Pack (TQFP) A100

51-85048-B

HOTLink is a registered trademark of Cypress Semiconductor, Inc. AMD, TAXI, and TAXIchip are trademarks of Advanced Micro

Devices. Inc. All product and company names mentioned in this document are trademarks of their respective holders.

Document #: 38-02020 Rev. *C

Page 45 of 46

of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize

its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress

Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

CY7C9689A

Document Title: CY7C9689A TAXI™-compatible HOTLink Transceiver

Document Number: 38-02020

Issue

Date

Orig. of

Change

REV.

**

ECN NO.

106249

107695

113563

Description of Change

Change from Spec number: 38-00758 to 38-02020

Changed part number: CY7C9689 to CY7C9689A

04/20/01

06/28/01

04/10/02

SZV

SPN

REV

*A

*B

Removed parity reference

Deleted mention of Byte-packer

Fixed formatting to change mF to µF

*C

118318

11/08/02

REV

Changed pins 23 and 29 to RXDATA[11:10]/RXCMD[1:0]

LFI was changed from “three state” to just output pin

Fixed flip flop to Q as output and D as input

Font problem with up-arrow symbols corrected

Document #: 38-02020 Rev. *C

Page 46 of 46


型号：	CY7C9689A
厂家：	CYPRESS
描述：	TAXI-compatible HOTLink Transceiver TAXI兼容的HOTLink收发器
文件：	总46页 (文件大小：567K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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