CY7C68016A_技术文档

CY7C68013A/CY7C68014A

CY7C68015A/CY7C68016A

EZ-USB FX2LP™ USB Microcontroller

• Integrated, industry-standard enhanced 8051

1.0

Features (CY7C68013A/14A/15A/16A)

— 48-MHz, 24-MHz, or 12-MHz CPU operation

— Four clocks per instruction cycle

— Two USARTS

• USB 2.0–USB-IF high speed certified (TID # 40440111)

• Single-chip integrated USB 2.0 transceiver, smart SIE,

and enhanced 8051 microprocessor

— Three counter/timers

• Fit, form and function compatible with the FX2

— Expanded interrupt system

— Two data pointers

— Pin-compatible

— Object-code-compatible

• 3.3V operation with 5V tolerant inputs

— Functionally-compatible (FX2LP is a superset)

• Vectored USB interrupts and GPIF/FIFO interrupts

• Ultra Low power: I no more than 85 mA in any mode

CC

• Separate data buffers for the Set-up and Data portions

of a CONTROL transfer

— Ideal for bus and battery powered applications

• Software: 8051 code runs from:

2

• Integrated I C controller, runs at 100 or 400 kHz

— Internal RAM, which is downloaded via USB

— Internal RAM, which is loaded from EEPROM

— External memory device (128 pin package)

• 16 KBytes of on-chip Code/Data RAM

• Four integrated FIFOs

— Integrated glue logic and FIFOs lower system cost

— Automatic conversion to and from 16-bit buses

— Master or slave operation

• Four programmable BULK/INTERRUPT/ISOCHRO-

NOUS endpoints

— Uses external clock or asynchronous strobes

— Easy interface to ASIC and DSP ICs

— Buffering options: double, triple, and quad

• Additional programmable (BULK/INTERRUPT) 64-byte

endpoint

1.1

Features (CY7C68013A/14A only)

• CY7C68014A: Ideal for battery powered applications

— Suspend current: 100 µA (typ)

• 8- or 16-bit external data interface

• Smart Media Standard ECC generation

• GPIF (General Programmable Interface)

— Allows direct connection to most parallel interface

• CY7C68013A: Ideal for non-battery powered applica-

tions

— Suspend current: 300 µA (typ)

• Available in four lead-free packages with up to 40 GPIOs

— Programmable waveform descriptors and configu-

ration registers to define waveforms

— 128-pin TQFP (40 GPIOs), 100-pin TQFP (40 GPIOs),

56-pin QFN (24 GPIOs) and 56-pin SSOP (24 GPIOs)

— Supports multiple Ready (RDY) inputs and Control

(CTL) outputs

High-performance micro

using standard tools

24 MHz

Ext. XTAL

with lower-power options

FX2LP

2

/0.5

/1.0

/2.0

I C

8051 Core

x20

Master

VCC

12/24/48 MHz,

four clocks/cycle

PLL

Abundant I/O

including two USARTS

Additional I/Os (24)

1.5k

connected for

full speed

General

ADDR (9)

programmable I/F

to ASIC/DSP or bus

standards such as

D+

D–

GPIF

USB

2.0

XCVR

CY

Smart

USB

16 KB

RAM

RDY (6)

CTL (6)

ATAPI, EPP, etc.

ECC

1.1/2.0

Engine

Integrated

full- and high-speed

XCVR

Up to 96 MBytes/s

burst rate

4 kB

FIFO

8/16

Enhanced USB core

Simplifies 8051 code

“Soft Configuration”

Easy firmware changes

FIFO and endpoint memory

(master or slave operation)

Figure 1-1. Block Diagram

Cypress Semiconductor Corporation

Document #: 38-08032 Rev. *G

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Revised February 1, 2005

CY7C68013A/CY7C68014A

CY7C68015A/CY7C68016A

an easy and glueless interface to popular interfaces such as

ATA, UTOPIA, EPP, PCMCIA, and most DSP/processors.

1.2

Features (CY7C68015A/16A only)

• CY7C68016A: Ideal for battery powered applications

The FX2LP draws considerably less current than the FX2

(CY7C68013), has double the on-chip code/data RAM and is

fit, form and function compatible with the 56-, 100-, and 128-

pin FX2.

— Suspend current: 100 µA (typ)

• CY7C68015A: Ideal for non-battery powered applica-

tions

— Suspend current: 300 µA (typ)

• Available in lead-free 56-pin QFN package (26 GPIOs)

Four packages are defined for the family: 56 SSOP, 56 QFN,

100 TQFP, and 128 TQFP.

— 2 more GPIOs than CY7C68013A/14A enabling addi-

tional features in same footprint

2.0

Applications

• Portable video recorder

• MPEG/TV conversion

• DSL modems

Cypress Semiconductor Corporation’s (Cypress’s) EZ-USB

FX2LP (CY7C68013A/14A) is a low-power version of the

EZ-USB FX2 (CY7C68013), which is a highly integrated,

low-power USB 2.0 microcontroller. By integrating the USB 2.0

transceiver, serial interface engine (SIE), enhanced 8051

microcontroller, and a programmable peripheral interface in a

single chip, Cypress has created a very cost-effective solution

that provides superior time-to-market advantages with low

power to enable bus powered applications.

• ATA interface

• Memory card readers

• Legacy conversion devices

• Cameras

• Scanners

The ingenious architecture of FX2LP results in data transfer

rates of over 53 Mbytes per second, the maximum-allowable

USB 2.0 bandwidth, while still using a low-cost 8051 microcon-

troller in a package as small as a 56 QFN. Because it incorpo-

rates the USB 2.0 transceiver, the FX2LP is more economical,

providing a smaller footprint solution than USB 2.0 SIE or

external transceiver implementations. With EZ-USB FX2LP,

the Cypress Smart SIE handles most of the USB 1.1 and 2.0

protocol in hardware, freeing the embedded microcontroller for

application-specific functions and decreasing development

time to ensure USB compatibility.

• Home PNA

• Wireless LAN

• MP3 players

• Networking

The “Reference Designs” section of the Cypress web site

provides additional tools for typical USB 2.0 applications. Each

reference design comes complete with firmware source and

object code, schematics, and documentation. Please visit

http://www.cypress.com for more information.

The General Programmable Interface (GPIF) and

Master/Slave Endpoint FIFO (8- or 16-bit data bus) provides

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The CLKOUT pin, which can be three-stated and inverted

using internal control bits, outputs the 50% duty cycle 8051

clock, at the selected 8051 clock frequency—48, 24, or 12

MHz.

3.0

3.1

Functional Overview

USB Signaling Speed

FX2LP operates at two of the three rates defined in the USB

Specification Revision 2.0, dated April 27, 2000:

3.2.2

USARTS

• Full speed, with a signaling bit rate of 12 Mbps

• High speed, with a signaling bit rate of 480 Mbps.

FX2LP contains two standard 8051 USARTs, addressed via

Special Function Register (SFR) bits. The USART interface

pins are available on separate I/O pins, and are not multi-

plexed with port pins.

FX2LP does not support the low-speed signaling mode of

1.5 Mbps.

UART0 and UART1 can operate using an internal clock at

230 KBaud with no more than 1% baud rate error. 230-KBaud

operation is achieved by an internally derived clock source that

generates overflow pulses at the appropriate time. The

internal clock adjusts for the 8051 clock rate (48, 24, 12 MHz)

such that it always presents the correct frequency for 230-

3.2

8051 Microprocessor

The 8051 microprocessor embedded in the FX2LP family has

256 bytes of register RAM, an expanded interrupt system,

three timer/counters, and two USARTs.

[1]

KBaud operation.

3.2.1

8051 Clock Frequency

3.2.3

Special Function Registers

FX2LP has an on-chip oscillator circuit that uses an external

24-MHz (±100-ppm) crystal with the following characteristics:

Certain 8051 SFR addresses are populated to provide fast

access to critical FX2LP functions. These SFR additions are

shown in Table 3-1. Bold type indicates non-standard,

enhanced 8051 registers. The two SFR rows that end with “0”

and “8” contain bit-addressable registers. The four I/O ports

A–D use the SFR addresses used in the standard 8051 for

ports 0–3, which are not implemented in FX2LP. Because of

the faster and more efficient SFR addressing, the FX2LP I/O

ports are not addressable in external RAM space (using the

MOVX instruction).

• Parallel resonant

• Fundamental mode

• 500-µW drive level

• 12-pF (5% tolerance) load capacitors.

An on-chip PLL multiplies the 24-MHz oscillator up to

480 MHz, as required by the transceiver/PHY, and internal

counters divide it down for use as the 8051 clock. The default

8051 clock frequency is 12 MHz. The clock frequency of the

8051 can be changed by the 8051 through the CPUCS

register, dynamically.

2

3.3

I C Bus

2

FX2LP supports the I C bus as a master only at 100-/400-KHz.

SCL and SDA pins have open-drain outputs and hysteresis

inputs. These signals must be pulled up to 3.3V, even if no I C

24 MHz

C1

C2

2

device is connected.

12 pf

3.4

Buses

All packages: 8- or 16-bit “FIFO” bidirectional data bus, multi-

plexed on I/O ports B and D. 128-pin package: adds 16-bit

output-only 8051 address bus, 8-bit bidirectional data bus.

20 × PLL

12-pF capacitor values assumes a trace capacitance

of 3 pF per side on a four-layer FR4 PCA

Figure 3-1. Crystal Configuration

Note:

1. 115-KBaud operation is also possible by programming the 8051 SMOD0 or SMOD1 bits to a “1” for UART0 and/or UART1, respectively.

Document #: 38-08032 Rev. *G

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Table 3-1. Special Function Registers

x

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

8x

IOA

9x

IOB

Ax

Bx

Cx

Dx

Ex

Fx

IOC

IOD

SCON1

SBUF1

PSW

ACC

B

SP

EXIF

INT2CLR

INT4CLR

IOE

DPL0

DPH0

DPL1

DPH1

DPS

MPAGE

OEA

OEB

OEC

OED

OEE

PCON

TCON

TMOD

TL0

SCON0

SBUF0

IE

IP

T2CON

EICON

EIE

EIP

AUTOPTRH1

AUTOPTRL1

reserved

EP2468STAT

EP24FIFOFLGS

EP68FIFOFLGS

EP01STAT

GPIFTRIG

RCAP2L

RCAP2H

TL2

TL1

TH0

TH1

AUTOPTRH2

AUTOPTRL2

reserved

GPIFSGLDATH

GPIFSGLDATLX

TH2

CKCON

AUTOPTRSET-UP GPIFSGLDATLNOX

RENUM. To simulate a USB disconnect, the firmware sets

DISCON to 1. To reconnect, the firmware clears DISCON to 0.

3.5

USB Boot Methods

2

During the power-up sequence, internal logic checks the I C

port for the connection of an EEPROM whose first byte is

either 0xC0 or 0xC2. If found, it uses the VID/PID/DID values

in the EEPROM in place of the internally stored values (0xC0),

or it boot-loads the EEPROM contents into internal RAM

(0xC2). If no EEPROM is detected, FX2LP enumerates using

internally stored descriptors. The default ID values for FX2LP

are VID/PID/DID (0x04B4, 0x8613, 0xAxxx where xxx = Chip

Before reconnecting, the firmware sets or clears the RENUM

bit to indicate whether the firmware or the Default USB Device

will handle device requests over endpoint zero: if RENUM = 0,

the Default USB Device will handle device requests; if RENUM

= 1, the firmware will.

3.7

Bus-powered Applications

[2]

revision).

The FX2LP fully supports bus-powered designs by enumer-

ating with less than 100 mA as required by the USB 2.0 speci-

fication.

Table 3-2. Default ID Values for FX2LP

Default VID/PID/DID

Vendor ID

Product ID

0x04B4 Cypress Semiconductor

0x8613 EZ-USB FX2LP

3.8

Interrupt System

Device release 0xAnnn Depends chip revision

(nnn = chip revision where first

silicon = 001)

3.8.1

INT2 Interrupt Request and Enable Registers

FX2LP implements an autovector feature for INT2 and INT4.

There are 27 INT2 (USB) vectors, and 14 INT4 (FIFO/GPIF)

vectors. See EZUSB Technical Reference Manual (TRM) for

more details.

3.6

ReNumeration™

Because the FX2LP’s configuration is soft, one chip can take

on the identities of multiple distinct USB devices.

3.8.2

USB-Interrupt Autovectors

The main USB interrupt is shared by 27 interrupt sources. To

save the code and processing time that normally would be

required to identify the individual USB interrupt source, the

FX2LP provides a second level of interrupt vectoring, called

Autovectoring. When a USB interrupt is asserted, the FX2LP

pushes the program counter onto its stack then jumps to

address 0x0043, where it expects to find a “jump” instruction

to the USB Interrupt service routine.

When first plugged into USB, the FX2LP enumerates automat-

ically and downloads firmware and USB descriptor tables over

the USB cable. Next, the FX2LP enumerates again, this time

as a device defined by the downloaded information. This

patented two-step process, called ReNumeration, happens

instantly when the device is plugged in, with no hint that the

initial download step has occurred.

Two control bits in the USBCS (USB Control and Status)

register control the ReNumeration process: DISCON and

Note:

2. The I²C bus SCL and SDA pins must be pulled up, even if an EEPROM is not connected. Otherwise this detection method does not work properly.

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The FX2LP jump instruction is encoded as follows.

Table 3-3. INT2 USB Interrupts

USB INTERRUPT TABLE FOR INT2

Source

Priority

1

INT2VEC Value

Notes

00

04

08

0C

10

14

18

1C

20

24

28

2C

30

34

38

3C

40

44

48

4C

50

54

58

5C

60

64

68

6C

70

74

78

7C

SUDAV

Set-up Data Available

2

SOF

Start of Frame (or microframe)

Set-up Token Received

3

SUTOK

4

SUSPEND

USB RESET

HISPEED

EP0ACK

USB Suspend request

5

Bus reset

6

Entered high speed operation

FX2LP ACK’d the CONTROL Handshake

reserved

7

8

9

EP0-IN

EP0-OUT

EP1-IN

EP1-OUT

EP2

EP0-IN ready to be loaded with data

EP0-OUT has USB data

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

EP1-IN ready to be loaded with data

EP1-OUT has USB data

IN: buffer available. OUT: buffer has data

IN-Bulk-NAK (any IN endpoint)

reserved

EP4

EP6

EP8

IBN

EP0PING

EP1PING

EP2PING

EP4PING

EP6PING

EP8PING

ERRLIMIT

EP0 OUT was Pinged and it NAK’d

EP1 OUT was Pinged and it NAK’d

EP2 OUT was Pinged and it NAK’d

EP4 OUT was Pinged and it NAK’d

EP6 OUT was Pinged and it NAK’d

EP8 OUT was Pinged and it NAK’d

Bus errors exceeded the programmed limit

reserved

EP2ISOERR

EP4ISOERR

EP6ISOERR

EP8ISOERR

ISO EP2 OUT PID sequence error

ISO EP4 OUT PID sequence error

ISO EP6 OUT PID sequence error

ISO EP8 OUT PID sequence error

If Autovectoring is enabled (AV2EN = 1 in the INTSET-UP

register), the FX2LP substitutes its INT2VEC byte. Therefore,

if the high byte (“page”) of a jump-table address is preloaded

at location 0x0044, the automatically-inserted INT2VEC byte

at 0x0045 will direct the jump to the correct address out of the

27 addresses within the page.

3.8.3

FIFO/GPIF Interrupt (INT4)

Just as the USB Interrupt is shared among 27 individual USB-

interrupt sources, the FIFO/GPIF interrupt is shared among 14

individual FIFO/GPIF sources. The FIFO/GPIF Interrupt, like

the USB Interrupt, can employ autovectoring. Table 3-4 shows

the priority and INT4VEC values for the 14 FIFO/GPIF

interrupt sources.

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Table 3-4. Individual FIFO/GPIF Interrupt Sources

Priority

INT4VEC Value

Source

EP2PF

EP4PF

EP6PF

EP8PF

EP2EF

EP4EF

EP6EF

EP8EF

EP2FF

EP4FF

EP6FF

EP8FF

GPIFDONE

GPIFWF

Notes

1

2

80

84

88

8C

90

94

98

9C

A0

A4

A8

AC

B0

B4

Endpoint 2 Programmable Flag

Endpoint 4 Programmable Flag

Endpoint 6 Programmable Flag

Endpoint 8 Programmable Flag

Endpoint 2 Empty Flag

Endpoint 4 Empty Flag

Endpoint 6 Empty Flag

Endpoint 8 Empty Flag

Endpoint 2 Full Flag

3

4

5

6

7

8

9

10

11

12

13

14

Endpoint 4 Full Flag

Endpoint 6 Full Flag

Endpoint 8 Full Flag

GPIF Operation Complete

GPIF Waveform

If Autovectoring is enabled (AV4EN = 1 in the INTSET-UP

register), the FX 2LP substitutes its INT4VEC byte. Therefore,

if the high byte (“page”) of a jump-table address is preloaded

at location 0x0054, the automatically-inserted INT4VEC byte

at 0x0055 will direct the jump to the correct address out of the

14 addresses within the page. When the ISR occurs, the

FX2LP pushes the program counter onto its stack then jumps

to address 0x0053, where it expects to find a “jump” instruction

to the ISR Interrupt service routine.

used with the CY7C680xxA the reset period must allow for the

stabilization of the crystal and the PLL. This reset period

should be approximately 5 ms after VCC has reached 3.0V. If

the crystal input pin is driven by a clock signal the internal PLL

[3]

stabilizes in 200 µs after VCC has reached 3.0V . Figure 3-2

shows a power-on reset condition and a reset applied during

operation. A power-on reset is defined as the time reset is

asserted while power is being applied to the circuit. A powered

reset is defined to be when the FX2LP has previously been

powered on and operating and the RESET# pin is asserted.

Cypress provides an application note which describes and

recommends power on reset implementation and can be found

on the Cypress web site. For more information on reset imple-

mentation for the FX2 family of products visit the

http://www.cypress.com.

3.9

Reset and Wakeup

3.9.1

Reset Pin

The input pin, RESET#, will reset the FX2LP when asserted.

This pin has hysteresis and is active LOW. When a crystal is

Note:

3. If the external clock is powered at the same time as the CY7C680xxA and has a stabilization wait period, it must be added to the 200 µs.

Document #: 38-08032 Rev. *G

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RESET#

V

IL

V

IL

3.3V

3.0V

3.3V

VCC

0V

T

RESET

Powered Reset

RESET

Power on Reset

Figure 3-2. Reset Timing Plots

3.10 Program/Data RAM

3.10.1 Size

Table 3-5. Reset Timing Values

Condition

T

RESET

Power-on Reset with crystal

5 ms

The FX2LP has 16 KBytes of internal program/data RAM,

where PSEN#/RD# signals are internally ORed to allow the

8051 to access it as both program and data memory. No USB

control registers appear in this space.

Power-on Reset with external 200 µs + Clock stability time

clock

Powered Reset

200 µs

Two memory maps are shown in the following diagrams:

Figure 3-3 Internal Code Memory, EA = 0

3.9.2 Wakeup Pins

The 8051 puts itself and the rest of the chip into a power-down

mode by setting PCON.0 = 1. This stops the oscillator and

PLL. When WAKEUP is asserted by external logic, the oscil-

lator restarts, after the PLL stabilizes, and then the 8051

receives a wakeup interrupt. This applies whether or not

FX2LP is connected to the USB.

Figure 3-4 External Code Memory, EA = 1.

3.10.2 Internal Code Memory, EA = 0

This mode implements the internal 16-KByte block of RAM

(starting at 0) as combined code and data memory. When

external RAM or ROM is added, the external read and write

strobes are suppressed for memory spaces that exist inside

the chip. This allows the user to connect a 64-KByte memory

without requiring address decodes to keep clear of internal

memory spaces.

The FX2LP exits the power-down (USB suspend) state using

one of the following methods:

• USB bus activity (if D+/D– lines are left floating, noise on

these lines may indicate activity to the FX2LP and initiate a

wakeup).

Only the internal 16 KBytes and scratch pad 0.5 KBytes RAM

spaces have the following access:

• External logic asserts the WAKEUP pin

• External logic asserts the PA3/WU2 pin.

• USB download

• USB upload

The second wakeup pin, WU2, can also be configured as a

general purpose I/O pin. This allows a simple external R-C

network to be used as a periodic wakeup source. Note that

WAKEUP is by default active LOW.

• Set-up data pointer

2

• I C interface boot load.

3.10.3 External Code Memory, EA = 1

The bottom 16 KBytes of program memory is external, and

therefore the bottom 16 KBytes of internal RAM is accessible

only as data memory.

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Inside FX2LP

Outside FX2LP

FFFF

7.5 KBytes

(OK to populate

data memory

here—RD#/WR#

strobes are not

active)

USB regs and

4K FIFO buffers

(RD#,WR#)

E200

E1FF

0.5 KBytes RAM

Data (RD#,WR#)*

E000

48 KBytes

External

Code

Memory

(PSEN#)

40 KBytes

External

Data

Memory

(RD#,WR#)

3FFF

(Ok to populate

data memory

here—RD#/WR#

strobes are not

active)

(OK to populate

program

memory here—

PSEN# strobe

is not active)

16 KBytes RAM

Code and Data

(PSEN#,RD#,WR#)*

0000

Data

2

Code

*SUDPTR, USB upload/download, I C interface boot access

Figure 3-3. Internal Code Memory, EA = 0

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Inside FX2LP

Outside FX2LP

FFFF

7.5 KBytes

(OK to populate

USB regs and

4K FIFO buffers

(RD#,WR#)

data memory

here—RD#/WR#

strobes are not

active)

E200

E1FF

0.5 KBytes RAM

Data (RD#,WR#)*

E000

40 KBytes

External

Data

Memory

(RD#,WR#)

64 KBytes

External

Code

Memory

(PSEN#)

3FFF

(Ok to populate

data memory

here—RD#/WR#

strobes are not

active)

16 KBytes

RAM

Data

(RD#,WR#)*

0000

Data

2

Code

*SUDPTR, USB upload/download, I C interface boot access

Figure 3-4. External Code Memory, EA = 1

3.11

Register Addresses

FFFF

4 KBytes EP2-EP8

buffers

(8 x 512)

F000

EFFF

2 KBytes RESERVED

E800

E7FF

64 Bytes EP1IN

E7C0

E7BF

E780

64 Bytes EP1OUT

E77F

E740

64 Bytes EP0 IN/OUT

E73F

64 Bytes RESERVED

E700

E6FF

8051 Addressable Registers

(512)

E500

E4FF

Reserved (128)

E480

E47F

128 bytes GPIF Waveforms

E400

E3FF

E200

Reserved (512)

E1FF

512 bytes

8051 xdata RAM

E000

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3.12.3 Set-up Data Buffer

3.12

Endpoint RAM

A separate 8-byte buffer at 0xE6B8-0xE6BF holds the Set-up

data from a CONTROL transfer.

3.12.1 Size

• 3× 64 bytes

(Endpoints 0 and 1)

3.12.4 Endpoint Configurations (High-speed Mode)

• 8 × 512 bytes (Endpoints 2, 4, 6, 8)

Endpoints 0 and 1 are the same for every configuration.

Endpoint 0 is the only CONTROL endpoint, and endpoint 1 can

be either BULK or INTERRUPT. The endpoint buffers can be

configured in any 1 of the 12 configurations shown in the

vertical columns. When operating in full-speed BULK mode

only the first 64 bytes of each buffer are used. For example in

high-speed, the max packet size is 512 bytes but in full-speed

it is 64 bytes. Even though a buffer is configured to be a 512

byte buffer, in full-speed only the first 64 bytes are used. The

unused endpoint buffer space is not available for other opera-

tions. An example endpoint configuration would be:

3.12.2 Organization

• EP0

• Bidirectional endpoint zero, 64-byte buffer

• EP1IN, EP1OUT

• 64-byte buffers, bulk or interrupt

• EP2,4,6,8

• Eight 512-byte buffers, bulk, interrupt, or isochronous. EP4

and EP8 can be double buffered, while EP2 and 6 can be

either double, triple, or quad buffered. For high-speed end-

point configuration options, see Figure 3-5.

EP2—1024 double buffered; EP6—512 quad buffered

(column 8).

64

EP0 IN&OUT

EP1 IN

EP1 OUT

EP2

512

EP2

EP2 EP2

EP2

512

EP2

512

EP2

512

1024

512

1024

EP4

512

EP4 EP4

512

EP6

1024

512

EP6

512

EP6

512

EP6

EP6 EP6

EP6

EP6 EP6

512

1024

512

1024

512

EP8

512

EP8

512

EP8

512

EP8

512

EP8

512

1024

512

1024

512

10

12

9

11

4

5

8

1

2

7

3

6

Figure 3-5. Endpoint Configuration

Document #: 38-08032 Rev. *G

Page 10 of 55

CY7C68013A/CY7C68014A

CY7C68015A/CY7C68016A

3.12.5 Default Full-Speed Alternate Settings

[4, 5]

Table 3-6. Default Full-Speed Alternate Settings

Alternate Setting

0

64

0

1

2

3

ep0

64

ep1out

ep1in

ep2

64 bulk

64 int

0

64 bulk out (2×)

64 bulk in (2×)

64 int out (2×)

64 bulk out (2×)

64 int in (2×)

64 iso out (2×)

64 bulk out (2×)

64 iso in (2×)

ep4

0

ep6

0

ep8

0

64 bulk in (2×)

3.12.6 Default High-Speed Alternate Settings

[4, 5]

Table 3-7. Default High-Speed Alternate Settings

Alternate Setting

0

1

2

3

ep0

64

0

64

[6]

ep1out

ep1in

ep2

512 bulk

64 int

0

64 int

0

512 bulk out (2×)

512 bulk in (2×)

512 int out (2×)

512 bulk out (2×)

512 int in (2×)

512 bulk in (2×)

512 iso out (2×)

512 bulk out (2×)

512 iso in (2×)

512 bulk in (2×)

ep4

0

ep6

0

ep8

0

port in the 8051-I/O domain. The blocks can be configured as

single, double, triple, or quad buffered as previously shown.

3.13

External FIFO Interface

3.13.1 Architecture

The I/O control unit implements either an internal-master (M

for master) or external-master (S for Slave) interface.

The FX2LP slave FIFO architecture has eight 512-byte blocks

in the endpoint RAM that directly serve as FIFO memories,

and are controlled by FIFO control signals (such as IFCLK,

SLCS#, SLRD, SLWR, SLOE, PKTEND, and flags).

In Master (M) mode, the GPIF internally controls

FIFOADR[1..0] to select a FIFO. The RDY pins (two in the 56-

pin package, six in the 100-pin and 128-pin packages) can be

used as flag inputs from an external FIFO or other logic if

desired. The GPIF can be run from either an internally derived

clock or externally supplied clock (IFCLK), at a rate that

transfers data up to 96 Megabytes/s (48-MHz IFCLK with 16-

bit interface).

In operation, some of the eight RAM blocks fill or empty from

the SIE, while the others are connected to the I/O transfer

logic. The transfer logic takes two forms, the GPIF for internally

generated control signals, or the slave FIFO interface for

externally controlled transfers.

In Slave (S) mode, the FX2LP accepts either an internally

derived clock or externally supplied clock (IFCLK, max.

frequency 48 MHz) and SLCS#, SLRD, SLWR, SLOE,

PKTEND signals from external logic. When using an external

IFCLK, the external clock must be present before switching to

the external clock with the IFCLKSRC bit. Each endpoint can

individually be selected for byte or word operation by an

internal configuration bit, and a Slave FIFO Output Enable

signal SLOE enables data of the selected width. External logic

must insure that the output enable signal is inactive when

writing data to a slave FIFO. The slave interface can also

operate asynchronously, where the SLRD and SLWR signals

act directly as strobes, rather than a clock qualifier as in

synchronous mode. The signals SLRD, SLWR, SLOE and

PKTEND are gated by the signal SLCS#.

3.13.2 Master/Slave Control Signals

The FX2LP endpoint FIFOS are implemented as eight physi-

cally distinct 256x16 RAM blocks. The 8051/SIE can switch

any of the RAM blocks between two domains, the USB (SIE)

domain and the 8051-I/O Unit domain. This switching is done

virtually instantaneously, giving essentially zero transfer time

between “USB FIFOS” and “Slave FIFOS.” Since they are

physically the same memory, no bytes are actually transferred

between buffers.

At any given time, some RAM blocks are filling/emptying with

USB data under SIE control, while other RAM blocks are

available to the 8051 and/or the I/O control unit. The RAM

blocks operate as single-port in the USB domain, and dual-

Notes:

4. “0” means “not implemented.”

5. “2×” means “double buffered.”

6. Even though these buffers are 64 bytes, they are reported as 512 for USB 2.0 compliance. The user must never transfer packets larger than 64 bytes to EP1.

Document #: 38-08032 Rev. *G

Page 11 of 55

CY7C68013A/CY7C68014A

CY7C68015A/CY7C68016A

ECC Generation^[7]

3.13.3 GPIF and FIFO Clock Rates

3.15

An 8051 register bit selects one of two frequencies for the

internally supplied interface clock: 30 MHz and 48 MHz. Alter-

natively, an externally supplied clock of 5 MHz–48 MHz

feeding the IFCLK pin can be used as the interface clock.

IFCLK can be configured to function as an output clock when

the GPIF and FIFOs are internally clocked. An output enable

bit in the IFCONFIG register turns this clock output off, if

desired. Another bit within the IFCONFIG register will invert

the IFCLK signal whether internally or externally sourced.

The EZ-USB can calculate ECCs (Error-Correcting Codes) on

data that passes across its GPIF or Slave FIFO interfaces.

There are two ECC configurations: Two ECCs, each calcu-

lated over 256 bytes (SmartMedia™ Standard); and one ECC

calculated over 512 bytes.

The ECC can correct any one-bit error or detect any two-bit

error.

3.15.1 ECC Implementation

The two ECC configurations are selected by the ECCM bit:

3.14

GPIF

The GPIF is a flexible 8- or 16-bit parallel interface driven by a

user-programmable finite state machine. It allows the

CY7C68013A/15A to perform local bus mastering, and can

implement a wide variety of protocols such as ATA interface,

printer parallel port, and Utopia.

3.15.1.1 ECCM=0

Two 3-byte ECCs, each calculated over a 256-byte block of

data. This configuration conforms to the SmartMedia

Standard.

Write any value to ECCRESET, then pass data across the

GPIF or Slave FIFO interface. The ECC for the first 256 bytes

of data will be calculated and stored in ECC1. The ECC for the

next 256 bytes will be stored in ECC2. After the second ECC

is calculated, the values in the ECCx registers will not change

until ECCRESET is written again, even if more data is subse-

quently passed across the interface.

The GPIF has six programmable control outputs (CTL), nine

address outputs (GPIFADRx), and six general-purpose ready

inputs (RDY). The data bus width can be 8 or 16 bits. Each

GPIF vector defines the state of the control outputs, and deter-

mines what state a ready input (or multiple inputs) must be

before proceeding. The GPIF vector can be programmed to

advance a FIFO to the next data value, advance an address,

etc. A sequence of the GPIF vectors make up a single

waveform that will be executed to perform the desired data

move between the FX2LP and the external device.

3.15.1.2 ECCM=1

One 3-byte ECC calculated over a 512-byte block of data.

Write any value to ECCRESET then pass data across the

GPIF or Slave FIFO interface. The ECC for the first 512 bytes

of data will be calculated and stored in ECC1; ECC2 is unused.

After the ECC is calculated, the value in ECC1 will not change

until ECCRESET is written again, even if more data is subse-

quently passed across the interface

3.14.1 Six Control OUT Signals

The 100- and 128-pin packages bring out all six Control Output

pins (CTL0-CTL5). The 8051 programs the GPIF unit to define

the CTL waveforms. The 56-pin package brings out three of

these signals, CTL0–CTL2. CTLx waveform edges can be

programmed to make transitions as fast as once per clock

(20.8 ns using a 48-MHz clock).

3.16

USB Uploads and Downloads

The core has the ability to directly edit the data contents of the

internal 16-KByte RAM and of the internal 512-byte scratch

pad RAM via a vendor-specific command. This capability is

normally used when “soft” downloading user code and is

available only to and from internal RAM, only when the 8051

is held in reset. The available RAM spaces are 16 KBytes from

0x0000–0x3FFF (code/data) and 512 bytes from

3.14.2 Six Ready IN Signals

The 100- and 128-pin packages bring out all six Ready inputs

(RDY0–RDY5). The 8051 programs the GPIF unit to test the

RDY pins for GPIF branching. The 56-pin package brings out

two of these signals, RDY0–1.

[8]

0xE000–0xE1FF (scratch pad data RAM).

3.14.3 Nine GPIF Address OUT Signals

Nine GPIF address lines are available in the 100- and 128-pin

packages, GPIFADR[8..0]. The GPIF address lines allow

indexing through up to a 512-byte block of RAM. If more

address lines are needed, I/O port pins can be used.

3.17

Autopointer Access

FX2LP provides two identical autopointers. They are similar to

the internal 8051 data pointers, but with an additional feature:

they can optionally increment after every memory access. This

capability is available to and from both internal and external

RAM. The autopointers are available in external FX2LP

registers, under control of a mode bit (AUTOPTRSET-UP.0).

Using the external FX2LP autopointer access (at 0xE67B –

0xE67C) allows the autopointer to access all RAM, internal

and external to the part. Also, the autopointers can point to any

FX2LP register or endpoint buffer space. When autopointer

access to external memory is enabled, location 0xE67B and

0xE67C in XDATA and code space cannot be used.

3.14.4 Long Transfer Mode

In master mode, the 8051 appropriately sets GPIF transaction

count registers (GPIFTCB3, GPIFTCB2, GPIFTCB1, or

32

GPIFTCB0) for unattended transfers of up to 2 transactions.

The GPIF automatically throttles data flow to prevent under or

overflow until the full number of requested transactions

complete. The GPIF decrements the value in these registers

to represent the current status of the transaction.

Notes:

7. To use the ECC logic, the GPIF or Slave FIFO interface must be configured for byte-wide operation.

8. After the data has been downloaded from the host, a “loader” can execute from internal RAM in order to transfer downloaded data to external memory.

Document #: 38-08032 Rev. *G

Page 12 of 55

CY7C68013A/CY7C68014A

CY7C68015A/CY7C68016A

2

to increased internal memory) is required for more information

about migrating from EZ-USB FX2 to EZ-USB FX2LP, please

see further details in the application note titled Migrating from

EZ-USB FX2 to EZ-USB FX2LP, which is available on the

Cypress Website.

3.18

I C Controller

2

FX2LP has one I C port that is driven by two internal

controllers, one that automatically operates at boot time to

load VID/PID/DID and configuration information, and another

that the 8051, once running, uses to control external I C

devices. The I C port operates in master mode only.

2

Table 3-9. Part Number Conversion Table

EZ-USB FX2

Part Number

EZ-USB FX2LP

Part Number

Package

Description

2

3.18.1 I C Port Pins

2

The I C- pins SCL and SDA must have external 2.2-kΩ pull-

CY7C68013-

56PVC

CY7C68013A-56PVXC or 56-pin SSOP

CY7C68014A-56PVXC

up resistors even if no EEPROM is connected to the FX2LP.

External EEPROM device address pins must be configured

properly. See Table 3-8 for configuring the device address

pins.

CY7C68013- CY7C68013A-56PVXCT or 56-pin SSOP

56PVCT

CY7C68014A-56PVXCT – Tape and

Reel

Table 3-8. Strap Boot EEPROM Address Lines to These

Values

CY7C68013-

56LFC

CY7C68013A-56LFXC or 56-pin QFN

CY7C68014A-56LFXC

CY7C68013-

100AC

CY7C68013A-100AXC or 100-pinTQFP

CY7C68014A-100AXC

Bytes

16

Example EEPROM

A2

N/A

0

A1

N/A

0

A0

N/A

0

[9]

24LC00

CY7C68013-

128AC

CY7C68013A-128AXC or 128-pinTQFP

CY7C68014A-128AXC

128

256

4K

24LC01

24LC02

24LC32

24LC64

24LC128

0

1

3.20

CY7C68013A/14A and CY7C68015A/16A

Differences

8K

0

1

16K

0

1

CY7C68013A is identical to CY7C68014A in form, fit, and

functionality. CY7C68015A is identical to CY7C68016A in

form, fit, and functionality. CY7C68014A and CY7C68016A

have a lower suspend current than CY7C68013A and

CY7C68015A respectively. CY7C68014A and CY7C68016A

have a lower suspend current than CY7C68013A and

CY7C68015A respectively: hence are ideal for power-

sensitive battery applications.

2

3.18.2 I C Interface Boot Load Access

2

At power-on reset the I C interface boot loader will load the

VID/PID/DID configuration bytes and up to 16 KBytes of

program/data. The available RAM spaces are 16 KBytes from

0x0000–0x3FFF and 512 bytes from 0xE000–0xE1FF. The

2

8051 will be in reset. I C interface boot loads only occur after

CY7C68015A and CY7C68016A are available in 56-pin QFN

package only. Two additional GPIO signals are available on

the CY7C68015A and CY7C68016A to provide more flexibility

when neither IFCLK or CLKOUT are needed in the 56-pin

package. The USB developers who want to convert their FX2

56-pin application to a bus-powered system will directly benefit

from these additional signals. The two GPIOs will give these

developers the signals they need for the power control circuitry

of their bus-powered application without pushing them to a

high-pincount version of FX2LP. The CY7C68015A is only

available in the 56-pin QFN package

power-on reset.

2

3.18.3 I C Interface General-Purpose Access

2

The 8051 can control peripherals connected to the I C bus

using the I2CTL and I2DAT registers. FX2LP provides I C

master control only, it is never an I C slave.

2

3.19

Compatible with Previous Generation

EZ-USB FX2

The EZ-USB FX2LP is form/fit and with minor exceptions

functionally compatible with its predecessor, the EZ-USB FX2.

This makes for an easy transition for designers wanting to

upgrade their systems from the FX2 to the FX2LP. The pinout

and package selection are identical, and the vast majority of

firmware previously developed for the FX2 will function in the

FX2LP.

Table 3-10. CY7C68013A/14A and CY7C68015A/16A pin

differences

CY7C68013A/CY7C68014A CY7C68015A/CY7C68016A

IFCLK

PE0/T0OUT

PE1/T1OUT

CLKOUT

For designers migrating from the FX2 to the FX2LP a change

in the bill of material and review of the memory allocation (due

Note:

9. This EEPROM does not have address pins.

Document #: 38-08032 Rev. *G

Page 13 of 55

CY7C68013A/CY7C68014A

CY7C68015A/CY7C68016A

• PORTE or alternate GPIFADR[8] address signal and seven

additional 8051 signals

4.0

Pin Assignments

Figure 4-1 identifies all signals for the four package types. The

following pages illustrate the individual pin diagrams, plus a

combination diagram showing which of the full set of signals

are available in the 128-, 100-, and 56-pin packages.

• Three GPIF Control signals

• Four GPIF Ready signals

• Nine 8051 signals (two USARTs, three timer inputs,

INT4,and INT5#)

The signals on the left edge of the 56-pin package in

Figure 4-1 are common to all versions in the FX2LP family with

the noted differences between the CY7C68013A and the

CY7C68015A. Three modes are available in all package

versions: Port, GPIF master, and Slave FIFO. These modes

define the signals on the right edge of the diagram. The 8051

selects the interface mode using the IFCONFIG[1:0] register

bits. Port mode is the power-on default configuration.

• BKPT, RD#, WR#.

The 128-pin package adds the 8051 address and data buses

plus control signals. Note that two of the required signals, RD#

and WR#, are present in the 100-pin version. In the 100-pin

and 128-pin versions, an 8051 control bit can be set to pulse

the RD# and WR# pins when the 8051 reads from/writes to

PORTC.

The 100-pin package adds functionality to the 56-pin package

by adding these pins:

• PORTC or alternate GPIFADR[7:0] address signals

Document #: 38-08032 Rev. *G

Page 14 of 55

CY7C68013A/CY7C68014A

CY7C68015A/CY7C68016A

Port

GPIF Master

Slave FIFO

PD7

PD6

PD5

PD4

PD3

PD2

PD1

PD0

PB7

PB6

PB5

PB4

PB3

PB2

PB1

PB0

FD[15]

FD[14]

FD[13]

FD[12]

FD[11]

FD[10]

FD[9]

FD[8]

FD[7]

FD[6]

FD[5]

FD[4]

FD[3]

FD[2]

FD[1]

FD[0]

FD[15]

FD[14]

FD[13]

FD[12]

FD[11]

FD[10]

FD[9]

FD[8]

FD[7]

FD[6]

FD[5]

FD[4]

FD[3]

FD[2]

FD[1]

FD[0]

XTALIN

XTALOUT

RESET#

WAKEUP#

SCL

SDA

56

SLRD

SLWR

RDY0

RDY1

**PE0 replaces IFCLK

& PE1 replaces CLKOUT

on CY7C68015A

FLAGA

FLAGB

FLAGC

CTL0

CTL1

CTL2

**PE0/T0OUT

**PE1/T1OUT

INT0#/PA0

INT1#/PA1

PA2

WU2/PA3

PA4

INT0#/ PA0

INT1#/ PA1

SLOE

INT0#/PA0

INT1#/PA1

PA2

WU2/PA3

PA4

PA5

PA6

IFCLK

CLKOUT

WU2/PA3

FIFOADR0

FIFOADR1

PKTEND

DPLUS

DMINUS

PA5

PA6

PA7

PA7/FLAGD/SLCS#

PA7

CTL3

CTL4

CTL5

RDY2

RDY3

RDY4

RDY5

100

BKPT

PORTC7/GPIFADR7

PORTC6/GPIFADR6

PORTC5/GPIFADR5

PORTC4/GPIFADR4

PORTC3/GPIFADR3

PORTC2/GPIFADR2

PORTC1/GPIFADR1

PORTC0/GPIFADR0

RxD0

TxD0

RxD1

TxD1

INT4

INT5#

T2

PE7/GPIFADR8

PE6/T2EX

PE5/INT6

PE4/RxD1OUT

PE3/RxD0OUT

PE2/T2OUT

PE1/T1OUT

PE0/T0OUT

T1

T0

RD#

WR#

CS#

OE#

PSEN#

D7

D6

D5

D4

D3

D2

D1

D0

A15

A14

A13

A12

A11

A10

A9

128

A8

A7

A6

A5

A4

A3

EA

A2

A1

A0

Figure 4-1. Signals

** pinout for CY7C68015A/CY7C68016A only

Document #: 38-08032 Rev. *G

Page 15 of 55

CY7C68013A/CY7C68014A

CY7C68015A/CY7C68016A

1

102

CLKOUT

VCC

GND

PD0/FD8

*WAKEUP

VCC

RESET#

2

101

3

100

4

99

RDY0/*SLRD

RDY1/*SLWR

RDY2

RDY3

RDY4

RDY5

AVCC

XTALOUT

XTALIN

AGND

NC

5

98

CTL5

6

97

A3

A2

A1

A0

7

96

8

95

9

94

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

93

GND

92

PA7/*FLAGD/SLCS#

91

PA6/*PKTEND

PA5/FIFOADR1

PA4/FIFOADR0

90

89

88

NC

D7

D6

D5

87

86

AVCC

DPLUS

DMINUS

AGND

A11

A12

A13

A14

A15

VCC

GND

INT4

T0

T1

T2

85

CY7C68013A/CY7C68014A

128-pin TQFP

PA3/*WU2

PA2/*SLOE

PA1/INT1#

PA0/INT0#

84

83

82

81

VCC

GND

PC7/GPIFADR7

PC6/GPIFADR6

PC5/GPIFADR5

PC4/GPIFADR4

PC3/GPIFADR3

PC2/GPIFADR2

PC1/GPIFADR1

PC0/GPIFADR0

CTL2/*FLAGC

CTL1/*FLAGB

80

79

78

77

76

75

74

73

72

71

*IFCLK

RESERVED

BKPT

EA

SCL

SDA

70

69

CTL0/*FLAGA

68

VCC

CTL4

CTL3

GND

67

66

65

OE#

Figure 4-2. CY7C68013A/CY7C68014A 128-pin TQFP Pin Assignment

* denotes programmable polarity

Document #: 38-08032 Rev. *G

Page 16 of 55

CY7C68013A/CY7C68014A

CY7C68015A/CY7C68016A

1

80

VCC

PD0/FD8

2

79

GND

*WAKEUP

3

78

RDY0/*SLRD

RDY1/*SLWR

RDY2

RDY3

RDY4

RDY5

AVCC

XTALOUT

XTALIN

AGND

NC

VCC

RESET#

CTL5

GND

PA7/*FLAGD/SLCS#

4

77

5

76

6

75

7

74

8

73

PA6/*PKTEND

PA5/FIFOADR1

PA4/FIFOADR0

9

72

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

71

70

PA3/*WU2

PA2/*SLOE

PA1/INT1#

PA0/INT0#

69

68

67

NC

CY7C68013A/CY7C68014A

100-pin TQFP

66

VCC

GND

PC7/GPIFADR7

PC6/GPIFADR6

PC5/GPIFADR5

PC4/GPIFADR4

PC3/GPIFADR3

PC2/GPIFADR2

PC1/GPIFADR1

PC0/GPIFADR0

CTL2/*FLAGC

CTL1/*FLAGB

65

AVCC

DPLUS

DMINUS

AGND

VCC

GND

INT4

T0

T1

64

63

62

61

60

59

58

57

56

T2

55

*IFCLK

RESERVED

BKPT

SCL

54

CTL0/*FLAGA

53

VCC

CTL4

CTL3

52

51

SDA

Figure 4-3. CY7C68013A/CY7C68014A 100-pin TQFP Pin Assignment

* denotes programmable polarity

Document #: 38-08032 Rev. *G

Page 17 of 55

CY7C68013A/CY7C68014A

CY7C68015A/CY7C68016A

CY7C68013A/CY7C68014A

56-pin SSOP

1

2

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

PD5/FD13

PD4/FD12

PD3/FD11

PD2/FD10

PD1/FD9

PD0/FD8

*WAKEUP

VCC

PD6/FD14

PD7/FD15

GND

CLKOUT/T1OUT

VCC

3

4

5

6

7

GND

8

RDY0/*SLRD

RDY1/*SLWR

AVCC

XTALOUT

XTALIN

AGND

AVCC

DPLUS

DMINUS

AGND

VCC

RESET#

9

GND

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

PA7/*FLAGD/SLCS#

PA6/PKTEND

PA5/FIFOADR1

PA4/FIFOADR0

PA3/*WU2

PA2/*SLOE

PA1/INT1#

PA0/INT0#

VCC

GND

CTL2/*FLAGC

CTL1/*FLAGB

CTL0/*FLAGA

GND

*IFCLK/T0OUT

RESERVED

SCL

SDA

VCC

PB0/FD0

PB1/FD1

PB2/FD2

PB3/FD3

VCC

GND

PB7/FD7

PB6/FD6

PB5/FD5

PB4/FD4

Figure 4-4. CY7C68013A/CY7C68014A 56-pin SSOP Pin Assignment

* denotes programmable polarity

Document #: 38-08032 Rev. *G

Page 18 of 55

CY7C68013A/CY7C68014A

CY7C68015A/CY7C68016A

RESET#

42

RDY0/*SLRD

RDY1/*SLWR

AVCC

1

2

GND

41

PA7/*FLAGD/SLCS#

40

3

PA6/*PKTEND

39

XTALOUT

XTALIN

4

PA5/FIFOADR1

38

5

PA4/FIFOADR0

AGND

6

CY7C68013A/CY7C68014A

37

36

35

34

33

32

31

30

29

&

PA3/*WU2

PA2/*SLOE

PA1/INT1#

PA0/INT0#

VCC

AVCC

7

CY7C68015A/CY7C68016A

DPLUS

8

DMINUS

9

56-pin QFN

AGND

10

11

12

13

14

VCC

CTL2/*FLAGC

CTL1/*FLAGB

CTL0/*FLAGA

GND

*IFCLK/**PE0/T0OUT

RESERVED

Figure 4-5. CY7C68013A/14A/15A/16A 56-pin QFN Pin Assignment

* denotes programmable polarity

** denotes CY7C68015A/CY7C68016A pinout

Document #: 38-08032 Rev. *G

Page 19 of 55

CY7C68013A/CY7C68014A

CY7C68015A/CY7C68016A

4.1

CY7C68013A/15A Pin Descriptions

[10]

Table 4-1. FX2LP Pin Descriptions

128 100 56 56

TQFP TQFP SSOP QFN

Name

AVCC

Type

Default

Description

10

9

10

3

7

6

Power

N/A

Analog VCC. Connect this pin to 3.3V power source.

This signal provides power to the analog section of the

chip.

17

16

14

AVCC

AGND

Power

N/A

Analog VCC. Connect this pin to 3.3V power source.

This signal provides power to the analog section of the

chip.

13

20

12

19

13

17

Ground

N/A

Analog Ground. Connecttoground with asshort apath

as possible.

10 AGND

Analog Ground. Connecttoground with asshort apath

as possible.

19

18

17

16

15

9

8

DMINUS

I/O/Z

Z

L

Z

H

USB D– Signal. Connect to the USB D– signal.

USB D+ Signal. Connect to the USB D+ signal.

DPLUS

A0

94

Output

I/O/Z

8051 Address Bus. This bus is driven at all times.

When the 8051 is addressing internal RAM it reflects

the internal address.

95

A1

96

A2

97

A3

117

118

119

120

126

127

128

21

A4

A5

A6

A7

A8

A9

A10

A11

A12

A13

A14

A15

D0

22

23

24

25

59

8051 Data Bus. This bidirectional bus is high-

impedance when inactive, input for bus reads, and

output for bus writes. The data bus is used for external

8051 program and data memory. The data bus is active

only for external bus accesses, and is driven LOW in

suspend.

60

D1

I/O/Z

61

D2

I/O/Z

62

D3

I/O/Z

63

D4

I/O/Z

86

D5

I/O/Z

87

D6

I/O/Z

88

D7

I/O/Z

39

PSEN#

Output

Program Store Enable. This active-LOW signal

indicates an 8051 code fetch from external memory. It

is active for program memory fetches from

0x4000–0xFFFF when the EA pin is LOW, or from

0x0000–0xFFFF when the EA pin is HIGH.

Note:

10. Unused inputs should not be left floating. Tie either HIGH or LOW as appropriate. Outputs should only be pulled up or down to ensure signals at power-up and

in standby. Note also that no pins should be driven while the device is powered down.

Document #: 38-08032 Rev. *G

Page 20 of 55

CY7C68013A/CY7C68014A

CY7C68015A/CY7C68016A

[10]

Table 4-1. FX2LP Pin Descriptions (continued)

128 100 56 56

TQFP TQFP SSOP QFN

Name

Type

Default

Description

34

28

BKPT

Output

L

Breakpoint. This pin goes active (HIGH)when the 8051

address bus matches the BPADDRH/L registers and

breakpoints are enabled in the BREAKPT register

(BPEN = 1). If the BPPULSE bit in the BREAKPT

register is HIGH, this signal pulses HIGH for eight 12-

/24-/48-MHz clocks. If the BPPULSE bit is LOW, the

signal remains HIGH until the 8051 clears the BREAK

bit (by writing 1 to it) in the BREAKPT register.

99

35

77

11

49

12

42 RESET#

EA

Input

N/A

Active LOW Reset. Resets the entire chip. See section

3.9 ”Reset and Wakeup” on page 6 for more details.

External Access. This pin determines where the 8051

fetches code between addresses 0x0000 and 0x3FFF.

If EA = 0 the 8051 fetches this code from its internal

RAM. IF EA = 1 the 8051 fetches this code from external

memory.

12

5

4

XTALIN

Input

N/A

Crystal Input. Connect this signal to a 24-MHz parallel-

resonant, fundamental mode crystal and load capacitor

to GND.

It is also correct to drive XTALIN with an external

24-MHz square wave derived from another clock

source. When driving from an external source, the

driving signal should be a 3.3V square wave.

11

1

10

11

5

XTALOUT

Output

O/Z

Crystal Output. Connect this signal to a 24-MHz

parallel-resonant, fundamental mode crystal and load

capacitor to GND.

If an external clock is used to drive XTALIN, leave this

pin open.

100

54 CLKOUT on

CY7C68013A

12 MHz CLKOUT: 12-, 24- or 48-MHz clock, phase locked to the

24-MHz input clock. The 8051 defaults to 12-MHz

operation. The 8051 may three-state this output by

setting CPUCS.1 = 1.

------------------

PE1 or

T1OUT on

CY7C68015A

----------- ---------- ------------------------------------------------------------------------

I/O/Z

I

Multiplexed pin whose function is selected by the

(PE1) PORTECFG.0 bit.

PE1 is a bidirectional I/O port pin.

T1OUT is an active-HIGH signal from 8051 Timer-

counter1. T1OUT outputs a high level for one CLKOUT

clock cycle when Timer1 overflows. If Timer1 is

operated in Mode 3 (two separate timer/counters),

T1OUT is active when the low byte timer/counter

overflows.

Port A

82

67

68

40

41

33 PA0 or

INT0#

I/O/Z

I

Multiplexed pin whose function is selected by

(PA0) PORTACFG.0

PA0 is a bidirectional IO port pin.

INT0# is the active-LOW 8051 INT0 interrupt input

signal, which is either edge triggered (IT0 = 1) or level

triggered (IT0 = 0).

83

34 PA1 or

INT1#

I

Multiplexed pin whose function is selected by:

(PA1) PORTACFG.1

PA1 is a bidirectional IO port pin.

INT1# is the active-LOW 8051 INT1 interrupt input

signal, which is either edge triggered (IT1 = 1) or level

triggered (IT1 = 0).

Document #: 38-08032 Rev. *G

Page 21 of 55

CY7C68013A/CY7C68014A

CY7C68015A/CY7C68016A

[10]

Table 4-1. FX2LP Pin Descriptions (continued)

128 100 56 56

TQFP TQFP SSOP QFN

Name

Type

Default

Description

84

69

42

35 PA2 or

I/O/Z

I

Multiplexed pin whose function is selected by two bits:

SLOE or

(PA2) IFCONFIG[1:0].

PA2 is a bidirectional IO port pin.

SLOE is an input-only output enable with program-

mable polarity (FIFOPINPOLAR.4) for the slave FIFOs

connected to FD[7..0] or FD[15..0].

85

70

43

36 PA3 or

WU2

I/O/Z

I

Multiplexed pin whose function is selected by:

(PA3) WAKEUP.7 and OEA.3

PA3 is a bidirectional I/O port pin.

WU2 is an alternate source for USB Wakeup, enabled

by WU2EN bit (WAKEUP.1) and polarity set by

WU2POL (WAKEUP.4). If the 8051 is in suspend and

WU2EN = 1, a transition on this pin starts up the oscil-

lator and interrupts the 8051 to allow it to exit the

suspend mode. Asserting this pin inhibits the chip from

suspending, if WU2EN=1.

89

90

91

71

72

73

44

45

46

37 PA4 or

FIFOADR0

I/O/Z

I

Multiplexed pin whose function is selected by:

(PA4) IFCONFIG[1..0].

PA4 is a bidirectional I/O port pin.

FIFOADR0 is an input-only address select for the slave

FIFOs connected to FD[7..0] or FD[15..0].

38 PA5 or

FIFOADR1

I

Multiplexed pin whose function is selected by:

(PA5) IFCONFIG[1..0].

PA5 is a bidirectional I/O port pin.

FIFOADR1 is an input-only address select for the slave

FIFOs connected to FD[7..0] or FD[15..0].

39 PA6 or

PKTEND

I

Multiplexed pin whose function is selected by the

(PA6) IFCONFIG[1:0] bits.

PA6 is a bidirectional I/O port pin.

PKTEND is an input used to commit the FIFO packet

data to the endpoint and whose polarity is program-

mable via FIFOPINPOLAR.5.

92

74

47

40 PA7 or

FLAGD or

SLCS#

I/O/Z

I

Multiplexed pin whose function is selected by the

(PA7) IFCONFIG[1:0] and PORTACFG.7 bits.

PA7 is a bidirectional I/O port pin.

FLAGD is a programmable slave-FIFO output status

flag signal.

SLCS# gates all other slave FIFO enable/strobes

Port B

44

34

35

36

37

25

26

27

28

18 PB0 or

FD[0]

I/O/Z

I

Multiplexed pin whose function is selected by the

(PB0) following bits: IFCONFIG[1..0].

PB0 is a bidirectional I/O port pin.

FD[0] is the bidirectional FIFO/GPIF data bus.

45

46

47

19 PB1 or

FD[1]

I

Multiplexed pin whose function is selected by the

(PB1) following bits: IFCONFIG[1..0].

PB1 is a bidirectional I/O port pin.

FD[1] is the bidirectional FIFO/GPIF data bus.

20 PB2 or

FD[2]

I

Multiplexed pin whose function is selected by the

(PB2) following bits: IFCONFIG[1..0].

PB2 is a bidirectional I/O port pin.

FD[2] is the bidirectional FIFO/GPIF data bus.

21 PB3 or

FD[3]

I

Multiplexed pin whose function is selected by the

(PB3) following bits: IFCONFIG[1..0].

PB3 is a bidirectional I/O port pin.

FD[3] is the bidirectional FIFO/GPIF data bus.

Document #: 38-08032 Rev. *G

Page 22 of 55

CY7C68013A/CY7C68014A

CY7C68015A/CY7C68016A

[10]

Table 4-1. FX2LP Pin Descriptions (continued)

128 100 56 56

TQFP TQFP SSOP QFN

Name

Type

Default

Description

54

55

56

57

44

45

46

47

29

30

31

32

22 PB4 or

I/O/Z

I

Multiplexed pin whose function is selected by the

FD[4]

(PB4) following bits: IFCONFIG[1..0].

PB4 is a bidirectional I/O port pin.

FD[4] is the bidirectional FIFO/GPIF data bus.

23 PB5 or

FD[5]

I/O/Z

I

Multiplexed pin whose function is selected by the

(PB5) following bits: IFCONFIG[1..0].

PB5 is a bidirectional I/O port pin.

FD[5] is the bidirectional FIFO/GPIF data bus.

24 PB6 or

FD[6]

I

Multiplexed pin whose function is selected by the

(PB6) following bits: IFCONFIG[1..0].

PB6 is a bidirectional I/O port pin.

FD[6] is the bidirectional FIFO/GPIF data bus.

25 PB7 or

FD[7]

I

Multiplexed pin whose function is selected by the

(PB7) following bits: IFCONFIG[1..0].

PB7 is a bidirectional I/O port pin.

FD[7] is the bidirectional FIFO/GPIF data bus.

PORT C

72

57

58

59

60

61

62

63

64

PC0 or

GPIFADR0

I/O/Z

I

Multiplexed pin whose function is selected by

(PC0) PORTCCFG.0

PC0 is a bidirectional I/O port pin.

GPIFADR0 is a GPIF address output pin.

73

74

75

76

77

78

79

PC1 or

GPIFADR1

I

Multiplexed pin whose function is selected by

(PC1) PORTCCFG.1

PC1 is a bidirectional I/O port pin.

GPIFADR1 is a GPIF address output pin.

PC2 or

GPIFADR2

I

Multiplexed pin whose function is selected by

(PC2) PORTCCFG.2

PC2 is a bidirectional I/O port pin.

GPIFADR2 is a GPIF address output pin.

PC3 or

GPIFADR3

I

Multiplexed pin whose function is selected by

(PC3) PORTCCFG.3

PC3 is a bidirectional I/O port pin.

GPIFADR3 is a GPIF address output pin.

PC4 or

GPIFADR4

I

Multiplexed pin whose function is selected by

(PC4) PORTCCFG.4

PC4 is a bidirectional I/O port pin.

GPIFADR4 is a GPIF address output pin.

PC5 or

GPIFADR5

I

Multiplexed pin whose function is selected by

(PC5) PORTCCFG.5

PC5 is a bidirectional I/O port pin.

GPIFADR5 is a GPIF address output pin.

PC6 or

GPIFADR6

I

Multiplexed pin whose function is selected by

(PC6) PORTCCFG.6

PC6 is a bidirectional I/O port pin.

GPIFADR6 is a GPIF address output pin.

PC7 or

I

Multiplexed pin whose function is selected by

GPIFADR7

(PC7) PORTCCFG.7

PC7 is a bidirectional I/O port pin.

GPIFADR7 is a GPIF address output pin.

PORT D

102

80

52

45 PD0 or

FD[8]

I/O/Z

I

Multiplexed pin whose function is selected by the

(PD0) IFCONFIG[1..0] and EPxFIFOCFG.0 (wordwide) bits.

FD[8] is the bidirectional FIFO/GPIF data bus.

Document #: 38-08032 Rev. *G

Page 23 of 55

CY7C68013A/CY7C68014A

CY7C68015A/CY7C68016A

[10]

Table 4-1. FX2LP Pin Descriptions (continued)

128 100 56 56

TQFP TQFP SSOP QFN

Name

Type

Default

Description

103

104

105

121

122

123

124

81

82

83

95

96

97

98

53

54

55

56

1

46 PD1 or

I/O/Z

I

Multiplexed pin whose function is selected by the

FD[9]

(PD1) IFCONFIG[1..0] and EPxFIFOCFG.0 (wordwide) bits.

FD[9] is the bidirectional FIFO/GPIF data bus.

47 PD2 or

FD[10]

I/O/Z

I

Multiplexed pin whose function is selected by the

(PD2) IFCONFIG[1..0] and EPxFIFOCFG.0 (wordwide) bits.

FD[10] is the bidirectional FIFO/GPIF data bus.

48 PD3 or

FD[11]

I

Multiplexed pin whose function is selected by the

(PD3) IFCONFIG[1..0] and EPxFIFOCFG.0 (wordwide) bits.

FD[11] is the bidirectional FIFO/GPIF data bus.

49 PD4 or

FD[12]

I

Multiplexed pin whose function is selected by the

(PD4) IFCONFIG[1..0] and EPxFIFOCFG.0 (wordwide) bits.

FD[12] is the bidirectional FIFO/GPIF data bus.

50 PD5 or

FD[13]

I

Multiplexed pin whose function is selected by the

(PD5) IFCONFIG[1..0] and EPxFIFOCFG.0 (wordwide) bits.

FD[13] is the bidirectional FIFO/GPIF data bus.

2

51 PD6 or

FD[14]

I

Multiplexed pin whose function is selected by the

(PD6) IFCONFIG[1..0] and EPxFIFOCFG.0 (wordwide) bits.

FD[14] is the bidirectional FIFO/GPIF data bus.

3

52 PD7 or

FD[15]

I

Multiplexed pin whose function is selected by the

(PD7) IFCONFIG[1..0] and EPxFIFOCFG.0 (wordwide) bits.

FD[15] is the bidirectional FIFO/GPIF data bus.

Port E

108

86

PE0 or

T0OUT

I/O/Z

I

Multiplexed pin whose function is selected by the

(PE0) PORTECFG.0 bit.

PE0 is a bidirectional I/O port pin.

T0OUT is an active-HIGH signal from 8051 Timer-

counter0. T0OUT outputs a high level for one CLKOUT

clock cycle when Timer0 overflows. If Timer0 is

operated in Mode 3 (two separate timer/counters),

T0OUT is active when the low byte timer/counter

overflows.

109

87

PE1 or

T1OUT

I/O/Z

I

Multiplexed pin whose function is selected by the

(PE1) PORTECFG.1 bit.

PE1 is a bidirectional I/O port pin.

T1OUT is an active-HIGH signal from 8051 Timer-

counter1. T1OUT outputs a high level for one CLKOUT

clock cycle when Timer1 overflows. If Timer1 is

operated in Mode 3 (two separate timer/counters),

T1OUT is active when the low byte timer/counter

overflows.

110

111

88

89

PE2 or

T2OUT

I/O/Z

I

Multiplexed pin whose function is selected by the

(PE2) PORTECFG.2 bit.

PE2 is a bidirectional I/O port pin.

T2OUT is the active-HIGH output signal from 8051

Timer2. T2OUT is active (HIGH) for one clock cycle

when Timer/Counter 2 overflows.

PE3 or

RXD0OUT

I

Multiplexed pin whose function is selected by the

(PE3) PORTECFG.3 bit.

PE3 is a bidirectional I/O port pin.

RXD0OUT is an active-HIGH signal from 8051 UART0.

If RXD0OUT is selected and UART0 is in Mode 0, this

pin provides the output data for UART0 only when it is

in sync mode. Otherwise it is a 1.

Document #: 38-08032 Rev. *G

Page 24 of 55

CY7C68013A/CY7C68014A

CY7C68015A/CY7C68016A

[10]

Table 4-1. FX2LP Pin Descriptions (continued)

128 100 56 56

TQFP TQFP SSOP QFN

Name

Type

Default

Description

112

90

PE4 or

I/O/Z

I

Multiplexed pin whose function is selected by the

RXD1OUT

(PE4) PORTECFG.4 bit.

PE4 is a bidirectional I/O port pin.

RXD1OUT is an active-HIGH output from 8051 UART1.

When RXD1OUT is selected and UART1 is in Mode 0,

this pin provides the output data for UART1 only when

it is in sync mode. In Modes 1, 2, and 3, this pin is HIGH.

113

114

91

92

PE5 or

INT6

I/O/Z

I

Multiplexed pin whose function is selected by the

(PE5) PORTECFG.5 bit.

PE5 is a bidirectional I/O port pin.

INT6 is the 8051 INT6 interruptrequestinput signal. The

INT6 pin is edge-sensitive, active HIGH.

PE6 or

T2EX

I

Multiplexed pin whose function is selected by the

(PE6) PORTECFG.6 bit.

PE6 is a bidirectional I/O port pin.

T2EX is an active-HIGH input signal to the 8051 Timer2.

T2EX reloads timer 2 on its falling edge. T2EX is active

only if the EXEN2 bit is set in T2CON.

115

4

93

3

PE7 or

GPIFADR8

I/O/Z

Input

I

Multiplexed pin whose function is selected by the

(PE7) PORTECFG.7 bit.

PE7 is a bidirectional I/O port pin.

GPIFADR8 is a GPIF address output pin.

8

9

1

2

RDY0 or

SLRD

N/A

Multiplexed pin whose function is selected by the

following bits:

IFCONFIG[1..0].

RDY0 is a GPIF input signal.

SLRD is the input-only read strobe with programmable

polarity (FIFOPINPOLAR.3) for the slave FIFOs

connected to FD[7..0] or FD[15..0].

5

4

RDY1 or

SLWR

Input

N/A

Multiplexed pin whose function is selected by the

following bits:

IFCONFIG[1..0].

RDY1 is a GPIF input signal.

SLWR is the input-only write strobe with programmable

polarity (FIFOPINPOLAR.2) for the slave FIFOs

connected to FD[7..0] or FD[15..0].

6

7

5

6

RDY2

RDY3

RDY4

RDY5

Input

O/Z

N/A

H

RDY2 is a GPIF input signal.

RDY3 is a GPIF input signal.

RDY4 is a GPIF input signal.

RDY5 is a GPIF input signal.

8

7

9

8

69

54

36

29 CTL0 or

FLAGA

Multiplexed pin whose function is selected by the

following bits:

IFCONFIG[1..0].

CTL0 is a GPIF control output.

FLAGA is a programmable slave-FIFO output status

flag signal.

Defaults to programmable for the FIFO selected by the

FIFOADR[1:0] pins.

Document #: 38-08032 Rev. *G

Page 25 of 55

CY7C68013A/CY7C68014A

CY7C68015A/CY7C68016A

[10]

Table 4-1. FX2LP Pin Descriptions (continued)

128 100 56 56

TQFP TQFP SSOP QFN

Name

Type

Default

Description

70

55

37

30 CTL1 or

O/Z

H

Multiplexed pin whose function is selected by the

following bits:

FLAGB

IFCONFIG[1..0].

CTL1 is a GPIF control output.

FLAGB is a programmable slave-FIFO output status

flag signal.

Defaults to FULL for the FIFO selected by the

FIFOADR[1:0] pins.

71

56

38

31 CTL2 or

FLAGC

O/Z

H

Multiplexed pin whose function is selected by the

following bits:

IFCONFIG[1..0].

CTL2 is a GPIF control output.

FLAGC is a programmable slave-FIFO output status

flag signal.

Defaults to EMPTY for the FIFO selected by the

FIFOADR[1:0] pins.

66

67

98

32

51

52

76

26

CTL3

CTL4

O/Z

H

Z

CTL3 is a GPIF control output.

CTL4 is a GPIF control output.

CTL5 is a GPIF control output.

Output

I/O/Z

CTL5

20

13 IFCLK on

Interface Clock, used for synchronously clocking data

into or out of the slave FIFOs. IFCLK also serves as a

timing reference for all slave FIFO control signals and

GPIF. When internal clocking is used (IFCONFIG.7 = 1)

the IFCLK pin can be configured to output 30/48 MHz

by bits IFCONFIG.5 and IFCONFIG.6. IFCLK may be

inverted, whether internally or externally sourced, by

setting the bit IFCONFIG.4 =1.

CY7C68013A

------------------

PE0 or T0OUT

on

----------- ---------- -----------------------------------------------------------------------

I/O/Z

I

Multiplexed pin whose function is selected by the

(PE0) PORTECFG.0 bit.

PE0 is a bidirectional I/O port pin.

CY7C68015A

T0OUT is an active-HIGH signal from 8051 Timer-

counter0. T0OUT outputs a high level for one CLKOUT

clock cycle when Timer0 overflows. If Timer0 is

operated in Mode 3 (two separate timer/counters),

T0OUT is active when the low byte timer/counter

overflows.

28

106

31

22

84

25

INT4

INT5#

T2

Input

N/A

INT4 is the 8051 INT4 interruptrequestinput signal. The

INT4 pin is edge-sensitive, active HIGH.

INT5# is the 8051 INT5 interrupt request input signal.

The INT5 pin is edge-sensitive, active LOW.

T2 is the active-HIGH T2 input signal to 8051 Timer2,

which provides the input to Timer2 when C/T2 = 1.

When C/T2 = 0, Timer2 does not use this pin.

30

29

24

23

T1

T0

Input

N/A

T1 is the active-HIGH T1 signal for 8051 Timer1, which

provides the input to Timer1 when C/T1 is 1. When C/T1

is 0, Timer1 does not use this bit.

T0 is the active-HIGH T0 signal for 8051 Timer0, which

provides the input to Timer0 when C/T0 is 1. When C/T0

is 0, Timer0 does not use this bit.

53

52

43

42

RXD1

TXD1

Input

N/A

H

RXD1is an active-HIGH input signal for 8051 UART1,

which provides data to the UART in all modes.

Output

TXD1is an active-HIGH output pin from 8051 UART1,

which provides the output clock in sync mode, and the

output data in async mode.

Document #: 38-08032 Rev. *G

Page 26 of 55

CY7C68013A/CY7C68014A

CY7C68015A/CY7C68016A

[10]

Table 4-1. FX2LP Pin Descriptions (continued)

128 100 56 56

TQFP TQFP SSOP QFN

Name

Type

Default

Description

51

50

41

40

RXD0

Input

N/A

RXD0 is the active-HIGH RXD0 input to 8051 UART0,

which provides data to the UART in all modes.

TXD0

Output

H

TXD0 is the active-HIGH TXD0 output from 8051

UART0, which provides the output clock in sync mode,

and the output data in async mode.

42

41

CS#

Output

H

CS# is the active-LOW chip select for external memory.

32

31

WR#

WR# is the active-LOW write strobe output for external

memory.

40

38

RD#

OE#

Output

H

RD# is the active-LOW read strobe output for external

memory.

OE# is the active-LOW output enable for external

memory.

33

27

79

21

51

14 Reserved

44 WAKEUP

Input

N/A

Reserved. Connect to ground.

101

USB Wakeup. If the 8051 is in suspend, asserting this

pin starts up the oscillator and interrupts the 8051 to

allow it to exit the suspend mode. Holding WAKEUP



asserted inhibits the EZ-USB chip from suspending.

This pin has programmable polarity (WAKEUP.4).

2

36

37

29

30

22

23

15 SCL

16 SDA

OD

Z

Clock for the I C interface. Connect to VCC with a 2.2K

2

resistor, even if no I C peripheral is attached.

2

Data for I C-compatible interface. Connect to VCC

with a 2.2K resistor, even if no I C-compatible

2

peripheral is attached.

2

26

1

6

55 VCC

11 VCC

17 VCC

VCC

Power

N/A

VCC. Connect to 3.3V power source.

20

33

38

49

53

66

78

85

18

24

43

48

64

34

27 VCC

VCC

68

81

39

50

32 VCC

43 VCC

VCC

100

107

3

27

2

7

56 GND

12 GND

GND

Ground

N/A

Ground.

21

39

48

50

65

75

94

99

19

49

58

33

35

26 GND

28 GND

GND

65

80

93

48

4

41 GND

GND

116

125

53 GND

14

15

16

13

14

15

NC

N/A

No Connect. This pin must be left open.

Document #: 38-08032 Rev. *G

Page 27 of 55

CY7C68013A/CY7C68014A

CY7C68015A/CY7C68016A

5.0

Register Summary

FX2LP register bit definitions are described in the FX2LP TRM

in greater detail.

Table 5-1. FX2LP Register Summary

Hex Size Name

Description

b7

b6

b5

b4

b3

b2

b1

b0

Default

Access

GPIF Waveform Memories

E400 128 WAVEDATA

GPIF Waveform

Descriptor 0, 1, 2, 3 data

D7

D6

D5

D4

D3

D2

D1

D0

xxxxxxxx RW

E480 128 reserved

GENERAL CONFIGURATION

E600

E601

1

CPUCS

CPU Control & Status

0

PORTCSTB CLKSPD1 CLKSPD0 CLKINV

CLKOE

IFCFG1

8051RES

IFCFG0

00000010 rrbbbbbr

10000000 RW

IFCONFIG

Interface Configuration

(Ports, GPIF, slave FIFOs)

IFCLKSRC 3048MHZ

IFCLKOE

FLAGB1

FLAGD1

0

IFCLKPOL ASYNC

GSTATE

FLAGA2

FLAGC2

EP2

[11]

E602

E603

E604

1

PINFLAGSAB

Slave FIFO FLAGA and FLAGB3

FLAGB Pin Configuration

FLAGB2

FLAGD2

0

FLAGB0

FLAGD0

0

FLAGA3

FLAGC3

EP3

FLAGA1

FLAGC1

EP1

FLAGA0

FLAGC0

EP0

00000000 RW

PINFLAGSCD

Slave FIFO FLAGC and FLAGD3

FLAGD Pin Configuration

[11]

FIFORESET

Restore FIFOS to default NAKALL

state

xxxxxxxx

W

E605

E606

E607

E608

1

BREAKPT

BPADDRH

BPADDRL

UART230

Breakpoint Control

0

BREAK

A11

A3

BPPULSE BPEN

0

00000000 rrrrbbbr

xxxxxxxx RW

Breakpoint Address H

Breakpoint Address L

A15

A7

0

A14

A6

0

A13

A5

0

A12

A4

0

A10

A2

0

A9

A1

A8

A0

230 Kbaud internally

generated ref. clock

0

230UART1 230UART0 00000000 rrrrrrbb

[11]

E609

1

FIFOPINPOLAR

Slave FIFO Interface pins 0

polarity

0

PKTEND

SLOE

rv4

SLRD

rv3

SLWR

rv2

EF

FF

00000000 rrbbbbbb

E60A 1

E60B 1

REVID

Chip Revision

rv7

rv6

0

rv5

0

rv1

rv0

RevA

00000001

R

[11]

REVCTL

Chip Revision Control

0

dyn_out

enh_pkt

00000000 rrrrrrbb

UDMA

E60C 1

3

GPIFHOLDAMOUNT MSTB Hold Time

(for UDMA)

0

HOLDTIME1 HOLDTIME0 00000000 rrrrrrbb

reserved

ENDPOINT CONFIGURATION

E610

E611

1

EP1OUTCFG

Endpoint 1-OUT

Configuration

VALID

0

TYPE1

TYPE0

0

10100000 brbbrrrr

EP1INCFG

Endpoint 1-IN

Configuration

E612

E613

E614

E615

1

2

1

EP2CFG

EP4CFG

EP6CFG

EP8CFG

reserved

Endpoint 2 Configuration VALID

Endpoint 4 Configuration VALID

Endpoint 6 Configuration VALID

Endpoint 8 Configuration VALID

DIR

TYPE1

TYPE0

SIZE

0

BUF1

0

BUF0

0

10100010 bbbbbrbb

10100000 bbbbrrrr

11100010 bbbbbrbb

11100000 bbbbrrrr

SIZE

0

BUF1

0

BUF0

0

[11]

E618

E619

EP2FIFOCFG

Endpoint 2 / slave FIFO

configuration

0

INFM1

OEP1

AUTOOUT AUTOIN

ZEROLENIN 0

WORDWIDE 00000101 rbbbbbrb

1

EP4FIFOCFG

EP6FIFOCFG

EP8FIFOCFG

reserved

Endpoint 4 / slave FIFO

configuration

E61A 1

E61B 1

E61C 4

Endpoint 6 / slave FIFO

configuration

Endpoint 8 / slave FIFO

configuration

[11

E620

E621

E622

E623

E624

E625

E626

E627

1

EP2AUTOINLENH Endpoint 2 AUTOIN

0

PL10

PL2

0

PL9

PL8

PL0

PL8

PL0

PL8

PL0

PL8

PL0

00000010 rrrrrbbb

00000000 RW

Packet Length H

[11]

EP2AUTOINLENL

Endpoint 2 AUTOIN

Packet Length L

PL7

0

PL6

0

PL5

0

PL4

0

PL3

0

PL1

PL9

PL1

PL9

PL1

PL9

PL1

[11

EP4AUTOINLENH Endpoint 4 AUTOIN

00000010 rrrrrrbb

00000000 RW

]

Packet Length H

[11]

EP4AUTOINLENL

Endpoint 4 AUTOIN

Packet Length L

PL7

0

PL6

0

PL5

0

PL4

0

PL3

0

PL2

PL10

PL2

0

[11

EP6AUTOINLENH Endpoint 6 AUTOIN

00000010 rrrrrbbb

00000000 RW

]

Packet Length H

[11]

EP6AUTOINLENL

Endpoint 6 AUTOIN

Packet Length L

PL7

0

PL6

0

PL5

0

PL4

0

PL3

0

[11

EP8AUTOINLENH Endpoint 8 AUTOIN

00000010 rrrrrrbb

00000000 RW

]

Packet Length H

[11]

EP8AUTOINLENL

Endpoint 8 AUTOIN

Packet Length L

PL7

PL6

PL5

PL4

PL3

PL2

E628

E629

1

ECCCFG

ECCRESET

ECC1B0

ECC1B1

ECC1B2

ECC2B0

ECC Configuration

ECC Reset

0

ECCM

x

00000000 rrrrrrrb

x

00000000

W

R

E62A 1

E62B 1

E62C 1

E62D 1

Note:

ECC1 Byte 0 Address

ECC1 Byte 1 Address

ECC1 Byte 2 Address

ECC2 Byte 0 Address

LINE15

LINE7

COL5

LINE15

LINE14

LINE6

COL4

LINE14

LINE13

LINE5

COL3

LINE13

LINE12

LINE4

COL2

LINE12

LINE11

LINE3

COL1

LINE11

LINE10

LINE2

COL0

LINE10

LINE9

LINE1

LINE17

LINE9

LINE8

LINE0

LINE16

LINE8

11. Read and writes to these registers may require synchronization delay, see Technical Reference Manual for “Synchronization Delay.”

Document #: 38-08032 Rev. *G

Page 28 of 55

CY7C68013A/CY7C68014A

CY7C68015A/CY7C68016A

Table 5-1. FX2LP Register Summary (continued)

Hex Size Name

Description

b7

b6

b5

b4

b3

b2

b1

b0

Default

Access

E62E 1

E62F 1

ECC2B1

ECC2 Byte 1 Address

ECC2 Byte 2 Address

LINE7

COL5

LINE6

COL4

PKTSTAT

LINE5

COL3

LINE4

COL2

LINE3

COL1

LINE2

COL0

0

LINE1

0

LINE0

0

00000000

R

ECC2B2

[11]

E630

H.S.

1

EP2FIFOPFH

Endpoint 2 / slave FIFO DECIS

Programmable Flag H

IN:PKTS[2] IN:PKTS[1] IN:PKTS[0]

OUT:PFC12 OUT:PFC11 OUT:PFC10

PFC9

PFC8

10001000 bbbbbrbb

E630

F.S.

EP2FIFOPFH

Endpoint 2 / slave FIFO DECIS

Programmable Flag H

PKTSTAT

PFC6

OUT:PFC12 OUT:PFC11 OUT:PFC10 0

PFC9

PFC1

0

IN:PKTS[2] 10001000 bbbbbrbb

OUT:PFC8

[11]

E631

H.S.

EP2FIFOPFL

Endpoint 2 / slave FIFO PFC7

Programmable Flag L

PFC5

PFC4

PFC3

PFC2

PFC0

PFC8

PFC0

PFC8

00000000 RW

E631

F.S

Endpoint 2 / slave FIFO IN:PKTS[1] IN:PKTS[0] PFC5

Programmable Flag L OUT:PFC7 OUT:PFC6

00000000 RW

E632

H.S.

EP4FIFOPFH

Endpoint 4 / slave FIFO DECIS

Programmable Flag H

PKTSTAT

PFC6

0

IN: PKTS[1] IN: PKTS[0] 0

OUT:PFC10 OUT:PFC9

10001000 bbrbbrrb

00000000 RW

[11]

E632

F.S

EP4FIFOPFH

Endpoint 4 / slave FIFO DECIS

Programmable Flag H

0

OUT:PFC10 OUT:PFC9

0

[11]

E633

H.S.

EP4FIFOPFL

Endpoint 4 / slave FIFO PFC7

Programmable Flag L

PFC5

PFC4

PFC3

PFC2

0

PFC1

PFC9

PFC1

0

E633

F.S

Endpoint 4 / slave FIFO IN: PKTS[1] IN: PKTS[0] PFC5

Programmable Flag L OUT:PFC7 OUT:PFC6

00000000 RW

E634

H.S.

EP6FIFOPFH

Endpoint 6 / slave FIFO DECIS

Programmable Flag H

PKTSTAT

PFC6

IN:PKTS[2] IN:PKTS[1] IN:PKTS[0]

OUT:PFC12 OUT:PFC11 OUT:PFC10

00001000 bbbbbrbb

[11]

E634

F.S

EP6FIFOPFH

Endpoint 6 / slave FIFO DECIS

Programmable Flag H

OUT:PFC12 OUT:PFC11 OUT:PFC10 0

IN:PKTS[2] 00001000 bbbbbrbb

OUT:PFC8

[11]

E635

H.S.

EP6FIFOPFL

Endpoint 6 / slave FIFO PFC7

Programmable Flag L

PFC5

PFC4

PFC3

PFC2

PFC0

PFC8

PFC0

00000000 RW

E635

F.S

Endpoint 6 / slave FIFO IN:PKTS[1] IN:PKTS[0] PFC5

Programmable Flag L OUT:PFC7 OUT:PFC6

00000000 RW

E636

H.S.

EP8FIFOPFH

Endpoint 8 / slave FIFO DECIS

Programmable Flag H

PKTSTAT

PFC6

0

IN: PKTS[1] IN: PKTS[0] 0

OUT:PFC10 OUT:PFC9

00001000 bbrbbrrb

00000000 RW

[11]

E636

F.S

EP8FIFOPFH

Endpoint 8 / slave FIFO DECIS

Programmable Flag H

0

OUT:PFC10 OUT:PFC9

0

[11]

E637

H.S.

EP8FIFOPFL

reserved

Endpoint 8 / slave FIFO PFC7

Programmable Flag L

PFC5

PFC4

PFC3

PFC2

PFC1

E637

F.S

Endpoint 8 / slave FIFO IN: PKTS[1] IN: PKTS[0] PFC5

Programmable Flag L OUT:PFC7 OUT:PFC6

00000000 RW

8

1

E640

E641

E642

E643

EP2ISOINPKTS

EP4ISOINPKTS

EP6ISOINPKTS

EP8ISOINPKTS

reserved

EP2 (if ISO) IN Packets AADJ

per frame (1-3)

0

INPPF1

INPPF0

00000001 brrrrrbb

00000001 brrrrrrr

00000001 brrrrrbb

00000001 brrrrrrr

1

EP4 (if ISO) IN Packets AADJ

per frame (1-3)

EP6 (if ISO) IN Packets AADJ

per frame (1-3)

EP8 (if ISO) IN Packets AADJ

per frame (1-3)

E644

E648

E649

4

1

7

[11]

INPKTEND

Force IN Packet End

Skip

0

EP3

EP2

EP1

EP0

xxxxxxxx

W

[11]

OUTPKTEND

Force OUT Packet End Skip

INTERRUPTS

[11]

E650

E651

E652

E653

E654

E655

E656

E657

E658

E659

1

EP2FIFOIE

Endpoint 2 slave FIFO

Flag Interrupt Enable

0

EDGEPF

PF

EF

EP1

0

FF

00000000 RW

[11,12]

EP2FIFOIRQ

Endpoint 2 slave FIFO

Flag Interrupt Request

0

PF

FF

00000000 rrrrrbbb

00000000 RW

[11]

EP4FIFOIE

Endpoint 4 slave FIFO

Flag Interrupt Enable

0

EDGEPF

0

PF

FF

[11,12]

EP4FIFOIRQ

Endpoint 4 slave FIFO

Flag Interrupt Request

0

PF

FF

00000000 rrrrrbbb

00000000 RW

[11]

EP6FIFOIE

Endpoint 6 slave FIFO

Flag Interrupt Enable

0

EDGEPF

0

PF

FF

EP6FIFOIRQ

Endpoint 6 slave FIFO

Flag Interrupt Request

0

PF

FF

00000000 rrrrrbbb

00000000 RW

[11]

EP8FIFOIE

EP8FIFOIRQ

IBNIE

Endpoint 8 slave FIFO

Flag Interrupt Enable

0

EDGEPF

0

PF

FF

Endpoint 8 slave FIFO

Flag Interrupt Request

0

PF

FF

00000000 rrrrrbbb

00000000 RW

IN-BULK-NAK Interrupt

Enable

0

EP8

EP4

EP6

EP2

EP4

EP2

EP0

IBN

[12]

IBNIRQ

IN-BULK-NAK interrupt

Request

0

EP4

00xxxxxx rrbbbbbb

00000000 RW

E65A 1

E65B 1

NAKIE

Endpoint Ping-NAK / IBN EP8

Interrupt Enable

EP6

EP1

[12]

NAKIRQ

Endpoint Ping-NAK / IBN EP8

Interrupt Request

EP1

0

xxxxxx0x bbbbbbrb

E65C 1

E65D 1

E65E 1

USBIE

USB Int Enables

0

EP0ACK

EP6

HSGRANT URES

SUSP

SUTOK

EP1IN

SOF

SUDAV

EP0IN

00000000 RW

[12]

USBIRQ

USB Interrupt Requests

0

SUSP

SOF

0xxxxxxx rbbbbbbb

00000000 RW

EPIE

Endpoint Interrupt

Enables

EP8

EP4

0

EP2

0

EP1OUT

EP0OUT

[12]

E65F 1

EPIRQ

Endpoint Interrupt

Requests

EP8

0

EP6

0

EP1OUT

0

EP1IN

0

EP0OUT

GPIFWF

EP0IN

0

RW

[11]

E660

1

GPIFIE

GPIF Interrupt Enable

GPIFDONE 00000000 RW

Note:

12. The register can only be reset, it cannot be set.

Document #: 38-08032 Rev. *G

Page 29 of 55

CY7C68013A/CY7C68014A

CY7C68015A/CY7C68016A

Table 5-1. FX2LP Register Summary (continued)

Hex Size Name

Description

b7

b6

b5

b4

b3

0

b2

0

b1

b0

Default

Access

[11]

E661

E662

1

GPIFIRQ

GPIF Interrupt Request

0

GPIFWF

0

GPIFDONE 000000xx RW

USBERRIE

USB Error Interrupt

Enables

ISOEP8

ISOEP6

ISOEP4

ISOEP2

0

ERRLIMIT

LIMIT0

00000000 RW

[12]

E663

E664

1

USBERRIRQ

ERRCNTLIM

USB Error Interrupt

Requests

ISOEP8

EC3

ISOEP6

EC2

ISOEP4

EC1

ISOEP2

EC0

0

0000000x bbbbrrrb

xxxx0100 rrrrbbbb

USB Error counter and

limit

LIMIT3

LIMIT2

LIMIT1

E665

E666

1

CLRERRCNT

INT2IVEC

Clear Error Counter EC3:0 x

x

xxxxxxxx

W

R

Interrupt 2 (USB)

Autovector

0

1

0

I2V4

I2V3

I2V2

I2V1

I2V0

0

00000000

E667

1

INT4IVEC

Interrupt 4 (slave FIFO &

GPIF) Autovector

0

I4V3

0

I4V2

0

I4V1

I4V0

0

10000000

R

E668

E669

1

7

INTSET-UP

reserved

Interrupt 2&4 set-up

AV2EN

INT4SRC

AV4EN

00000000 RW

INPUT / OUTPUT

PORTACFG

E670

E671

E672

1

I/O PORTA Alternate

Configuration

FLAGD

GPIFA7

GPIFA8

0

SLCS

GPIFA6

T2EX

0

INT1

GPIFA1

T1OUT

0

INT0

00000000 RW

00000000 rrrrrrrb

PORTCCFG

PORTECFG

I/O PORTC Alternate

Configuration

GPIFA5

INT6

0

GPIFA4

GPIFA3

GPIFA2

GPIFA0

T0OUT

EXTCLK

I/O PORTE Alternate

Configuration

RXD1OUT RXD0OUT T2OUT

E673

E677

E678

4

1

XTALINSRC

reserved

I2CS

XTALIN Clock Source

0

I²C Bus

Control & Status

START

STOP

d6

LASTRD

ID1

d4

0

ID0

d3

0

BERR

d2

ACK

d1

DONE

d0

000xx000 bbbrrrrr

xxxxxxxx RW

00000000 RW

xxxxxxxx RW

E679

1

I2DAT

I²C Bus

Data

d7

0

d5

0

E67A 1

E67B 1

E67C 1

I2CTL

I²C Bus

Control

0

STOPIE

D1

400KHZ

D0

XAUTODAT1

XAUTODAT2

UDMA CRC

Autoptr1 MOVX access, D7

when APTREN=1

D6

D5

D4

D3

D2

Autoptr2 MOVX access, D7

when APTREN=1

D1

D0

[11]

E67D 1

E67E 1

E67F 1

UDMACRCH

UDMA CRC MSB

UDMA CRC LSB

UDMA CRC Qualifier

CRC15

CRC14

CRC6

0

CRC13

CRC5

0

CRC12

CRC4

0

CRC11

CRC3

CRC10

CRC2

CRC9

CRC1

CRC8

CRC0

01001010 RW

10111010 RW

[11]

UDMACRCL

CRC7

UDMACRC-

QUALIFIER

QENABLE

QSTATE

QSIGNAL2 QSIGNAL1 QSIGNAL0 00000000 brrrbbbb

USB CONTROL

USBCS

E680

E681

E682

E683

E684

E685

E686

E687

E688

1

2

USB Control & Status

Put chip into suspend

HSM

x

0

DISCON

NOSYNSOF RENUM

SIGRSUME x0000000 rrrrbbbb

SUSPEND

WAKEUPCS

TOGCTL

x

xxxxxxxx

W

Wakeup Control & Status WU2

WU

S

WU2POL

WUPOL

0

DPEN

EP2

FC10

FC2

MF2

FA2

WU2EN

EP1

FC9

FC1

MF1

FA1

WUEN

EP0

FC8

FC0

MF0

FA0

xx000101 bbbbrbbb

x0000000 rrrbbbbb

Toggle Control

Q

R

IO

EP3

0

USBFRAMEH

USBFRAMEL

MICROFRAME

FNADDR

USB Frame count H

USB Frame count L

Microframe count, 0-7

USB Function address

0

00000xxx

xxxxxxxx

00000xxx

0xxxxxxx

R

FC7

0

FC6

0

FC5

0

FC4

0

FC3

0

FA6

FA5

FA4

FA3

reserved

ENDPOINTS

[11]

E68A 1

E68B 1

E68C 1

E68D 1

EP0BCH

Endpoint 0 Byte Count H (BC15)

Endpoint 0 Byte Count L (BC7)

(BC14)

BC6

(BC13)

BC5

(BC12)

BC4

(BC11)

BC3

(BC10)

BC2

(BC9)

BC1

(BC8)

BC0

xxxxxxxx RW

[11]

EP0BCL

reserved

EP1OUTBC

Endpoint 1 OUT Byte

Count

0

BC6

BC5

BC4

BC3

BC2

BC1

BC0

0xxxxxxx RW

E68E 1

E68F 1

reserved

EP1INBC

Endpoint 1 IN Byte Count 0

Endpoint 2 Byte Count H

Endpoint 2 Byte Count L BC7/SKIP

BC6

0

BC5

0

BC4

0

BC3

0

BC2

BC10

BC2

BC1

BC9

BC1

BC0

BC8

BC0

0xxxxxxx RW

00000xxx RW

xxxxxxxx RW

[11]

E690

E691

E692

E694

E695

E696

E698

E699

1

2

1

2

1

EP2BCH

0

[11]

EP2BCL

BC6

BC5

BC4

BC3

reserved

[11]

EP4BCH

Endpoint 4 Byte Count H

0

BC9

BC1

BC8

BC0

000000xx RW

xxxxxxxx RW

[11]

EP4BCL

Endpoint 4 Byte Count L BC7/SKIP

BC6

BC5

BC4

BC3

BC2

reserved

[11]

EP6BCH

Endpoint 6 Byte Count H

0

BC10

BC2

BC9

BC1

BC8

BC0

00000xxx RW

xxxxxxxx RW

[11]

EP6BCL

Endpoint 6 Byte Count L BC7/SKIP

BC6

BC5

BC4

BC3

E69A 2

E69C 1

E69D 1

E69E 2

E6A0 1

reserved

[11]

EP8BCH

Endpoint 8 Byte Count H

0

BC9

BC1

BC8

BC0

000000xx RW

xxxxxxxx RW

[11]

EP8BCL

Endpoint 8 Byte Count L BC7/SKIP

BC6

BC5

BC4

BC3

BC2

reserved

EP0CS

Endpoint 0 Control and

Status

HSNAK

0

BUSY

STALL

10000000 bbbbbbrb

00000000 bbbbbbrb

E6A1 1

E6A2 1

EP1OUTCS

EP1INCS

Endpoint 1 OUT Control

and Status

Endpoint 1 IN Control and 0

Status

Document #: 38-08032 Rev. *G

Page 30 of 55

CY7C68013A/CY7C68014A

CY7C68015A/CY7C68016A

Table 5-1. FX2LP Register Summary (continued)

Hex Size Name

Description

b7

0

b6

b5

b4

b3

b2

b1

0

b0

Default

Access

E6A3 1

E6A4 1

E6A5 1

E6A6 1

E6A7 1

E6A8 1

E6A9 1

E6AA 1

E6AB 1

E6AC 1

E6AD 1

E6AE 1

E6AF 1

E6B0 1

E6B1 1

E6B2 1

E6B3 1

E6B4 1

E6B5 1

EP2CS

Endpoint 2 Control and

Status

NPAK2

NPAK1

NPAK0

FULL

EMPTY

STALL

00101000 rrrrrrrb

00000100 rrrrrrrb

EP4CS

Endpoint 4 Control and

Status

0

NPAK1

NPAK0

FULL

0

EMPTY

PF

0

STALL

FF

EP6CS

Endpoint 6 Control and

Status

0

NPAK2

NPAK1

NPAK0

0

EP8CS

Endpoint 8 Control and

Status

0

NPAK1

NPAK0

0

EP2FIFOFLGS

EP4FIFOFLGS

EP6FIFOFLGS

EP8FIFOFLGS

EP2FIFOBCH

EP2FIFOBCL

EP4FIFOBCH

EP4FIFOBCL

EP6FIFOBCH

EP6FIFOBCL

EP8FIFOBCH

EP8FIFOBCL

SUDPTRH

Endpoint 2 slave FIFO

Flags

0

EF

00000010

00000110

00000000

R

Endpoint 4 slave FIFO

Flags

0

PF

EF

FF

Endpoint 6 slave FIFO

Flags

0

PF

EF

FF

Endpoint 8 slave FIFO

Flags

0

PF

EF

FF

Endpoint 2 slave FIFO

total byte count H

0

BC12

BC4

0

BC11

BC3

0

BC10

BC2

BC10

BC2

BC10

BC2

BC10

BC2

A10

BC9

BC1

BC9

BC1

BC9

BC1

BC9

BC1

A9

BC8

BC0

BC8

BC0

BC8

BC0

BC8

BC0

A8

Endpoint 2 slave FIFO

total byte count L

BC7

0

BC6

0

BC5

0

Endpoint 4 slave FIFO

total byte count H

Endpoint 4 slave FIFO

total byte count L

BC7

0

BC6

0

BC5

0

BC4

0

BC3

BC11

BC3

0

Endpoint 6 slave FIFO

total byte count H

Endpoint 6 slave FIFO

total byte count L

BC7

0

BC6

0

BC5

0

BC4

0

Endpoint 8 slave FIFO

total byte count H

Endpoint 8 slave FIFO

total byte count L

BC7

BC6

A14

A6

0

BC5

A13

A5

0

BC4

A12

A4

0

BC3

A11

A3

Set-up Data Pointer high A15

address byte

xxxxxxxx RW

SUDPTRL

Set-up Data Pointer low A7

address byte

A2

A1

0

xxxxxxx0 bbbbbbbr

SUDPTRCTL

Set-up Data Pointer Auto

Mode

0

SDPAUTO 00000001 RW

2

reserved

E6B8 8

SET-UPDAT

8 bytes of set-up data

D7

D6

D5

D4

D3

D2

D1

D0

xxxxxxxx

R

SET-UPDAT[0] =

bmRequestType

SET-UPDAT[1] =

bmRequest

SET-UPDAT[2:3] = wVal-

ue

SET-UPDAT[4:5] = wInd-

ex

SET-UPDAT[6:7] =

wLength

GPIF

E6C0 1

E6C1 1

GPIFWFSELECT

GPIFIDLECS

Waveform Selector

SINGLEWR1 SINGLEWR0 SINGLERD1 SINGLERD0 FIFOWR1 FIFOWR0

FIFORD1

0

FIFORD0

IDLEDRV

11100100 RW

10000000 RW

GPIF Done, GPIF IDLE DONE

drive mode

0

E6C2 1

E6C3 1

E6C4 1

E6C5 1

GPIFIDLECTL

GPIFCTLCFG

Inactive Bus, CTL states

CTL Drive Type

0

CTL5

0

CTL4

0

CTL3

0

CTL2

0

CTL1

0

CTL0

11111111 RW

00000000 RW

TRICTL

0

CTL0

[11]

GPIFADRH

GPIF Address H

0

GPIFA8

GPIFA0

[11]

GPIFADRL

GPIF Address L

GPIFA7

GPIFA6

GPIFA5

GPIFA4

GPIFA3

GPIFA2

GPIFA1

FLOWSTATE

E6C6 1

Flowstate Enable and

Selector

FSE

0

FS2

FS1

FS0

00000000 brrrrbbb

E6C7 1

E6C8 1

FLOWLOGIC

Flowstate Logic

LFUNC1

CTL0E3

LFUNC0

CTL0E2

TERMA2

TERMA1

TERMA0

CTL3

TERMB2

CTL2

TERMB1

CTL1

TERMB0

CTL0

00000000 RW

FLOWEQ0CTL

CTL-Pin States in

Flowstate

(when Logic = 0)

CTL0E1/

CTL5

CTL0E0/

CTL4

E6C9 1

E6CA 1

E6CB 1

E6CC 1

FLOWEQ1CTL

FLOWHOLDOFF

FLOWSTB

CTL-Pin States in Flow- CTL0E3

state (when Logic = 1)

CTL0E2

CTL0E1/

CTL5

CTL0E0/

CTL4

CTL3

CTL2

CTL1

CTL0

00000000 RW

00010010 RW

00100000 RW

00000001 rrrrrrbb

Holdoff Configuration

HOPERIOD3 HOPERIOD2 HOPERIOD1 HOPERIOD HOSTATE HOCTL2

0

HOCTL1

MSTB1

FALLING

HOCTL0

MSTB0

RISING

Flowstate Strobe

Configuration

SLAVE

RDYASYNC CTLTOGL

SUSTAIN

0

MSTB2

FLOWSTBEDGE

Flowstate Rising/Falling

Edge Configuration

0

E6CD 1

E6CE 1

FLOWSTBPERIOD Master-Strobe Half-Period D7

[11]

D6

D5

D4

D3

D2

D1

D0

00000010 RW

00000000 RW

GPIFTCB3

GPIFTCB2

GPIFTCB1

GPIF Transaction Count TC31

Byte 3

TC30

TC29

TC28

TC27

TC26

TC25

TC24

[11]

E6CF 1

E6D0 1

GPIF Transaction Count TC23

Byte 2

TC22

TC14

TC21

TC13

TC20

TC12

TC19

TC11

TC18

TC10

TC17

TC9

TC16

TC8

00000000 RW

GPIF Transaction Count TC15

Byte 1

Document #: 38-08032 Rev. *G

Page 31 of 55

CY7C68013A/CY7C68014A

CY7C68015A/CY7C68016A

Table 5-1. FX2LP Register Summary (continued)

Hex Size Name

Description

b7

b6

b5

b4

b3

b2

b1

b0

Default

Access

[11]

E6D1 1

GPIFTCB0

GPIF Transaction Count TC7

Byte 0

TC6

TC5

TC4

TC3

TC2

TC1

TC0

00000001 RW

2

reserved

00000000 RW

[11]

E6D2 1

E6D3 1

EP2GPIFFLGSEL

Endpoint 2 GPIF Flag

select

0

x

0

x

0

x

0

x

0

x

0

x

FS1

0

FS0

00000000 RW

EP2GPIFPFSTOP Endpoint 2 GPIF stop

FIFO2FLAG 00000000 RW

transaction on prog. flag

[11]

E6D4 1

3

EP2GPIFTRIG

reserved

Endpoint 2 GPIF Trigger

x

xxxxxxxx

W

reserved

[11]

E6DA 1

E6DB 1

EP4GPIFFLGSEL

Endpoint 4 GPIF Flag

select

0

x

0

x

0

x

0

x

0

x

0

x

FS1

0

FS0

00000000 RW

EP4GPIFPFSTOP Endpoint 4 GPIF stop

FIFO4FLAG 00000000 RW

transaction on GPIF Flag

[11]

E6DC 1

3

EP4GPIFTRIG

reserved

Endpoint 4 GPIF Trigger

x

xxxxxxxx

W

reserved

[11]

E6E2 1

E6E3 1

EP6GPIFFLGSEL

Endpoint 6 GPIF Flag

select

0

x

0

x

0

x

0

x

0

x

0

x

FS1

0

FS0

00000000 RW

EP6GPIFPFSTOP Endpoint 6 GPIF stop

FIFO6FLAG 00000000 RW

transaction on prog. flag

[11]

E6E4 1

3

EP6GPIFTRIG

reserved

Endpoint 6 GPIF Trigger

x

xxxxxxxx

W

reserved

[11]

E6EA 1

E6EB 1

EP8GPIFFLGSEL

Endpoint 8 GPIF Flag

select

0

x

0

x

0

x

0

x

0

x

0

x

FS1

0

FS0

00000000 RW

EP8GPIFPFSTOP Endpoint 8 GPIF stop

FIFO8FLAG 00000000 RW

transaction on prog. flag

[11]

E6EC 1

3

EP8GPIFTRIG

reserved

Endpoint 8 GPIF Trigger

x

xxxxxxxx

W

E6F0 1

XGPIFSGLDATH

GPIF Data H

D15

D14

D6

D13

D12

D4

0

D11

D3

0

D10

D2

0

D9

D1

0

D8

D0

0

xxxxxxxx RW

(16-bit mode only)

E6F1 1

E6F2 1

E6F3 1

XGPIFSGLDATLX

Read/WriteGPIF Data L& D7

trigger transaction

D5

XGPIFSGLDATL-

NOX

Read GPIF Data L, no

transaction trigger

D7

D6

D5

xxxxxxxx

R

GPIFREADYCFG

InternalRDY,Sync/Async, INTRDY

RDY pin states

SAS

TCXRDY5

00000000 bbbrrrrr

E6F4 1

E6F5 1

E6F6 2

GPIFREADYSTAT

GPIFABORT

GPIF Ready Status

0

x

0

x

RDY5

x

RDY4

x

RDY3

x

RDY2

x

RDY1

x

RDY0

x

00xxxxxx

xxxxxxxx

R

Abort GPIF Waveforms

W

reserved

ENDPOINT BUFFERS

E740 64 EP0BUF

E780 64 EP10UTBUF

E7C0 64 EP1INBUF

2048 reserved

EP0-IN/-OUT buffer

EP1-OUT buffer

EP1-IN buffer

D7

D6

D5

D4

D3

D2

D1

D0

xxxxxxxx RW

RW

F000 1024 EP2FIFOBUF

512/1024-byte EP 2 /

slave FIFO buffer (IN or

OUT)

D7

D6

D5

D4

D3

D2

D1

D0

xxxxxxxx RW

F400 512 EP4FIFOBUF

512byteEP 4/slaveFIFO D7

buffer (IN or OUT)

xxxxxxxx RW

F600 512 reserved

F800 1024 EP6FIFOBUF

512/1024-byte EP 6 /

slave FIFO buffer (IN or

OUT)

D7

D6

D5

D4

D3

D2

D1

D0

xxxxxxxx RW

FC00 512 EP8FIFOBUF

FE00 512 reserved

512byteEP 8/slaveFIFO D7

buffer (IN or OUT)

xxxx

I²C Configuration Byte

0

DISCON

0

400KHZ

xxxxxxxx n/a

[14]

Special Function Registers (SFRs)

[13]

80

81

82

83

84

85

1

IOA

SP

Port A (bit addressable) D7

D6

D5

D4

D3

A3

D2

D1

A1

A9

A1

A9

D0

A0

A8

A0

A8

xxxxxxxx RW

00000111 RW

00000000 RW

Stack Pointer

D7

D6

D5

D4

D2

DPL0

DPH0

Data Pointer 0 L

Data Pointer 0 H

Data Pointer 1 L

Data Pointer 1 H

A7

A6

A5

A4

A2

A15

A7

A14

A6

A13

A5

A12

A4

A11

A3

A10

A2

[13]

DPL1

DPH1

[13]

A15

A14

A13

A12

A11

A10

Notes:

13. SFRs not part of the standard 8051 architecture.

14. If no EEPROM is detected by the SIE then the default is 00000000.

Document #: 38-08032 Rev. *G

Page 32 of 55

CY7C68013A/CY7C68014A

CY7C68015A/CY7C68016A

Table 5-1. FX2LP Register Summary (continued)

Hex Size Name

Description

b7

b6

0

b5

0

b4

0

b3

0

b2

0

b1

0

b0

Default

Access

[13]

86

87

88

1

DPS

Data Pointer 0/1 select

Power Control

0

SEL

IDLE

IT0

00000000 RW

00110000 RW

00000000 RW

PCON

TCON

SMOD0

TF1

x

1

x

Timer/Counter Control

(bit addressable)

TR1

TF0

TR0

IE1

IT1

IE0

89

1

TMOD

Timer/Counter Mode

Control

GATE

CT

M1

M0

GATE

CT

M1

M0

00000000 RW

8A

8B

8C

8D

8E

8F

90

91

92

1

TL0

Timer 0 reload L

Timer 1 reload L

Timer 0 reload H

Timer 1 reload H

Clock Control

D7

D15

x

D6

D14

x

D5

D4

D3

D2

D1

D0

00000000 RW

00000001 RW

TL1

D5

D4

D3

D2

D1

D0

TH0

D13

T2M

D12

T1M

D11

T0M

D10

MD2

D9

D8

TH1

D9

D8

[13]

CKCON

MD1

MD0

reserved

[13]

IOB

Port B (bit addressable) D7

External Interrupt Flag(s) IE5

D6

D5

D4

D3

1

D2

0

D1

0

D0

0

xxxxxxxx RW

00001000 RW

00000000 RW

[13]

EXIF

IE4

A14

I²CINT

A13

USBNT

A12

[13]

MPAGE

Upper Addr Byte ofMOVX A15

using @R0 / @R1

A11

A10

A9

A8

93

98

5

1

reserved

SCON0

Serial Port 0 Control

(bit addressable)

SM0_0

SM1_0

SM2_0

REN_0

TB8_0

RB8_0

TI_0

RI_0

00000000 RW

99

9A

9B

9C

9D

9E

9F

A0

A1

A2

A3

A8

1

5

1

SBUF0

Serial Port 0 Data Buffer D7

Autopointer 1 Address H A15

Autopointer 1 Address L A7

D6

D5

D4

D3

A11

A3

D2

D1

A9

A1

D0

A8

A0

00000000 RW

[13]

AUTOPTRH1

A14

A6

A13

A5

A12

A4

A10

A2

[13]

AUTOPTRL1

reserved

[13]

AUTOPTRH2

Autopointer 2 Address H A15

Autopointer 2 Address L A7

A14

A6

A13

A5

A12

A4

A11

A3

A10

A2

A9

A1

A8

A0

00000000 RW

[13]

AUTOPTRL2

reserved

[13]

IOC

Port C (bit addressable) D7

D6

x

D5

x

D4

x

D3

x

D2

x

D1

x

D0

x

xxxxxxxx RW

[13]

INT2CLR

Interrupt 2 clear

Interrupt 4 clear

x

xxxxxxxx

W

[13]

INT4CLR

x

reserved

IE

Interrupt Enable

(bit addressable)

EA

ES1

ET2

ES0

ET1

EX1

ET0

EX0

00000000 RW

A9

AA

1

reserved

[13]

EP2468STAT

Endpoint 2,4,6,8 status

flags

EP8F

EP8E

EP6F

EP6E

EP4F

EP4E

EP2F

EP2E

01011010

00100010

01100110

R

AB

AC

1

EP24FIFOFLGS

[13]

Endpoint 2,4 slave FIFO

status flags

0

EP4PF

EP8PF

EP4EF

EP8EF

EP4FF

EP8FF

0

EP2PF

EP6PF

EP2EF

EP6EF

EP2FF

EP6FF

EP68FIFOFLGS

[13]

Endpoint 6,8 slave FIFO

status flags

AD

AF

2

1

reserved

AUTOPTRSET-

Autopointer 1&2 set-up

0

APTR2INC APTR1INC APTREN

00000110 RW

[13]

UP

[13]

B0

B1

1

IOD

Port D (bit addressable) D7

D6

D5

D4

D3

D2

D1

D0

xxxxxxxx RW

[13]

IOE

Port E

D7

(NOT bit addressable)

[13]

B2

B3

B4

B5

B6

B7

B8

1

OEA

Port A Output Enable

Port B Output Enable

Port C Output Enable

Port D Output Enable

Port E Output Enable

D7

D6

D5

D4

D3

D2

D1

D0

00000000 RW

[13]

OEB

[13]

OEC

[13]

OED

[13]

OEE

reserved

IP

Interrupt Priority (bit ad-

dressable)

1

PS1

PT2

PS0

PT1

PX1

PT0

PX0

10000000 RW

B9

BA

1

reserved

[13]

EP01STAT

Endpoint 0&1 Status

0

EP1INBSY EP1OUTBS EP0BSY

Y

00000000 R

[13, 11]

BB

1

GPIFTRIG

Endpoint 2,4,6,8 GPIF

slave FIFO Trigger

DONE

RW

EP1

EP0

10000xxx brrrrbbb

BC

BD

1

reserved

[13]

GPIFSGLDATH

GPIF Data H (16-bit mode D15

only)

D14

D13

D12

D11

D10

D9

D8

xxxxxxxx RW

[13]

BE

BF

1

GPIFSGLDATLX

GPIFSGLDAT

GPIF Data L w/ Trigger

D7

D6

D5

D4

D3

D2

D1

D0

GPIF Data L w/ No Trigger D7

xxxxxxxx

R

[13]

LNOX

[13]

C0

1

SCON1

Serial Port 1 Control (bit SM0_1

addressable)

SM1_1

D6

SM2_1

D5

REN_1

D4

TB8_1

D3

RB8_1

D2

TI_1

D1

RI_1

D0

00000000 RW

[13]

C1

C2

C8

1

6

1

SBUF1

Serial Port 1 Data Buffer D7

reserved

T2CON

Timer/Counter 2 Control TF2

(bit addressable)

EXF2

D6

RCLK

D5

TCLK

D4

EXEN2

D3

TR2

D2

CT2

D1

CPRL2

D0

00000000 RW

C9

CA

1

reserved

RCAP2L

Capture for Timer 2, auto- D7

reload, up-counter

Document #: 38-08032 Rev. *G

Page 33 of 55

CY7C68013A/CY7C68014A

CY7C68015A/CY7C68016A

Table 5-1. FX2LP Register Summary (continued)

Hex Size Name

Description

b7

b6

b5

b4

b3

b2

b1

b0

Default

Access

CB

1

RCAP2H

Capture for Timer 2, auto- D7

reload, up-counter

D6

D5

D4

D3

D2

D1

D0

00000000 RW

CC

CD

CE

D0

1

2

1

TL2

Timer 2 reload L

Timer 2 reload H

D7

D6

D5

D4

D3

D2

D1

D9

D0

D8

00000000 RW

TH2

D15

D14

D13

D12

D11

D10

reserved

PSW

Program Status Word (bit CY

addressable)

AC

F0

RS1

RS0

OV

F1

P

00000000 RW

D1

D8

D9

E0

7

1

7

1

reserved

[13]

EICON

reserved

ACC

External Interrupt Control SMOD1

1

ERESI

D5

RESI

D4

INT6

D3

0

01000000 RW

00000000 RW

Accumulator (bit address- D7

able)

D6

D2

D1

D0

E1

E8

7

1

reserved

[13]

EIE

External Interrupt En-

able(s)

1

EX6

EX5

EX4

EI²C

EUSB

11100000 RW

E9

F0

F1

F8

7

1

7

1

reserved

B

B (bit addressable)

D7

1

D6

1

D5

1

D4

D3

D2

D1

D0

00000000 RW

11100000 RW

reserved

[13]

EIP

External Interrupt Priority

Control

PX6

PX5

PX4

PI²C

PUSB

F9

7

reserved

R = all bits read-only

W = all bits write-only

r = read-only bit

w = write-only bit

b = both read/write bit

Document #: 38-08032 Rev. *G

Page 34 of 55

CY7C68013A/CY7C68014A

CY7C68015A/CY7C68016A

6.0

Absolute Maximum Ratings

Storage Temperature ............................................................................................................................................–65°C to +150°C

Ambient Temperature with Power Supplied................................................................................................................0°C to +70°C

Supply Voltage to Ground Potential.........................................................................................................................–0.5V to +4.0V

[15]

DC Input Voltage to Any Input Pin .................................................................................................................................... 5.25V

DC Voltage Applied to Outputs in High Z State.............................................................................................. –0.5V to VCC + 0.5V

Power Dissipation ............................................................................................................................................................. 300 mW

Static Discharge Voltage................................................................................................................................................... > 2000V

Max Output Current, per I/O port ......................................................................................................................................... 10 mA

Max Output Current, all five I/O ports (128- and 100-pin packages) ................................................................................... 50 mA

7.0

Operating Conditions

T (Ambient Temperature Under Bias) .......................................................................................................................0°C to +70°C

A

Supply Voltage.....................................................................................................................................................+3.15V to +3.45V

Ground Voltage........................................................................................................................................................................... 0V

F

(Oscillator or Crystal Frequency)............................................................................................................. 24 MHz ± 100 ppm

OSC

............................................................................................................................................................................ Parallel Resonant

8.0

DC Characteristics

Table 8-1. DC Characteristics

Parameter Description

VCC Supply Voltage

VCC Ramp Up 0 to 3.3V

Conditions

Min.

3.15

200

2

Typ.

Max.

Unit

V

3.3

3.45

µs

V

Input HIGH Voltage

5.25

0.8

IH

Input LOW Voltage

–0.5

2

V

IL

Crystal input HIGH Voltage

Crystal input LOW Voltage

Input Leakage Current

Output Voltage HIGH

Output LOW Voltage

Output Current HIGH

Output Current LOW

Input Pin Capacitance

5.25

0.8

V

IH_X

IL_X

-0.5

V

I

0< V < VCC

±10

µA

V

I

IN

V

I

= 4 mA

2.4

OH

OL

OUT

= –4 mA

0.4

4

V

I

mA

pF

µA

mA

mS

µS

OH

OL

4

C

Except D+/D–

10

15

IN

D+/D–

[16]

I

Suspend Current

Connected

300

100

0.5

0.3

50

380

150

SUSP

[16]

CY7C68014/CY7C68016

Suspend Current

Disconnected

[16]

Connected

1.2

1.0

CY7C68013/CY7C68015

Supply Current

Disconnected

I

8051 running, connected to USB HS

8051 running, connected to USB FS

VCC min = 3.0V

85

65

CC

35

T

Reset Time after Valid Power

Pin Reset after powered on

5.0

RESET

200

8.1

USB Transceiver

USB 2.0-compliant in full- and high-speed modes.

Notes:

15. It is recommended to not power I/O with chip power is off.

16. Measured at Max VCC, 25°C.

Document #: 38-08032 Rev. *G

Page 35 of 55

CY7C68013A/CY7C68014A

CY7C68015A/CY7C68016A

9.0

9.1

AC Electrical Characteristics

USB Transceiver

USB 2.0-compliant in full- and high-speed modes.

9.2

Program Memory Read

t_CL

[17]

CLKOUT

t_AV

A[15..0]

t_STBH

t_STBL

PSEN#

D[7..0]

[18]

t_ACC1

t_DH

data in

t_SOEL

OE#

CS#

t_SCSL

Figure 9-1. Program Memory Read Timing Diagram

Table 9-1. Program Memory Read Parameters

Parameter Description

1/CLKOUT Frequency

Min.

Typ.

20.83

41.66

83.2

Max.

Unit

ns

Notes

48 MHz

24 MHz

12 MHz

t

CL

t

Delay from Clock to Valid Address

Clock to PSEN Low

Clock to PSEN High

Clock to OE Low

0

10.7

8

AV

STBL

STBH

SOEL

SCSL

DSU

8

11.1

13

Clock to CS Low

Data Set-up to Clock

Data Hold Time

9.6

0

DH

Notes:

17. CLKOUT is shown with positive polarity.

18. t_ACC1is computed from the above parameters as follows:

t_ACC1(24 MHz) = 3*t_CL– t_AV–t_DSU= 106 ns

t_ACC1(48 MHz) = 3*t_CL– t_AV– t_DSU= 43 ns.

Document #: 38-08032 Rev. *G

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9.3

Data Memory Read

t_CL

Stretch = 0

[17]

CLKOUT

t_AV

A[15..0]

RD#

t_STBH

t_STBL

t_SCSL

CS#

OE#

t_SOEL

t_DSU

[19

t_DH

t_ACC1

D[7..0]

data in

Stretch = 1

t_CL

[17]

CLKOUT

t_AV

A[15..0]

RD#

CS#

t_DSU

t_DH

[19]

t_ACC1

D[7..0]

data in

Figure 9-2. Data Memory Read Timing Diagram

Table 9-2. Data Memory Read Parameters

Parameter Description

1/CLKOUT Frequency

Min.

Typ.

20.83

41.66

83.2

Max.

Unit

ns

Notes

48 MHz

24 MHz

12 MHz

t

CL

t

Delay from Clock to Valid Address

Clock to RD LOW

10.7

11

AV

STBL

STBH

SCSL

SOEL

DSU

Clock to RD HIGH

11

Clock to CS LOW

13

Clock to OE LOW

11.1

Data Set-up to Clock

Data Hold Time

9.6

0

DH

Note:

19. t_ACC2and t_ACC3are computed from the above parameters as follows:

t_ACC2(24 MHz) = 3*t_CL– t_AV–t_DSU= 106 ns

t_ACC2(48 MHz) = 3*t_CL– t_AV– t_DSU= 43 ns

t_ACC3(24 MHz) = 5*t_CL– t_AV–t_DSU= 190 ns

t_ACC3(48 MHz) = 5*t_CL– t_AV– t_DSU= 86 ns.

Document #: 38-08032 Rev. *G

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9.4

Data Memory Write

t_CL

CLKOUT

t_AV

t_STBL

t_STBH

t_AV

A[15..0]

WR#

CS#

t_SCSL

t_ON1

t_OFF1

data out

D[7..0]

Stretch = 1

t_CL

CLKOUT

A[15..0]

t_AV

WR#

CS#

t_ON1

t_OFF1

data out

D[7..0]

Figure 9-3. Data Memory Write Timing Diagram

Table 9-3. Data Memory Write Parameters

Parameter Description

Min.

Max.

10.7

11.2

13.0

13.1

Unit

ns

Notes

t

Delay from Clock to Valid Address

Clock to WR Pulse LOW

Clock to WR Pulse HIGH

Clock to CS Pulse LOW

Clock to Data Turn-on

0

AV

ns

STBL

STBH

SCSL

ON1

ns

0

ns

Clock to Data Hold Time

ns

OFF1

Document #: 38-08032 Rev. *G

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9.5

GPIF Synchronous Signals

t_IFCLK

IFCLK

t_SGA

GPIFADR[8:0]

RDY_X

t_SRY

t_RYH

valid

DATA(input)

t_SGD

t_DAH

CTL_X

t_XCTL

DATA(output)

N

N+1

t_XGD

[19]

Figure 9-4. GPIF Synchronous Signals Timing Diagram

[20, 21]

Table 9-4. GPIF Synchronous Signals Parameters with Internally Sourced IFCLK

Parameter

Description

Min.

20.83

8.9

0

Max.

Unit

ns

t

IFCLK Period

RDY to Clock Set-up Time

IFCLK

SRY

RYH

SGD

DAH

SGA

XGD

XCTL

X

Clock to RDY

X

GPIF Data to Clock Set-up Time

GPIF Data Hold Time

9.2

0

Clock to GPIF Address Propagation Delay

Clock to GPIF Data Output Propagation Delay

7.5

11

Clock to CTL Output Propagation Delay

6.7

X

[21]

Table 9-5. GPIF Synchronous Signals Parameters with Externally Sourced IFCLK

Parameter

Description

Min.

20.83

2.9

Max.

Unit

ns

[22]

t

IFCLK Period

RDY to Clock Set-up Time

200

IFCLK

SRY

RYH

SGD

DAH

SGA

XGD

XCTL

X

Clock to RDY

3.7

X

GPIF Data to Clock Set-up Time

GPIF Data Hold Time

3.2

4.5

Clock to GPIF Address Propagation Delay

Clock to GPIF Data Output Propagation Delay

11.5

15

Clock to CTL Output Propagation Delay

10.7

X

Notes:

20. Dashed lines denote signals with programmable polarity.

21. GPIF asynchronous RDY_xsignals have a minimum Set-up time of 50 ns when using internal 48-MHz IFCLK.

22. IFCLK must not exceed 48 MHz.

Document #: 38-08032 Rev. *G

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9.6

Slave FIFO Synchronous Read

t_IFCLK

IFCLK

SLRD

t_RDH

t_SRD

t_XFLG

FLAGS

DATA

N+1

t_XFD

N

t_OEon

t_OEoff

SLOE

[19]

Figure 9-5. Slave FIFO Synchronous Read Timing Diagram

[21]

Table 9-6. Slave FIFO Synchronous Read Parameters with Internally Sourced IFCLK

Parameter

Description

Min.

20.83

18.7

0

Max.

Unit

ns

t

IFCLK Period

IFCLK

SLRD to Clock Set-up Time

ns

SRD

Clock to SLRD Hold Time

ns

RDH

OEon

OEoff

XFLG

XFD

SLOE Turn-on to FIFO Data Valid

SLOE Turn-off to FIFO Data Hold

Clock to FLAGS Output Propagation Delay

Clock to FIFO Data Output Propagation Delay

10.5

9.5

ns

TBD

11

ns

[21]

Table 9-7. Slave FIFO Synchronous Read Parameters with Externally Sourced IFCLK

Parameter

Description

Min.

20.83

12.7

3.7

Max.

Unit

ns

t

IFCLK Period

200

IFCLK

SLRD to Clock Set-up Time

ns

SRD

Clock to SLRD Hold Time

ns

RDH

OEon

OEoff

XFLG

XFD

SLOE Turn-on to FIFO Data Valid

SLOE Turn-off to FIFO Data Hold

Clock to FLAGS Output Propagation Delay

Clock to FIFO Data Output Propagation Delay

10.5

13.5

15

ns

TBD

ns

Document #: 38-08032 Rev. *G

Page 40 of 55

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CY7C68015A/CY7C68016A

9.7

Slave FIFO Asynchronous Read

t_RDpwh

SLRD

t_RDpwl

t_XFLG

t_XFD

FLAGS

DATA

SLOE

N+1

N

t_OEon

t_OEoff

[19]

Figure 9-6. Slave FIFO Asynchronous Read Timing Diagram

[23]

Table 9-8. Slave FIFO Asynchronous Read Parameters

Parameter Description

SLRD Pulse Width LOW

Min.

50

Max.

Unit

ns

t

RDpwl

SLRD Pulse Width HIGH

50

ns

RDpwh

XFLG

XFD

SLRD to FLAGS Output Propagation Delay

SLRD to FIFO Data Output Propagation Delay

SLOE Turn-on to FIFO Data Valid

SLOE Turn-off to FIFO Data Hold

70

15

ns

10.5

ns

OEon

ns

OEoff

Note:

23. Slave FIFO asynchronous parameter values use internal IFCLK setting at 48 MHz.

Document #: 38-08032 Rev. *G

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CY7C68015A/CY7C68016A

9.8

Slave FIFO Synchronous Write

t_IFCLK

IFCLK

t_WRH

SLWR

t_SWR

DATA

Z

N

Z

t_SFDt_FDH

FLAGS

t_XFLG

[19]

Figure 9-7. Slave FIFO Synchronous Write Timing Diagram

[21]

Table 9-9. Slave FIFO Synchronous Write Parameters with Internally Sourced IFCLK

Parameter

Description

Min.

20.83

18.1

0

Max.

Unit

ns

t

IFCLK Period

IFCLK

SLWR to Clock Set-up Time

ns

SWR

WRH

SFD

Clock to SLWR Hold Time

ns

FIFO Data to Clock Set-up Time

Clock to FIFO Data Hold Time

Clock to FLAGS Output Propagation Time

9.2

0

ns

FDH

9.5

ns

XFLG

[21]

Table 9-10. Slave FIFO Synchronous Write Parameters with Externally Sourced IFCLK

Parameter

Description

Min.

20.83

12.1

3.6

Max.

Unit

ns

t

IFCLK Period

200

IFCLK

SLWR to Clock Set-up Time

ns

SWR

WRH

SFD

Clock to SLWR Hold Time

ns

FIFO Data to Clock Set-up Time

Clock to FIFO Data Hold Time

Clock to FLAGS Output Propagation Time

3.2

ns

4.5

ns

FDH

13.5

ns

XFLG

Document #: 38-08032 Rev. *G

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9.9

Slave FIFO Asynchronous Write

t_WRpwh

SLWR/SLCS#

t_WRpwl

t_FDH

t_SFD

DATA

t_XFD

FLAGS

[19]

Figure 9-8. Slave FIFO Asynchronous Write Timing Diagram

[23]

Table 9-11. Slave FIFO Asynchronous Write Parameters with Internally Sourced IFCLK

Parameter

Description

Min.

50

Max.

Unit

ns

t

SLWR Pulse LOW

SLWR Pulse HIGH

WRpwl

70

ns

WRpwh

SFD

SLWR to FIFO DATA Set-up Time

FIFO DATA to SLWR Hold Time

10

ns

10

ns

FDH

SLWR to FLAGS Output Propagation Delay

70

ns

XFD

9.10

Slave FIFO Synchronous Packet End Strobe

IFCLK

t_PEH

PKTEND

FLAGS

t_SPE

t_XFLG

[19]

Figure 9-9. Slave FIFO Synchronous Packet End Strobe Timing Diagram

[21]

Table 9-12. Slave FIFO Synchronous Packet End Strobe Parameters with Internally Sourced IFCLK

Parameter

Description

Min.

20.83

14.6

0

Max.

Unit

ns

t

IFCLK Period

IFCLK

PKTEND to Clock Set-up Time

ns

SPE

Clock to PKTEND Hold Time

ns

PEH

XFLG

Clock to FLAGS Output Propagation Delay

9.5

ns

[21]

Table 9-13. Slave FIFO Synchronous Packet End Strobe Parameters with Externally Sourced IFCLK

Parameter

Description

Min.

20.83

8.6

Max.

Unit

ns

t

IFCLK Period

200

IFCLK

PKTEND to Clock Set-up Time

ns

SPE

Clock to PKTEND Hold Time

2.5

ns

PEH

XFLG

Clock to FLAGS Output Propagation Delay

13.5

ns

the FIFOs or thereafter. The only consideration is the set-up

time t and the hold time t must be met.

There is no specific timing requirement that needs to be met

for asserting PKTEND pin with regards to asserting SLWR.

PKTEND can be asserted with the last data value clocked into

SPE

PEH

Although there are no specific timing requirement for the

PKTEND assertion, there is a specific corner case condition

Document #: 38-08032 Rev. *G

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CY7C68015A/CY7C68016A

that needs attention while using the PKTEND to commit a one

byte/word packet. There is an additional timing requirement

that need to be met when the FIFO is configured to operate in

auto mode and it is desired to send two packets back to back:

a full packet (full defined as the number of bytes in the FIFO

meeting the level set in AUTOINLEN register) committed

automatically followed by a short one byte/word packet

committed manually using the PKTEND pin. In this particular

scenario, user must make sure to assert PKTEND atleast one

clock cycle after the rising edge that caused the last byte/word

to be clocked into the previous auto committed packet. Figure

9-10 below shows this scenario. X is the value the

AUTOINLEN register is set to when the IN endpoint is

configured to be in auto mode.

t

IFCLK

t

SFA

FAH

FIFOADR

>= t

WRH

>= t

SWR

SLWR

DATA

t

FDH

t

FDH

t

SFD

t

FDH

t

SFD

FDH

SFD

FDH

SFD

FDH

X-4

X-2

X-1

1

X-3

X

At least one IFCLK cycle

t

SPE

t

PEH

PKTEND

Figure 9-10. Slave FIFO Synchronous Write Sequence and Timing Diagram

The above figure shows a scenario where two packets are

being committed. The first packet gets comitted automatically

when the number of bytes in the FIFO reaches X (value set in

AUTOINLEN register) and the second one byte/word short

packet being committed manually using PKTEND. Note that

there is atleast one IFCLK cycle timing between the assertion

of PKTEND and clocking of the last byte of the previous packet

(causing the packet to be committed automatically). Failing to

adhere to this timing, will result in the FX2 failing to send the

one byte/word short packet.

9.11

Slave FIFO Asynchronous Packet End Strobe

t_PEpwh

PKTEND

t_PEpwl

FLAGS

t_XFLG

[19]

Figure 9-11. Slave FIFO Asynchronous Packet End Strobe Timing Diagram

[23]

Table 9-14. Slave FIFO Asynchronous Packet End Strobe Parameters

Parameter Description

PKTEND Pulse Width LOW

Min.

50

Max.

Unit

ns

t

PEpwl

PKTEND Pulse Width HIGH

50

ns

PWpwh

XFLG

PKTEND to FLAGS Output Propagation Delay

115

ns

Document #: 38-08032 Rev. *G

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CY7C68013A/CY7C68014A

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9.12

Slave FIFO Output Enable

SLOE

t_OEoff

t_OEon

DATA

[19]

Figure 9-12. Slave FIFO Output Enable Timing Diagram

Table 9-15. Slave FIFO Output Enable Parameters

Parameter

Description

SLOE Assert to FIFO DATA Output

SLOE Deassert to FIFO DATA Hold

Min.

Max.

10.5

Unit

ns

t

OEon

OEoff

ns

9.13

Slave FIFO Address to Flags/Data

FIFOADR [1.0]

t_XFLG

FLAGS

DATA

t_XFD

N

N+1

[19]

Figure 9-13. Slave FIFO Address to Flags/Data Timing Diagram

Table 9-16. Slave FIFO Address to Flags/Data Parameters

Parameter

Description

Min.

Max.

10.7

14.3

Unit

ns

t

FIFOADR[1:0] to FLAGS Output Propagation Delay

FIFOADR[1:0] to FIFODATA Output Propagation Delay

XFLG

XFD

ns

Document #: 38-08032 Rev. *G

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CY7C68015A/CY7C68016A

9.14

Slave FIFO Synchronous Address

IFCLK

SLCS/FIFOADR [1:0]

t_SFA

t_FAH

Figure 9-14. Slave FIFO Synchronous Address Timing Diagram

[21]

Table 9-17. Slave FIFO Synchronous Address Parameters

Parameter Description

Interface Clock Period

Min.

20.83

25

Max.

Unit

ns

t

200

IFCLK

FIFOADR[1:0] to Clock Set-up Time

Clock to FIFOADR[1:0] Hold Time

ns

SFA

FAH

10

ns

9.15

Slave FIFO Asynchronous Address

SLCS/FIFOADR [1:0]

t_FAH

t_SFA

SLRD/SLWR/PKTEND

[19]

Figure 9-15. Slave FIFO Asynchronous Address Timing Diagram

[23]

Slave FIFO Asynchronous Address Parameters

Parameter

Description

Min.

10

Max.

Unit

ns

t

FIFOADR[1:0] to SLRD/SLWR/PKTEND Set-up Time

RD/WR/PKTEND to FIFOADR[1:0] Hold Time

SFA

FAH

10

ns

Document #: 38-08032 Rev. *G

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9.16

Sequence Diagram

9.16.1 Single and Burst Synchronous Read Example

t

IFCLK

t

SFA

t

FAH

FIFOADR

t=0

T=0

t

>= t

SRD

>= t

RDH

SRD

SLRD

SLCS

t=3

t=2

T=3

T=2

t

XFLG

FLAGS

DATA

SLOE

t

XFD

N+4

Data Driven: N

OEon

N+1

N+2

N+3

t

OEon

t

OEoff

t

OEoff

t=4

T=4

T=1

t=1

Figure 9-16. Slave FIFO Synchronous Read Sequence and Timing Diagram

IFCLK

N

IFCLK

N

IFCLK

N+1

IFCLK

N+1

IFCLK

N+1

IFCLK

N+2

IFCLK

N+3

IFCLK

N+4

IFCLK

N+4

IFCLK

N+4

FIFO POINTER

SLOE

SLRD

SLOE

SLRD

SLOE

SLRD

N+4

SLOE

FIFO DATA BUS Not Driven

Driven: N

N+1

Not Driven

N+1

N+2

N+3

N+4

Not Driven

Figure 9-17. Slave FIFO Synchronous Sequence of Events Diagram

Figure 9-16 shows the timing relationship of the SLAVE FIFO

signals during a synchronous FIFO read using IFCLK as the

synchronizing clock. The diagram illustrates a single read

followed by a burst read.

with SLRD, or before SLRD is asserted (i.e., the SLCS and

SLRD signals must both be asserted to start a valid read

condition).

• The FIFO pointeris updated ontherising edge of the IFCLK,

while SLRD is asserted. This starts the propagation of data

from the newly addressed location to the data bus. After a

• At t = 0 the FIFO address is stable and the signal SLCS is

asserted (SLCS may be tied low in some applications).

Note: t

hasaminimum of25ns. Thismeanswhen IFCLK

propagation delay of t

(measured from the rising edge

SFA

XFD

is running at 48 MHz, the FIFO address set-up time is more

than one IFCLK cycle.

of IFCLK) the new data value is present. N is the first data

value read from the FIFO. In order to have data on the FIFO

data bus, SLOE MUST also be asserted.

• At = 1, SLOE is asserted. SLOE is an output enable only,

whose sole function is to drive the data bus. The data that

is driven on the bus is the data that the internal FIFO pointer

is currently pointing to. In this example it is the first data

value in the FIFO. Note: the data is pre-fetched and is driven

on the bus when SLOE is asserted.

The same sequence of events are shown for a burst read and

are marked with the time indicators of T = 0 through 5. Note:

For the burst mode, the SLRD and SLOE are left asserted

during the entire duration of the read. In the burst read mode,

when SLOE is asserted, data indexed by the FIFO pointer is

on the data bus. During the first read cycle, on the rising edge

of the clock the FIFO pointer is updated and increments to

point to address N+1. For each subsequent rising edge of

IFCLK, while the SLRD is asserted, the FIFO pointer is incre-

mented and the next data value is placed on the data bus.

• At t = 2, SLRD is asserted. SLRD must meet the set-up time

of t

(time from asserting the SLRD signal to the rising

SRD

edge of the IFCLK) and maintain a minimum hold time of

(time from the IFCLK edge to the deassertion of the

t

RDH

SLRDsignal). If theSLCS signalis used, itmustbe asserted

Document #: 38-08032 Rev. *G

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9.16.2 Single and Burst Synchronous Write

t

IFCLK

t

SFA

t

SFA

t

FAH

FIFOADR

>= t

WRH

t=0

t

>= t

T=0

SWR

WRH

SWR

SLWR

SLCS

T=2

T=5

t=2

t=3

t

XFLG

t

XFLG

FLAGS

DATA

t

FDH

t

SFD

FDH

SFD

FDH

SFD

FDH

N+1

N+3

N

N+2

T=4

T=3

t=1

T=1

t

SPE

t

PEH

PKTEND

[19]

Figure 9-18. Slave FIFO Synchronous Write Sequence and Timing Diagram

The Figure 9-18 shows the timing relationship of the SLAVE

FIFO signals during a synchronous write using IFCLK as the

synchronizing clock. The diagram illustrates a single write

followed by burst write of 3 bytes and committing all 4 bytes as

a short packet using the PKTEND pin.

of IFCLK. The FIFO pointer is updated on each rising edge of

IFCLK. In Figure 9-18, once the four bytes are written to the

FIFO, SLWR is deasserted. The short 4-byte packet can be

committed to the host by asserting the PKTEND signal.

There is no specific timing requirement that needs to be met

for asserting PKTEND signal with regards to asserting the

SLWR signal. PKTEND can be asserted with the last data

value or thereafter. The only requirement is that the set-up time

• At t = 0 the FIFO address is stable and the signal SLCS is

asserted. (SLCS may be tied low in some applications)

Note: t

hasa minimum of25ns. This means when IFCLK

SFA

is running at 48 MHz, the FIFO address set-up time is more

than one IFCLK cycle.

t

and the hold time t

must be met. In the scenario of

SPE

PEH

Figure 9-18, the number of data values committed includes the

last value written to the FIFO. In this example, both the data

value and the PKTEND signal are clocked on the same rising

edge of IFCLK. PKTEND can also be asserted in subsequent

clock cycles. The FIFOADDR lines should be held constant

during the PKTEND assertion.

• At t = 1, the external master/peripheral must outputs the

data value onto the data bus with a minimum set up time of

t

before the rising edge of IFCLK.

SFD

• At t = 2, SLWR is asserted. The SLWR must meet the set-

up time of t (time from asserting the SLWR signal to the

SWR

Although there are no specific timing requirement for the

PKTEND assertion, there is a specific corner case condition

that needs attention while using the PKTEND to commit a one

byte/word packet. Additional timing requirements exists when

the FIFO is configured to operate in auto mode and it is desired

to send two packets: a full packet (full defined as the number

of bytes in the FIFO meeting the level set in AUTOINLEN

register) committed automatically followed by a short one

byte/word packet committed manually using the PKTEND pin.

In this case, the external master must make sure to assert the

PKTEND pin atleast one clock cycle after the rising edge that

caused the last byte/word to be clocked into the previous auto

committed packet (the packet with the number of bytes equal

to what is set in the AUTOINLEN register). Refer to Figure 9-

10 for further details on this timing.

rising edge of IFCLK) and maintain a minimum hold time of

(time from the IFCLK edge to the deassertion of the

SLWR signal). If SLCS signal is used, it must be asserted

with SLWR or before SLWR is asserted. (i.e. the SLCS and

SLWR signals must both be asserted to start a valid write

condition).

t

WRH

• While the SLWR is asserted, data is written to the FIFO and

on the rising edge of the IFCLK, the FIFO pointer is incre-

mented. The FIFO flag will also be updated after a delay of

t

from the rising edge of the clock.

XFLG

The same sequence of events are also shown for a burst write

and are marked with the time indicators of T = 0 through 5.

Note: For the burst mode, SLWR and SLCS are left asserted

for the entire duration of writing all the required data values. In

this burst write mode, once the SLWR is asserted, the data on

the FIFO data bus is written to the FIFO on every rising edge

Document #: 38-08032 Rev. *G

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9.16.3 Sequence Diagram of a Single and Burst Asynchronous Read

t

FAH

SFA

FAH

FIFOADR

t=0

t

RDpwh

t

RDpwl

t

T=0

RDpwl

RDpwh

SLRD

SLCS

t=3

t=2

T=2

T=3

T=5

T=4

T=6

t

XFLG

t

XFLG

FLAGS

DATA

SLOE

t

XFD

t

XFD

t

XFD

Data (X)

Driven

N+3

N

N+1

N+2

N

t

OEon

t

OEoff

OEon

t=4

T=1

T=7

t=1

Figure 9-19. Slave FIFO Asynchronous Read Sequence and Timing Diagram

SLOE

SLRD

SLOE

SLRD

N+1

SLRD

N+1

SLRD

N+2

SLRD

N+2

SLOE

FIFO POINTER

N

N+1

N

N+1

N+3

N+2

N+3

FIFO DATA BUS Not Driven

Driven: X

Not Driven

N

N+1

N+2

Not Driven

Figure 9-20. Slave FIFO Asynchronous Read Sequence of Events Diagram

Figure 9-19 diagrams the timing relationship of the SLAVE

FIFO signals during an asynchronous FIFO read. It shows a

single read followed by a burst read.

• The data that will be driven, after asserting SLRD, is the

updated data from the FIFO. This data is valid after a propa-

gation delay of t

from the activating edge of SLRD. In

XFD

Figure 9-19, data N is the firstvalid data read from the FIFO.

For data to appear on the data bus during the read cycle

(i.e. ,SLRD is asserted), SLOE MUST be in an asserted

state. SLRD and SLOE can also be tied together.

• At t = 0 the FIFO address is stable and the SLCS signal is

asserted.

• At t = 1, SLOE is asserted. This results in the data bus being

driven. The data that is driven on to the bus is previous data,

it data that was in the FIFO from a prior read cycle.

The same sequence of events is also shown for a burst read

marked with T = 0 through 5. Note: In burst read mode, during

SLOE is assertion, the data bus is in a driven state and outputs

the previous data. Once SLRD is asserted, the data from the

FIFO is driven on the data bus (SLOE must also be asserted)

and then the FIFO pointer is incremented.

• At t = 2, SLRD is asserted. The SLRD must meet the

minimum active pulse of t

and minimum de-active

RDpwl

pulse width of t

. If SLCS is used then, SLCS must be

RDpwh

in asserted with SLRD or before SLRD is asserted (i.e., the

SLCS and SLRD signals must both be asserted to start a

valid read condition.)

Document #: 38-08032 Rev. *G

Page 49 of 55

CY7C68013A/CY7C68014A

CY7C68015A/CY7C68016A

9.16.4 Sequence Diagram of a Single and Burst Asynchronous Write

t

FAH

t

SFA

FAH

FIFOADR

t=0

T=0

t

WRpwh

t

WRpwl

WRpwh

WRpwl

WRpwh

SLWR

SLCS

t =1

t=3

T=4

T=1

T=7

T=3

T=6

T=9

t

XFLG

t

XFLG

FLAGS

DATA

t

SFD

t

SFD FDH

FDH

N

N+1

N+2

N+3

t=2

T=8

T=2

T=5

t

PEpwl

PEpwh

PKTEND

[19]

Figure 9-21. Slave FIFO Asynchronous Write Sequence and Timing Diagram

Figure 9-21 diagrams the timing relationship of the SLAVE

FIFO write in an asynchronous mode. The diagram shows a

single write followed by a burst write of 3 bytes and committing

the 4-byte-short packet using PKTEND.

pointer. The FIFO flag is also updated after t

asserting edge of SLWR.

from the de-

XFLG

The same sequence of events are shown for a burst write and

is indicated by the timing marks of T = 0 through 5. Note: In

the burst write mode, once SLWR is deasserted, the data is

written to the FIFO and then the FIFO pointer is incremented

to the next byte in the FIFO. The FIFO pointer is post incre-

mented.

·At t = 0 the FIFO address is applied, insuring that it meets the

set-up time of t

. If SLCS is used, it must also be asserted

SFA

(SLCS may be tied low in some applications).

·..At t = 1 SLWR is asserted. SLWR must meet the minimum

active pulse of t

and minimum de-active pulse width of

In Figure 9-21 once the four bytes are written to the FIFO and

SLWR is deasserted, the short 4-byte packet can be

committed to the host using the PKTEND. The external device

should be designed to not assert SLWR and the PKTEND

signal at the same time. It should be designed to assert the

PKTEND after SLWR is de-asserted and met the minimum de-

asserted pulse width. The FIFOADDR lines are to be held

constant during the PKTEND assertion.

WRpwl

t

. If the SLCS is used, it must be in asserted with SLWR

WRpwh

or before SLWR is asserted.

·At t = 2, data must be present on the bus t

asserting edge of SLWR.

before the de-

SFD

·At t = 3, de-asserting SLWR will cause the data to be written

from the data bus to the FIFO and then increments the FIFO

Document #: 38-08032 Rev. *G

Page 50 of 55

CY7C68013A/CY7C68014A

CY7C68015A/CY7C68016A

10.0

Ordering Information

Table 10-1. Ordering Information

8051 Address

Ordering Code

Ideal for battery powered applications

CY7C68014A-128AXC

Package Type

RAM Size

# Prog I/Os

/Data Busses

128 TQFP – Lead-Free

100 TQFP – Lead-Free

56 SSOP – Lead-Free

56 QFN – Lead-Free

16K

40

24

26

16/8 bit

CY7C68014A-100AXC

–

CY7C68014A-56PVXC

CY7C68014A-56LFXC

CY7C68015A-56LFXC

Ideal for non-battery powered applications

CY7C68013A-128AXC

128 TQFP – Lead-Free

100 TQFP – Lead-Free

56 SSOP – Lead-Free

56 QFN – Lead-Free

16K

40

24

26

16/8 bit

CY7C68013A-100AXC

–

CY7C68013A-56PVXC

CY7C68013A-56LFXC

CY7C68015A-56LFXC

CY3684

EZ-USB FX2LP Development Kit

11.0

Package Diagrams

The FX2LP is available in four packages:

• 56-pin SSOP

• 56-pin QFN

• 100-pin TQFP

• 128-pin TQFP

Package Diagrams

51-85062-*C

Figure 11-1. 56-lead Shrunk Small Outline Package O56

Document #: 38-08032 Rev. *G

Page 51 of 55

CY7C68013A/CY7C68014A

CY7C68015A/CY7C68016A

Package Diagrams (continued)

Dimensions in millimeters

E-Pad size 4.3 mm x 5.0 mm (typ).

Figure 11-2. 56-lead Quad Flatpack No Lead Package (8 – 8 mm) LF56

51-85144-*D

51-85050-*A

Figure 11-3. 100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101

Document #: 38-08032 Rev. *G

Page 52 of 55

CY7C68013A/CY7C68014A

CY7C68015A/CY7C68016A

Package Diagrams (continued)

51-85101-*B

Figure 11-4. 128-Lead Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A128

PCB Layout Recommendations^[24]

• It is preferred is to have no vias placed on the DPLUS or

DMINUS trace routing.

12.0

The following recommendations should be followed to ensure

reliable high-performance operation.

• Isolate the DPLUS and DMINUS traces from all other signal

traces by no less than 10 mm.

• At least a four-layer impedance controlled boards are re-

quired to maintain signal quality.

13.0

Quad Flat Package No Leads (QFN)

• Specify impedance targets (ask your board vendor what

they can achieve).

Package Design Notes

Electrical contact of the part to the Printed Circuit Board (PCB)

is made by soldering the leads on the bottom surface of the

package to the PCB. Hence, special attention is required to the

heat transfer area below the package to provide a good

thermal bond to the circuit board. A Copper (Cu) fill is to be

designed into the PCB as a thermal pad under the package.

Heat is transferred from the FX2LP through the device’s metal

paddle on the bottom side of the package. Heat from here, is

conducted to the PCB at the thermal pad. It is then conducted

from the thermal pad to the PCB inner ground plane by a 5 x 5

array of via. A via is a plated through hole in the PCB with a

finished diameter of 13 mil. The QFN’s metal die paddle must

be soldered to the PCB’s thermal pad. Solder mask is placed

on the board top side over each via to resist solder flow into

the via. The mask on the top side also minimizes outgassing

during the solder reflow process.

• To controlimpedance, maintain trace widths and trace spac-

ing.

• Minimize stubs to minimize reflected signals.

• Connections between the USB connector shell and signal

ground must be done near the USB connector.

• Bypass/flyback caps on VBus, near connector, are recom-

mended.

• DPLUS and DMINUS trace lengths should be kept to within

2 mm of each other in length, with preferred length of 20-

30 mm.

• Maintain a solid ground plane under the DPLUS and DMI-

NUS traces. Do not allow the plane to be split under these

traces.

Note:

24. Source for recommendations: EZ-USB FX2™PCB Design Recommendations, http://www.cypress.com/cfuploads/support/app_notes/FX2_PCB.pdf and High

Speed USB Platform Design Guidelines, http://www.usb.org/developers/docs/hs_usb_pdg_r1_0.pdf.

Document #: 38-08032 Rev. *G

Page 53 of 55

CY7C68013A/CY7C68014A

CY7C68015A/CY7C68016A

For further information on this package design please refer to

the application note Surface Mount Assembly of AMKOR’s

MicroLeadFrame (MLF) Technology. This application note can

be downloaded from AMKOR’s website from the following

URL

http://www.amkor.com/products/notes_papers/MLF_AppNote

_0902.pdf. The application note provides detailed information

on board mounting guidelines, soldering flow, rework process,

etc.

Figure 13-1 below displays a cross-sectional area underneath

the package. The cross section is of only one via. The solder

paste template needs to be designed to allow at least 50%

solder coverage. The thickness of the solder paste template

should be 5 mil. It is recommended that “No Clean” type 3

solder paste is used for mounting the part. Nitrogen purge is

recommended during reflow.

Figure 13-2 is a plot of the solder mask pattern and Figure 13-

3 displays an X-Ray image of the assembly (darker areas

indicate solder).

0.017” dia

Solder Mask

Cu Fill

0.013” dia

PCB Material

Via hole for thermally connecting the

This figure only shows the top three layers of the

circuit board: Top Solder, PCB Dielectric, and

the Ground Plane

QFN to the circuit board ground plane.

Figure 13-1. Cross-section of the Area Underneath the QFN Package

Figure 13-2. Plot of the Solder Mask (White Area)

Figure 13-3. X-ray Image of the Assembly

Purchase of I C components from Cypress, or one of its sublicensed Associated Companies, conveys a license under the Philips

2

I C Patent Rights to use these components in an I C system, provided that the system conforms to the I C Standard Specification

as defined by Philips. EZ-USB FX2LP, EZ-USB FX2 and ReNumeration are trademarks, and EZ-USB is a registered trademark,

of Cypress Semiconductor Corporation. All product and company names mentioned in this document are the trademarks of their

respective holders.

Document #: 38-08032 Rev. *G

Page 54 of 55

of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be

used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its

products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress

CY7C68013A/CY7C68014A

CY7C68015A/CY7C68016A

Document History Page

Document Title: CY7C68013A EZ-USB FX2LP™ USB Microcontroller High-Speed USB Peripheral Controller

Document Number: 38-08032

Orig. of

REV.

**

ECN NO. Issue Date Change

Description of Change

124316

128461

03/17/03

09/02/03

VCS

New data sheet

*A

Added PN CY7C68015A throughout data sheet

Modified Figure 1-1 to add ECC block and fix errors

2

Removed word “compatible” where associated with I C

Corrected grammar and formatting in various locations

Updated Sections 3.2.1, 3.9, 3.11, Table 3-9, Section 5.0

Added Sections 3.15, 3.18.4, 3.20

Modified Figure 3-5 for clarity

Updated Figure 11-2 to match current spec revision

*B

*C

130335

131673

10/09/03

02/12/04

KKV

KKU

Restored PRELIMINARY to header (had been removed in error from rev. *A)

Section 8.1 changed “certified” to “compliant”

Table 8-1 added parameter V

and V

IH_X

IL_X

Added Sequence diagrams Section 9.16

Updated Ordering information with lead-free parts

Updated Registry Summary

Section 3.12.4:example changed to column 8 from column 9

Updated Figure 9-3 memory write timing Diagram

Updated section 3.9 (reset)

Updated section 3.15 ECC Generation

*D

230713

See ECN

KKU

Changed Lead free Marketing part numbers in Table 10-1 according to spec

change in 28-00054.

*E

*F

242398

271169

See ECN

TMD

MON

Minor Change: data sheet posted to the web,

Added USB-IF Test ID number

Added USB 2.0 logo

Added values for Isusp, Icc, Power Dessipation, Vih_x, Vil_x

Changed VCC from + 10% to + 5%

Changed E-Pad size to 4.3 mm x 5.0 mm

Changed PKTEND to FLAGS output propagation delay (asynchronous

interface) in Table 9-14 from a max value of 70 ns to 115 ns

*G

316313

See ECN

MON

Removed CY7C68013A-56PVXCT part availability

Added parts ideal for battery powered applications

-CY7C68014A

-CY7C68016A

Provided additional timing restrictions and requirement regarding the use of

PKETEND pin to commit a short one byte/word packet subsequent to

commiting a packet automatically (when in auto mode).

Added MIn Vcc Ramp Up time (0 to 3.3v)

Document #: 38-08032 Rev. *G

Page 55 of 55


型号：	CY7C68016A
厂家：	CYPRESS
描述：	EZ-USB FX2LP USB Microcontroller EZ- USB FX2LP USB微控制器微控制器
文件：	总55页 (文件大小：1861K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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