CY7C65215-32LTXI [CYPRESS]
USB Bus Controller, CMOS, QFN-32;
| 型号： | CY7C65215-32LTXI |
| 厂家： | 
CYPRESS |
| 描述： | USB Bus Controller, CMOS, QFN-32 时钟 外围集成电路 |
| 文件： | 总35页 (文件大小：421K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C65215
CY7C65215A
USB-Serial Dual Channel (UART/I2C/SPI)
Bridge with CapSense® and BCD
USB-Serial Dual Channel (UART/I2C/SPI) Bridge with CapSense® and BCD
❐ CapSense
❐ Charger detection
❐ GPIO
Features
■ USB 2.0 certified, Full-Speed (12 Mbps)
❐ Support for communication driver class (CDC), personal
■ Driver support for VCOM and DLL
❐ Windows 10: 32- and 64-bit versions
❐ Windows 8.1: 32- and 64-bit versions
❐ Windows 8: 32- and 64-bit versions
❐ Windows 7: 32- and 64-bit versions
❐ Windows Vista: 32- and 64-bit versions
❐ Windows XP: 32- and 64-bit versions
❐ Windows CE
health care device class (PHDC), and vendor device class
❐ Battery charger detection (BCD) compliant with USB Battery
Charging Specification Rev 1.2 (Peripheral Detect only)
❐ Integrated USB termination resistors
■ Two-channel configurable UART interfaces
❐ CY7C65215 supports 2-pin, 4-pin and 6-pin UART interface
whereas CY7C65215A supports 2-pin, 4-pin, 6-pin and 8-pin
UART interface
❐ Data rates up to 3 Mbps
❐ 190 bytes each transmit and receive buffer per channel
❐ Data format:
❐ Mac OS-X: 10.6, and later versions
❐ Linux: Kernel version 2.6.35 onwards
❐ Android: Gingerbread and later versions
• 7 or 8 data bits
• 1 or 2 stop bits
• No parity, even, odd, mark, or space parity
❐ Supports parity, overrun, and framing errors
❐ Supports flow control using CTS, RTS, DTR, DSR
❐ Supports UART break signal
■ Clocking: Integrated 48-MHz clock oscillator
■ Supports bus-/self-powered configurations
■ USB suspend mode for low power
■ Operating voltage: 1.71 to 5.5 V
■ Operating temperature:
❐ Commercial: 0 °C to 70 °C
❐ Industrial: –40 °C to 85 °C
❐ CY7C65215supportsdualchannelRS232/RS422interfaces
whereas CY7C65215A supports RS232/RS422/RS485
interfaces
■ Two-channel configurable SPI interfaces
❐ Data rate up to 3 MHz for SPI master and 1 MHz for SPI slave
❐ Data width: 4 bits to 16 bits
■ ESD protection: 2.2 kV HBM
■ RoHS compliant package
❐ 32-pin QFN (5 × 5 × 1 mm. 0.5 mm pitch)
❐ 256 bytes for each transmit and receive buffer per channel
❐ Supports Motorola, TI, and National SPI modes
■ Two-channel configurable I2C interfaces
❐ Master/slave up to 400 kHz
■ Ordering part number
❐ CY7C65215-32LTXI
❐ CY7C65215A-24LTXI
❐ Supports multi-master I2C
❐ 256 bytes for each transmit and receive buffer per channel
■ CapSense®
Applications
❐ SmartSense™ Auto-Tuning is supported through a
Cypress-supplied configuration utility
❐ Max CapSense buttons: 8
❐ GPIOs linked to CapSense buttons
■ JTAG interface: JTAG master for code flashing at 400 kHz
■ Medical/healthcare devices
■ Point-of-Sale (POS) terminals
■ Test and measurement system
■ Gaming systems
■ General-purpose input/output (GPIO) pins: 17
■ Set-top box PC-USB interface
■ Industrial
■ Supports unique serial number feature for each device, which
fixes the COM port number permanently when USB-Serial
Bridge controller as CDC device plugs in
■ Networking
■ Configuration utility (Windows) to configure the following:
■ Enabling USB connectivity in legacy peripherals
❐ Vendor ID (VID), Product ID (PID), and Product and Manu-
facturer descriptors
❐ UART/I2C/SPI/JTAG
USB Compliant
The USB-Serial Dual-Channel Bridge with CapSense and BCD (CY7C65215/CY7C65215A) is fully
compliant with the USB 2.0 specification and Battery Charging Specification v1.2, USB-IF Test-ID (TID)
40001521.
Cypress Semiconductor Corporation
Document Number: 001-81006 Rev. *K
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised May 4, 2017
CY7C65215
CY7C65215A
CY7C65215 and CY7C65215A Features Comparison
Table 1. CY7C65215 and CY7C65215A Features Comparison
Features
CY7C65215
CY7C65215A
UART
I2C
Can be configured as Virtual COM Can be configured as Virtual COM
port or USB vendor device
port or USB vendor device
Can be configured as USB vendor
device
Can be configured as Virtual COM
port or USB vendor device
SPI
Can be configured as USB vendor
device
Can be configured as Virtual COM
port or USB vendor device
RS485 Support
8-pin UART Support
JTAG Support
No
No
Yes
Yes
Yes
No
More Information
Cypress provides a wealth of data at www.cypress.com to help you to select the right device for your design, and to help you to quickly
and effectively integrate the device into your design. For a comprehensive list of resources, see the document USB-Serial Bridge
Controller Product Overview.
■ Overview: USB Portfolio, USB Roadmap
For complete list of knowledge base articles, click here.
■ USB 2.0 Product Selectors: USB-Serial Bridge Controller, USB
■ Code Examples: USB Full-Speed
to UART Controller (Gen I)
■ Development Kits:
■ Knowledge Base Articles: Cypress offers a large number of
USB knowledge base articles covering a broad range of topics,
from basic to advanced level. Recommended knowledge base
articles for getting started with USB-Serial Bridge Controller
are:
❐ CYUSBS232, Cypress USB-UART LP Reference Design Kit
❐ CYUSBS234, Cypress USB-Serial (Single Channel)
Development Kit
❐ CYUSBS236, Cypress USB-Serial (Dual Channel)
Development Kit
❐ KBA85909 – Key Features of the Cypress® USB-Serial
■ Models: IBIS
Cypress USB-Serial (Dual Channel) Development Kit
Bridge Controller
❐ KBA85920 – USB-UART and USB-Serial
❐ KBA85921
–
Replacing FT232R with CY7C65213
The Cypress USB-Serial (Dual Channel) Development Kit is a
complete development resource. It provides a platform to
develop and test custom projects. The development kit contains
collateral materials for the firmware, hardware, and software
aspects of a design.
USB-UART LP Bridge Controller
❐ KBA85913 – Voltage supply range for USB-Serial
❐ KBA89355 – USB Serial Cypress Default VID and PID
❐ KBA92641 – USB-Serial Bridge Controller Managing I/Os
using API
❐ KBA92442 – Non-Standard Baud Rates in USB-Serial Bridge
Controllers
❐ KBA91366
–
Binding
a
USB-Serial Device to
a
Microsoft® CDC Driver
❐ KBA92551 – Testing a USB-Serial Bridge Controller
Configured as USB-UART with Linux®
❐ KBA91299 – Interfacing an External I2C Device with the
CYUSBS234/236 DVK
Document Number: 001-81006 Rev. *K
Page 2 of 35
CY7C65215
CY7C65215A
Contents
Block Diagram ..................................................................4
Functional Overview ........................................................4
USB and Charger Detect .............................................4
Serial Communication .................................................5
CapSense ....................................................................6
JTAG Interface ............................................................6
GPIO Interface ............................................................6
Memory .......................................................................6
System Resources ......................................................6
Suspend and Resume .................................................7
WAKEUP .....................................................................7
Software ......................................................................7
Internal Flash Configuration ........................................8
Electrical Specifications ..................................................9
Absolute Maximum Ratings .........................................9
Operating Conditions ...................................................9
Device Level Specifications .........................................9
GPIO .........................................................................10
nXRES .......................................................................11
SPI Specifications .....................................................12
I2C Specifications ......................................................14
JTAG Specifications ..................................................14
CapSense Specifications ..........................................14
Flash Memory Specifications ....................................14
Pin Description ...............................................................15
USB Power Configurations ............................................18
USB Bus-Powered Configuration ..............................18
Self-Powered Configuration ......................................19
USB Bus Powered with Variable I/O Voltage ............20
Application Examples ....................................................21
USB-to-Dual UART Bridge
with Battery-Charge Detection ..........................................21
USB to RS485 Application ........................................23
CapSense ..................................................................24
USB to Dual Channel (I2C/SPI) Bridge .....................25
Ordering Information ......................................................30
Ordering Code Definitions .........................................30
Package Information ......................................................31
Acronyms ........................................................................32
Document Conventions .................................................32
Units of Measure .......................................................32
Document History Page .................................................33
Sales, Solutions, and Legal Information ......................35
Worldwide Sales and Design Support .......................35
Products ....................................................................35
PSoC® Solutions ......................................................35
Cypress Developer Community .................................35
Technical Support .....................................................35
Document Number: 001-81006 Rev. *K
Page 3 of 35
CY7C65215
CY7C65215A
Block Diagram
nXRES
Reset
Internal
48 MHz OSC
Internal
SCB 0
VDDD
VCCD
Voltage
Regulator
Channel 0
256 Bytes
UART/SPI/I2C
TX Buffer
UART/
SPI/I2C
32 KHz OSC
256 Bytes
RX Buffer
USB
SCB 1
VBUS
VBUS Regulator
256 Bytes
TX Buffer
Channel 1
UART/
SPI/I2C
UART/SPI/I2C
Battery Charger
Detection
256 Bytes
RX Buffer
USBDP
USBDM
GND
512 Bytes
Flash
Memory
SIE
CapSense
CapSense
USB
Transceiver with
Integrated
JTAG
(Master)
JTAG
GPIO
Resistor
GPIO
termination resistors on the USB data lines and a 1.5-k pull-up
resistor on USBDP.
Functional Overview
The CY7C65215/CY7C65215A is a Full-Speed USB controller
that enables seamless PC connectivity for peripherals with
dual-channel serial interfaces such as UART, SPI, and I2C.
CY7C65215/CY7C65215A also integrates CapSense and BCD,
which is compliant with the USB Battery Charging Specification
Rev. 1.2. It integrates a voltage regulator, oscillator, and flash
memory for storing configuration parameters, offering a
cost-effective solution. CY7C65215/CY7C65215A supports
bus-powered and self-powered modes, and enables efficient
system power management with suspend and remote wake-up
signals. It is available in a 32-pin QFN package.
Charger Detection
CY7C65215/CY7C65215A supports BCD for Peripheral Detect
only and complies with the USB Battery Charging Specification
Rev. 1.2. It supports the following charging ports:
■ Standard Downstream Port (SDP): allows the system to draw
up to 500 mA current from the host
■ Charging Downstream Port (CDP): allows the system to draw
up to 1.5 A current from the host
■ Dedicated Charging Port (DCP): allows the system to draw up
to 1.5 A of current from the wall charger
USB and Charger Detect
USB
CY7C65215/CY7C65215A has a built-in USB 2.0 Full-Speed
transceiver. The transceiver incorporates the internal USB series
Document Number: 001-81006 Rev. *K
Page 4 of 35
CY7C65215
CY7C65215A
Table 2 shows maximum speed supported on both SCBs when
they are configured as UART/I2C/SPI.
Serial Communication
CY7C65215/CY7C65215A has two serial communication blocks
(SCBs). Each SCB can implement UART, SPI, or an I2C
interface. A 256-byte buffer is available in both the TX and RX
lines.
Table 2. Maximum Speed supported on both SCBs
No.
1
Configuration
SCB0 Maximum Speed
SCB1 Maximum Speed
SCB0 = UART, SCB1 = Disabled
SCB0 = I2C Master, SCB1 = Disabled
SCB0 = I2CSlave, SCB1 = Disabled
SCB0 = SPI Master, SCB1 = Disabled
SCB0 = SPI Slave, SCB1 = Disabled
SCB0 = UART, SCB1 = UART
3M (Either TX/RX)
NA
NA
NA
NA
NA
2
400 kHz (Both TX and RX)
400 kHz (Both TX and RX)
3M (Both TX and RX)
1M (Both TX and RX)
1M (Either TX/RX)
3
4
5
6
1M (Either TX/RX)
7
SCB0 = UART, SCB1 = I2C Master
SCB0 = I2C Master, SCB1 = UART
SCB0 = UART, SCB1 = I2C Slave
SCB0 = I2C slave, SCB1 = UART
SCB0 = UART, SCB1 = SPI Master
SCB1 = SPI Master, SCB0 = UART
1M (Either TX/RX)
400 kHz (Both TX and RX)
8
9
1M (Either TX/RX)
1M (Either TX/RX)
1M (Either TX/RX)
400 kHz (Both TX and RX)
1M (Both TX and RX)
1M (Both TX and RX)
10 SCB0 = UART, SCB1 = SPI Slave
SCB0 = SPI Slave, SCB1 = UART
11 SCB0 = I2C, SCB1 = I2C
400 kHz (Both TX and RX)
1M (Both TX and RX)
400 kHz (Both TX and RX)
1M (Both TX and RX)
12 SCB0 = SPI, SCB1 = SPI
UART Interface
UART Flow Control
The UART interface provides asynchronous serial
communication with other UART devices operating at speeds of
up to 3 Mbps. It supports 7 to 8 data bits, 1 to 2 stop bits, odd,
even, mark, space, and no parity. The UART interface supports
full duplex communication with a signaling format that is
compatible with the standard UART protocol. In CY7C65215,
UART pins may be interfaced to industry standard
RS232/RS422 transceivers whereas in CY7C65215A these
UART pins may be interfaced to RS232/RS422/RS485.
The CY7C65215/CY7C65215A device supports UART
hardware flow control using control signal pairs such as RTS#
(Request to Send) / CTS# (Clear to Send) and DTR# (Data
Terminal Ready) / DSR# (Data Set Ready). Data flow control is
enabled by default. Flow control can be disabled using the
configuration utility.
The following section describes the flow control signals:
■ CTS# (Input) / RTS# (Output)
CY7C65215/CY7C65215A supports common UART functions
such as parity error and frame error. In addition,
CY7C65215/CY7C65215A supports baud rates ranging from
300 baud to 3 Mbaud. UART baud rates can be set using the
configuration utility.
CTS# can pause or resume data transmission over the UART
interface. Data transmission can be paused by de-asserting the
CTS signal and resumed with CTS# assertion. The pause and
resume operation does not affect data integrity. With flow control
enabled, receive buffer has a watermark level of 93%. After the
data in the receive buffer reaches that level, the RTS# signal is
de-asserted, instructing the transmitting device to stop data
transmission. The start of data consumption by the application
reduces device data backlog. When it reaches the 75%
watermark level, the RTS# signal is asserted to resume data
reception.
Notes:
Parity error gets detected when UART transmitter device is
configured for odd parity and UART receiver device is configured
for even parity.
Frame error gets detected when UART transmitter device is
configured for 7 bits data width and 1 stop bit, whereas UART
receiver device is configured for 8 bit data width and 2 stop bits.
■ DSR# (Input) /DTR# (Output)
DSR#/DTR# signals are used to establish the communication
link with the UART. These signals complement each other in their
functionality, similar to CTS# and RTS#.
Document Number: 001-81006 Rev. *K
Page 5 of 35
CY7C65215
CY7C65215A
SPI Interface
UART) serial interface is implemented. The configuration utility
allows configuration of the GPIO pins. The configurable options
are as follows:
The SPI interface supports SPI Master and SPI Slave. This
interface supports the Motorola, TI, and National Microwire
protocols. The maximum frequency of operation is 3 MHz in SPI
master mode and 1 MHz in SPI slave mode. It can support
transaction sizes ranging from 4 bits to 16 bits in length, SPI
slave supports 4 bits to 8 bits and 12 bits to 16 bits data width at
1 MHz operation. Whereas, it supports 9 bits,10 bits and 11 bits
data width operation at 500 kHz operation (for more details, refer
to USB to Dual Channel (I2C/SPI) Bridge on page 25).
■ TRISTATE: GPIO tristated
■ DRIVE 1: Output static 1
■ DRIVE 0: Output static 0
■ POWER#: Power control for bus power designs
■ TXLED#: Drives LED during USB transmit
■ RXLED#: Drives LED during USB receive
■ TX or RX LED#: Drives LED during USB transmit or receive
GPIO can be configured to drive LED at 8-mA drive strength.
I2C Interface
The I2C interface implements full multi-master/slave modes and
supports up to 400 kHz. The configuration utility tool is used to
set the I2C address in slave mode. This tool enables only even
slave addresses. For further details on protocol, refer to the NXP
I2C specification rev5.
■ BCD0/BCD1: Two-pin output to indicate the type of USB
charger
■ BUSDETECT: Connects VBUS pin for USB host detection
■ CS0–CS7: CapSense button input (Sense pin)
Notes
■ I2C ports are not tolerant of higher voltages and cannot be
hot-swapped or powered up independently from the rest of the
I2C system.
■ CSout0–CSout3: Indicates which CapSense button is pressed
■ Cmod: External modulator capacitor that connects a 2.2-nF
capacitor (±10%) to ground (GPIO_0 only)
■ The minimum fall time of the SCL is met (as per NXP I2C
specification Rev. 5) when VDDD is between 1.71 V and 3.0 V.
When VDDD is within the range of 3.0 V to 3.6 V, it is
recommended to add a 50 pF capacitor on the SCL signal.
■ Cshield: Shield for waterproofing
Memory
CY7C65215/CY7C65215A has a 512-byte flash. The flash is
used to store the USB parameters such as VID/PID, serial
number, Product, and Manufacturer Descriptors, which can be
programmed by the configuration utility.
CapSense
CapSense functionality is supported on all the GPIO pins. Any
GPIO pin can be configured as a sense pin (CS0–CS7) using the
configuration utility. When implementing CapSense functionality,
the GPIO_0 pin (configured as the modulator capacitor - Cmod)
should be connected to ground through a 2.2-nF capacitor (see
Figure 12 on page 24). CY7C65215/CY7C65215A supports
SmartSense auto-tuning of CapSense parameters and does not
require manual tuning. SmartSense auto-tuning compensates
for printed circuit board (PCB) variations and device process
variations.
System Resources
Power System
CY7C65215/CY7C65215A supports the USB Suspend mode to
control power usage. CY7C65215/CY7C65215A operates in
bus-powered or self-powered modes over a range of 3.15 to
5.5 V.
Optionally, any GPIO pin can be configured as a Cshield and
connected to the shield of the CapSense button as shown in
Figure 12 on page 24. The shield prevents false triggering of
buttons due to water droplets and guarantees CapSense
operation (sensors respond to finger touch). GPIOs can be
linked to CapSense buttons to indicate the presence of a finger.
CapSense functionality can be configured using configuration
utility.
Clock System
CY7C65215/CY7C65215A has a fully integrated clock and does
not require any external components. The clock system is
responsible for providing clocks to all subsystems.
Internal 48-MHz Oscillator
The internal 48-MHz oscillator is the primary source of internal
clocking in CY7C65215/CY7C65215A.
CY7C65215/CY7C65215A supports up to eight CapSense
buttons. For more information on CapSense, refer to Getting
Started with CapSense.
Internal 32-kHz Oscillator
The internal 32-kHz oscillator is primarily used to generate
clocks for peripheral operation in the USB Suspend mode.
JTAG Interface
CY7C65215/CY7C65215A supports a 5-pin JTAG in master
mode for code flashing at 400 kHz.
Reset
Note: When JTAG is enabled, other interfaces in the
CY7C65215/CY7C65215A device cannot be used.
The reset block ensures reliable power-on reset and brings the
device back to the default known state. The nXRES (active low)
pin can be used by external devices to reset the
CY7C65215/CY7C65215A.
GPIO Interface
CY7C65215/CY7C65215A has 17 GPIOs. A maximum of 17
GPIOs are available for configuration if one 2-pin (I2C/2-pin
Document Number: 001-81006 Rev. *K
Page 6 of 35
CY7C65215
CY7C65215A
In addition, the CY7C65215 device also supports the native Mac
OSx CDC UART driver, and CY7C65215A supports native Mac
OSx CDC UART/SPI/I2C driver.
Suspend and Resume
The CY7C65215/CY7C65215A device asserts the SUSPEND
pin when the USB bus enters the suspend state. This helps in
meeting the stringent suspend current requirement of the USB
2.0 specification, while using the device in bus-powered mode.
The device will resume from the suspend state under any of the
following conditions:
Drivers for Windows Operating Systems
For Windows operating systems (XP, Vista, Win7, Win8, and
Win8.1), Cypress delivers a User Mode dynamically linked
library–CyUSBSerial DLL–that abstracts vendor-specific
interface of CY7C65215/CY7C65215A devices and provides
convenient APIs to the user. It provides interface APIs for
vendor-specific UART/SPI/I2C and class-specific APIs for
PHDC.
1. Any activity is detected on the USB bus
2. The WAKEUP pin is asserted to generate remote wakeup to
the host
WAKEUP
USB-Serial Bridge Controller works with the Windows-standard
USB CDC class driver, when either CY7C65215 is configured as
CDC USB to UART device or when CY7C65215A is configured
as CDC USB to UART/SPI/I2C device. A virtual COM port
driver–CyUSBSerial.sys–is also delivered, which implements
the USB CDC class driver. The Cypress Windows drivers are
Windows hardware certification kit-compliant.
The WAKEUP pin is used to generate a remote wakeup signal
on the USB bus. The remote wakeup signal is sent only if the
host enables this feature through the SET_FEATURE request.
The device communicates support for the remote wakeup to the
host through the configuration descriptor during the USB
enumeration process. The CY7C65215/CY7C65215A device
allows enabling/disabling and polarity of the remote wakeup
feature through the configuration utility.
These drivers are bound to device through WU (Windows
Update) services.
Software
Cypress drivers also support Windows plug-and-play and power
management and USB Remote Wake-up.
Cypress delivers a complete set of software drivers and the
configuration utility to enable product configuration during
system development.
Windows-CE support
The CY7C65215/CY7C65215A solution includes a CDC UART
driver library for Windows-CE platforms.
Drivers for Linux Operating Systems
Cypress provides a User Mode USB driver library (libcyusb-
serial.so) that abstracts vendor commands for the UART
interface and provides a simplified API interface to the user appli-
cations. This library makes use of the standard open source
libUSB library to enable the USB communication. The Cypress
serial library supports the USB plug-and-play feature using the
Linux 'udev' mechanism.
Device Configuration Utility (Windows Only)
A Windows-based configuration utility is available to configure
various device initialization parameters. This graphical user
application provides an interactive interface to define the various
boot parameters stored in the device flash.
This utility allows the user to save a user-selected configuration
to text or xml formats. It also allows users to load a selected
configuration from text or xml formats. The configuration utility
allows the following operations:
CY7C65215/CY7C65215A supports the standard USB CDC
UART class driver, which is bundled with the Linux kernel.
Android Support
■ View current device configuration
The CY7C65215/CY7C65215A solution includes an Android
Java class–CyUsbSerial.java–which exposes a set of interface
functions to communicate with the device.
■ Select and configure UART/I2C/SPI, CapSense, battery
charging, and GPIOs
■ Configure USB VID, PID, and string descriptors
■ Save or Load configuration
Drivers for Mac OSx
Cypress delivers
a
dynamically linked shared library
You can download the free configuration utility and drivers from
www.cypress.com.
(CyUSBSerial.dylib) based on libUSB, which enables
communication to the CY7C65215/CY7C65215A device.
Document Number: 001-81006 Rev. *K
Page 7 of 35
CY7C65215
CY7C65215A
Internal Flash Configuration
The internal flash memory can be used to store the configuration parameters shown in the following table. A free configuration utility
is provided to configure the parameters listed in the table to meet application specific requirements over USB interface. The configu-
ration utility can be downloaded from www.cypress.com/go/usbserial.
Table 3. Internal Flash Configuration for both CY7C65215 and CY7C65215A
Parameter
Default Value
Description
USB Configuration
USB Vendor ID (VID)
USB Product ID (PID)
Manufacturer string
Product string
0x04B4
0x0005
Cypress
Default Cypress VID. Can be configured to customer VID
Default Cypress PID. Can be configured to customer PID
Can be configured with any string up to 64 characters
USB-Serial (Dual Channel) Can be configured with any string up to 64 characters
Can be configured with any string up to 64 characters
Serial string
Power mode
Bus powered
100 mA
Can be configured to bus-powered or self-powered mode
Max current draw
Can be configured to any value from 0 to 500 mA. Based on this, the config-
uration descriptor will be updated.
Remote wakeup
USB interface protocol
BCD
Enabled
CDC
Can be disabled. Remote wakeup is initiated by asserting WAKEUP pin
Can be configured to function in CDC, PHDC, or Cypress vendor class
Disabled
Charger detect is disabled by default. When BCD is enabled, three of the
GPIOs must be configured for BCD
GPIO Configuration
GPIO_0
GPIO_1
GPIO_2
GPIO_3
GPIO_4
GPIO_5
GPIO_6
GPIO_7
GPIO_8
GPIO_9
GPIO_10
GPIO_11
GPIO_12
GPIO_13
GPIO_14
GPIO_15
GPIO_16
GPIO_17
GPIO_18
TXLED#
RXLED#
DSR#_0
RTS#_0
CTS#_0
TxD_0
POWER#
TRISTATE
RxD_0
DTR#_0
RxD_1
GPIO can be configured as shown in Table 18 on page 17.
TxD_1
RTS#_1
CTS#1
DSR#_1
DTR#_1
TRISTATE
TRISTATE
TRISTATE
Document Number: 001-81006 Rev. *K
Page 8 of 35
CY7C65215
CY7C65215A
Electrical Specifications
Static discharge voltage ESD protection levels:
Absolute Maximum Ratings
Exceeding maximum ratings [1] may shorten the useful life of the
device.
■ 2.2-kV HBM per JESD22-A114
Latch-up current ........................................................... 140 mA
Current per GPIO ........................................................... 25 mA
Storage temperature .................................... –55 °C to +100 °C
Ambient temperature with
Operating Conditions
power supplied (Industrial) ............................ –40 °C to +85 °C
Supply voltage to ground potential
VDDD ..................................................................................6.0 V
TA (ambient temperature under bias)
Industrial ........................................................ –40 °C to +85 °C
VBUS ..................................................................................6.0 V
VCCD ................................................................................1.95 V
VGPIO ............................................................... .....VDDD + 0.5 V
V
BUS supply voltage ........................................ 3.15 V to 5.25 V
VDDD supply voltage ........................................ 1.71 V to 5.50 V
CCD supply voltage ........................................ 1.71 V to 1.89 V
V
Device Level Specifications
All specifications are valid for –40 °C TA 85 °C, TJ 100 °C, and 1.71 V to 5.50 V, except where noted.
Table 4. DC Specifications
Parameter
VBUS
Description
VBUS supply voltage
Min
3.15
4.35
Typ
3.30
5.00
Max
3.45
5.25
Units
Details/Conditions
V
V
Set and configure correct voltage
range using the configuration
utility for VBUS
.
VDDD
VDDD supply voltage
1.71
2.0
1.80
3.3
1.89
5.5
V
V
Used to set I/O and core voltage.
Set and configure correct voltage
range using the configuration
utility for VDDD
.
VCCD
Output voltage (for core logic)
–
1.80
–
V
Do not use this supply to drive
external device.
• 1.71 V VDDD 1.89 V: Short
the VCCD pin with the VDDD pin
• VDDD > 2 V – connect a 1-µF
capacitor (Cefc) between the
VCCD pin and ground
Cefc
IDD1
External regulator voltage bypass
Operating supply current
1.00
–
1.30
13
1.60
18
µF
X5R ceramic or better
mA
USB 2.0 FS, UART at 1 Mbps
single channel,
no GPIO switching at
VBUS = 5 V, VDDD = 5 V
IDD2
USB Suspend supply current
–
5
–
µA
Does not include current through
a pull-up resistor on USBDP.
In USB suspend mode, the D+
voltage can go up to a maximum
of 3.8 V.
Table 5. AC Specifications
Parameter
Description
Min
28
–
Typ
–
Max
44
–
Units
Details/Conditions
Zout
USB driver output impedance
Twakeup
Wakeup from USB Suspend mode
25
µs
Note
1. Usage above the absolute maximum conditions may cause permanent damage to the device. Exposure to Absolute Maximum conditions for extended periods of
time may affect device reliability. When used below Absolute Maximum conditions but above normal operating conditions the device may not operate to specification.
Document Number: 001-81006 Rev. *K
Page 9 of 35
CY7C65215
CY7C65215A
GPIO
Table 6. GPIO DC Specification
Parameter
Description
Min
Typ
–
Max
Units
Details/Conditions
[2]
VIH
Input voltage high threshold
Input voltage low threshold
LVTTL input, VDDD< 2.7 V
LVTTL input, VDDD < 2.7 V
LVTTL input, VDDD > 2.7 V
LVTTL input, VDDD > 2.7 V
CMOS output voltage high level
0.7 × VDDD
–
V
V
V
V
V
V
V
CMOS Input
VIL
VIH
VIL
VIH
VIL
–
–
0.3 × VDDD
CMOS Input
[2]
[2]
0.7 × VDDD
–
–
–
–
0.3 × VDDD
2
–
–
0.8
–
–
–
VOH
VOH
VOH
VOL
VOL
VOL
VDDD – 0.4
–
IOH = 4 mA,
VDDD = 5 V +/- 10%
CMOS output voltage high level
CMOS output voltage high level
CMOS output voltage low level
CMOS output voltage low level
CMOS output voltage low level
VDDD – 0.6
–
–
–
–
–
–
V
V
V
V
V
IOH = 4 mA,
VDDD = 3.3 V +/- 10%
VDDD – 0.5
–
IOH = 1 mA,
VDDD = 1.8 V +/- 5%
–
–
–
0.4
0.6
0.6
IOL = 8 mA,
VDDD = 5 V +/- 10%
IOL = 8 mA,
VDDD = 3.3 V +/- 10%
IOL = 4 mA,
VDDD = 1.8 V +/- 5%
Rpullup
Rpulldown
IIL
Pull-up resistor
3.5
5.6
5.6
–
8.5
8.5
2
kΩ
kΩ
nA
pF
Pull-down resistor
3.5
Input leakage current (absolute value)
Input capacitance
–
25 °C, VDDD = 3.0 V
CIN
–
25
–
7
Vhysttl
Vhyscmos
Input hysteresis LVTTL; VDDD > 2.7 V
Input hysteresis CMOS
40
–
–
mV
mV
0.05 × VDDD
–
Table 7. GPIO AC Specification
Parameter Description
TRiseFast1
Min
Typ
Max
Units
Details/Conditions
Rise Time in Fast mode
Fall Time in Fast mode
Rise Time in Slow mode
Fall Time in Slow mode
2
–
12
ns
VDDD = 3.3 V/ 5.5 V,
Cload = 25 pF
TFallFast1
TRiseSlow1
TFallSlow1
2
–
–
–
12
60
60
ns
ns
ns
VDDD = 3.3 V/ 5.5 V,
Cload = 25 pF
10
10
VDDD = 3.3 V/ 5.5 V,
Cload = 25 pF
VDDD = 3.3 V/ 5.5 V,
Cload = 25 pF
TRiseFast2
TFallFast2
TRiseSlow2
TFallSlow2
Rise Time in Fast mode
Fall Time in Fast mode
Rise Time in Slow mode
Fall Time in Slow mode
2
20
2
–
–
–
–
20
100
20
ns
ns
ns
ns
VDDD = 1.8 V, Cload = 25 pF
VDDD = 1.8 V, Cload = 25 pF
VDDD = 1.8 V, Cload = 25 pF
VDDD = 1.8 V, Cload = 25 pF
20
100
Note
2.
V
must not exceed V
+ 0.2 V.
IH
DDD
Document Number: 001-81006 Rev. *K
Page 10 of 35
CY7C65215
CY7C65215A
nXRES
Table 8. nXRES DC Specifications
Parameter
VIH
Description
Min
Typ
–
Max
Units
V
Details/Conditions
Input voltage high threshold
Input voltage low threshold
Pull-up resistor
0.7 × VDDD
–
VIL
–
3.5
–
–
0.3 × VDDD
V
Rpullup
CIN
5.6
5
8.5
–
kΩ
pF
Input capacitance
Vhysxres
Input voltage hysteresis
–
100
–
mV
Table 9. nXRES AC Specifications
Parameter
Description
Reset pulse width
Min
Typ
Max
Units
Details/Conditions
Details/Conditions
Tresetwidth
1
–
–
µs
Table 10. UART AC Specifications
Parameter Description
FUART UART bit rate
Min
Typ
Max
Units
0.3
–
3000
kbps
Single SCB: TX + RX
Dual SCB: TX or RX
Document Number: 001-81006 Rev. *K
Page 11 of 35
CY7C65215
CY7C65215A
SPI Specifications
Figure 1. SPI Master Timing
FSPI
SCK
(CPOL=0,
Output)
SCK
(CPOL=1,
Output)
TDSI
MISO
(input)
MSB
THMO
LSB
TDMO
MOSI
(output)
MSB
LSB
SPI Master Timing for CPHA = 0 (Refer to Table 17)
FSPI
SCK
(CPOL=0,
Output)
SCK
(CPOL=1,
Output)
TDSI
MISO
(input)
LSB
THMO
MSB
TDMO
MOSI
(output)
MSB
LSB
SPI Master Timing for CPHA = 1 (Refer to Table 17)
Document Number: 001-81006 Rev. *K
Page 12 of 35
CY7C65215
CY7C65215A
Figure 2. SPI Slave Timing
SSN
(Input)
FSPI
SCK
(CPOL=0,
Input)
TSSELSCK
SCK
(CPOL=1,
Input)
TDSO
THSO
MISO
(Output)
MSB
MSB
LSB
LSB
TDMI
MOSI
(Input)
SPI Slave Timing for CPHA = 0 (Refer to Table 17)
SSN
(Input)
FSPI
SCK
(CPOL=0,
Input)
TSSELSCK
SCK
(CPOL=1,
Input)
THSO
TDSO
MISO
(Ouput)
LSB
LSB
MSB
MSB
TDMI
MOSI
(Input)
SPI Slave Timing for CPHA = 1 (Refer to Table 17)
Document Number: 001-81006 Rev. *K
Page 13 of 35
CY7C65215
CY7C65215A
Table 11. SPI AC Specifications
Parameter Description
FSPI
Min
Typ
Max
Units
Details/Conditions
SPI operating frequency
(Master/Slave)
–
–
3
MHz
Single SCB: TX + RX
Dual SCB: TX or RX
WLSPI
SPI word length
4
–
16
bits
SPI Master Mode
TDMO
MOSI valid after SClock driving edge
–
–
–
15
–
ns
ns
TDSI
MISO valid before SClock capturing
edge
20
THMO
Previous MOSI data hold time with
respect to capturing edge at slave
0
–
–
ns
SPI Slave Mode
TDMI
MOSI valid before Sclock Capturing
edge
40
–
–
ns
TDSO
MISO valid after Sclock driving edge
Previous MISO data hold time
–
0
–
–
–
104.4
ns
ns
ns
THSO
–
–
TSSELSCK
SSEL valid to first SCK valid edge
100
2
I C Specifications
Table 12. I2C AC Specifications
Parameter
FI2C
Description
I2C frequency
Min
Typ
Max
Units
Details/Conditions
1
–
400
kHz
JTAG Specifications
Table 13. JTAG AC Specifications
Parameter
FJTAG
Description
JTAG operating frequency (master)
Min
Typ
Max
Units
Details/Conditions
–
–
400
kHz
Code flashing
CapSense Specifications
Table 14. CapSense AC Specifications
Parameter
VCSD
SNR
Description
Min
1.71
5
Typ
–
Max
5.50
–
Units
V
Details/Conditions
Voltage range of operation
Ratio of counts of finger to noise
–
Ratio
Sensor capacitance range of
9 to 35 pF; finger capacitance
>= 0.1 pF sensitivity
Flash Memory Specifications
Table 15. Flash Memory Specifications
Parameter
Fend
Fret
Description
Flash endurance
Min
100 K
10
Typ
Max
Units
Details/Conditions
–
–
–
–
cycles
years
Flash retention. TA 85 °C, 10 K
program/erase cycles
Document Number: 001-81006 Rev. *K
Page 14 of 35
CY7C65215
CY7C65215A
Pin Description
Pin[3]
Type
Name
Default
Description
1
Power
VDDD
–
Supply to the device core and Interface, 1.71 to 5.5 V
2
3
SCB/GPIO
SCB/GPIO
Power
SCB0_0
GPIO_8
GPIO_9
RxD_0
DTR#_0
–
GPIO/SCB0. See Table 16 and Table 18 on page 17
GPIO/SCB0. See Table 16 and Table 18 on page 17
Digital Ground
SCB0_5
4
VSSD
5
SCB/GPIO
SCB/GPIO
SCB/GPIO
SCB/GPIO
SCB/GPIO
SCB/GPIO
Output
SCB1_0
SCB1_1
SCB1_2
SCB1_3
SCB1_4
SCB1_5
GPIO_10
GPIO_11
GPIO_12
GPIO_13
GPIO_14
GPIO_15
RxD_1
TxD_1
RTS#_1
CTS#_1
DSR#_1
DTR#_1
–
GPIO/SCB1. See Table 17 and Table 18 on page 17
GPIO/SCB1. See Table 17 and Table 18 on page 17
GPIO/SCB1. See Table 17 and Table 18 on page 17
GPIO/SCB1. See Table 17 and Table 18 on page 17
GPIO/SCB1. See Table 17 and Table 18 on page 17
GPIO/SCB1. See Table 17 and Table 18 on page 17
6
7
8
9
10
11
SUSPEND
Indicates device in suspend mode. Can be configured as active
low/high using configuration utility
12
Input
WAKEUP
–
Wakeup device from suspend mode. Can be configured as
active low/high using configuration utility
13
14
GPIO
GPIO_16
USBDP
TRISTATE
–
GPIO. See Table 18 on page 17
USBIO
USB DataSignal Plus, integrates termination resistor and 1.5-k
pull up resistor
15
16
17
18
USBIO
Power
Power
nXRES
USBDM
VCCD
VSSD
–
–
–
–
USB Data Signal Minus, integrates termination resistor
Regulated supply, connect to 1-µF cap or 1.8 V
Digital Ground
nXRES
Chip reset, active low. Can be left unconnected or have a pull-up
resistor connected if not used.
19
20
21
22
23
24
Power
Power
GPIO
GPIO
Power
Power
VBUS
VSSD
–
VBUS Supply, 3.15 V to 5.25 V
Digital Ground
–
GPIO_17
GPIO_18
VDDD
TRISTATE
GPIO. See Table 18 on page 17
GPIO. See Table 18 on page 17
Supply to the device core and Interface, 1.71 to 5.5 V
Analog Ground
TRISTATE
–
–
VSSA
25
26
27
28
GPIO
GPIO
GPIO_0
GPIO_1
TXLED#
RXLED#
DSR#_0
RTS#_0
GPIO. See Table 18 on page 17
GPIO. See Table 18 on page 17
SCB/GPIO
SCB/GPIO
SCB0_1
GPIO_2
GPIO_3
GPIO/SCB0. See Table 16 and Table 18 on page 17
GPIO/SCB0. See Table 16 and Table 18 on page 17
SCB0_2
29
30
31
32
SCB/GPIO
SCB/GPIO
GPIO
SCB0_3
SCB0_4
GPIO_4
GPIO_5
CTS#_0
TxD_0
GPIO/SCB0. See Table 16 and Table 18 on page 17
GPIO/SCB0. See Table 16 and Table 18 on page 17
GPIO. See Table 18 on page 17
GPIO_6
GPIO_7
POWER#
TRISTATE
GPIO
GPIO. See Table 18 on page 17
Note
3. Any pin acting as an Input pin should not be left unconnected.
Document Number: 001-81006 Rev. *K
Page 15 of 35
CY7C65215
CY7C65215A
Figure 3. 32-Pin QFN Pinout
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
VSSA
VDDD
VDDD
SCB0_0/GPIO_8
SCB0_5/GPIO_9
VSSD
CY7C65215 /
CY7C65215A
GPIO_18
GPIO_17
VSSD
32 QFN
-
SCB1_0/GPIO_10
SCB1_1/ GPIO_11
VBUS
Top View
nXRES
VSSD
SCB1_2/GPIO_12
SCB1_3/GPIO_13
Table 16. Serial Communication Block (SCB0) Configuration
Mode 0*
Mode 1
Mode 2
Mode 3
SPI Master
GPIO_8
Mode 4
Mode 5
I2C Master
Mode 6
I2C Slave
GPIO_8
GPIO_2
Pin
Serial Port 0
6-pin UART 4-pin UART 2-pin UART
SPI Slave
RxD_0
DSR#_0
RTS#_0
CTS#_0
TxD_0
RxD_0
GPIO_2
RTS#_0
CTS#_0
TxD_0
RxD_0
GPIO_2
GPIO_3
GPIO_4
TxD_0
GPIO_8
GPIO_8
2
SCB0_0
SCB0_1
SCB0_2
SCB0_3
SCB0_4
SCB0_5
SSEL_OUT_0 SSEL_IN_0
GPIO_2
27
28
29
30
3
MISO_IN_0 MISO_OUT_0 SCL_OUT_0 SCL_IN_0
MOSI_OUT_0 MOSI_IN_0
SCLK_OUT_0 SCLK_IN_0
SDA_0
GPIO_5
GPIO_9
SDA_0
GPIO_5
GPIO_9
DTR#_0
GPIO_9
GPIO_9
GPIO_9
GPIO_9
*Note: Device configured in Mode 0 as default. Other modes can be configured through Cypress-supplied configuration utility.
Table 17. Serial Communication Block (SCB1) Configuration
Mode 0*
Mode 1
Mode 2
Mode 3
Mode 4
Mode 5
Mode 6
Mode 7
Pin
Serial Port 1
6-pin
UART
4-pin
UART
2-pin
UART
JTAG
Master
SPI Master
SPI Slave
I2C Master I2C Slave
RxD_1
TxD_1
RxD_1
TxD_1
RxD_1
TxD_1
MISO_IN_1 MISO_OUT_1 SCL_OUT_1 SCL_IN_1
TDO
TDI
5
6
SCB1_0
SCB1_1
SCB1_2
SCB1_3
SCB1_4
SCB1_5
MOSI_OUT_1 MOSI_IN_1
SDA_1
SDA_1
RTS#_1
CTS#_1
RTS#_1
CTS#_1
GPIO_12 SSEL_OUT_1 SSEL_IN_1
GPIO_13 SCLK_OUT_1 SCLK_IN_1
GPIO_12
GPIO_13
GPIO_14
GPIO_15
GPIO_12
GPIO_13
GPIO_14
TMS
TCK
7
8
DSR#_1 GPIO_14 GPIO_14
DTR#_1 GPIO_15 GPIO_15
GPIO_14
GPIO_15
GPIO_14
GPIO_15
TRST#
9
GPIO_15 GPIO_15
10
*Note: Device configured in Mode 0 as default. Other modes can be configured via Cypress-supplied configuration utility.
GPIO
SCB0
SCB1
Document Number: 001-81006 Rev. *K
Page 16 of 35
CY7C65215
CY7C65215A
Table 18. GPIO Configuration
GPIO Configuration Option
TRISTATE
Description
I/O tristated
DRIVE 1
Output static 1
Output static 0
DRIVE 0
POWER#
This output is used to control power to an external logic via switch to cut power off during
unconfigured USB device and USB suspend.
0 - USB device in Configured state
1 - USB device in Unconfigured state or during USB suspend mode
TXLED#
RXLED#
Drives LED during USB transmit
Drives LED during USB receive
TX or RX LED#
Drives LED during USB transmit or receive
BCD0
BCD1
Configurable battery charger detect pins to indicate type of USB charger (SDP, CDP, or
DCP)
Configuration example:
00 - Draw up to 100 mA (Unconfigured state)
01 - SDP (up to 500 mA)
10 - CDP/DCP (up to 1.5 A)
11 - Suspend (up to 2.5 mA)
This truth table can be configured using the configuration utility
BUSDETECT
VBUS detection. Connect VBUS to this pin via resistor network for VBUS detection when
using BCD feature (refer to page 20).
CS0, CS1, CS2, CS3, CS4, CS5, CS6, CapSense button input (Max up to 8)
CS7
CSout0, CSout1, CSout2, CSout3
Indicates which CapSense button is pressed
Cmod
External modulator capacitor, connect a 2.2 nF capacitor (±10%) to ground
(Available on GPIO_0 only)
Cshield (optional)
Shield for waterproofing
Note: These signal options can be configured on any of the available GPIO pins using Cypress-supplied configuration utility.
Document Number: 001-81006 Rev. *K
Page 17 of 35
CY7C65215
CY7C65215A
USB Power Configurations
The following section describes possible USB power configurations for the CY7C65215/CY7C65215A. Refer to the Pin Description
on page 15 for signal details.
USB Bus-Powered Configuration
Figure 4 shows an example of the CY7C65215/CY7C65215A in
a bus-powered design. VBUS is connected directly to the
CY7C65215/CY7C65215A because it has an internal regulator.
The USB bus-powered system must comply with the following
requirements:
3. A high-power bus-powered system (can draw more than
100 mA when operational) must use POWER# (configured
over GPIO) to keep the current consumption below 100 mA
prior to USB enumeration, and 2.5 mA during USB Suspend
state.
1. The system should not draw more than 100 mA prior to USB
enumeration (Unconfigured state).
4. The system should not draw more than 500 mA from the USB
host.
2. The system should not draw more than 2.5 mA during USB
Suspend mode.
The configuration descriptor in the CY7C65215/CY7C65215A
flash should be updated to indicate bus power and the maximum
current required by the system using the configuration utility.
Figure 4. Bus-Powered Configuration
CY7C65215/CY7C65215A
GPIO_0
25
26
27
GPIO_1
GPIO_2 / SCB0_1
GPIO_3 / SCB0_2
28
29
GPIO_4 / SCB0_3
GPIO_5 / SCB0_4
GPIO_6
30
31
32
2
GPIO_7
GPIO_8 / SCB0_0
GPIO_9 / SCB0_5
1
3
USB
VDDD
CONNECTOR
5
6
7
8
19
14
15
GPIO_10 / SCB1_0
GPIO_11 / SCB1_1
GPIO_12 / SCB1_2
VBUS
USBDP
USBDM
VBUS
D+
D-
GND
GPIO_13 / SCB1_3
GPIO_14 / SCB1_4
GPIO_15 / SCB1_5
GPIO_16
4.7 uF
0.1 uF
8
10
13
21
22
18
GPIO_17
XRES
VCCD
GPIO_18
11
12
16
SUSPEND
WAKEUP
1 uF
24 20 17
4
Document Number: 001-81006 Rev. *K
Page 18 of 35
CY7C65215
CY7C65215A
Self-Powered Configuration
Figure 5 shows an example of CY7C65215/CY7C65215A in a
self-powered design.
In this configuration:
removes the 1.5-k pull-up resistor on USBDP, and this ensures
no current flows from the USBDP to the USB host via a 1.5-k
pull-up resistor, to comply with USB 2.0 specification.
When reset is asserted to CY7C65215, all the I/O pins are
tristated.
Using the configuration utility, the configuration descriptor in the
CY7C65215/CY7C65215A flash should be updated to indicate
that it is self-powered.
■ VBUS is powered from USB VBUS. VBUS pin is also used to
detect USB connection.
■ VDDD is powered from an external power supply.
When VBUS is present, CY7C65215/CY7C65215A enables an
internal, 1.5-k pull-up resistor on USBDP. When VBUS is
absent (USB host is powered down), CY7C65215/CY7C65215A
Figure 5. Self-Powered Configuration
3.3 V
3.3 V
CY7C65215/CY7C65215A
GPIO_0
25
26
27
GPIO_1
GPIO_2 / SCB0_1
GPIO_3 / SCB0_2
1
28
29
VDDD
VBUS
GPIO_4 / SCB0_3
GPIO_5 / SCB0_4
GPIO_6
19
30
31
32
2
GPIO_7
GPIO_8 / SCB0_0
GPIO_9 / SCB0_5
3
USB
CONNECTOR
5
6
7
8
GPIO_10 / SCB1_0
GPIO_11 / SCB1_1
GPIO_12 / SCB1_2
VBUS
D+
D-
14
15
USBDP
USBDM
GND
GPIO_13 / SCB1_3
GPIO_14 / SCB1_4
GPIO_15 / SCB1_5
GPIO_16
8
10
13
0.1 uF
4.7 uF
18 4.7 KO
21
22
GPIO_17
XRES
VCCD
GPIO_18
10 KO
11
12
16
SUSPEND
WAKEUP
1 uF
24 20 17
4
Document Number: 001-81006 Rev. *K
Page 19 of 35
CY7C65215
CY7C65215A
USB Bus Powered with Variable I/O Voltage
Figure 6 shows CY7C65215/CY7C65215A in a bus-powered
system with variable I/O voltage. A low dropout (LDO) regulator
is used to supply 1.8 V or 3.3 V (using a jumper switch) the input
of which is 5 V from VBUS. Another jumper switch is used to
select 1.8/3.3 V or 5 V from VBUS for the VDDD pin of
CY7C65215/CY7C65215A. This allows I/O voltage and supply
to external logic to be selected among 1.8 V, 3.3 V, or 5 V.
■ The system should not draw more than 2.5 mA during USB
Suspend mode.
■ A high-power bus-powered system (can draw more than 100
mA when operational) must use POWER# (configured over
GPIO) to keep the current consumption below 100 mA prior to
USB enumeration and 2.5 mA during USB Suspend state.
The USB bus-powered system must comply with the following:
■ The system should not draw more than 100 mA prior to USB
enumeration (Unconfigured state).
Figure 6. USB Bus-Powered with 1.8 V, 3.3 V, or 5 V Variable I/O Voltage [4]
Power
Switch
CY7C65215/CY7C65215A
GPIO_0
25
26
27
GPIO_1
1.8v or 3.3v or 5v
Supply to External Logic
GPIO_2 / SCB0_1
GPIO_3 / SCB0_2
28
29
GPIO_4 / SCB0_3
GPIO_5 / SCB0_4
GPIO_6
30
31
32
2
1.8/3.3 V
GPIO_7
GPIO_8 / SCB0_0
GPIO_9 / SCB0_5
1
2
3
1
Jumper to select
1.8 V/3.3 V or 5 V
3
VDDD
5
6
7
8
19
14
15
GPIO_10 / SCB1_0
GPIO_11 / SCB1_1
GPIO_12 / SCB1_2
VBUS
USBDP
USBDM
VBUS
D+
D-
GND
USB
CONNECTOR
GPIO_13 / SCB1_3
GPIO_14 / SCB1_4
GPIO_15 / SCB1_5
GPIO_16
0.1uF
8
10
13
21
22
18
GPIO_17
XRES
VCCD
GPIO_18
VBUS
11
12
16
SUSPEND
WAKEUP
TC 1070
Vout Vin
SHDn
Vadj GND
1.8/3.3 V
1 uF
0.1 uF
24 20 17
4
1M
1uF
1 2 3
VBUS
VDDD
0.1 uF
3.3 V
1.8 V
562K
2M
4.7 uF
0.1 uF
4.7 uF
Jumper to select
1.8 V or 3.3 V
Note
4. 1.71 V VDDD 1.89 V - Short VCCD pin with VDDD pin; VDDD > 2 V - connect a 1-µF decoupling capacitor to the VCCD pin.
Document Number: 001-81006 Rev. *K
Page 20 of 35
CY7C65215
CY7C65215A
Application Examples
The following section provides CY7C65215/CY7C65215A application examples.
USB-to-Dual UART Bridge with Battery-Charge Detection
CY7C65215/CY7C65215A can connect any embedded system,
with a serial port, to a host PC through USB.
CY7C65215/CY7C65215A enumerates as a dual COM port on
the host PC.
SUSPEND is connected to the MCU to indicate USB suspend or
USB Unconfigured and the WAKEUP pin is used to wake up
CY7C65215/CY7C65215A, which in turn issues a remote
wakeup to the USB host. GPIO1 and GPIO0 are configured as
RXLED# and TXLED# to drive two LEDs indicating data receive
and transmit respectively.
CY7C65215/CY7C65215A implements the battery charger
detection functionality based on the USB Battery Charging
Specification Rev 1.2.
Battery-operated bus power systems must comply with the
following conditions:
■ The system should not draw more than 500 mA for SDP and
1.5 A for CDP/DCP
To comply with the first requirement, VBUS from the USB host is
connected
to
the
battery
charger
as
well
as
CY7C65215/CY7C65215A as shown in Figure 7. When VBUS
is connected, CY7C65215/CY7C65215A initiates battery
charger detection and indicates the type of USB charger over
BCD0 and BCD1. If the USB charger is SDP or CDP,
CY7C65215/CY7C65215A enables a 1.5-K pull-up resistor on
the USBDP for Full-Speed enumeration. When VBUS is
disconnected CY7C65215/CY7C65215A indicates absence of
the USB charger over BCD0 and BCD1, and removes the 1.5-K
pull-up resistor on USBDP. Removing this resistor ensures no
current flows from the supply to the USB host through the
USBDP, to comply with the USB 2.0 specification.
To comply with the second and third requirements, two signals
(BCD0 and BCD1) are configured over GPIO to communicate
the type of USB host charger and the amount of current it can
draw from the battery charger. The BCD0 and BCD1 signals can
be configured using the configuration utility.
■ Thesystemcanbepoweredfromthe battery(ifnotdischarged)
and be operational if VBUS is not connected or powered down.
■ The system should not draw more than 100 mA from the VBUS
prior to USB enumeration and USB Suspend mode.
Figure 7. USB to Dual UART Bridge with Battery Charge Detection[5]
CY7C65215/CY7C65215A
VCC
28
29
30
2
RTS#_0
GPIO_3 / SCB0_2
CTS#
RTS#
CTS#_0
TXD_0
GPIO_4 / SCB0_3
1
GPIO_5 / SCB0_4
GPIO_8 / SCB0_0
RXD
TXD
VDDD
MCU
10K
10K
RXD_0
EN1
22
13
BCD0
BCD1
SYS
BAT
GPIO_18
GPIO_16
Battery
Charger
(MAX8856)
12
11
I/O
I/O
WAKEUP
EN2
SUSPEND
GND
IN
VCC
VCC
RTS#_1
CTS#_1
TXD_1
7
8
6
5
RTSout
RTSin
19
GPIO_12 / SCB1_2
GPIO_13 / SCB1_3
GPIO_11 / SCB1_1
VBUS
OVP
VBUS
D+
D-
GND
1K
1K
14
15
RS232
Level
Convertor
USBDP
USBDM
CTSin
TXDout
RXDin
CTSout
TXDin
RXD_1
0.1 uF
GPIO_10 / SCB1_0
RXDout
USB
CONNECTOR
18
XRES
TXLED#
RXLED#
25
26
GPIO_0
GPIO_1
16
VBUS
0.1 uF
VDDD
VCCD
1 uF
4.7 uF
24 20 17
4
4.7 uF
0.1 uF
Note
5. Add a 100 K pull-down resistor on the V
pin for quick discharge.
BUS
Document Number: 001-81006 Rev. *K
Page 21 of 35
CY7C65215
CY7C65215A
In a battery charger system.a 9-V spike on the VBUS is possible. The CY7C65215/CY7C65215A VBUS pin is intolerant to voltage
above 6 V. In the absence of over-voltage protection (OVP) on the VBUS line, VBUS should be connected to BUSDETECT (GPIO
configured) using the resistive network and the output of battery charger to the VBUS pin of CY7C65215/CY7C65215A, as shown in
the following figure.
B
A
Rs
Rs = 10 K
VBUS
VBUS = VDDD
SYS
BAT
CY7C65215/
CY7C65215A
Battery Charger
B
B
A
R1
R2
R1 = 10 k?
R2/(R1+R2) = VDDD/VBUS
BUSDETECT
A
GPIO
VBUS > VDDD
VBUS
When VBUS and VDDD are at the same voltage potential, VBUS
can be connected to GPIO using a series resistor (Rs). This is
shown in Figure 8. If there is a charger failure and VBUS
becomes 9 V, then the 10-k resistor plays two roles. It reduces
the amount of current flowing into the forward biased diodes in
the GPIO, and it reduces the voltage seen on the pad.
When VBUS > VDDD, a resistor voltage divider is necessary to
reduce the voltage from VBUS down to VDDD for the GPIO
sensing the VBUS voltage. This is shown in the following figure.
The resistors should be sized as follows:
R1 >= 10 K
R2 / (R1 + R2) = VDDD / VBUS
The first condition limits the voltage and current for the charger
failure situation, as described in the previous paragraph, while
the second condition allows for normal-operation VBUS
detection.
Figure 8. GPIO VBUS Detection, VBUS = VDDD
VDDD
BUSDETECT
CY7C65215/
CY7C65215A
VBUS
Rs
Figure 9. GPIO VBUS Detection, VBUS > VDDD
VDDD
BUSDETECT
CY7C65215/
CY7C65215A
VBUS
R1
R2
Document Number: 001-81006 Rev. *K
Page 22 of 35
CY7C65215
CY7C65215A
GPIO can be configured using USB-Serial Configuration utility.
Figure 11 shows timing diagram of this GPIO.
USB to RS485 Application
CY7C7C65215 can be configured as dual USB to UART
interface. This UART interface operates at TTL level and it can
be converted to RS485 interface using a GPIO and any half
duplex RS485 transceiver IC (to convert TTL level to RS485
level) as shown in following figure. This GPIO (TXD Enable)
enables and disables the RS485 transceiver IC based on
availability of character in UART buffer of CY7C65215A. This
RS485 is a multi-drop network – i.e. many devices can
communicate with each other over a single two wire cable
connection. The RS485 cable requires to be terminated at each
end of the cable. Links are provided to allow the cable to be
terminated if the device is physically positioned at either end of
the cable.
Figure 10. USB to RS485 Bridge
CY7C65215A
VCC
30
2
TXD_0
RXD_0
GPIO_5 / SCB0_4
TXDout RS485
TXDin
Level
1
GPIO_8 / SCB0_0
RXDout
Convertor
VDDD
RXDin
1.8/3.3 V
GND
TXDEN
6
GPIO_17
1
2
3
VDDD
VCC
VDDD
VDDD
19
VBUS
VBUS
D+
D-
GND
1K
1K
TXD_1
RXD_1
14
15
6
5
RS485
Level
Convertor
GPIO_11 / SCB1_1
GPIO_10 / SCB1_0
USBDP
USBDM
TXDin
TXDout
RXDin
GND
RXDout
TXDEN
USB
CONNECTOR
6
18
GPIO_18
XRES
TXLED#
RXLED#
25
26
GPIO_0
GPIO_1
VBUS
TC 1070
1.8/3.3 V
16
Vout
Vin
VCCD
4
SHDn
0.1 uF
VBUS
0.1 uF
VDDD
0.1 uF
1 uF
Vadj GND
24 20 17
1M
1uF
1 2 3
4.7 uF
4.7 uF
3.3 V
1.8 V
562K
2M
Jumper to select
1.8 V or 3.3 V
Figure 11. RS485 GPIO (TXDEN) Timing diagram
Document Number: 001-81006 Rev. *K
Page 23 of 35
CY7C65215
CY7C65215A
CapSense
In Figure 12 CY7C65215/CY7C65215A is configured to support
six CapSense buttons. Three GPIOs (CSout0, CSout1, and
CSout2) are configured to indicate which CapSense button is
pressed by the finger. It also implements a 2-pin UART on SCB0
and a 4-pin UART on SCB1.
A 2.2-nF (10%) capacitor (Cmod) must be connected on the
GPIO_0 pin for proper CapSense operation. Optionally, the
GPIO_7 pin is configured as Cshield and connected to the shield
of the CapSense (pin 2 of Watershield jumper) as shown in
Figure 12. The shield prevents false triggering of buttons due to
water droplets and guarantees CapSense operation (sensors
respond to finger touch).
For further information on CapSense, refer to Getting Started
with CapSense.
Figure 12. CapSense Schematic
CY7C65215/CY7C65215A
GPIO_5 / SCB0_4
VCC
1
VDDD
VDDD
23
30
2
TXD_0
RXD_0
Jumper to select
Shield or No shield
Capsense
button
No
button
pressed
CS0
CS1
CS2
CS3
CS4
RXD
TXD
CSout2 CSout0 CSout1
GPIO_8 / SCB0_0
Cshield
1
2
3
32
0
0
0
GPIO_7
27
CSout0
0
0
0
1
1
1
0
1
1
0
0
1
1
0
1
0
1
0
GPIO_2 / SCB0_1
GPIO_3 / SCB0_2
GPIO_4 / SCB0_3
GPIO_6
I/O
MCU
3
9
28
29
31
CSout1
CSout2
I/O
I/O
GPIO_9 / SCB0_5
GPIO_14 / SCB1_4
CS0
CS1
560R
560R
560R
CS5
10
CS2
GPIO_15 / SCB1_5
GPIO_18
12
11
22
21
CS3
CS4
CS5
WAKEUP
I/O
I/O
560R
560R
SUSPEND
GPIO_17
GPIO_16
13
VCC
560R
1K
RTS#_1
CTS#_1
TXD_1
7
RTSout
RTSin
GPIO_12 / SCB1_2
GPIO_13 / SCB1_3
GPIO_11 / SCB1_1
8
6
5
RS232
Level
Convertor
CTSin
TXDout
RXDin
CTSout
TXDin
19
VBUS
VBUS
D+
D-
GND
14
15
RXD_1
GPIO_10 / SCB1_0
RXDout
USBDP
USBDM
0.1 uF
18
26
25
USB
CONNECTOR
GPIO_1
GPIO_0
XRES
VCCD
Cmod
16
2.2 nF
VBUS
0.1 uF
VDDD
0.1 uF
1 uF
24 20 17
4
4.7 uF
4.7 uF
Document Number: 001-81006 Rev. *K
Page 24 of 35
CY7C65215
CY7C65215A
USB to Dual Channel (I2C/SPI) Bridge
In Figure 13, CY7C65215/CY7C65215A is configured as a USB-to-Dual Channel (I2C/SPI) Bridge. GPIO1 and GPIO0 are configured
as RXLED# and TXLED# to drive two LEDs indicating data USB receive and transmit respectively.
Figure 13. USB to I2C/SPI Bridge
1.8/3.3 V
VDDD
CY7C65215/CY7565215A
2.2K
2.2K
1
2
3
1
Jumper to select
1.8 V/3.3 V or 5 V
VDDD
VCC
SCL
SDA
28
29
GPIO_3 / SCB0_2
GPIO_4 / SCB0_3
I2C
Master/Slave
GND
19
VDDD
VBUS
USBDP
USBDM
VBUS
D+
D-
14
15
USB
CONNECTOR
10K
GND
0.1 uF
7
5
SSEL
MISO
VCC
GPIO_12 / SCB1_2
GPIO_10 / SCB1_0
SPI
6
8
Master/Slave
MOSI
SCLK
GPIO_11 / SCB1_1
GPIO_13 / SCB1_3
18
GND
XRES
16
VCCD
4
VBUS
1 uF
VBUS
0.1 uF
VDDD
0.1 uF
TC 1070
Vout Vin
SHDn
Vadj GND
1.8/3.3 V
24 20 17
0.1 uF
4.7 uF
4.7 uF
1M
1uF
1 2 3
3.3 V
1.8 V
562K
2M
Jumper to select
1.8 V or 3.3 V
I2C
The CY7C65215/CY7C65215A I2C can be configured as a
Master or Slave using the configuration utility.
CY7C65215/CY7C65215A supports I2C data rates up to
100 kbits/s in the standard mode (SM) and 400 kbits/s in the fast
mode (FM).
SPI
The CY7C65215/CY7C65215A SPI can be configured as a
Master or Slave using the configuration utility.
CY7C65215/CY7C65215A supports SPI master frequency up to
3 MHz and SPI slave frequency up to 1 MHz. It can support
transaction sizes ranging from 4 bits to 16 bits, which can be
configured using the configuration utility.
In
the
master
mode,
SCL
is
output
from
CY7C65215/CY7C65215A. In the slave mode, SCL is input to
CY7C65215/CY7C65215A. The I2C slave address for
CY7C65215/CY7C65215A can be configured using the config-
uration utility. The SDA data line is bi-directional in the master
and slave modes. The drive modes of the SCL and SDA port pins
are always open drain.
In the master mode, SCLK, MOSI and SSEL lines act as output
and MISO acts as an input. In the slave mode, SCL SCLK, MOSI,
and SSEL lines act as input and MISO acts as an output.
CY7C65215/CY7C65215A supports three versions of the SPI
protocol:
■ Motorola - This is the original SPI protocol.
Refer to the NXP I2C specification for further details on protocol.
■ Texas Instruments - A variation of the original SPI protocol in
which data frames are identified by a pulse on the SSEL line.
■ National Semiconductors - A half-duplex variation of the
original SPI protocol.
Document Number: 001-81006 Rev. *K
Page 25 of 35
CY7C65215
CY7C65215A
Motorola
When not transmitting data, the SSEL line is '1' and SCLK is
typically off.
The Motorola SPI protocol has four different modes that
determine how data is driven and captured on the MOSI and
MISO lines. These modes are determined by clock polarity
(CPOL) and clock phase (CPHA). Clock polarity determines the
value of the SCLK line when not transmitting data:
The original SPI protocol is defined by Motorola. It is a full-duplex
protocol: transmission and reception occur at the same time.
A single (full-duplex) data transfer follows these steps: The
master selects a slave by driving its SSEL line to '0'. Next, it
drives data on its MOSI line and it drives a clock on its SCLK line.
The slave uses the edges of the transmitted clock to capture the
data on the MOSI line. The slave drives data on its MISO line.
The master captures the data on the MISO line. The process is
repeated for all the bits in the data transfer.
■ CPOL is '0': SCLK is '0' when not transmitting data.
■ CPOL is '1': SCLK is '1' when not transmitting data.
Multiple data transfers may happen without the SSEL line
changing from '0' to '1' and back from '1' to '0' in between the
individual transfers. As a result, slaves must keep track of the
progress of data transfers to separate individual transfers.
Clock phase determines when data is driven and captured. It is
dependent on the value of CPOL:
Table 19. SPI Protocol Modes
Mode
CPOL
CPHA
Description
0
1
2
3
0
0
1
1
0
1
0
1
Data is driven on a falling edge of SCLK. Data is captured on a rising edge of SCLK
Data is driven on a rising edge of SCLK. Data is captured on a falling edge of SCLK
Data is driven on a rising edge of SCLK. Data is captured on a falling edge of SCLK
Data is driven on a falling edge of SCLK. Data is captured on a rising edge of SCLK
Figure 14. Driving and Capturing of MOSI/MISO Data As A Function of CPOL and CPHA
CPOL: ‘0’, CPHA: ‘0’
SCLK
MOSI/MISO
MSB
LSB
CPOL: ‘0’, CPHA: ‘1’
CPOL: ‘1’, CPHA: ‘0’
SCLK
MOSI/MISO
MSB
LSB
SCLK
MOSI/MISO
MSB
LSB
CPOL: ‘1’, CPHA: ‘0’
SCLK
MOSI/MISO
MSB
LSB
LEGEND:
CPOL:
CPHA:
SCLK:
MOSI:
MISO:
Clock Polarity
Clock Phase
SPI interface clock
SPI Master Out / Slave In
SPI Master In / Slave Out
Document Number: 001-81006 Rev. *K
Page 26 of 35
CY7C65215
CY7C65215A
Figure 15. Single 8-bit Data Transfer and Two Successive 8-bit Data Transfers in Mode 0 (CPOL is ‘0’, CPHA is ‘0’)
CPOL: ‘0’, CPHA: ‘0’, single data transfer
SCLK
SSEL
MOSI
MISO
MSB
MSB
LSB
LSB
CPOL: ‘0’, CPHA: ‘0’, two successive data transfers
SCLK
SSEL
MOSI
MISO
MSB
MSB
LSB MSB
LSB
LSB
LSB
MSB
LEGEND:
CPOL:
CPHA:
SCLK:
SSEL:
Clock Polarity
Clock Phase
SPI interface clock
SPI slave select
MOSI:
MISO:
SPI Master Out / Slave In
SPI Master In / Slave Out
Document Number: 001-81006 Rev. *K
Page 27 of 35
CY7C65215
CY7C65215A
Texas Instruments
The TI SPI protocol only supports mode 1 (CPOL is '0' and CPHA
is '1'): data is driven on a rising edge of SCLK and data is
captured on a falling edge of SCLK.
The following figure illustrates a single 8-bit data transfer and two
successive 8-bit data transfers. The SSEL pulse precedes the
first data bit. Note how the SSEL pulse of the second data
transfer coincides with the last data bit of the first data transfer.
The Texas Instruments' SPI protocol redefines the use of the
SSEL signal. It uses the signal to indicate the start of a data
transfer, rather than a low, active slave-select signal. The start of
a transfer is indicated by a high, active pulse of a single-bit
transfer period. This pulse may occur one cycle before the
transmission of the first data bit, or may coincide with the
transmission of the first data bit. The transmitted clock SCLK is
a free-running clock.
Single data transfer
SCLK
SSEL
MOSI
MSB
MSB
LSB
LSB
MISO
SCLK
Two successive data transfers
SSEL
MOSI
MSB
MSB
LSB
LSB
MSB
MSB
LSB
LSB
MISO
LEGEND:
SCLK:
SSEL:
MOSI:
MISO:
SPI interface clock
SPI slave select pulse
SPI Master Out / Slave In
SPI Master In / Slave Out
The following figure illustrates a single 8-bit data transfer and two successive 8-bit data transfers. The SSEL pulse coincides with the
first data bit.
Single data transfer
SCLK
SSEL
MOSI
MISO
MSB
MSB
LSB
LSB
Two successive data transfers
SCLK
SSEL
MOSI
MISO
MSB
MSB
LSB
LSB
MSB
MSB
LSB
LSB
LEGEND:
SCLK:
SPI interface clock
SSEL:
SPI slave select pulse
MOSI:
MISO:
SPI Master Out / Slave In
SPI Master In / Slave Out
Document Number: 001-81006 Rev. *K
Page 28 of 35
CY7C65215
CY7C65215A
National Semiconductors
The transmission data transfer size and reception data transfer
size may differ. The National Semiconductors' SPI protocol only
supports mode 0: data is driven on a falling edge of SCLK and
data is captured on a rising edge of SCLK.
The following figure illustrates a single data transfer and two
successive data transfers. In both cases, the transmission data
transfer size is 8 bits and the reception transfer size is 4 bits.
The National Semiconductors' SPI protocol is a half-duplex
protocol. Rather than transmission and reception occurring at
the same time, transmission and reception take turns (trans-
mission happens before reception). A single “idle” bit transfer
period separates transmission from reception.
Note: Successive data transfers are NOT separated by an “idle”
bit transfer period.
Single data transfer
SCLK
SSEL
MOSI
MISO
MSB
LSB
MSB
LSB
“idle” ‘0’ cycle
Two successive data transfers
SCLK
SSEL
MOSI
MISO
MSB
LSB
MSB
MSB
“idle” ‘0’ cycle
LSB
no “idle” cycle
LEGEND:
SCLK:
SSEL:
MOSI:
MISO:
SPI interface clock
SPI slave select
SPI Master Out / Slave In
SPI Master In / Slave Out
The above figure defines MISO and MOSI as undefined when
the lines are considered idle (not carrying valid information). It
will drive the outgoing line values to '0' during idle time (to satisfy
the requirements of specific master devices (NXP LPC17xx) and
specific slave devices (MicroChip EEPROM)).
Document Number: 001-81006 Rev. *K
Page 29 of 35
CY7C65215
CY7C65215A
Ordering Information
Table 20 lists the CY7C65215/CY7C65215A key package features and ordering codes. For more information, contact your local sales
representative.
Table 20. Key Features and Ordering Information
Package
Ordering Code
CY7C65215-32LTXI
Operating Range
Industrial
32-pin QFN (5 × 5 × 1 mm, 0.5 mm pitch) (Pb-free)
32-pin QFN (5 × 5 × 1 mm, 0.5 mm pitch) (Pb-free) – Tape CY7C65215-32LTXIT
and Reel
Industrial
32-pin QFN (5 × 5 × 1 mm, 0.5 mm pitch) (Pb-free)
CY7C65215A-32LTXI
Industrial
Industrial
32-pin QFN (5 × 5 × 1 mm, 0.5 mm pitch) (Pb-free) – Tape CY7C65215A-32LTXIT
and Reel
Ordering Code Definitions
CY
7
C
65 XXXX - 32 LT
X
I
X
X = blank or T
blank = Tube; T = Tape and Reel
Temperature Range:
I = Industrial
Pb-free
Package Type:
LT = QFN
Number of pins: 32 pins
Part Number: XXXX = 215 or 215A
Family Code:
65 = USB Hubs
Technology Code: C = CMOS
Marketing Code: 7 = Cypress products
Company ID: CY = Cypress
Document Number: 001-81006 Rev. *K
Page 30 of 35
CY7C65215
CY7C65215A
Package Information
The package currently planned to be supported is the 32-pin QFN.
Figure 16. 32-pin QFN 5 × 5 × 1.0 mm LT32B 3.5 × 3.5 EPAD (Sawn)
001-30999 *D
Table 21. Package Characteristics
Parameter Description
Min
–40
–
Typ
25
Max
85
–
Units
°C
TA
THJ
Operating ambient temperature
Package JA
19
°C/W
Table 22. Solder Reflow Peak Temperature
Package
Maximum Peak Temperature
Maximum Time at Peak Temperature
32-pin QFN
260 °C
30 seconds
Table 23. Package Moisture Sensitivity Level (MSL), IPC/JEDEC J-STD-2
Package
MSL
32-pin QFN
MSL 3
Document Number: 001-81006 Rev. *K
Page 31 of 35
CY7C65215
CY7C65215A
Acronyms
Document Conventions
Table 24. Acronyms Used in this Document
Units of Measure
Acronym
BCD
CDC
CDP
DCP
DLL
Description
battery charger detection
Table 25. Units of Measure
Symbol
Unit of Measure
communication driver class
charging downstream port
dedicated charging port
dynamic link library
C
degree Celsius
DMIPS
dhrystone million instructions per second
k
kilo-ohm
KB
kilobyte
ESD
GPIO
HBM
I2C
electrostatic discharge
general purpose input/output
human-body model
kHz
kV
kilohertz
kilovolt
Mbps
MHz
mm
V
megabits per second
megahertz
millimeter
volt
inter-integrated circuit
Microcontroller Unit
MCU
OSC
PHDC
PID
oscillator
personal health care device class
Product Identification
SCB
SCL
serial communication block
I2C Serial Clock
SDA
SDP
SIE
I2C Serial Data
Standard Downstream Port
serial interface engine
serial peripheral interface
virtual communication port
Universal Serial Bus
SPI
VCOM
USB
UART
VID
universal asynchronous receiver transmitter
Vendor Identification
Document Number: 001-81006 Rev. *K
Page 32 of 35
CY7C65215
CY7C65215A
Document History Page
Document Title: CY7C65215/CY7C65215A, USB-Serial Dual Channel (UART/I2C/SPI) Bridge with CapSense® and BCD
Document Number: 001-81006
Orig. of
Change
Submission
Date
Revision
ECN
Description of Change
*G
*H
4287738
4430603
SAMT
MVTA
02/21/2014 Updated Ordering Information (Updated part numbers).
07/11/2014 Updated Features.
Updated Functional Overview:
Updated JTAG Interface:
Updated description.
Updated Software:
Updated Drivers for Windows Operating Systems:
Updated description.
Updated Electrical Specifications:
Updated Device Level Specifications:
Updated Table 4:
Updated details in “Details/Conditions” column of VBUS and VDDD parameters.
Updated typical and maximum values of IDD1 parameter.
Updated details in “Details/Conditions” column of IDD1 parameter.
Updated Table 5:
Removed F1 and F2 parameters and their details.
Updated GPIO:
Updated Table 6:
Updated details in “Description” column of VOH and VOL parameters.
Updated Pin Description:
Updated Table 17:
Updated details in “Mode 7” column of pin 6 and pin 7.
Updated USB Power Configurations:
Updated Self-Powered Configuration:
Updated description.
Updated Figure 5.
Updated Application Examples:
Updated CapSense:
Updated description.
Updated Figure 12.
Completing Sunset Review.
*I
4807404
RRSH
06/23/2015 Updated Features.
Updated Functional Overview:
Updated Serial Communication:
Updated UART Interface:
Updated description.
Updated I2C Interface:
Updated description.
Updated System Resources:
Updated Power System:
Updated description.
Updated Internal 32-kHz Oscillator:
Updated description.
Updated Reset:
Updated description.
Updated Software:
Updated Drivers for Windows Operating Systems:
Updated description.
Updated Windows-CE support:
Updated description.
Updated Electrical Specifications:
Updated Operating Conditions:
Updated details corresponding to VBUS supply voltage.
Updated Device Level Specifications:
Updated Table 4:
Changed maximum value of VBUS parameter from 5.25 V to 5.5 V.
Updated GPIO:
Updated Table 6:
Updated details in “Description” column of VOH and VOL parameters.
Document Number: 001-81006 Rev. *K
Page 33 of 35
CY7C65215
CY7C65215A
Document History Page (continued)
Document Title: CY7C65215/CY7C65215A, USB-Serial Dual Channel (UART/I2C/SPI) Bridge with CapSense® and BCD
Document Number: 001-81006
Orig. of
Change
Submission
Date
Revision
ECN
Description of Change
*I (cont.)
4807404
RRSH
06/23/2015 Updated Pin Description:
Updated details in “Description” column of pin 19.
Updated Application Examples:
Updated USB to Dual Channel (I2C/SPI) Bridge:
Updated description.
Updated to new template.
Completing Sunset Review.
*J
5063358
MVTA
12/24/2015 Updated Document Title to read as “CY7C65215/CY7C65215A, USB-Serial
Dual Channel (UART/I2C/SPI) Bridge with CapSense® and BCD”.
Included details of CY7C65215A part number in all instances across the
document.
Updated Features:
Updated description.
Added CY7C65215 and CY7C65215A Features Comparison.
Added More Information.
Updated Functional Overview:
Updated Serial Communication:
Added Table 2.
Updated UART Interface:
Updated description.
Updated UART Flow Control:
Updated description.
Updated SPI Interface:
Updated description.
Updated Electrical Specifications:
Updated Operating Conditions:
Updated details corresponding to “VBUS supply voltage”.
Updated Device Level Specifications:
Updated Table 4:
Changed maximum value of VBUS parameter from 5.5 V to 5.25 V.
Updated details in “Details/Conditions” column corresponding to IDD2
parameter.
Updated Pin Description:
Updated details in “Description” column corresponding to VBUS pin.
Updated USB Power Configurations:
Updated USB Bus-Powered Configuration:
Updated Figure 4.
Updated Self-Powered Configuration:
Updated Figure 5.
Updated USB Bus Powered with Variable I/O Voltage:
Updated Figure 6.
Updated Application Examples:
Updated USB-to-Dual UART Bridge with Battery-Charge Detection:
Updated Figure 7.
Added USB to RS485 Application.
Updated CapSense:
Updated Figure 12.
Updated USB to Dual Channel (I2C/SPI) Bridge:
Updated Figure 13.
Updated Ordering Information:
Updated part numbers.
Updated Ordering Code Definitions.
*K
5726562
GNKK
05/04/2017 Updated the Cypress logo and copyright information.
Document Number: 001-81006 Rev. *K
Page 34 of 35
CY7C65215
CY7C65215A
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
Products
PSoC® Solutions
Automotive
cypress.com/go/automotive
cypress.com/go/clocks
cypress.com/go/interface
cypress.com/go/powerpsoc
cypress.com/go/memory
cypress.com/go/psoc
psoc.cypress.com/solutions
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP
Clocks & Buffers
Interface
Cypress Developer Community
Lighting & Power Control
Memory
Community | Forums | Blogs | Video | Training
Technical Support
PSoC
cypress.com/go/support
Touch Sensing
USB Controllers
Wireless/RF
cypress.com/go/touch
cypress.com/go/USB
cypress.com/go/wireless
© Cypress Semiconductor Corporation, 2012-2017. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress
hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to
modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users
(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as
provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation
of the Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent
permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any
product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is
the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products
are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or
systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the
device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably
expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim,
damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other
liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners
Document Number: 001-81006 Rev. *K
Revised May 4, 2017
Page 35 of 35
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