CY7C53120E4-40SIT
更新时间：2024-09-18 18:55:02
品牌：CYPRESS
描述：LAN Controller, 5 Channel(s), CMOS, PDSO32, 0.450 INCH, SOIC-32
概述
规格参数
数据手册CY7C53120E4-40SIT 概述
LAN Controller, 5 Channel(s), CMOS, PDSO32, 0.450 INCH, SOIC-32 串行 IO/通信控制器
CY7C53120E4-40SIT 规格参数
| 生命周期： | Obsolete | 零件包装代码： | SOIC |
| 包装说明： | SOP, | 针数： | 32 |
| Reach Compliance Code： | unknown | HTS代码： | 8542.31.00.01 |
| 风险等级： | 5.82 | 地址总线宽度： | |
| 边界扫描： | NO | 最大时钟频率： | 40 MHz |
| 数据编码/解码方法： | DIFF BIPHASE-LEVEL | 外部数据总线宽度： | |
| JESD-30 代码： | R-PDSO-G32 | JESD-609代码： | e0 |
| 长度： | 20.447 mm | 低功率模式： | NO |
| 串行 I/O 数： | 5 | 端子数量： | 32 |
| 最高工作温度： | 85 °C | 最低工作温度： | -40 °C |
| 封装主体材料： | PLASTIC/EPOXY | 封装代码： | SOP |
| 封装形状： | RECTANGULAR | 封装形式： | SMALL OUTLINE |
| 认证状态： | Not Qualified | 座面最大高度： | 2.8194 mm |
| 最大供电电压： | 5.5 V | 最小供电电压： | 4.5 V |
| 标称供电电压： | 5 V | 表面贴装： | YES |
| 技术： | CMOS | 温度等级： | INDUSTRIAL |
| 端子面层： | TIN LEAD | 端子形式： | GULL WING |
| 端子节距： | 1.27 mm | 端子位置： | DUAL |
| 宽度： | 11.303 mm | uPs/uCs/外围集成电路类型： | SERIAL IO/COMMUNICATION CONTROLLER, LAN |
| Base Number Matches： | 1 |
CY7C53120E4-40SIT 数据手册
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PDF下载CY7C53150
CY7C53120
Neuron® Chip Network Processor
Features
Functional Description
• Three eight-bit pipelined processors for concurrent
processing of application code and network traffic
• 11-pin I/O port programmablein 34 modes for fast appli-
cation program development
• Two 16-bit timer/counters for measuring and gener-
ating I/O device waveforms
• Five-pin communication port that supports direct
connect and network transceiver interfaces
• Programmable pull-ups on IO4–IO7 and 20-mA sink
current on IO0–IO3
• Unique 48-bit ID number in every device to facilitate
network installation and management
The CY7C531x0 Neuron chip implements a node for
LonWorks distributed intelligent control networks. It incorpo-
rates, on a single chip, the necessary communication and
control functions, both in hardware and firmware, that facilitate
the design of a LonWorks node.
The CY7C531x0 contains a very flexible five-pin communi-
cation port that can be configured to interface with a wide
variety of media transceivers at a wide range of data rates. The
most common transceiver types are twisted-pair, powerline,
RF, IR, fiber-optics, and coaxial.
The CY7C531x0 is manufactured using state-of-the-art
0.35-µm Flash technology, providing to designers the most
cost-effective Neuron chip solution.
• Low operating current; sleep mode operation for
reduced current consumption[1]
Services at every layer of the OSI networking reference model
are implemented in the LonTalk firmware-based protocol
stored in 10-KB ROM (CY7C53120E2), 12-KB ROM
(CY7C53120E4), or off-chip memory (CY7C53150). The
firmware also contains 34 preprogrammed I/O drivers, greatly
simplifying application programming. The application program
is stored in the Flash memory (CY7C53120) and/or off-chip
memory (CY7C53150), and may be updated by downloading
over the network.
• 0.35-µm Flash process technology
• 5.0V operation
• On-chip LVD circuit to prevent nonvolatile memory
corruption during voltage drops
• 2,048 bytes of SRAM for buffering network data,
system, and application data storage
• 512 bytes (CY7C53150), 2048 bytes (CY7C53120E2),
4096 bytes (CY7C53120E4) of Flash memory with
on-chip charge pump for flexible storage of configu-
ration data and application code
• Addresses up to 58 KB of external memory
(CY7C53150)
• 10 KB (CY7C53120E2), 12 KB (CY7C53120E4) of ROM
containing LonTalk network protocol firmware
• Maximum input clock operation of 20 MHz
(CY7C53150), 10 MHz (CY7C53120E2), 40 MHz
(CY7C53120E4) over a –40°C to 85°C[2] temperature
range
The CY7C53150 incorporates an external memory interface
that can address up to 64 KB with 6 KB of the address space
mapped internally. LonWorks nodes that require large appli-
cation programs can take advantage of this external memory
capability.
The CY7C53150 Neuron chip is an exact replacement for the
Motorola MC143150Bx and Toshiba TMPN3150B1 devices.
The CY7C53120E2 Neuron chip is an exact replacement for
the Motorola MC143120E2 device since it contains the same
firmware in ROM.
• 64-pin TQFP package (CY7C53150)
• 32-pin SOIC or 44-pin TQFP package (CY7C53120)
Logic Block Diagram
CP4
CP0
Media Access
Control Processor
Communications
Port
IO10
IO0
Network
Internal
I/O Block
Processor
Data Bus
(0:7)
Application
Processor
2 Timer/
Counters
Internal
Address Bus
(0:15)
2 KB RAM
CLK1
Oscillator,
Clock, and
Control
CLK2
SERVICE
RESET
Flash
External
Address/Data Bus
(CY7C53150)
ROM
(CY7C53120)
Notes:
1. Rare combinations of wake-up events occurring during the go to sleep sequence could produce unexpected sleep behavior. For details please refer to Cypress’s
Neuron Metastability Description application note.
2. Maximum Junction Temperature is 105°C. TJunction = TAmbient + V•I•θJA. 32-pin SOIC θJA = 51C/W. 44-pin TQFP θJA = 43C/W. 64-pin TQFP θJA = 44C/W.
Cypress Semiconductor Corporation
Document #: 38-10001 Rev. *D
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Revised March 24, 2003
CY7C53150
CY7C53120
.
Pin Configurations
CY7C53150
64-lead Thin Quad Flat Pack
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
[4]
NC
49
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
CP4
CP3
A14
A13
A12
A11
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
CP2
CP1
CP0
[4]
NC
V
A10
A9
DD
V
A8
A7
SS
CLK1
CLK2
CY7C53150-20AI
A6
A5
V
DD
A4
A3
A2
V
V
SS
DD
V
SS
[4]
A1
A0
NC
SERVICE
1
2 3 4 5 6 7 8 9 10 11 1213 14 15 16
Pin 1
[3]
Indicator
Notes:
3. The smaller dimple at the bottom left of the marking indicates pin 1.
4. No Connect (NC) — Should not be used. (These pins may be used for internal testing.)
Document #: 38-10001 Rev. *D
Page 2 of 12
CY7C53150
CY7C53120
Pin Configurations (continued)
44-lead QFP
32-lead SOIC
RESET
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
V
DD
SS
V
2
[4]
DD
[4]
34
35
36
22
NC
NC
IO4
IO3
3
IO5
IO6
IO7
IO8
IO9
CP1
CP0
21
20
19
18
IO6
IO5
4
IO2
5
V
IO1
6
V
37
38
DD
SS
IO0
7
CP2
V
DD
[4]
CY7C53120Ex-yyAI
SERVICE
8
V
[4]
DD
NC
V
NC
39
40
41
42
17
16
15
14
V
9
IO10
SS
RESET
SS
V
10
11
12
13
14
15
16
V
SS
pp
CLK1
CLK2
V
DD
V
V
CP4
CP3
CP1
CP0
DD
IO4
IO3
DD
V
V
43
44
SS
13
12
SS
[4]
CLK2
CLK1
[4]
NC
NC
V
DD
V
CP2
SS
PIN 1
INDICATOR
Document #: 38-10001 Rev. *D
Page 3 of 12
CY7C53150
CY7C53120
Pin Descriptions
CY7C53150
CY7C53120xx
CY7C53120xx
Pin Name
I/O
Pin Function
TQFP-64 Pin No. SOIC-32 Pin No. TQFP-44 Pin No.
CLK1
Input
Oscillator connection or external clock
input.
24
23
15
14
15
14
CLK2
Output
Oscillator connection. Leave open when
external clock is input to CLK1. Maximum
of one external load.
RESET
SERVICE
IO0–IO3
I/O (Built-In
Pull-up)
Reset pin (active LOW). Note. The
allowable external capacitance connected
to the RESET pin is 100 –1000 pF.
6
17
1
8
40
5
I/O (Built-In
Service pin (active LOW). Alternates
Configurable between input and output at a 76-Hz rate.
Pull-up)
I/O
Large current-sink capacity (20 mA).
General I/O port. The output of timer/
counter 1 may be routed to IO0. The output
of timer/counter 2 may be routed to IO1.
2, 3, 4, 5
7, 6, 5, 4
4, 3, 2, 43
IO4–IO7
I/O (Built-In
General I/O port. The input to
10, 11, 12, 13
3, 30, 29, 28
42, 36, 35, 32
Configurable timer/counter 1 maybe derivedfrom one of
Pull-ups)
IO4–IO7. The input to timer/counter 2 may
be derived from IO4.
IO8–IO10
D0–D7
R/W
I/O
General I/O port. May be used for serial
communication under firmware control.
14, 15, 16
27, 26, 24
N/A
31, 30, 27
N/A
I/O
Bidirectional memory data bus.
43, 42, 38, 37,
36, 35, 34, 33
Output
Output
Output
Read/write control output for external
memory.
45
N/A
N/A
E
Enable clock control output for external
memory.
46
N/A
N/A
A0–A15
Memory address output port.
64, 63, 62, 61, 60,
59, 58, 57, 56, 55,
54, 53, 52, 51, 50,
47
N/A
N/A
VDD
VSS
Vpp
Input
Input
Input
Power input (5V nom). All VDD pins must
be connected together externally.
7, 20, 22, 26,
40, 41, 44
2, 11, 12,
18, 25, 32
9, 10, 19,
29, 38, 41
Power input (0V, GND). All VSS pins must 8,19, 21, 25, 39 9, 13, 16, 23, 31 7,13, 16, 26, 37
be connected together externally.
In-circuittestmodecontrol. IfVppishigh
when RESET is asserted, the I/O, address
and data buses become Hi-Z.
9
10
8
CP0–CP4 Communication Bidirectional port supporting communi- 28, 29, 30, 31, 32 19, 20, 17, 21, 22 20, 21, 18, 24, 25
Network
cations in three modes.
Interface
NC
—
Noconnect. Must notbeconnectedonthe 1, 18, 27, 48, 49
user’s PC board, since they may be
connected internal to the chip.
N/A
1, 6, 11, 12, 17,
22, 23, 28, 33, 34,
39, 44
Memory Usage
All Neuron chips require system firmware to be present when
they are powered up. In the case of the CY7C53120 family,
this firmware is preprogrammed in the factory in an on-chip
ROM. In the case of the CY7C53150, the system firmware
must be present in the first 16 KB of an off-chip nonvolatile
memory such as Flash, EPROM, EEPROM, or NVRAM.
These devices must be programmed in a device programmer
before board assembly. Because the system firmware imple-
ments the network protocol, it cannot itself be downloaded
over the network.
For the CY7C53120 family, the user application program is
stored in on-chip Flash memory. It may be programmed using
a device programmer before board assembly, or may be
Document #: 38-10001 Rev. *D
Page 4 of 12
CY7C53150
CY7C53120
downloaded and updated over the LonTalk network from an
external network management tool.
transceiver is responsible for encoding and decoding the data
stream.
For the CY7C53150, the user application program is stored in
on-chip Flash Memory and also in off-chip memory. The user
program may initially be programmed into the off-chip memory
device using a device programmer.
In Differential Mode, pins CP0 and CP1 form a differential
receiver with built-in programmable hysteresis and low-pass
filtering. Pins CP2 and CP3 form a differential driver. Serial
data is communicated using Differential Manchester encoding.
The following tables describe the communications port when
used in Differential Mode.
Flash Memory Retention and Endurance
Data and code stored in Flash Memory is guaranteed to be
retained for at least 10 years for programming temperature
range of –25°C to 85°C.
CP0 – CP1
+ 200 mV
≥
V
hys
CP0
/2
The Flash Memory can typically be written 100,000 times
without any data loss.[5] An erase/write cycle takes 20 ms. The
system firmware extends the effective endurance of Flash
memory in two ways. If the data being written to a byte of Flash
memory is the same as the data already present in that byte,
the firmware does not perform the physical write. So for
example, an application that sets its own address in Flash
memory after every reset will not use up any write cycles if the
address has not changed. In addition, system firmware
version 13.1 or higher is able to aggregate writes to eight
V
DD
CP1
≤ 3 ns
Figure 1. Receiver Input Waveform
Programmable Hysteresis Values
(Expressed as differential peak-to-peak voltages in terms of VDD
)
Hysteresis[6]
Vhys Min.
0.019 VDD
0.040 VDD
0.061 VDD
0.081 VDD
0.101 VDD
0.121 VDD
0.142 VDD
0.162 VDD
Vhys Typ.
0.027 VDD
0.054 VDD
0.081 VDD
0.108 VDD
0.135 VDD
0.162 VDD
0.189 VDD
0.216 VDD
Vhys Max.
0.035 VDD
0.068 VDD
0.101 VDD
0.135 VDD
0.169 VDD
0.203 VDD
0.236 VDD
0.270 VDD
0
1
2
3
4
5
6
7
successive address locations into
a single write for
CY7C53120E4 devices. For example, if 4 KB of code is
downloaded over the network, the firmware would execute
only 512 writes rather than 4,096.
40-MHz 3120 Operation
The CY7C53120E4-40 device was designed to run at
frequencies up to 40 MHz using an external clock oscillator. It
is important to note that external oscillators may typically take
on the order of 5 ms to stabilize after power-up. The Neuron
chip should be held in reset until the CLK1 input is stable. With
some oscillators, this may require the use of a reset-stretching
Low-Voltage Detection chip/circuit. Check the oscillator
vendor’s specification for more information about start-up
stabilization times.
Programmable Glitch Filter Values[7]
(Receiver (end-to-end) filter values expressed as transient
pulse suppression times)
Filter (F)
Min.
10
Typ.
75
Max.
140
Unit
ns
0
1
2
3
Low-Voltage Inhibit Operation
120
240
480
410
800
1500
700
ns
The on-chip Low-voltage Inhibit circuit trips the Neuron chip
whenever the VDD input is less than 4.1 ± 0.3V. This feature
prevents the corruption of nonvolatile memory during voltage
drops.
1350
2600
ns
ns
Receiver[8] (End-to-End) Absolute Asymmetry
(Worst case across hysteresis)
Communications Port
Filter (F)
Max ( tPLH – tPHL
)
Unit
ns
The Neuron chip includes a versatile 5-pin communications
port that can be configured in three different ways. In
Single-Ended Mode, pin CP0 is used for receiving serial data,
pin CP1 for transmitting serial data, and pin CP2 enables an
external transceiver. Data is communicated using Differential
Manchester encoding.
0
1
2
3
35
150
250
400
ns
ns
ns
Differential Receiver (End-to-End) Absolute Symmetry[9, 10]
In Special Purpose Mode, pin CP0 is used for receiving serial
data, pin CP1 for transmitting serial data, pin CP2 transmits a
bit clock, and pin CP4 transmits a frame clock for use by an
external intelligent transceiver. In this mode, the external
Filter (F)
Hysteresis (H) Max ( tPLH – tPHL
24
)
Unit
0
0
ns
Notes:
5. For detailed information about data retention after 100K cycles, please see Cypress qualification report.
6. Hysteresis values are on the condition that the input signal swing is 200 mV greater than the programmed value.
7. Must be disabled if data rate is 1.25 Mbps or greater.
8. Receiver input, VD = VCP0 – VCP1, at least 200 mV greater than hysteresis levels. See Figure 1.
9. CP0 and CP1 inputs each 0.60 Vp – p, 1.25 MHz sine wave 180° out of phase with each other as shown in Figure 8. VDD = 5.00 V ± 5%.
10. tPLH: Time from input switching states from low to high to output switching states. tPHL: Time from input switching states from high to low to output switching states.
Document #: 38-10001 Rev. *D
Page 5 of 12
CY7C53150
CY7C53120
Electrical Characteristics (VDD = 4.5V–5.5V)
Parameter
Description
Min.
Typ.
Max.
Unit
VIL
Input Low Voltage
IO0–IO10, CP0, CP3, CP4, SERVICE, D0-D7, RESET
CP0, CP1 (Differential)
V
—
—
—
—
0.8
Programmable
VIH
Input High Voltage
IO0–IO10, CP0, CP3, CP4, SERVICE, D0-D7,RESET
CP0, CP1 (Differential)
V
V
2.0
—
—
—
—
Programmable
VOL
Low-Level Output Voltage
Iout < 20 µA
—
—
—
—
—
—
—
—
—
—
—
—
0.1
0.4
0.8
0.4
1.0
0.4
Standard Outputs (IOL = 1.4 mA)[11]
High Sink (IO0–IO3), SERVICE, RESET (IOL = 20 mA)
High Sink (IO0–IO3), SERVICE, RESET (IOL = 10 mA)
Maximum Sink (CP2, CP3) (IOL = 40 mA)
Maximum Sink (CP2, CP3) (IOL = 15 mA)
VOH
High-Level Output Voltage
Iout < 20 µA
V
VDD – 0.1
VDD – 0.4
—
—
—
—
—
—
—
—
—
—
Standard Outputs (IOH = –1.4 mA)[11]
High Sink (IO0 – IO3), SERVICE (IOH = –1.4 mA)
Maximum Source (CP2, CP3) (IOH = –40 mA)
Maximum Source (CP2, CP3) (IOH = –15 mA)
VDD – 0.4
VDD – 1.0
VDD – 0.4
Vhys
Iin
Hysteresis (Excluding CLK1)
175
—
—
—
—
—
mV
µA
[12]
Input Current (Excluding Pull-Ups) (VSS to VDD
Pull-Up Source Current (Vout = 0 V, Output = High-Z)[12]
)
±10
260
Ipu
60
µA
IDD
Operating Mode Supply Current[13]40-MHz Clock[14]
20-MHz Clock
10-MHz Clock
5-MHz Clock
2.5-MHz Clock
—
—
—
—
—
—
—
—
—
—
—
—
—
—
55
32
20
12
8
7
3
mA
1.25-MHz Clock
0.625-MHz Clock[14]
IDDsleep
Sleep Mode Supply Current[1, 13]
—
—
100
µA
LVI Trip Point (V
)
DD
Part Number
Min.
Typ.
Max.
Unit
CY7C53120E2, CY7C53120E4, and CY7C53150
3.8
4.1
4.4
V
Notes:
11. Standard outputs are IO4–IO10, CP0, CP1, and CP4. (RESET is an open drain input/output. CLK2 must have < 15 pF load.) For CY7C53150, standard
outputs also include A0–A15, D0–D7, E, and R/W.
12. IO4–IO7 and SERVICE have configurable pull-ups. RESET has a permanent pull-up.
13. Supply current measurement conditions: VDD = 5V, all outputs under no-load conditions, all inputs < 0.2V or > (VDD – 0.2V), configurable pull-ups off, crystal
oscillator clock input, differential receiver disabled. The differential receiver adds approximately 200 µA typical and 600 µA maximum when enabled. It is
enabled on either of the following conditions:
• Neuron chip in Operating mode and Comm Port in Differential mode.
• Neuron chip in Sleep mode and Comm Port in Differential mode and Comm Port Wake-up not masked.
14. Supported through an external oscillator only.
Document #: 38-10001 Rev. *D
Page 6 of 12
CY7C53150
CY7C53120
External Memory Interface Timing — CY7C53150, V ± 10% (VDD = 4.5V to 5.5 V, TA = –40°C to+ 85°C [2]
)
DD
Parameter
tcyc
Description
Memory Cycle Time (System Clock Period)[15]
Pulse Width, E High[16]
Min.
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
100
3200
PWEH
PWEL
tAD
tcyc/2 – 5
tcyc/2 + 5
Pulse Width, E Low[16]
tcyc/2 – 5
tcyc/2 + 5
35
Delay, E High to Address Valid[20]
Address Hold Time After E High[20]
Delay, E High to R/W Valid Read[20]
R/W Hold Time Read After E High
Delay, E High to R/W Valid Write
R/W Hold Time Write After E High
Read Data Setup Time to E High
Data Hold Time Read After E High
Data Hold Time Write After E High[17, 18]
Delay, E Low to Data Valid
—
10
—
5
tAH
—
tRD
25
tRH
—
tWR
—
5
25
tWH
—
tDSR
tDHR
tDHW
tDDW
tDHZ
tDDZ
tacc
15
0
—
—
10
—
0
—
12
Data Three State Hold Time After E Low[19]
Delay, E High to Data Three-State[18]
—
—
50
42
External Memory Access Time (tacc = tcyc – tAD – tDSR) at
20-MHz input clock
—
Differential Transceiver Electrical Characteristics
Characteristic
Receiver Common Mode Voltage Range to maintain hysteresis[21]
Receiver Common Mode Range to operate with unspecified hysteresis
Input Offset Voltage
Min.
Max.
VDD – 2.2
VDD – 1.75
0.05Vhys + 35
230 ns
—
Unit
V
1.2
0.9
V
–0.05Vhys – 35
mV
ns
Propagation Delay (F = 0, VID = Vhys/2 + 200 mV)
Input Resistance
—
5
MΩ
µs
Ω
Wake-up Time
Differential Output Impedance for CP2 and CP3[22]
—
10
35
TEST SIGNAL
C = 20 pF for E
L
C = 30 pF for A0–A15, D0–D7, and R/W
L
C
L
C = 50 pF for all other signals
L
Figure 2. Signal Loading for Timing Specifications Unless Otherwise Specified
PW
PW
EL
EH
2.0V
2.0V
0.8V
Figure 3. Test Point Levels for E Pulse Width Measurements
Notes:
15. cyc = 2(1/f), where f is the input clock (CLK1) frequency (20, 10, 5, 2.5, 1.25, or 0.625 MHz).
t
16. Refer to Figure 3 for detailed measurement information.
17. The data hold parameter, tDHW, is measured to the disable levels shown in Figure 5, rather than to the traditional data invalid levels.
18. Refer to Figure 6 and Figure 5 for detailed measurement information.
19. The three-state condition is when the device is not actively driving data. Refer to Figure 2 and Figure 5 for detailed measurement information.
20. To meet the timing above for 20-MHz operation, the loading on A0–A15, D0–D7, and R/W is 30 pF. Loading on E is 20 pF.
21. Common mode voltage is defined as the average value of the waveform at each input at the time switching occurs.
22. Z0 = |V[CP2]-V[CP3] |/40mA for 4.75 < VDD < 5.25V.
Document #: 38-10001 Rev. *D
Page 7 of 12
CY7C53150
CY7C53120
DRIVE TO 2.4V
DRIVE TO 0.4V
2.0V
0.8V
A
B
2.0V
0.8V
A — Signal valid-to-signal valid specification (maximum or minimum)
B — Signal valid-to-signal invalid specification (maximum or minimum)
Figure 4. Drive Levels and Test Point Levels for Timing Specifications Unless Otherwise Specified
V
– 0.5 V
OH
V
+ 0.5 V
OL
V
V
– Measured high output drive level
– Measured low output drive level
OH
OL
Figure 5. Test Point Levels for Driven-to-Three-State Time Measurements
V
/2
TEST SIGNAL
C = 30 pF
DD
I
= 1.4 mA
L
LOAD
Figure 6. Signal Loading for Driven-to-Three-State Time Measurements
tcyc
PWEH
PWEL
E
20 pF Load
tAD
tAD
tAD
tAD
Address
(A0 – A15)
30 pF Load
Address
Address
Address
Address
tAH
tAH
tAH
tAH
tWR
tRD
R/W
30 pF Load
tRH
tWH
tDSR
Data In
tDHR
tDSR
Data (In)
(D0 – D7)
Data In
tDDW
tDHR
tDDZ
tDDZ
tDHZ
tDHW
Data Out
tDDW
tDHW
Data Out
Data (Out)
tDHZ
(D0 – D7)
30 pF Load
Memory READ
Memory READ
Memory WRITE
Memory WRITE
Figure 7. External Memory Interface Timing Diagram
Document #: 38-10001 Rev. *D
Page 8 of 12
CY7C53150
CY7C53120
5
4
3
V(CP0)
Vcm
V(CP1)
2
1
V(CP0)-V(CP1)
Tim e
Vtrip+
Vh
Vtrip-
- 1
5V
0V
Neuron Chip’s
Internal
C om parator
Com m on-M ode voltage: Vcm = ( V(CP0) + V(CP1) ) / 2
Hysteresis Voltage: Vh = [Vtrip+] - [Vtrip-]
Figure 8. Differential Receiver Input Hysteresis Voltage Measurement Waveforms
Ordering Information[23]
Max. Input
Clock
(MHz)
Flash
(KB)
ROM
(KB)
Firmware
Version
Package
Name
Part Number
Package Type
CY7C53150-20AI
0.5
2
0
N/A
6
20[25]
A65
S34
S34
A44
A44
64-lead Thin Plastic Quad Flat Pack
32-lead (450 mil) Molded SOIC
32-lead (450 mil) Molded SOIC
44-lead Thin Plastic Quad Flat Pack
44-lead Thin Plastic Quad Flat Pack
CY7C53120E2-10SI[24]
CY7C53120E4-40SI[26]
CY7C53120E2-10AI[24]
CY7C53120E4-40AI[26]
10
12
10
12
10
4
12
6
40
2
10
4
12
40
Notes:
23. All parts contain 2KB of SRAM.
24. CY7C53120E2 firmware is bit-for-bit identical with Motorola MC143120E2 firmware.
25. CY7C53150 may be used with 20-MHz input clock only if the firmware in external memory is version 13 or later.
26. CY7C53120E4 requires upgraded LonBuilder and NodeBuilder software.
Document #: 38-10001 Rev. *D
Page 9 of 12
CY7C53150
CY7C53120
Package Diagrams
44-lead Thin Plastic Quad Flat Pack A44
51-85064-B
64-lead Thin Plastic Quad Flat Pack (14 × 14 × 1.4 mm) A65
51-85046-B
Document #: 38-10001 Rev. *D
Page 10 of 12
CY7C53150
CY7C53120
Package Diagrams (continued)
32-lead (450-mil) Molded SOIC S34
51-85081-A
Echelon, LonWorks, LonTalk, and Neuron are registered trademarks of Echelon Corporation. All product and company names
mentioned in this document are the trademarks of their respective holders.
Document #: 38-10001 Rev. *D
Page 11 of 12
© Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C53150
CY7C53120
Document History Page
Document Title: CY7C53150/CY7C53120 Neuron® Chip Network Processor
Document Number: 38-10001
Orig. of
REV.
**
ECN NO. Issue Date Change Description of Change
111472
111990
11/28/01
02/06/02
DSG
CFB
Change from Spec number: 38-00891 to 38-10001
*A
Changed the max. cur rent values
Specified the Flash endurance of “100K typical” with reference to qual report
Fixed some incorrect footnotes and figure numbering
*B
114465
04/24/02
KBO
Added Sleep Metastability footnote
Added Junction Temperature footnote
Added maximum sleep current footnote
Changed “EEPROM” references to “Flash Memory”
*C
*D
115269
124450
04/26/02
03/25/03
KBO
KBO
Repositioned Note 3
Removed Note 2 regarding data retention
Removed Note 16 regarding max sleep current
Changed the system image firmware version from V12 to V13.1
Document #: 38-10001 Rev. *D
Page 12 of 12
CY7C53120E4-40SIT 相关器件
| 型号 | 制造商 | 描述 | 价格 | 文档 |
| CY7C53120E4-40SXI | CYPRESS | Neuron㈢ Chip Network Processor | 获取价格 |
|
| CY7C53120E4-40SXI | INFINEON | Control Communications | 获取价格 |
|
| CY7C53120E4-40SXIT | CYPRESS | Neuron㈢ Chip Network Processor | 获取价格 |
|
| CY7C53120E4-40SXIT | INFINEON | Control Communications | 获取价格 |
|
| CY7C53120L8 | CYPRESS | 3.3V Neuron Chip Network Processor | 获取价格 |
|
| CY7C53120L8-32SI | CYPRESS | 3.3V Neuron Chip Network Processor | 获取价格 |
|
| CY7C53120L8-44AI | CYPRESS | 3.3V Neuron Chip Network Processor | 获取价格 |
|
| CY7C53150 | CYPRESS | Neuron?? Chip Network Processor | 获取价格 |
|
| CY7C53150-20AI | CYPRESS | Neuron?? Chip Network Processor | 获取价格 |
|
| CY7C53150-20AIT | CYPRESS | LAN Controller, 5 Channel(s), CMOS, PQFP64, 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-64 | 获取价格 |
|
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