CY7C374I-66JC [CYPRESS]
UltraLogic 128-Macrocell Flash CPLD; UltraLogic 128个宏单元CPLD的Flash
| 型号： | CY7C374I-66JC |
| 厂家： | 
CYPRESS |
| 描述： | UltraLogic 128-Macrocell Flash CPLD |
| 文件： | 总13页 (文件大小：277K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
fax id: 6139
CY7C374i
UltraLogic™ 128-Macrocell Flash CPLD
Features
Functional Description
• 128 macrocells in eight logic blocks
• 64 I/O pins
• 5 dedicated inputs including 4 clock pins
• In-System Reprogrammable (ISR™) Flash technology
— JTAG interface
The CY7C374i is an In-System Reprogrammable Complex
Programmable Logic Device (CPLD) and is part of the
FLASH370i™ family of high-density, high-speed CPLDs. Like
all members of the FLASH370i family, the CY7C374i is de-
signed to bring the ease of use as well as PCI Local Bus Spec-
ification support and high performance of the 22V10 to
high-density CPLDs.
• Bus Hold capabilities on all I/Os and dedicated inputs
• No hidden delays
• High speed
Like all of the UltraLogic™ FLASH370i devices, the CY7C374i
is electrically erasable and In-System Reprogrammable (ISR),
which simplifies both design and manufacturing flows thereby
reducing costs. The Cypress ISR function is implemented
through a JTAG serial interface. Data is shifted in and out
through the SDI and SDO pin. The ISR interface is enabled
— f
= 125 MHz
MAX
— t = 10 ns
PD
— t = 5.5 ns
S
using the programming voltage pin (ISR ). Additionally, be-
EN
— t
= 6.5 ns
CO
cause of the superior routability of the FLASH370i devices, ISR
often allows users to change existing logic designs while si-
multaneously fixing pinout assignments.
• Fully PCI compliant
• 3.3V or 5.0V I/O operation
• Available in 84-pin PLCC, 84-pin CLCC, and 100-pin
TQFP packages
• Pin compatible with the CY7C373i
The 128 macrocells in the CY7C374i are divided between
eight logic blocks. Each logic block includes 16 macrocells, a
72 x 86 product term array, and an intelligent product term
allocator.
CLOCK
INPUTS
Logic Block Diagram
INPUTS
1
4
INPUT/CLOCK
MACROCELLS
INPUT
MACROCELL
4
4
8 I/Os
LOGIC
BLOCK
A
LOGIC
BLOCK
H
8 I/Os
I/O0–I/O7
36
16
36
16
I/O56–I/O63
PIM
LOGIC
BLOCK
B
LOGIC
BLOCK
G
8 I/Os
8 I/Os
8 I/Os
8 I/Os
36
16
36
16
I/O8–I/O15
I/O16–I/O23
I/O48–I/O55
I/O40–I/O47
LOGIC
BLOCK
C
LOGIC
BLOCK
F
36
16
36
16
8 I/Os
LOGIC
BLOCK
D
LOGIC
BLOCK
E
8 I/Os
36
16
36
16
I/O24–I/O31
I/O32–I/O39
7C374i-1
32
32
Selection Guide
7C374i–125 7C374i–100 7C374i–83
7C374i–66 7C374iL–66
[1]
Maximum Propagation Delay , t (ns)
10
5.5
6.5
125
12
6
15
8
20
10
20
10
10
75
PD
Minimum Set-Up, t (ns)
S
[1]
Maximum Clock to Output , t
(ns)
7
8
10
CO
Typical Supply Current, I (mA)
125
125
125
CC
Note:
1. The 3.3V I/O mode timing adder, t3.3IO, must be added to this specification when VCCIO = 3.3V.
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
October 1995 – Revised December 19, 1997
CY7C374i
Pin Configurations
PLCC
Top View
11 10 9
8
7
6
5 4 3 2 1 84 83 82 81 80 79 78 77 76 75
GND
I/O
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
I/O
I/O
I/O /SCLK
12
13
14
15
16
17
18
19
20
8
55
9
I/O /SDI
54
10
I/O
53
I/O
52
I/O
11
I/O
12
I/O
I/O
I/O
I/O
51
50
49
48
I/O
13
I/O
14
I/O
15
CLK /I
0
0
CLK /I
4
3
3
V
CCIO 21
GND
GND
22
23
24
25
26
27
28
29
30
31
V
CCIO
CLK /I
1
1
CLK /I
2
I/O
47
I/O
46
I/O
16
17
I/O
I/O
I/O
I/O
I/O
18
19
20
21
I/O
I/O
I/O
I/O
I/O
I/O
45
44
43
57
56
55
54
42
41
40
I/O
I/O
22
23
GND
32 33
36 37
40 41 42
46 47 48 49 50 51 52 53
43 44 45
34 35
38 39
7C374i-2
PGA
Bottom View
L
I/O
I/O
25
I/O
I/O
I/O
SMODE
I/O
I/O
V
I/O
I/O
I/O
I/O
I/O
I/O
39
I/O
41
I/O
42
I/O
44
23
26
28
31
33
CC
34
36
37
I/O
27
I/O
30
I
2
I/O
GND
I/O
I/O
GND
K
J
24
32
35
38
21
SDO
I/O
22
I/O
29
V
CC
GND
I/O
40
20
18
H
I/O
43
I/O
I/O
19
CLK1 I/O
GND
16
CLK2 I/O
I/O
47
G
F
46
/
I1
/I
3
I/O
17
I/O
15
I/O
12
I/O
10
CLK0
V
CC
V
CC
I/O
45
GND
/I
0
I/O
14
I/O
11
I/O
13
I/O
49
I/O
I/O
CLK3
E
48
/I
4
I/O
50
D
C
51
I/O
I/O
V
I/O
54
SDI
I/O
52
I/O
1
CC
ISR
8
EN
SCLK
I/O
9
I/O
6
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND I/O
B
A
GND
3
0
61
62
63
59
56
53
I/O
55
I/O
1
I/O
5
I/O
4
I/O
4
I/O
I/O
57
7
2
60
58
V
CC
GND
6
2
3
5
7
8
9
10
11
7C374i–3
2
CY7C374i
Pin Configurations (continued)
TQFP
Top View
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
1
75
74
73
SDI
SCLK
GND
2
3
4
V
CCIO
I/O
8
I/O
9
I/O
I/O
55
72
71
70
69
54
I/O
10
I/O
11
5
6
7
8
I/O
I/O
I/O
I/O
I/O
I/O
53
52
51
50
49
I/O
I/O
12
68
13
I/O
I/O
14
15
9
67
66
10
11
12
13
48
CLK /I
0
CLK /I
3
GND
NC
0
65
64
63
62
4
3
V
CCIO
N/C
V
CCIO
GND
14
15
16
17
CLK /I
CLK /I
2
1
I/O
I/O
I/O
1
16
17
61
60
59
I O
/
47
I/O
I/O
I/O
46
18
18
19
20
21
58
45
I/O
19
I/O
20
I/O
21
57
56
55
54
53
44
43
I/O
I/O
I/O
42
41
I/O
22
23
22
23
I/O
40
I/O
V
GND
NC
24
25
52
51
CCIO
NC
26 27 28 29 30 31 32 33 34 35 36
38 39 40 41 42 43 44 45 46 47 48 49 50
37
7C374i-4
CLCC
Top View
11 10 9
8
7
6
5 4 3 2 1 84 83 82 81 80 79 78 77 76 75
GND
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
I/O
I/O
I/O /SCLK
12
13
14
15
16
17
8
I/O
55
9
I/O /SDI
54
10
I/O
53
I/O
52
I/O
11
I/O
12
I/O
I/O
I/O
I/O
51
50
49
48
I/O
13
I/O
14
I/O
15
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
CLK /I
0
0
CLK /I
4
3
3
V
CC
GND
GND
V
CC
CLK /I
1
16
17
1
I/O
CLK /I
2
I/O
47
I/O
46
I/O
I/O
I/O
I/O
I/O
18
19
20
21
I/O
I/O
I/O
I/O
I/O
I/O
45
44
43
42
57
56
55
54
I/O
I/O
22
41
40
23
GND
33
36 37
40 41 42
46 47 48 49 50 51 52 53
43 44 45
34 35
38 39
7C374i-2
3
CY7C374i
boring macrocell. The output of all buried macrocells is sent
directly to the PIM regardless of its configuration.
Functional Description (continued)
The logic blocks in the FLASH370i architecture are connected
with an extremely fast and predictable routing resource—the
Programmable Interconnect Matrix (PIM). The PIM brings flex-
ibility, routability, speed, and a uniform delay to the intercon-
nect.
Programmable Interconnect Matrix
The Programmable Interconnect Matrix (PIM) connects the
eight logic blocks on the CY7C374i to the inputs and to each
other. All inputs (including feedbacks) travel through the PIM.
There is no speed penalty incurred by signals traversing the
PIM.
Like all members of the FLASH370i family, the CY7C374i is rich
in I/O resources. Every two macrocells in the device feature
an associated I/O pin, resulting in 64 I/O pins on the
CY7C374i. In addition, there is one dedicated input and four
input/clock pins.
Programming
For an overview of ISR programming, refer to the FLASH370i
Family data sheet and for ISR cable and software specifica-
tions, refer to ISR data sheets. For a detailed description of
ISR capabilities, refer to the Cypress application note, “An In-
troduction to In System Reprogramming with FLASH370i.”
Finally, the CY7C374i features a very simple timing model.
Unlike other high-density CPLD architectures, there are no
hidden speed delays such as fanout effects, interconnect de-
lays, or expander delays. Regardless of the number of re-
sources used or the type of application, the timing parameters
on the CY7C374i remain the same.
PCI Compliance
The FLASH370i family of CMOS CPLDs are fully compliant with
the PCI Local Bus Specification published by the PCI Special
Interest Group. The simple and predictable timing model of
FLASH370i ensures compliance with the PCI AC specifications
independent of the design. On the other hand, in CPLD and
FPGA architectures without simple and predictable timing, PCI
compliance is dependent upon routing and product term dis-
tribution.
Logic Block
The number of logic blocks distinguishes the members of the
FLASH370i family. The CY7C374i includes eight logic blocks.
Each logic block is constructed of a product term array, a prod-
uct term allocator, and 16 macrocells.
Product Term Array
The product term array in the FLASH370i logic block includes
36 inputs from the PIM and outputs 86 product terms to the
product term allocator. The 36 inputs from the PIM are avail-
able in both positive and negative polarity, making the overall
array size 72 x 86. This large array in each logic block allows
for very complex functions to be implemented in single passes
through the device.
3.3V or 5.0V I/O Operation
The FLASH370i family can be configured to operate in both 3.3V
and 5.0V systems. All devices have two sets of VCC pins: one
set, VCCINT, for internal operation and input buffers, and
another set, VCCIO, for I/O output drivers. VCCINT pins must
always be connected to a 5.0V power supply. However, the
VCCIO pins may be connected to either a 3.3V or 5.0V power
supply, depending on the output requirements. When VCCIO
pins are connected to a 5.0V source, the I/O voltage levels are
Product Term Allocator
The product term allocator is a dynamic, configurable resource
that shifts product terms to macrocells that require them. Any
number of product terms between 0 and 16 inclusive can be
assigned to any of the logic block macrocells (this is called
product term steering). Furthermore, product terms can be
shared among multiple macrocells. This means that product
terms that are common to more than one output can be imple-
mented in a single product term. Product term steering and
product term sharing help to increase the effective density of
the FLASH370i CPLDs. Note that product term allocation is
handled by software and is invisible to the user.
compatible with 5.0V systems.
When VCCIO pins are
connected to a 3.3V source, the input voltage levels are
compatible with both 5.0V and 3.3V systems, while the output
voltage levels are compatible with 3.3V systems. There will be
an additional timing delay on all output buffers when operating
in 3.3V I/O mode. The added flexibility of 3.3V I/O capability
is available in commercial and industrial temperature ranges.
Bus Hold Capabilities on all I/Os and Dedicated Inputs
In addition to ISR capability, a new feature called bus-hold has
been added to all FLASH370i I/Os and dedicated input pins.
Bus-hold, which is an improved version of the popular internal
pull-up resistor, is a weak latch connected to the pin that does
not degrade the device’s performance. As a latch, bus-hold
recalls the last state of a pin when it is three-stated, thus re-
ducing system noise in bus-interface applications. Bus-hold
additionally allows unused device pins to remain unconnected
on the board, which is particularly useful during prototyping as
designers can route new signals to the device without cutting
I/O Macrocell
Half of the macrocells on the CY7C374i have I/O pins associ-
ated with them. The input to the macrocell is the sum of be-
tween 0 and 16 product terms from the product term allocator.
The I/O macrocell includes a register that can be optionally
bypassed, polarity control over the input sum-term, and two
global clocks to trigger the register. The macrocell also fea-
tures a separate feedback path to the PIM so that the register
can be buried if the I/O pin is used as an input.
trace connections to V or GND.
CC
Design Tools
Buried Macrocell
Development software for the CY7C371i is available from Cy-
press’s Warp2®, Warp2Sim™, and Warp3® software packag-
es. All of these products are based on the IEEE-standard
VHDL language. Cypress also actively supports third-party de-
sign tools from companies such as Synopsys, Mentor Graph-
ics, Cadence, and Synario. Please refer to third-party tool sup-
port for further information.
The buried macrocell is very similar to the I/O macrocell.
Again, it includes a register that can be configured as combi-
natorial, as a D flip-flop, a T flip-flop, or a latch. The clock for
this register has the same options as described for the I/O
macrocell. One difference on the buried macrocell is the addi-
tion of input register capability. The user can program the bur-
ied macrocell to act as an input register (D-type or latch)
whose input comes from the I/O pin associated with the neigh-
4
CY7C374i
Static Discharge Voltage ........................................... >2001V
(per MIL-STD-883, Method 3015)
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Latch-Up Current..................................................... >200 mA
Operating Range
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Ambient
Temperature
V
CC
CCINT
Range
V
V
CCIO
Supply Voltage to Ground Potential ............... –0.5V to +7.0V
Commercial
0°C to +70°C
−40°C to +85°C
–55°C to +125°C
5V ± .25V
5V ± .5V
5V ± .5V
5V ± .25V
OR
3.3V ± .3V
DC Voltage Applied to Outputs
in High Z State ............................................... –0.5V to +7.0V
Industrial
5V ± .5V
OR
3.3V ± .3V
DC Input Voltage............................................ –0.5V to +7.0V
DC Program Voltage.....................................................12.5V
Output Current into Outputs.........................................16 mA
[2]
Military
[3, 4]
Electrical Characteristics Over the Operating Range
Parameter
Description
Test Conditions
= –3.2 mA (Com’l/Ind)
= –2.0 mA (Mil)
Min.
Typ. Max. Unit
[5]
V
V
V
Output HIGH Voltage
V
V
V
= Min.
= Max.
= Min.
I
I
I
I
I
I
2.4
V
V
OH
CC
CC
CC
OH
OH
OH
OH
OL
OL
[5, 6]
Output HIGH Voltage
with Output Disabled
= 0 µA (Com’l/Ind)
= –50 µA (Com’l/Ind)
4.0
3.6
0.5
V
V
OHZ
OL
[9]
[5, 6]
[5]
Output LOW Voltage
= 16 mA (Com’l/Ind)
= 12 mA (Mil)
V
V
[7]
[7]
V
V
Input HIGH Voltage
Input LOW Voltage
Input Load Current
Output Leakage Current
Guaranteed Input Logical HIGH voltage for all inputs
Guaranteed Input Logical LOW voltage for all inputs
2.0
–0.5
–10
7.0
0.8
V
IH
IL
V
I
I
V = Internal GND, V = V
+10
+50
–125
–160
µA
µA
µA
mA
IX
I
I
CC
V
V
V
= Max., V = GND or V = V , Output Disabled –50
O O CC
OZ
CC
CC
CC
[6]
= Max., V = 3.3V, Output Disabled
0
–70
O
I
I
Output Short
Circuit Current
= Max., V
= 0.5V
–30
OS
CC
OUT
[8, 9]
Power Supply Current
V
= Max., I
= 0 mA,
Com’l/Ind.
Com’l “L” –66
Military
125
75
200
125
250
mA
mA
mA
µA
CC
OUT
[10]
f = 1 MHz, V = GND, V
IN
CC
125
I
I
I
I
Input Bus Hold LOW
Sustaining Current
V
V
V
V
= Min., V = 0.8V
+75
–75
BHL
CC
CC
CC
CC
IL
Input Bus Hold HIGH
Sustaining Current
= Min., V = 2.0V
µA
µA
µA
BHH
IH
Input Bus Hold LOW
Overdrive Current
= Max.
= Max.
+500
–500
BHLO
BHHO
Input Bus Hold HIGH
Overdrive Current
Notes:
2. A is the “instant on” case temperature.
3. See the last page of this specification for Group A subgroup testing information.
T
4. If VCCIO is not specified, the device can be operating in either 3.3V or 5V I/O mode; VCC=VCCINT
.
5. IOH = –2 mA, IOL = 2 mA for SDO.
6. When the I/O is three-stated, the bus-hold circuit can weakly pull the I/O to a maximum of 4.0V if no leakage current is allowed. This voltage is lowered significantly
by a small leakage current. Note that all I/Os are three-stated during ISR programming. Refer to the application note “Understanding Bus Hold” for additional
information.
7. These are absolute values with respect to device ground. All overshoots due to system or tester noise are included.
8. Not more than one output should be tested at a time. Duration of the short circuit should not exceed 1 second. VOUT = 0.5V has been chosen to avoid test
problems caused by tester ground degradation.
9. Tested initially and after any design or process changes that may affect these parameters.
10. Measured with 16-bit counter programmed into each logic block.
5
CY7C374i
Capacitance[9]
Parameter
[11, 12]
Description
Input Capacitance
Test Conditions
= 5.0V at f=1 MHz
= 5.0V at f = 1 MHz
Min.
Max.
8
Unit
pF
C
C
V
V
I/O
IN
IN
Clock Signal Capacitance
5
12
pF
CLK
Inductance[9]
84-Lead
PLCC
84-Lead
CLCC
Parameter
Description
Maximum Pin Inductance
Test Conditions
100-PinTQFP
Unit
L
V
= 5.0V at f = 1 MHz
8
8
5
nH
IN
Endurance Characteristics[9]
Parameter
Description
Maximum Reprogramming Cycles
Test Conditions
Normal Programming Conditions
Max.
100
Unit
N
Cycles
AC Test Loads and Waveforms
238 (COM'L)
Ω
238 (COM'L)
Ω
ALL INPUT PULSES
90% 90%
10%
319 (MIL)
Ω
319 (MIL)
Ω
3.0V
GND
5V
5V
10%
<2ns
170 (COM'L)
236 (MIL)
Ω
Ω
OUTPUT
OUTPUT
170 (COM'L)
236 (MIL)
Ω
Ω
35 pF
5 pF
<2ns
INCLUDING
JIG AND
SCOPE
INCLUDING
JIG AND
SCOPE
7C374i-6
(c)
7C374i-5
(a)
THÉVENIN EQUIVALENT
(b)
Equivalent to:
99 (COM'L)
Ω
136 (MIL)
Ω
2.08V (COM'L)
2.13V (MIL)
OUTPUT
[13]
Parameter
V
Output Waveform Measurement Level
X
t
t
t
1.5V
2.6V
1.5V
ER(–)
ER(+)
EA(+)
V
OH
–0.5V
–0.5V
V
X
V
X
V
OH
V
OH
–0.5V
–0.5V
V
X
t
V
thc
EA(–)
V
X
V
OH
Notes:
11.
12.
C
C
I/O for the CLCC package are 12 pF Max
I/O for dedicated Inputs, and for I/O pins with JTAG functionality is 12 pF Max., and for ISREN is 15 pF Max.
13. tER measured with 5-pF AC Test Load and tEA measured with 35-pF AC Test Load.
6
CY7C374i
[14]
Switching Characteristics Over the Operating Range
7C374i–66
7C374i–125 7C374i–100 7C374i–83 7C374iL–66
Parameter
Description
Min. Max. Min. Max. Min. Max. Min. Max. Unit
Combinatorial Mode Parameters
[1]
t
t
Input to Combinatorial Output
10
13
12
15
15
18
20
22
ns
ns
PD
Input to Output Through Transparent Input or
PDL
[1]
Output Latch
t
Input to Output Through Transparent Input
and Output Latches
15
16
19
24
ns
PDLL
[1]
[1]
t
t
Input to Output Enable
14
14
16
16
19
19
24
24
ns
ns
EA
ER
Input to Output Disable
Input Registered/Latched Mode Parameters
[9]
t
t
t
t
t
Clock or Latch Enable Input LOW Time
3
3
2
2
3
3
2
2
4
4
3
3
5
5
4
4
ns
ns
ns
ns
ns
WL
WH
IS
[9]
Clock or Latch Enable Input HIGH Time
Input Register or Latch Set-Up Time
Input Register or Latch Hold Time
IH
Input Register Clock or Latch Enable to Com-
14
16
16
18
19
21
24
26
ICO
[1]
binatorial Output
t
Input Register Clock or Latch Enable to Out-
ns
ICOL
[1]
put Through Transparent Output Latch
Output Registered/Latched Mode Parameters
[1]
t
t
Clock or Latch Enable to Output
6.5
14
7
8
10
24
ns
ns
CO
S
Set-Up Time from Input to Clock or Latch En-
able
5.5
0
6
0
8
0
10
0
t
t
Register or Latch Data Hold Time
ns
ns
H
Output Clock or Latch Enable to Output Delay
16
19
CO2
[1]
(Through Memory Array)
t
t
Output Clock or Latch Enable to Output Clock
or Latch Enable (Through Memory Array)
8
10
12
12
15
15
20
ns
ns
SCS
SL
Set-Up Time from Input Through Transparent
Latch to Output Register Clock or Latch En-
able
10
t
Hold Time for Input Through Transparent
Latch from Output Register Clock or Latch
Enable
0
0
0
0
ns
HL
f
f
Maximum Frequency with Internal Feedback
125
100
143
83
66
MHz
MHz
MAX1
MAX2
[9]
(Least of 1/t
, 1/(t + t ), or 1/t
)
SCS
S
H
CO
Maximum Frequency Data Path in Output
Registered/Latched Mode (Lesser of 1/(t
158.3
125
100
+
WL
t
), 1/(t + t ), or 1/t
)
WH
S
H
CO
f
t
Maximum Frequency with External Feedback 83.3
(Lesser of 1/(t + t ) and 1/(t + t ))
76.9
0
67.5
0
50
0
MHz
ns
MAX3
CO
S
WL
WH
–t
Output Data Stable from Output Clock Minus
0
OH IH
[9, 15]
37x
Input Register Hold Time for 7C37x
Pipelined Mode Parameters
t
f
Input Register Clock to Output Register Clock
Maximum Frequency in Pipelined Mode
8
10
12
15
ns
ICS
125
100
83.3
66.6
MHz
MAX4
(Least of 1/(t
+ t ), 1/t , 1/(t
+ t ),
CO
IS
ICS
WL WH
1/(t + t ), or 1/t
)
IS
IH
SCS
Notes:
14. All AC parameters are measured with 16 outputs switching and 35-pF AC Test Load.
15. This specification is intended to guarantee interface compatibility of the other members of the CY7C370i family with the CY7C374i. This specification is met
for the devices operating at the same ambient temperature and at the same power supply voltage.
7
CY7C374i
[14]
Switching Characteristics Over the Operating Range
(continued)
7C374i–66
7C374i–125 7C374i–100 7C374i–83 7C374iL–66
Parameter
Description
Min. Max. Min. Max. Min. Max. Min. Max. Unit
Reset/Preset Parameters
[9]
t
t
t
t
t
t
Asynchronous Reset Width
10
12
12
14
15
17
20
22
ns
ns
ns
ns
ns
ns
RW
RR
RO
PW
PR
PO
[9]
Asynchronous Reset Recovery Time
[1]
Asynchronous Reset to Output
16
16
18
18
21
21
26
26
[9]
Asynchronous Preset Width
10
12
12
14
15
17
20
22
[9]
Asynchronous Preset Recovery Time
[1]
Asynchronous Preset to Output
Tap Controller Parameter
Tap Controller Frequency
3.3V I/O Mode Parameters
3.3V I/O mode timing adder
f
500
500
500
500
kHz
ns
TAP
t
1
1
1
1
3.3IO
Switching Waveforms
Combinatorial Output
INPUT
tPD
COMBINATORIAL
OUTPUT
7C374i-7
Registered Output
INPUT
tS
tH
CLOCK
tCO
REGISTERED
OUTPUT
tWH
tWL
7C374i-8
CLOCK
Latched Output
INPUT
tS
tH
LATCH ENABLE
tPDL
tCO
LATCHED
OUTPUT
7C374i-9
8
CY7C374i
Switching Waveforms (continued)
Registered Input
REGISTERED
INPUT
t
IS
t
IH
INPUT REGISTER
CLOCK
t
ICO
COMBINATORIAL
OUTPUT
t
t
WL
WH
CLOCK
7C374i-10
Latched Input
LATCHED INPUT
t
IS
t
IH
LATCH ENABLE
t
t
ICO
PDL
COMBINATORIAL
OUTPUT
t
t
WL
WH
LATCH ENABLE
7C374i-11
Latched Input and Output
LATCHED INPUT
t
PDLL
LATCHED
OUTPUT
t
t
SL
ICOL
t
HL
INPUT LATCH
ENABLE
t
ICS
OUTPUT LATCH
ENABLE
t
t
WH
WL
LATCH ENABLE
7C374i-12
9
CY7C374i
Switching Waveforms (continued)
Asynchronous Reset
t
RW
INPUT
t
RO
REGISTERED
OUTPUT
t
RR
CLOCK
7C374i-13
Asynchronous Preset
t
PW
INPUT
t
PO
REGISTERED
OUTPUT
t
PR
CLOCK
7C374i-14
Output Enable/Disable
INPUT
t
t
EA
ER
OUTPUTS
7C374i-16
10
CY7C374i
Ordering Information
Speed
Package
Name
Operating
Range
(MHz)
Ordering Code
CY7C374i–125AC
CY7C374i–125JC
CY7C374i–100AC
CY7C374i–100JC
CY7C374i–83AC
CY7C374i–83JC
CY7C374i–83AI
CY7C374i–83JI
Package Type
125
A100
J83
100-Pin Thin Quad Flat Pack
Commercial
Commercial
Commercial
Industrial
84-Lead Plastic Leaded Chip Carrier
100-Pin Thin Quad Flat Pack
100
83
A100
J83
84-Lead Plastic Leaded Chip Carrier
100-Pin Thin Quad Flat Pack
A100
J83
84-Lead Plastic Leaded Chip Carrier
100-Pin Thin Quad Flat Pack
A100
J83
84-Lead Plastic Leaded Chip Carrier
84-Pin Ceramic Pin Grid Array
84-Pin Ceramic Leaded Chip Carrier
100-Pin Thin Quad Flat Pack
CY7C374i-83GMB
CY7C374i–83YMB
CY7C374i–66AC
CY7C374i–66JC
CY7C374i–66AI
CY7C374i–66JI
G84
Y84
A100
J83
Military
66
Commercial
Industrial
84-Lead Plastic Leaded Chip Carrier
100-Pin Thin Quad Flat Pack
A100
J83
84-Lead Plastic Leaded Chip Carrier
84-Pin Ceramic Pin Grid Array
84-Pin Ceramic Leaded Chip Carrier
100-Pin Thin Quad Flat Pack
CY7C374i-66GMB
CY7C374i–66YMB
CY7C374iL–66AC
CY7C374iL–66JC
G84
Y84
A100
J83
Military
Commercial
84-Lead Plastic Leaded Chip Carrier
MILITARY SPECIFICATIONS
Group A Subgroup Testing
Switching Characteristics
Parameter
Subgroups
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
t
DC Characteristics
PD
t
t
t
t
t
t
t
t
t
t
t
t
t
t
PDL
PDLL
CO
ICO
ICOL
S
Parameter
Subgroups
1, 2, 3
V
V
V
V
OH
OL
IH
1, 2, 3
1, 2, 3
1, 2, 3
IL
I
I
I
1, 2, 3
IX
SL
1, 2, 3
OZ
H
1, 2, 3
CC1
HL
IS
IH
ICS
EA
ER
Document #: 38-00496-C
ISR, UltraLogic, FLASH370, FLASH370i, and Warp2Sim are trademarks of Cypress Semiconductor Corporation.
Warp2 and Warp3 are registered trademarks of Cypress Semiconductor Corporation.
11
CY7C374i
Package Diagrams
100-PinThin Quad Flat Pack A100
84-Pin Grid Array (Cavity Up) G84
12
CY7C374i
Package Diagrams (continued)
84-Lead Plastic Leaded Chip Carrier J83
84-Pin Ceramic Leaded Chip Carrier Y84
© Cypress Semiconductor Corporation, 1997. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
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