CY7C344B-12PC/PI [CYPRESS]
32-Macrocell MAX㈢ EPLD; 32宏单元MAX® EPLD
| 型号： | CY7C344B-12PC/PI |
| 厂家： | 
CYPRESS |
| 描述： | 32-Macrocell MAX㈢ EPLD |
| 文件： | 总17页 (文件大小：296K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
1CY7C344B
fax id: 6101
CY7C344
CY7C344B
32-Macrocell MAX® EPLD
sents the densest EPLD of this size. Eight dedicated inputs
and 16 bidirectional I/O pins communicate to one logic array
block. In the CY7C344 LAB there are 32 macrocells and 64
expander product terms. When an I/O macrocell is used as an
input, two expanders are used to create an input path. Even if
all of the I/O pins are driven by macrocell registers, there are
still 16 “buried” registers available. All inputs, macrocells, and
I/O pins are interconnected within the LAB.
Features
• High-performance, high-density replacement for TTL,
74HC, and custom logic
• 32 macrocells, 64 expander product terms in one LAB
• 8 dedicated inputs, 16 I/O pins
• 0.8-micron double-metal CMOS EPROM technology
(CY7C344)
The speed and density of the CY7C344/CY7C344B makes it
a natural for all types of applications. With just this one device,
the designer can implement complex state machines, regis-
tered logic, and combinatorial “glue” logic, without using mul-
tiple chips. This architectural flexibility allows the
CY7C344/CY7C344B to replace multichip TTL solutions,
whether they are synchronous, asynchronous, combinatorial,
or all three.
• Advanced 0.65-micron CMOS EPROM technology to
increase performance (CY7C344B)
• 28-pin 300-mil DIP, cerDIP or 28-pin HLCC, PLCC
package
Functional Description
Available in a 28-pin 300-mil DIP or windowed J-leaded ce-
ramic chip carrier (HLCC), the CY7C344/CY7C344B repre-
Logic Block Diagram[1]
Pin Configurations
HLCC
15(22) INPUT
15(23) INPUT
INPUT
1(8)
Top View
INPUT/CLK 2(9)
27(6)
28(7)
INPUT
INPUT
INPUT
INPUT
13(20)
14(21)
4
3
2
1
28 27 26
25
5
6
7
8
9
10
11
I/O
I/O
I/O
INPUT
INPUT
INPUT
INPUT/CLK
I/O
24
23
22
21
20
19
MACROCELL 2
MACROCELL 1
I/O 3(10)
I/O 4(11)
I/O 5(12)
I/O 6(13)
I/O 9(16)
I/O 10(17)
I/O 11(18)
I/O 12(19)
I/O 17(24)
I/O 18(25)
I/O 19(26)
I/O 20(27)
I/O 23(2)
I/O 24(3)
I/O 25(4)
I/O 26(5)
INPUT
INPUT
INPUT
INPUT
I/O
MACROCELL 4
MACROCELL 6
MACROCELL 8
MACROCELL 10
MACROCELL 12
MACROCELL 14
MACROCELL 16
MACROCELL 18
MACROCELL 20
MACROCELL 22
MACROCELL 24
MACROCELL 26
MACROCELL 28
MACROCELL 30
MACROCELL 32
MACROCELL 3
MACROCELL 5
MACROCELL 7
MACROCELL 9
MACROCELL 11
MACROCELL 13
MACROCELL 15
MACROCELL 17
MACROCELL 19
MACROCELL 21
MACROCELL 23
MACROCELL 25
MACROCELL 27
MACROCELL 29
MACROCELL 31
G
L
I
O
O
B
A
L
I/O
12 13 141516 1718
C
O
N
T
C344–2
CerDIP
Top View
B
U
S
R
O
L
INPUT
INPUT
INPUT
I/O
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
INPUT/CLK
I/O
2
3
4
5
6
7
I/O
I/O
I/O
I/O
I/O
I/O
V
CC
V
CC
GND
I/O
GND
I/O
8
9
I/O
I/O
10
11
12
13
14
I/O
I/O
INPUT
I/O
I/O
INPUT
C344–1
32
64 EXPANDER PRODUCT TERM ARRAY
INPUT
INPUT
C344–3
Selection Guide
7C344–15
7C344–20
7C344–25
7C344B–10
7C344B–12
12
7C344B–15
7C344B–20
7C344B–25
Maximum Access Time (ns)
10
15
20
25
Maximum
Operating
Current (mA)
Commercial
Military
Industrial
Commercial
Military
200
200
220
220
150
170
170
200
200
220
220
150
170
170
200
220
220
150
170
170
220
150
Maximum Standby
Current (mA)
150
Industrial
170
Shaded area contains preliminary information.
Note:
1. Numbers in () refer to J-leaded packages.
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
January 1990 – Revised October 1995
CY7C344
CY7C344B
DC Output Current, per Pin......................–25 mA to +25 mA
Maximum Ratings
[2]
DC Input Voltage .........................................–3.0V to +7.0V
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
DC Program Voltage .................................................. +13.0V
Storage Temperature ................................. –65°C to +150°C
Operating Range
Ambient Temperature with
Ambient
Power Applied...................................................0°C to +70°C
Range
Commercial
Industrial
Military
Temperature
V
CC
Maximum Junction Temperature (Under Bias)............. 150°C
Supply Voltage to Ground Potential............... –2.0V to +7.0V
Maximum Power Dissipation...................................1500 mW
0°C to +70°C
5V ±5%
5V ±10%
5V ±10%
–40°C to +85°C
–55°C to +125°C (Case)
DC V or GND Current............................................500 mA
CC
Static Discharge Voltage
(per MIL-STD-883, Method 3015)..............................>2001V
[3]
Electrical Characteristics Over the Operating Range
Parameter
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Level
Test Conditions
Min.
Max.
Unit
V
V
V
V
V
V
= Min., I = –4.0 mA
2.4
V
V
OH
OL
IH
CC
CC
OH
= Min., I = 8 mA
0.45
+0.3
OL
2.2
–0.3
–10
–40
–30
V
V
CC
Input LOW Level
0.8
V
IL
I
I
I
I
Input Current
GND ≤ V ≤ V
CC
+10
+40
–90
150
170
200
220
100
100
µA
µA
mA
mA
mA
mA
mA
ns
ns
IX
IN
Output Leakage Current
Output Short Circuit Current
V
V
= V or GND
CC
OZ
O
[4, 5]
= Max., V = 0.5V
OUT
OS
CC
Power Supply
Current (Standby)
V = V or GND (No Load)
Commercial
CC1
I
CC
Military/Industrial
Commercial
I
Power Supply Current
V = V or GND (No Load)
I CC
CC2
[4,6]
f = 1.0 MHz
Military/Industrial
t
t
Recommended Input Rise Time
Recommended Input Fall Time
R
F
Capacitance
Parameter
Description
Input Capacitance
Output Capacitance
Test Conditions
= 2V, f = 1.0 MHz
Max.
10
Unit
pF
C
C
V
V
IN
IN
= 2.0V, f = 1.0 MHz
10
pF
OUT
OUT
AC Test Loads and Waveforms[7]
R1 464Ω
R1 464Ω
5V
5V
ALL INPUT PULSES
OUTPUT
OUTPUT
3.0V
90%
10%
90%
10%
R2
250Ω
R2
250Ω
50 pF
5 pF
GND
t
f
≤ 6ns
≤ 6ns
INCLUDING
JIGAND
t
t
F
R
SCOPE
C344–4
C344–5
(a)
(b)
Equivalent to:
THÉVENIN EQUIVALENT (commercial/military)
163Ω
OUTPUT
1.75V
C344–6
Notes:
2. Minimum DC input is –0.3V. During transitions, the inputs may undershoot to –2.0V for periods less than 20 ns.
3. Typical values are for TA = 25°C and VCC = 5V.
4. Guaranteed by design but not 100% tested.
5. Not more than one output should be tested at a time. Duration of the short circuit should not be more than one second. VOUT = 0.5V has been chosen to avoid
test problems caused by tester ground degradation.
6. Measured with device programmed as a 16-bit counter.
7. Part (a) in AC Test Load and Waveforms is used for all parameters except tER and tXZ, which is used for part (b) in AC Test Load and Waveforms. All external timing
parameters are measured referenced to external pins of the device.
2
CY7C344
CY7C344B
When expander logic is used in the data path, add the appro-
Timing Delays
priate maximum expander delay, t
to t . Determine which of
EXP
S1
Timing delays within the CY7C344/CY7C344B may be easily
determined using Warp2®, Warp2Sim™, or Warp3® software
or by the model shown in Figure 1. The CY7C344/CY7C344B
has fixed internal delays, allowing the user to determine the
worst case timing delays for any design. For complete timing
information, the Warp3 software provides a timing simulator.
1/(t
+ t ), 1/t
, or 1/(t
+ t ) is the lowest frequency. The
WH
WL
CO1
EXP S1
lowest of these frequencies is the maximum data-path frequency for
the synchronous configuration.
When calculating external asynchronous frequencies, use
t
if all inputs are on dedicated input pins. If any data is applied to
AS1
an I/O pin, t
must be used as the required set-up time. If (t
+
AS2
AS2
t
) is greater than t
, 1/(t
+ t ) becomes the limiting fre-
AH
ACO1
AS2 AH
Design Recommendations
quency in the data-path mode unless 1/(t
+ t
) is less than
AWH
AWL
1/(t
+ t ).
AS2
AH
Operation of the devices described herein with conditions
above those listed under “Absolute Maximum Ratings” may
cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of
this datasheet is not implied. Exposure to absolute maximum
ratings conditions for extended periods of time may affect de-
vice reliability. The CY7C344/CY7C344B contains circuitry to
protect device pins from high-static voltages or electric fields;
however, normal precautions should be taken to avoid applying
any voltage higher than maximum rated voltages.
When expander logic is used in the data path, add the appro-
priate maximum expander delay, t to t . Determine which
of 1/(t
Thelowest of thesefrequencies is themaximum data-path frequency
for the asynchronous configuration.
EXP
AS1
+t
), 1/t
, or 1/(t
+t
) is the lowest frequency.
AWH AWL
ACO1
EXP AS1
The parameter t indicates the system compatibility of this device
when driving other synchronous logic with positive input hold times,
which is controlled by the same synchronous clock. If t is greater
than the minimum required input hold time of the subsequent syn-
chronous logic, then the devices are guaranteed to function properly
with a common synchronous clock under worst-case environmental
and supply voltage conditions.
OH
OH
For proper operation, input and output pins must be con-
strained to the range GND ≤ (VIN or VOUT) ≤ VCC. Unused in-
puts must always be tied to an appropriate logic level (either VCC or
GND). Each set of VCC and GND pins must be connected together
directly at the device. Power supply decoupling capacitors of at least
0.2 µF must be connected between VCC and GND. For the most
effective decoupling, each VCC pin should be separately decoupled.
The parameter t
vice when driving subsequent registered logic with a positive hold
time and using the same clock as the CY7C344/CY7C344B.In gen-
indicates the system compatibility of this de-
AOH
eral, if t
is greater than the minimum required input hold time of
AOH
the subsequent logic (synchronousor asynchronous), then thedevic-
es are guaranteed to function properly under worst-case environ-
mental and supply voltage conditions, provided the clock signal
source is the same. This also applies if expander logic is used in the
clock signal path of the driving device, but not for the driven device.
This is due to the expander logic in the second device’s clock signal
path adding an additional delay (t
the preceding device to change prior to the arrival of the clock signal
at the following device’s register.
Timing Considerations
Unless otherwise stated, propagation delays do not include
expanders. When using expanders, add the maximum ex-
pander delay t
to the overall delay.
EXP
), causing the output data from
EXP
When calculating synchronous frequencies, use t if all inputs
S1
are on the input pins. t should be used if data is applied at an I/O
S2
pin. If t is greater than t
, 1/t becomes the limiting frequency
S2
CO1
S2
in the data-path mode unless 1/(t
+ t ) is less than 1/t .
WL S2
WH
EXPANDER
DELAY
t
EXP
REGISTER
LOGIC ARRAY
OUTPUT
DELAY
t
t
CONTROLDELAY
CLR
INPUT
t
LAC
PRE
OUTPUT
t
OD
XZ
ZX
INPUT
DELAY
IN
t
LOGIC ARRAY
DELAY
t
t
RD
t
RSU
t
t
COMB
LATCH
t
t
RH
t
LAD
SYSTEM CLOCK DELAYt
ICS
CLOCK
DELAY
I/O
I/O DELAY
I/O
t
IC
t
IO
FEEDBACK
DELAY
t
C344–7
FD
Figure 1. CY7C344/CY7C344B Timing Model
3
CY7C344
CY7C344B
External Synchronous Switching Characteristics[7] Over Operating Range
7C344–15
7C344B–10 7C344B–12 7C344B–15
Parameter
Description
Min. Max. Min. Max. Min. Max. Unit
[8]
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
f
Dedicated Input to Combinatorial Output Delay
Com’l /Ind
Mil
10
10
16
16
10
10
5
12
12
12
12
18
18
18
18
12
12
12
12
6
15
15
15
15
30
30
30
30
20
20
20
20
10
10
20
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
PD1
PD2
PD3
PD4
EA
[9]
I/O Input to Combinatorial Output Delay
Com’l/Ind
Mil
Dedicated Input to Combinatorial Output Delay Com’l /Ind
[10]
with Expander Delay
Mil
I/O Input to Combinatorial Output Delay with
Com’l/Ind
Mil
[4, 11]
Expander Delay
[4]
Input to Output Enable Delay
Com’l/Ind
Mil
[4]
Input to Output Disable Delay
Com’l /Ind
Mil
ER
Synchronous Clock Input to Output Delay
Com’l /Ind
Mil
CO1
CO2
S
6
Synchronous Clock to Local Feedback to Com- Com’l /Ind
10
12
12
[4, 12]
binatorial Output
Mil
Dedicated Input or Feedback Set-Up Time to
Synchronous Clock Input
Com’l/Ind
Mil
6
0
8
8
10
10
0
[7]
Input Hold Time from Synchronous Clock Input
Com’l /Ind
Mil
0
H
0
0
[4]
Synchronous Clock Input HIGH Time
Com’l/Ind
Mil
4
4.5
4.5
4.5
4.5
12
12
12
12
6
WH
WL
RW
RR
RO
PW
PR
6
[4]
Synchronous Clock Input LOW Time
Com’l /Ind
Mil
4
6
6
[4]
Asynchronous Clear Width
Com’l /Ind
Mil
10
10
20
20
20
20
[4]
Asynchronous Clear Recovery Time
Com’l /Ind
Mil
Asynchronous Clear to Registered Output De-
Com’l /Ind
Mil
10
12
12
15
15
[4]
lay
[4]
Asynchronous Preset Width
Com’l /Ind
Mil
10
10
12
12
12
12
20
20
20
20
[4]
Asynchronous Preset Recovery Time
Com’l /Ind
Mil
Asynchronous Preset to Registered Output
Com’l /Ind
Mil
10
3
12
12
3
15
15
4
PO
CF
[4]
Delay
[4, 13]
[4]
Synchronous Clock to Local Feedback Input
External Synchronous Clock Period (1/f
Com’l /Ind
Mil
3
4
)
MAX3
Com’l/Ind
Mil
8
9
13
13
P
9
[4, 14]
External Maximum Frequency(1/(t
+ t ))
Com’l/Ind 90.9
Mil
71.4
71.4
50.0
50.0
MAX1
CO1
S
Shaded area contains preliminary information.
4
CY7C344
CY7C344B
External Synchronous Switching Characteristics[7] Over Operating Range (continued)
7C344–15
7C344B–12 7C344B–15
7C344B–10
Parameter
Description
Min. Max. Min. Max. Min. Max. Unit
f
f
f
t
Maximum Frequency with Internal Only Feed- Com’l/Ind 111.1
90.9
90.9
111.1
111.1
111.1
111.1
3
71.4
71.4
83.3
83.3
83.3
83.3
3
MHz
MHz
MHz
ns
MAX2
MAX3
MAX4
OH
[4, 15]
back (1/(t + t ))
CF
S
Mil
Data Path Maximum Frequency, least of 1/(t
Com’l/Ind 125.0
WL
[4, 16]
+ t ), 1/(t + t ), or (1/t )
WH
S
H
CO1
Mil
Maximum Register Toggle Frequency 1/(t
+
Com’l/Ind 125.0
Mil
WL
[4, 17]
t
)
WH
Output Data Stable Time from Synchronous
Clock Input
Com’l/ Ind
Mil
3
[4, 18]
3
3
Shaded area contains preliminary information.
Notes:
8. This parameter is the delay from an input signal applied to a dedicated input pin to a combinatorial output on any output pin. This delay assumes no expander
terms are used to form the logic function.
9. This parameter is the delay associated with an input signal applied to an I/O macrocell pin to any output. This delay assumes no expander terms are used to
form the logic function.
10. This parameter is the delay associated with an input signal applied to a dedicated input pin to combinatorial output on any output pin. This delay assumes
expander terms are used to form the logic function and includes the worst-case expander logic delay for one pass through the expander logic. This parameter
is tested periodically by sampling production material.
11. This parameter is the delay associated with an input signal applied to an I/O macrocell pin to any output pin. This delay assumes expander terms are used
to form the logic function and includes the worst-case expander logic delay for one pass through the expander logic. This parameter is tested periodically by
sampling production material.
12. This specification is a measure of the delay from synchronous register clock input to internal feedback of the register output signal to a combinatorial output
for which the registered output signal is used as an input. This parameter assumes no expanders are used in the logic of the combinatorial output and the
register is synchronously clocked. This parameter is tested periodically by sampling production material.
13. This specification is a measure of the delay associated with the internal register feedback path. This delay plus the register set-up time, tS, is the minimum
internal period for an internal state machine configuration. This parameter is tested periodically by sampling production material.
14. This specification indicates the guaranteed maximum frequency at which a state machine configuration with external only feedback can operate.
15. This specification indicates the guaranteed maximum frequency at which a state machine with internal-only feedback can operate. If register output states
must also control external points, this frequency can still be observed as long as it is less than 1/tCO1. This specification assumes no expander logic is used. This
parameter is tested periodically by sampling production material.
16. This frequency indicates the maximum frequency at which the device may operate in data-path mode (dedicated input pin to output pin). This assumes that
no expander logic is used.
17. This specification indicates the guaranteed maximum frequency in synchronous mode, at which an individual output or buried register can be cycled by a
clock signal applied to either a dedicated input pin or an I/O pin.
18. This parameter indicates the minimum time after a synchronous register clock input that the previous register output data is maintained on the output pin.
5
CY7C344
CY7C344B
External Synchronous Switching Characteristics[7] Over Operating Range (continued)
7C344–20
7C344B–20
7C344–25
7C344B–25
Parameter
Description
Min.
Max.
20
20
20
20
30
30
30
30
20
20
20
20
12
12
22
22
Min.
Max.
25
25
25
25
40
40
40
40
25
25
25
25
15
15
29
29
Unit
[8]
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Dedicated Input to Combinatorial Output Delay
Com’l /Ind
Mil
ns
PD1
[9]
I/O Input to Combinatorial Output Delay
Com’l/Ind
Mil
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
PD2
PD3
PD4
EA
Dedicated Input to Combinatorial Output Delay with Ex- Com’l /Ind
[10]
pander Delay
Mil
I/O Input to Combinatorial Output Delay with Expander Com’l/Ind
[4, 11]
Delay
Mil
[4]
Input to Output Enable Delay
Com’l/Ind
Mil
[4]
Input to Output Disable Delay
Com’l /Ind
Mil
ER
CO1
CO2
S
Synchronous Clock Input to Output Delay
Com’l /Ind
Mil
Synchronous Clock to Local Feedback to Combinato- Com’l /Ind
[4, 12]
rial Output
Mil
Dedicated Input or Feedback Set-Up Time to Synchro- Com’l/Ind
12
12
0
15
15
0
nous Clock Input
Mil
[7]
Input Hold Time from Synchronous Clock Input
Com’l /Ind
Mil
H
0
0
[4]
Synchronous Clock Input HIGH Time
Com’l/Ind
Mil
7
8
WH
WL
RW
RR
RO
PW
PR
PO
CF
7
8
[4]
Synchronous Clock Input LOW Time
Com’l /Ind
Mil
7
8
7
8
[4]
Asynchronous Clear Width
Com’l /Ind
Mil
20
20
20
20
25
25
25
25
[4]
Asynchronous Clear Recovery Time
Com’l /Ind
Mil
[4]
Asynchronous Clear to Registered Output Delay
Com’l /Ind
Mil
20
20
25
25
[4]
Asynchronous Preset Width
Com’l /Ind
Mil
20
20
20
20
25
25
25
25
[4]
Asynchronous Preset Recovery Time
Com’l /Ind
Mil
[4]
Asynchronous Preset to Registered Output Delay
Com’l /Ind
Mil
20
20
4
25
25
7
[4, 13]
Synchronous Clock to Local Feedback Input
Com’l /Ind
Mil
4
7
[4]
External Synchronous Clock Period (1/f
)
MAX3
Com’l/Ind
Mil
14
14
16
16
P
6
CY7C344
CY7C344B
External Synchronous Switching Characteristics[7] Over Operating Range (continued)
7C344–20
7C344B–20
7C344–25
7C344B–25
Parameter
Description
External Maximum Frequency(1/(t + t ))
Min.
41.6
41.6
62.5
62.5
71.4
71.4
71.4
71.4
3
Max.
Min.
33.3
33.3
45.4
45.4
62.5
62.5
62.5
62.5
3
Max.
Unit
[4, 14]
f
f
f
f
t
Com’l/Ind
Mil
MHz
MAX1
CO1
S
Maximum Frequency with Internal Only Feedback
Com’l/Ind
Mil
MHz
MHz
MHz
ns
MAX2
MAX3
MAX4
OH
[4, 15]
(1/(t + t ))
CF
S
Data Path Maximum Frequency, least of 1/(t + t ), Com’l/Ind
WL WH
[4, 16]
1/(t + t ), or (1/t )
S
H
CO1
Mil
[4, 17]
Maximum Register Toggle Frequency 1/(t + t
)
Com’l/Ind
Mil
WL WH
Output Data Stable Time from
Com’l/ Ind
Mil
[4, 18]
Synchronous Clock Input
3
3
[7]
External Asynchronous Switching Characteristics Over Operating Range
7C344–15
7C344B–10 7C344B–12 7C344B–15
Parameter
Description
Min. Max. Min. Max. Min. Max. Unit
t
t
t
t
t
t
t
t
f
f
f
f
t
Asynchronous Clock Input to Output Delay
Com’l/ Ind
Mil
10
12
12
18
18
15
15
30
30
ns
ACO1
ACO2
AS
Asynchronous Clock Input to Local Feedback to Com’l/Ind
15
ns
[19]
Combinatorial Output
Mil
Dedicated Input or Feedback Set-Up Time to
Asynchronous Clock Input
Com’l/Ind
Mil
4
3
4
5
4
4
4
4
5
5
6
6
7
7
7
7
6
6
7
7
ns
Input Hold Time from Asynchronous Clock Input Com’l/Ind
ns
AH
Mil
[4, 20]
Asynchronous Clock Input HIGH Time
Com’l/Ind
Mil
ns
AWH
AWL
[4]
Asynchronous Clock Input LOW Time
Com’l/Ind
Mil
ns
[4,
Asynchronous Clock to Local Feedback Input
Com’l /Ind
Mil
7
9
9
18
18
ns
ACF
21]
[4]
External Asynchronous Clock Period (1/f
)
MAX4
Com’l/Ind
Mil
12
12.5
12.5
62.5
62.5
76.9
76.9
83.3
83.3
90.9
90.9
12
13
13
ns
AP
External Maximum Frequency in Asynchronous Com’l/Ind
71.4
90.9
45.4
45.4
40
MHz
MHz
MHz
MHz
ns
MAXA1
MAXA2
MAXA3
MAXA4
AOH
[4, 22]
Mode 1/(t
+ t
)
ACO1
AS
Mil
Maximum Internal Asynchronous Frequency
Com’l/Ind
Mil
[4, 23]
1/(t
+ t ) or 1/(t
+ t
)
ACF
AS
AWH
AWL
40
Data Path Maximum Frequencyin Asynchronous Com’l/Ind 100.0
66.6
66.6
76.9
76.9
15
[4, 24]
Mode
Mil
Maximum Asynchronous Register Toggle Fre-
Com’l /Ind 111.1
Mil
[4, 25]
quency 1/(t
+ t
)
AWH
AWL
Output Data Stable Time from Asynchronous
Com’l/Ind
Mil
12
[4, 26]
Clock Input
15
Shaded area contains preliminary information.
7
CY7C344
CY7C344B
[7]
External Asynchronous Switching Characteristics Over Operating Range (continued)
7C344–20
7C344B–20
7C344–25
7C344B–25
Parameter
Description
Min. Max. Min. Max.
Unit
t
t
t
t
t
t
t
t
f
f
f
f
t
Asynchronous Clock Input to Output Delay
Com’l/ Ind
Mil
20
20
30
30
25
25
37
37
ns
ACO1
Asynchronous Clock Input to Local Feedback to Com- Com’l/Ind
ns
ns
ACO2
AS
[19]
binatorial Output
Mil
Dedicated Input or Feedback Set-Up Time to Asyn-
chronous Clock Input
Com’l/Ind
Mil
9
9
9
9
7
7
9
9
12
12
12
12
9
Input Hold Time from Asynchronous Clock Input
Com’l/Ind
Mil
ns
AH
[4, 20]
Asynchronous Clock Input HIGH Time
Com’l/Ind
Mil
ns
AWH
AWL
9
[4]
Asynchronous Clock Input LOW Time
Com’l/Ind
Mil
11
11
ns
[4, 21]
Asynchronous Clock to Local Feedback Input
Com’l /Ind
Mil
18
18
21
21
ns
ACF
[4]
External Asynchronous Clock Period (1/f
)
Com’l/Ind
Mil
16
16
20
20
ns
AP
MAX4
External Maximum Frequency in Asynchronous Mode Com’l/Ind
34.4
34.4
37
27
MHz
MHz
MHz
MHz
ns
MAXA1
MAXA2
MAXA3
MAXA4
AOH
[4, 22]
1/(t
+ t
)
ACO1
AS
Mil
27
Maximum Internal Asynchronous Frequency 1/(t
+
Com’l/Ind
Mil
30.3
30.3
40
ACF
[4, 23]
t
) or 1/(t
+ t
)
AS
AWH AWL
37
Data Path Maximum Frequency in Asynchronous
Com’l/Ind
Mil
50
[4, 23]
Mode
50
40
Maximum Asynchronous Register Toggle Frequency Com’l /Ind
62.5
62.5
15
50
[4, 25]
1/(t
+ t
)
AWH AWL
Mil
50
Output Data Stable Time from Asynchronous Clock
Com’l/Ind
Mil
15
[4, 26]
Input
15
15
Notes:
19. This specification is a measure of the delay from an asynchronous register clock input to internal feedback of the registered output signal to a combinatorial
output for which the registered output signal is used as an input. Assumes no expanders are used in logic of combinatorial output or the asynchronous clock
input. This parameter is tested periodically by sampling production material.
20. This parameter is measured with a positive-edge-triggered clock at the register. For negative edge triggering, the tAWH and tAWL parameters must be swapped.
If a given input is used to clock multiple registers with both positive and negative polarity, tAWH should be used for both tAWH and tAWL
.
21. This specification is a measure of the delay associated with the internal register feedback path for an asynchronously clocked register. This delay plus the
asynchronous register set-up time, tAS, is the minimum internal period for an asynchronously clocked state machine configuration. This delay assumes no expander logic
in the asynchronous clock path. This parameter is tested periodically by sampling production material.
22. This parameter indicates the guaranteed maximum frequency at which an asynchronously clocked state machine configuration with external feedback can
operate. It is assumed that no expander logic is employed in the clock signal path or data path.
23. This specification indicates the guaranteed maximum frequency at which an asynchronously clocked state machine with internal-only feedback can operate.
If register output states must also control external points, this frequency can still be observed as long as this frequency is less than 1/tACO1. This specification
assumes no expander logic is utilized. This parameter is tested periodically by sampling production material.
24. This specification indicates the guaranteed maximum frequency at which an individual output or buried register can be cycled in asynchronously clocked
mode. This frequency is least of 1/(tAWH + tAWL), 1/(tAS + tAH), or 1/tACO1. It also indicates the maximum frequency at which the device may operate in the asynchronously
clocked data-path mode. Assumes no expander logic is used.
25. This specification indicates the guaranteed maximum frequency at which an individual output or buried register can be cycled in asynchronously clocked
mode by a clock signal applied to an external dedicated input or an I/O pin.
26. This parameter indicates the minimum time that the previous register output data is maintained on the output pin after an asynchronous register clock input
to an external dedicated input or I/O pin.
8
CY7C344
CY7C344B
[7]
Typical Internal Switching Characteristics Over Operating Range
7C344–15
7C344B–10 7C344B–12 7C344B–15
Parameter
Description
Min. Max. Min. Max. Min. Max. Unit
t
Dedicated Input Pad and Buffer Delay
Com’l/Ind
Mil
2
2
6
5
5
3
5
5
2.5
2.5
2.5
2.5
6
4
4
4
4
8
8
7
7
5
5
4
4
7
7
7
7
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
IN
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
I/O Input Pad and Buffer Delay
Expander Array Delay
Com’l/Ind
Mil
IO
Com’l/Ind
Mil
EXP
LAD
LAC
OD
6
Logic Array Data Delay
Com’l/Ind
Mil
6
6
Logic Array Control Delay
Output Buffer and Pad Delay
Com’l/Ind
Mil
5
5
Com’l/Ind
Mil
3
3
[27]
Output Buffer Enable Delay
Com’l /Ind
Mil
5
ZX
5
Output Buffer Disable Delay
Com’l/Ind
Mil
5
XZ
5
Register Set-Up Time Relative to Clock Signal Com’l/Ind
at Register
2
4
2
2
5
5
5
5
7
7
RSU
RH
Mil
Register Hold Time Relative to Clock Signal at Com’l/Ind
Register
Mil
Flow-Through Latch Delay
Register Delay
Com’l/Ind
Mil
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
1
1
1
1
1
1
LATCH
RD
Com’l/Ind
Mil
[28]
Transparent Mode Delay
Com’l/Ind
Mil
COMB
CH
Clock HIGH Time
Com’l/Ind
Mil
3
3
4
4
4
4
6
6
6
6
Clock LOW Time
Com’l/Ind
Mil
CL
Asynchronous Clock Logic Delay
Synchronous Clock Delay
Feedback Delay
Com’l/Ind
Mil
5
0.5
1
6
6
7
7
1
1
1
1
5
5
5
5
IC
Com’l/Ind
Mil
0.5
0.5
1
ICS
FD
Com’l/Ind
Mil
1
Asynchronous Register Preset Time
Asynchronous Register Clear Time
Asynchronous Preset and Clear Pulse Width
Com’l/Ind
Mil
2
3
PRE
CLR
PCW
PCR
3
Com’l/Ind
Mil
2
3
3
Com’l/Ind
Mil
2
2
3
3
3
3
5
5
5
5
Asynchronous Preset and Clear Recovery Time Com’l/Ind
Mil
Shaded area contains preliminary information.
Notes:
27. Sample tested only for an output change of 500 mV.
28. This specification guarantees the maximum combinatorial delay associated with the macrocell register bypass when the macrocell is configured for combi-
natorial operation.
9
CY7C344
CY7C344B
[7]
Typical Internal Switching Characteristics Over Operating Range (continued)
7C344–20
7C344B–20
7C344–25
7C344B–25
Parameter
Description
Min.
Max.
5
Min.
Max.
7
Unit
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Dedicated Input Pad and Buffer Delay
Com’l/Ind
Mil
ns
IN
5
7
I/O Input Pad and Buffer Delay
Expander Array Delay
Com’l/Ind
Mil
5
7
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
IO
5
7
Com’l/Ind
Mil
10
10
9
15
15
10
10
7
EXP
LAD
LAC
OD
Logic Array Data Delay
Com’l/Ind
Mil
9
Logic Array Control Delay
Output Buffer and Pad Delay
Com’l/Ind
Mil
7
7
7
Com’l/Ind
Mil
5
5
5
5
[27]
Output Buffer Enable Delay
Com’l /Ind
Mil
8
11
11
11
11
ZX
8
Output Buffer Disable Delay
Com’l/Ind
Mil
8
XZ
8
Register Set-Up Time Relative to Clock Signal at Reg- Com’l/Ind
ister
5
5
9
9
8
8
RSU
RH
Mil
Register Hold Time Relative to Clock Signal at Register Com’l/Ind
Mil
12
12
Flow-Through Latch Delay
Com’l/Ind
Mil
1
1
1
1
1
1
3
3
1
1
3
3
LATCH
RD
Register Delay
Com’l/Ind
Mil
[28]
Transparent Mode Delay
Com’l/Ind
Mil
COMB
CH
Clock HIGH Time
Com’l/Ind
Mil
7
7
7
7
8
8
8
8
Clock LOW Time
Com’l/Ind
Mil
CL
Asynchronous Clock Logic Delay
Synchronous Clock Delay
Com’l/Ind
Mil
8
8
2
2
1
1
6
6
6
6
10
10
3
IC
Com’l/Ind
Mil
ICS
FD
3
Feedback Delay
Com’l/Ind
Mil
1
1
Asynchronous Register Preset Time
Asynchronous Register Clear Time
Asynchronous Preset and Clear Pulse Width
Asynchronous Preset and Clear Recovery Time
Com’l/Ind
Mil
9
PRE
CLR
PCW
PCR
9
Com’l/Ind
Mil
9
9
Com’l/Ind
Mil
5
5
5
5
7
7
7
7
Com’l/Ind
Mil
10
CY7C344
CY7C344B
Switching Waveforms
External Combinatorial
DEDICATED INPUT/
I/O INPUT
t
/t
PD1 PD2
COMBINATORIAL
OUTPUT
t
ER
COMBINATORIAL OR
REGISTERED OUTPUT
HIGH-IMPEDANCE
THREE-STATE
t
EA
HIGH-IMPEDANCE
THREE-STATE
VALID OUTPUT
C344–8
C344–9
C344–10
External Synchronous
DEDICATED INPUTS OR
REGISTERED FEEDBACK
t
t
t
t
WL
S
H
WH
SYNCHRONOUS
CLOCK
t
t
/t
t /t
RR PR
CO1
RW PW
ASYNCHRONOUS
CLEAR/PRESET
t
OH
t
/t
RO PO
REGISTERED
OUTPUTS
t
CO2
COMBINATORIAL OUTPUT FROM
[12]
REGISTERED FEEDBACK
External Asynchronous
DEDICATED INPUTS OR
REGISTERED FEEDBACK
t
t
t
AWL
t
AH
AWH
AS
ASYNCHRONOUS
CLOCK INPUT
t
ACO1
t
/t
t
/t
RW PW
RR PR
ASYNCHRONOUS
CLEAR/PRESET
t
AOH
t
/t
RO PO
ASYNCHRONOUS REGISTERED
OUTPUTS
t
ACO2
COMBINATORIAL OUTPUT FROM
ASYNCH. REGISTERED
[19]
FEEDBACK
11
CY7C344
CY7C344B
Switching Waveforms (Continued)
Internal Combinatorial
t
IN
INPUT PIN
t
PIA
t
IO
I/O PIN
t
EXP
EXPANDER
ARRAY DELAY
t
, t
LAC LAD
LOGIC ARRAY
INPUT
LOGIC ARRAY
OUTPUT
C344–11
Internal Asynchronous
t
t
AWL
AWH
t
R
t
F
CLOCK PIN
t
IN
CLOCK INTO
LOGIC ARRAY
t
IC
CLOCK FROM
LOGIC ARRAY
t
t
RH
RSU
DATA FROM
LOGIC ARRAY
t
,t
t
FD
t
,t
t
FD
RD LATCH
CLR PRE
REGISTER OUTPUT
TO LOCAL LAB
LOGIC ARRAY
t
PIA
REGISTER OUTPUT
TO ANOTHER LAB
C344–12
Internal Synchronous (Input Path)
t
t
CL
CH
SYSTEM CLOCK PIN
t
IN
t
ICS
SYSTEM CLOCK
AT REGISTER
t
t
RH
RSU
DATA FROM
LOGIC ARRAY
C344–13
12
CY7C344
CY7C344B
Switching Waveforms (Continued)
Internal Synchronous (Output Path)
CLOCK FROM
LOGIC ARRAY
t
t
OD
RD
DATA FROM
LOGIC ARRAY
t
XZ
t
ZX
HIGH Z
OUTPUT PIN
C344–14
Ordering Information
Speed
Package
Name
Operating
Range
(ns)
Ordering Code
CY7C344B–10HC
CY7C344B–10JC
Package Type
10
H64
J64
28-Lead Windowed Leaded Chip Carrier Commercial
28-Lead Plastic Leaded Chip Carrier
28-Lead (300-Mil) Molded DIP
CY7C344B–10PC
P21
W22
H64
J64
CY7C344B–10WC
CY7C344B–12HC/HI
CY7C344B–12JC/JI
CY7C344B–12PC/PI
CY7C344B–12WC/WI
CY7C344B–12HMB
CY7C344B–12WMB
CY7C344–15HC/HI
CY7C344–15JC/JI
CY7C344–15PC/PI
CY7C344–15WC/WI
CY7C344B–15HC/HI
CY7C344B–15JC/JI
CY7C344B–15PC/PI
CY7C344B–15WC/WI
CY7C344B–15HMB
CY7C344B–15WMB
CY7C344–20HC/HI
CY7C344–20JC/JI
CY7C344–20PC/PI
CY7C344–20WC/WI
CY7C344B–20HC/HI
CY7C344B–20JC/JI
CY7C344B–20PC/PI
CY7C344B–20WC/WI
CY7C344–20HMB
CY7C344–20WMB
CY7C344B–20HMB
CY7C344B–20WMB
28-Lead Windowed CerDIP
12
15
28-Lead Windowed Leaded Chip Carrier Commercial/Industrial
28-Lead Plastic Leaded Chip Carrier
28-Lead (300-Mil) Molded DIP
P21
W22
H64
W22
H64
J64
28-Lead Windowed CerDIP
28-Lead Windowed Leaded Chip Carrier Military
28-Lead Windowed CerDIP
28-Lead Windowed Leaded Chip Carrier Commercial/Industrial
28-Lead Plastic Leaded Chip Carrier
28-Lead (300-Mil) Molded DIP
P21
W22
H64
J64
28-Lead Windowed CerDIP
28-Lead Windowed Leaded Chip Carrier
28-Lead Plastic Leaded Chip Carrier
28-Lead (300-Mil) Molded DIP
P21
W22
H64
W22
H64
J64
28-Lead Windowed CerDIP
28-Lead Windowed Leaded Chip Carrier Military
28-Lead Windowed CerDIP
20
28-Lead Windowed Leaded Chip Carrier Commercial/Industrial
28-Lead Plastic Leaded Chip Carrier
28-Lead (300-Mil) Molded DIP
P21
W22
H64
J64
28-Lead Windowed CerDIP
28-Lead Windowed Leaded Chip Carrier
28-Lead Plastic Leaded Chip Carrier
28-Lead (300-Mil) Molded DIP
P21
W22
H64
W22
H64
W22
28-Lead Windowed CerDIP
28-Lead Windowed Leaded Chip Carrier Military
28-Lead Windowed CerDIP
28-Lead Windowed Leaded Chip Carrier
28-Lead Windowed CerDIP
Shaded area contains preliminary information.
13
CY7C344
CY7C344B
Ordering Information (continued)
Speed
(ns)
Package
Operating
Range
Ordering Code
CY7C344–25HC/HI
CY7C344–25JC/JI
CY7C344–25PC/PI
CY7C344–25WC/WI
CY7C344B–25HC/HI
CY7C344B–25JC/JI
CY7C344B–25PC/PI
CY7C344B–25WC/WI
CY7C344–25HMB
CY7C344–25WMB
CY7C344B–25HMB
CY7C344B–25WMB
Name
H64
J64
Package Type
25
28-Lead Windowed Leaded Chip Carrier Commercial/Industrial
28-Lead Plastic Leaded Chip Carrier
28-Lead (300-Mil) Molded DIP
P21
W22
H64
J64
28-Lead Windowed CerDIP
28-Lead Windowed Leaded Chip Carrier
28-Lead Plastic Leaded Chip Carrier
28-Lead (300-Mil) Molded DIP
P21
W22
H64
W22
H64
W22
28-Lead Windowed CerDIP
28-Lead Windowed Leaded Chip Carrier Military
28-Lead Windowed CerDIP
28-Lead Windowed Leaded Chip Carrier
28-Lead Windowed CerDIP
Shaded area contains preliminary information.
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Switching Characteristics
Parameter
Subgroups
1, 2, 3
Parameter
Subgroups
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
V
V
V
V
t
t
t
t
t
t
t
t
t
t
OH
PD1
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
OL
IH
IL
PD2
PD3
CO1
S
I
I
I
IX
OZ
H
CC1
ACO1
ACO1
AS
AH
Document #: 38–00127–G
MAX is a registered trademark of Altera Corporation.
Warp2 and Warp3 are registered trademarks of Cypress Semiconductor Corporation.
Warp2Sim is a trademark of Cypress Semiconductor Corporation.
14
CY7C344
CY7C344B
Package Diagrams
28-Pin Windowed Leaded Chip Carrier H64
15
CY7C344
CY7C344B
Package Diagrams (Continued)
28-Lead Plastic Leaded Chip Carrier J64
28-Lead (300-Mil) Molded DIP P21
16
CY7C344
CY7C344B
Package Diagrams (Continued)
28-Lead (300-Mil) Windowed CerDIP W22
MIL–STD–1835 D– 15Config.A
© Cypress Semiconductor Corporation, 1995. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of anycircuitry other than circuitry embodied in a CypressSemiconductor product. Nor does it conveyor imply any license under patent or other rights. CypressSemiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
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