CY7C225A_06 [CYPRESS]
512 x 8 Registered PROM; 512 ×8 PROM注册
| 型号： | CY7C225A_06 |
| 厂家： | 
CYPRESS |
| 描述： | 512 x 8 Registered PROM |
| 文件： | 总10页 (文件大小：320K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C225A
512 x 8 Registered PROM
• Direct replacement for bipolar PROMs
Features
• Capable of withstanding greater than 2001V static
discharge
• CMOS for optimum speed/power
• High speed
Functional Description
— 25 ns address set-up
The CY7C225A is a high-performance 512-word by 8-bit
electrically programmable read only memory packaged in a
slim 300-mil plastic or hermetic DIP, 28-pin leadless chip
carrier, and 28-pin PLCC. The memory cells utilize proven
EPROM floating gate technology and byte-wide intelligent
programming algorithms.
— 12 ns clock to output
• Low power
— 495 mW (Commercial)
— 660 mW (Military)
• Synchronous and asynchronous output enables
• On-chip edge-triggered registers
• Buffered common PRESET and CLEAR inputs
• EPROM technology, 100% programmable
The CY7C225A replaces bipolar devices and offers the advan-
tages of lower power, superior performance, and high
programming yield. The EPROM cell requires only 12.5V for
the supervoltage and low current requirements allow for gang
programming. The EPROM cells allow for each memory
location to be tested 100%, as each location is written into,
erased, and repeatedly exercised prior to encapsulation. Each
PROM is also tested for AC performance to guarantee that
after customer programming the product will meet AC specifi-
cation limits.
• Slim 300-mil, 24-pin plastic or hermetic DIP, 28-pin LCC, or
28-pin PLCC
• 5V± 10% VCC, commercial and military
• TTL-compatible I/O
Logic Block Diagram
Pin Configurations
DIP
Top View
O
O
7
A
0
1
24
A
V
CC
7
A
1
2
3
4
5
6
A
23
22
21
6
A
8
6
ROW
A
5
PS
PROGRAMMABLE
ARRAY
A
2
ADDRESS
MULTIPLEXER
A
4
E
O
O
5
A
3
A
20
19
18
17
16
CLR
3
8-BIT
EDGE-
TRIGGERED
REGISTER
E
S
A
2
A
4
4
A
1
7
CP
ADDRESS
DECODER
A
5
A
0
8
O
7
O
6
O
5
O
3
O
O
9
0
A
6
10
11
12
1
15
14
O
2
O
1
O
2
O
O
A
7
4
COLUMN
ADDRESS
GND
13
3
A
8
LCC/PLCC
Top View
O
0
S
R
CP
PS
CLR
CP
3
2 1 2827
4
26
25
E
CLR
A
4
5
6
7
8
9
A
24
23
22
21
20
19
3
A
2
E
S
CP
NC
O
A
1
E
S
A
0
NC
7
10
11
O
0
O
6
E
12 131415161718
Cypress Semiconductor Corporation
Document #: 38-04001 Rev. *C
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised August 16, 2006
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CY7C225A
Selection Guide
7C225A-25
7C225A-30
7C225A-40
Unit
ns
Minimum Address Set-Up Time
Maximum Clock to Output
25
12
90
30
15
90
40
25
ns
Maximum Operating
Current
Commercial
Military
mA
mA
120
Maximum Ratings[1]
DC Program Voltage (Pins 7, 18, 20) ........................... 13.0V
Static Discharge Voltage............................................ >2001V
(per MIL-STD-883, Method 3015)
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Latch-Up Current.....................................................>200 mA
Storage Temperature ..................................... −65°C to +150°C
Ambient Temperature with
Power Applied.................................................. −55°C to +125°C
Operating Range
Supply Voltage to Ground Potential
(Pin 24 to Pin 12).................................................−0.5V to +7.0V
Ambient
Temperature
Range
VCC
DC Voltage Applied to Outputs
in High Z State .....................................................−0.5V to +7.0V
Commercial
Military[2]
0°C to +70°C
−55°C to +125°C
5V ± 10%
5V ± 10%
DC Input Voltage .................................................−3.0V to +7.0V
Electrical Characteristics Over the Operating Range[3,4]
Parameter
Description
Test Conditions
Min.
Max.
Unit
VOH
Output HIGH Voltage
VCC = Min., IOH = −4.0 mA
2.4
V
V
IN = VIH or VIL
VOL
VIH
VIL
Output LOW Voltage
Input HIGH Level
Input LOW Level
VCC = Min., IOL = 16 mA
IN = VIH or VIL
0.4
V
V
Guaranteed Input Logical HIGH Voltage for
All Inputs
2.0
V
GuaranteedInputLogicalLOWVoltageforAll
Inputs
0.8
V
IIX
Input Leakage Current
Input Clamp Diode Voltage
Output Leakage Current
GND < VIN < VCC
−10
+10
µA
VCD
IOZ
IOS
ICC
Note 4
GND < VOUT < VCC, Output Disabled[5]
−10
−20
+10
−90
90
µA
mA
mA
Output Short Circuit Current VCC = Max., VOUT = 0.0V[6]
Power Supply Current
IOUT = 0 mA
CC = Max.
Commercial
Military
V
120
13
VPP
IPP
Programming Supply Voltage
Programming Supply Current
12
V
mA
V
50
VIHP
Input HIGH Programming
Voltage
3.0
VILP
Input LOW Programming
Voltage
0.4
V
Notes
1. The Voltage on any input or I/O pin cannot exceed the power pin during power-up.
2. is the “instant on” case temperature.
3. See the last page of this specification for Group A subgroup testing information.
4. See the “Introduction to CMOS PROMs” section of the Cypress Data Book for general information on testing.
T
A
5. For devices using the synchronous enable, the device must be clocked after applying these voltages to perform this measurement.
6. For test purposes, not more than one output at a time should be shorted. Short circuit test duration should not exceed 30 seconds.
Document #: 38-04001 Rev. *C
Page 2 of 10
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CY7C225A
Capacitance[4]
Parameter
CIN
Description
Input Capacitance
Output Capacitance
Test Conditions
Max.
10
Unit
pF
TA = 25°C, f = 1 MHz,
CC =5.0V
V
COUT
10
pF
AC Test Loads and Waveforms[4]
R1 250Ω
R1 250Ω
5V
5V
ALL INPUT PULSES
OUTPUT
OUTPUT
3.0V
GND
90%
10%
90%
10%
50 pF
5pF
R2
167Ω
R2
167Ω
< 5 ns
< 5 ns
INCLUDING
JIG AND
SCOPE
INCLUDING
JIG AND
SCOPE
(a) NormalLoad
(b) HighZ Load
Equivalent to:
THÉVENIN EQUIVALENT
100Ω
OUTPUT
2.0V
the subsequent positive clock edge will return the output to the
active state if E is LOW. Following a positive clock edge, the
address and synchronous enable inputs are free to change
since no change in the output will occur until the next
LOW-to-HIGH transition of the clock. This unique feature
allows the CY7C225A decoders and sense amplifiers to
access the next location while previously addressed data
remains stable on the outputs.
Operating Modes
The CY7C225A incorporates a D-type, master-slave register
on chip, reducing the cost and size of pipelined micropro-
grammed systems and applications where accessed PROM
data is stored temporarily in a register. Additional flexibility is
provided with synchronous (ES) and asynchronous (E) output
enables and CLEAR and PRESET inputs.
Upon power-up, the synchronous enable (ES) flip-flop will be
in the set condition causing the outputs (O0−O7) to be in the
OFF or high-impedance state. Data is read by applying the
memory location to the address inputs (A0−A8) and a logic
LOW to the enable (ES) input. The stored data is accessed and
loaded into the master flip-flops of the data register during the
address set-up time. At the next LOW-to-HIGH transition of the
clock (CP), data is transferred to the slave flip-flops, which
drive the output buffers, and the accessed data will appear at
the outputs (O0−O7) provided the asynchronous enable (E) is
also LOW.
System timing is simplified in that the on-chip edge-triggered
register allows the PROM clock to be derived directly from the
system clock without introducing race conditions. The on-chip
register timing requirements are similar to those of discrete
registers available in the market.
The CY7C225A has buffered asynchronous CLEAR and
PRESET inputs. Applying a LOW to the PRESET input causes
an immediate load of all ones into the master and slave
flip-flops of the register, independent of all other inputs,
including the clock (CP). Applying a LOW to the CLEAR input,
resets the flip-flops to all zeros. The initialize data will appear
at the device outputs after the outputs are enabled by bringing
the asynchronous enable (E) LOW.
The outputs may be disabled at any time by switching the
asynchronous enable (E) to a logic HIGH, and may be
returned to the active state by switching the enable to a logic
LOW.
When power is applied, the (internal) synchronous enable
flip-flop will be in a state such that the outputs will be in the
high-impedance state. In order to enable the outputs, a clock
must occur and the ES input pin must be LOW at least a set-up
time prior to the clock LOW-to-HIGH transition. The E input
may then be used to enable the outputs.
Regardless of the condition of E, the outputs will go to the OFF
or high-impedance state upon the next positive clock edge
after the synchronous enable (ES) input is switched to a HIGH
level. If the synchronous enable pin is switched to a logic LOW,
Document #: 38-04001 Rev. *C
Page 3 of 10
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CY7C225A
Switching Characteristics Over the Operating Range[3,4]
7C225A-25
7C225A-30
7C225A-40
Unit
Parameter
tSA
Description
Min.
25
0
Max.
Min.
Max.
Min.
40
0
Max.
Address Set-Up to Clock HIGH
Address Hold from Clock HIGH
Clock HIGH to Valid Output
Clock Pulse Width
30
0
ns
ns
ns
ns
ns
ns
ns
tHA
tCO
12
15
25
tPWC
tSES
10
10
0
15
10
5
20
10
5
ES Set-Up to Clock HIGH
ES Hold from Clock HIGH
tHES
tDP, tDC
Delay from PRESET or CLEAR
to Valid Output
20
20
20
tRP, tRC
PRESET or CLEAR Recovery to
Clock HIGH
15
15
20
20
20
20
ns
tPWP, tPWC PRESET or CLEAR Pulse Width
ns
ns
ns
tCOS
tHZC
Valid Output from Clock HIGH[7]
20
20
20
20
30
30
Inactive Output from Clock
HIGH[7]
tDOE
tHZE
Valid Output from E LOW
20
20
20
20
30
30
ns
ns
Inactive Output from E HIGH
Switching Waveforms[4]
t
t
t
HA
HA
SA
A
0
− A
10
t
t
t
t
HES
SES
HES
SES
E
S
t
t
HES
SES
t
t
t
PWC
PWC
PWC
CP
t
t
t
PWC
PWC
PWC
O − O
0
7
t
t
t
COS
CO
HZC
t
CO
t
t
HZE
DOE
E
t
t
DP
DC
t , t
RP RC
PS or CLR
t
t
PWP
PWC
Note
7. Applies only when the synchronous (E ) function is used.
S
Document #: 38-04001 Rev. *C
Page 4 of 10
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CY7C225A
programming information, including a listing of software
packages, please see the PROM Programming Information
located at the end of this section. Programming algorithms can
be obtained from any Cypress representative.
Programming Information
Programming support is available from Cypress as well as
from a number of third-party software vendors. For detailed
Table 1. Mode Selection
Pin Function[8]
Read or Output Disable
Other
A8–A0
A8–A0
A8–A0
A8–A0
A8–A0
A8–A0
A8–A0
A8–A0
A8–A0
A–A0
CP
PGM
X
ES
VFY
VIL
CLR
VPP
VIH
E
PS
PS
O7−O0
D7−D0
O7−O0
High Z
High Z
Zeros
Mode
Read
E
VIL
VIH
Output Disable
Output Disable
Clear
X
VIH
VIH
X
VIH
X
X
VIH
VIH
VIL
VIH
X
VIL
VIL
VIH
Preset
X
VIL
VIH
VIL
VIL
Ones
Program
VILP
VIHP
VIHP
VILP
VIHP
VIHP
VILP
VIHP
VIHP
VILP
VPP
VPP
VPP
VPP
VPP
VIHP
VIHP
VIHP
VIHP
VIHP
VIHP
VIHP
VIHP
VIHP
VIHP
D7−D0
O7−O0
High Z
D7−D0
Zeros
Program Verify
Program Inhibit
Intelligent Program
Blank Check
A8–A0
A8–A0
Figure 1. Programming Pinouts
DIP
Top View
LCC/PLCC
Top View
A
24
V
1
2
3
4
5
6
7
CC
A
23
22
21
6
A
8
PS
E
3
2 1 28 27
4
26
25
24
A
5
E
V
A
A
A
A
A
5
6
7
8
9
4
3
2
1
0
PP
A
4
23 VFY
A
3
20
19
18
17
16
V
PP
PGM
NC
D
D
6
22
A
2
VFY
21
20
19
NC
D
A
1
PGM
10
11
7
7
0
A
0
D
7
D
6
8
1314151617 18
12
D
D
0
9
D
5
1
15
14
13
10
11
12
D
D
4
2
D
3
GND
Note
8. X = “don’t care” but not to exceed V ±5%.
CC
Document #: 38-04001 Rev. *C
Page 5 of 10
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CY7C225A
Typical DC and AC Characteristics
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
CLOCK TO OUTPUT TIME
vs. VCC
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
1.6
1.4
1.2
1.0
1.6
1.2
1.4
1.2
1.0
1.1
1.0
0.9
0.8
T =25°C
A
0.8
0.6
0.8
f = f
MAX
T =25°C
A
0.6
−55
25
125
4.0
4.5
5.0
5.5
6.0
4.0
4.5
5.0
5.5
6.0
AMBIENT TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
CLOCK TO OUTPUT TIME
vs. TEMPERATURE
NORMALIZED SET-UP TIME
vs. SUPPLY VOLTAGE
NORMALIZED SET-UP TIME
vs. TEMPERATURE
1.6
1.2
1.0
1.6
1.4
1.2
1.0
0.8
1.4
1.2
1.0
0.8
0.8
0.6
0.4
T =25°C
A
0.6
−55
0.6
–55
25
125
4.0
4.5
5.0
5.5
6.0
25
125
AMBIENT TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
AMBIENT TEMPERATURE (°C)
NORMALIZED SUPPLY CURRENT
vs. CLOCK PERIOD
TYPICAL ACCESS TIME CHANGE
vs. OUTPUT LOADING
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
175
150
1.02
1.00
0.98
30.0
25.0
20.0
15.0
V
CC
=5.5V
T =25°C
A
125
100
75
0.96
0.94
0.92
V
CC
=5.0V
10.0
5.0
50
T =25°C
A
T =25°C
A
V
CC
25
0
0.90
0.88
=4.5V
0.0
0.0
1.0
2.0
3.0
4.0
0
25
50
75
100
0
200 400
600 800 1000
CLOCK PERIOD (ns)
CAPACITANCE (pF)
OUTPUT VOLTAGE (V)
Document #: 38-04001 Rev. *C
Page 6 of 10
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CY7C225A
Ordering Information
Speed
Package
Type
Package
Type
Operating
Range
(ns)
Ordering
Code
tSA tCO
25
12 CY7C225A-25PC
P13
24-Lead (300-Mil) Molded DIP
Commercial
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Switching Characteristics
Parameter
VOH
VOL
VIH
Subgroups
1, 2, 3
Parameter
Subgroups
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
tSA
tHA
tCO
tDP
tRP
1, 2, 3
1, 2, 3
VIL
1, 2, 3
IIX
1, 2, 3
IOZ
1, 2, 3
ICC
1, 2, 3
Package Diagrams
Figure 2. 28-Lead Plastic Leaded Chip Carrier J64
51-85001-*A
Document #: 38-04001 Rev. *C
Page 7 of 10
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CY7C225A
Package Diagrams (Continued)
Figure 3. 28-Square Leadless Chip Carrier L64
MIL-STD-1835 C-4
51-80051-**
Document #: 38-04001 Rev. *C
Page 8 of 10
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CY7C225A
Package Diagrams (Continued)
Figure 4. 24-Lead (300-Mil) PDIP P13
51-85013-*B
All product and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-04001 Rev. *C
Page 9 of 10
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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CY7C225A
Document History Page
Document Title: CY7C225A 512 x 8 Registered PROM
Document Number: 38-04001
Issue
Date
Orig. of
Change
REV.
ECN NO.
Description of Change
**
113858
118892
122242
499538
03/06/02
10/09/02
12/27/02
See ECN
DSG
GBI
RBI
PCI
Changed from Spec number: 38-00228 to 38-04001
Updated ordering information
*A
*B
*C
Added power up requirements to Maximum Ratings Information
Updated ordering information
Document #: 38-04001 Rev. *C
Page 10 of 10
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