CY7C195-20PC [CYPRESS]
64K x 4 Static RAM; 64K ×4静态RAM
| 型号： | CY7C195-20PC |
| 厂家： | 
CYPRESS |
| 描述： | 64K x 4 Static RAM |
| 文件： | 总12页 (文件大小：218K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
96
CY7C194
CY7C195
CY7C196
64K x 4 Static RAM
able(s) (CE on the CY7C194 and CY7C195, CE1, CE2 on the
CY7C196) and three-state drivers. They have an automatic
power-down feature, reducing the power consumption by 75%
when deselected.
Features
• High speed
— 12 ns
Writing to the device is accomplished when the Chip Enable(s)
(CE on the CY7C194 and CY7C195, CE1, CE2 on the
CY7C196) and Write Enable (WE) inputs are both LOW. Data
on the four input pins (I/O0 through I/O3) is written into the
memory location, specified on the address pins (A0 through
A15).
• Output enable (OE) feature (7C195 and 7C196)
• CMOS for optimum speed/power
• Low active power
— 880 mW
• Low standby power
Reading the device is accomplished by taking the Chip En-
able(s) (CE on the CY7C194 and CY7C195, CE1, CE2 on the
CY7C196) LOW, while Write Enable (WE) remains HIGH. Un-
der these conditions the contents of the memory location
specified on the address pins will appear on the four data I/O
pins.
— 220 mW
• TTL-compatible inputs and outputs
• Automatic power-down when deselected
Functional Description
The CY7C194, CY7C195, and CY7C196 are high-perfor-
mance CMOS static RAMs organized as 65,536 by 4 bits.
Easy memory expansion is provided by active LOW Chip En-
A die coat is used to ensure alpha immunity.
Logic Block Diagram
Pin Configurations
DIP/SOJ
Top View
DIP/SOJ
Top View
V
28
27
26
1
2
3
4
5
6
V
NC
A
6
A
CC
1
24
CC
6
A
5
A
A
2
3
4
5
6
7
8
9
10
11
23
22
21
20
19
18
17
5
7
A
7
A
8
A
8
A
4
A
3
A
4
25
24
A
A
3
9
A
A
10
A
11
A
12
A
13
9
A
A
2
2
A
10
A
11
23
22
7C194
A
1
A
1
7C195
7C196
A
A
7
8
9
10
11
12
13
0
0
CE
A
12
A
13
2
21
20
19
18
17
NC
I/O
I/O
3
(7C196)
INPUT BUFFER
A
A
16
15
2
14
NC
A
A
I/O
I/O
I/O
15
14
3
1
(7C195)
A
1
I/O
I/O
I/O
15
2
1
0
CE
14
13
0
A
CE
2
12
1
GND
WE
I/O
I/O
3
A
OE
16
15
3
A
4
GND
WE
14
2
A
5
C194-2
1024 x 64 x 4
ARRAY
A
C194-3
6
A
7
A
I/O
I/O
1
8
A
9
0
A
10
POWER
DOWN
COLUMN
DECODER
CE (7C196 only)
1
2
CE
WE
(OE)
(7C195 and
7C196 ONLY)
C194-1
Selection Guide
7C194-12
7C195-12
7C196-12
7C194-15
7C195-15
7C196-15
7C194-20
7C195-20
7C196-20
7C194-25
7C195-25
7C196-25
7C194-35
7C195-35
7C196-35
7C194-45
7C196-45
Maximum Access Time (ns)
12
155
30
15
145
30
20
135
30
25
115
30
35
115
30
45
Maximum Operating Current (mA)
Maximum Standby Current (mA)
30
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Document #: 38-05162 Rev. **
Revised September 18, 2001
CY7C194
CY7C195
CY7C196
Output Current into Outputs (LOW)............................. 20 mA
Maximum Ratings
Static Discharge Voltage .......................................... >2001V
(per MIL-STD-883, Method 3015)
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Latch-Up Current.................................................... >200 mA
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Operating Range
Ambient
Supply Voltage to Ground Potential............... –0.5V to +7.0V
Range
Temperature[2]
VCC
DC Voltage Applied to Outputs
Commercial
0°C to +70°C
5V ± 10%
in High Z State[1]....................................–0.5V to VCC + 0.5V
]
DC Input Voltage[1] ................................–0.5V to VCC + 0.5V
Electrical Characteristics Over the Operating Range
7C194-12
7C195-12
7C196-12
7C194-15
7C195-15
7C196-15
Parameter
VOH
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Test Conditions
VCC = Min., IOH = −4.0 mA
VCC = Min., IOL = 8.0 mA
Min.
Max.
Min.
Max.
Unit
2.4
2.4
V
V
V
VOL
0.4
0.4
VIH
2.2
VCC
2.2
VCC
+ 0.3V
+ 0.3V
[1]
VIL
Input LOW Voltage
Input Load Current
−0.5
−5
0.8
+5
+5
−0.5
−5
0.8
+5
+5
V
IIX
GND < VI < VCC
µA
µA
IOZ
Output Leakage
Current
GND < VO < VCC
Output Disabled
,
−5
−5
IOS
ICC
ISB1
Output Short
VCC = Max.,
VOUT = GND
−300
155
30
−300
145
30
mA
mA
mA
Circuit Current[3]
VCC Operating
Supply Current
VCC=Max., IOUT=0 mA,
f=fMAX=1/tRC
Automatic CE
Max. VCC, CE1,2 > VIH,
VIN > VIH or VIN < VIL, f = fMAX
Power-Down Current
—TTL Inputs[4]
ISB2
Automatic CE
Max. VCC, CE1,2 > VCC - 0.3V,
VIN > VCC - 0.3V or
VIN < 0.3V, f = 0
10
10
mA
Power-Down Current
—CMOS Inputs[4]
Notes:
1. Minimum voltage is equal to –2.0V for pulse durations of less than 20 ns.
2. TA is the “Instant On” case temperature.
3. Not more than 1 output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
4. A pull-up resistor to VCC on the CE input is required to keep the device deselected during VCC power-up, otherwise ISB will exceed values given.
Document #: 38-05162 Rev. **
Page 2 of 12
CY7C194
CY7C195
CY7C196
)
Electrical Characteristics Over the Operating Range (continued)
7C194-20
7C195-20
7C196-20
7C194-25, 35, 45
7C195-25, 35
7C196-25, 35, 45
Parameter
VOH
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Test Conditions
VCC = Min., IOH = −4.0 mA
VCC = Min., IOL = 8.0 mA
Min.
Max.
Min.
Max.
Unit
V
2.4
2.4
VOL
VIH
0.4
0.4
V
2.2
VCC
2.2
VCC
V
+ 0.3V
+0.3V
VIL
IIX
Input LOW Voltage
Input Load Current
–0.5
–5
0.8
+5
+5
–0.5
–5
0.8
+5
+5
V
GND < VI < VCC
µA
µA
IOZ
Output Leakage
Current
GND < VO < VCC
Output Disabled
,
–5
–5
IOS
ICC
ISB1
Output Short
VCC = Max.,
VOUT = GND
–300
135
30
–300
115
30
mA
mA
mA
Circuit Current[3]
VCC Operating
Supply Current
VCC=Max., IOUT=0 mA,
f=fMAX=1/tRC
Automatic CE
Max. VCC, CE1,2 > VIH,
VIN > VIH or
VIN < VIL, f = fMAX
Power-Down Current
—TTL Inputs[4]
ISB2
Automatic CE
Max. VCC, CE1,2 > VCC –0.3V,
VIN > VCC – 0.3V or
VIN < 0.3V, f = 0
15
15
mA
Power-Down Current
—CMOS Inputs[4]
Capacitance[5]
Parameter
Description
Test Conditions
Max.
Unit
CIN
Input Capacitance
Output Capacitance
TA = 25°C, f = 1 MHz,
VCC = 5.0V
8
pF
pF
COUT
10
AC Test Loads and Waveforms[6]
R1 481Ω
R1 481Ω
5V
5V
OUTPUT
ALL INPUT PULSES
90%
OUTPUT
3.0V
GND
90%
10%
10%
< t
R2
255Ω
R2
255Ω
30 pF
5 pF
< t
r
r
INCLUDING
JIG AND
SCOPE
INCLUDING
JIG AND
SCOPE
C194-4
C194-5
(a)
(b)
Equivalent to:
THEÉVENIN EQUIVALENT
167Ω
OUTPUT
1.73V
Notes:
5. Tested initially and after any design or process changes that may affect these parameters.
6. tr = < 3 ns for the -12 and -15 speeds. T.r = < 5 ns for the -20 and slower speeds.
Document #: 38-05162 Rev. **
Page 3 of 12
CY7C194
CY7C195
CY7C196
:
Switching Characteristics Over the Operating Range[7]
7C194-12
7C195-12
7C196-12
7C194-15
7C195-15
7C196-15
7C194-20
7C195-20
7C196-20
7C194-25
7C195-25
7C196-25
7C194-35
7C195-35
7C196-35
7C194-45
7C196-45
Parameter
Description
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
READ CYCLE
tRC
tAA
Read Cycle Time
12
3
15
3
20
3
25
3
35
3
45
3
ns
ns
Address to Data
Valid
12
15
20
25
35
45
tOHA
Output Hold from
Address Change
ns
ns
ns
ns
ns
ns
ns
ns
ns
tACE1
tACE2
,
CE LOW to
Data Valid
12
5
15
7
20
9
25
10
35
16
45
16
tDOE
OE LOW to 7C195,
Data Valid
OE LOW to 7C195,
Low Z 7C196
7C196
tLZOE
tHZOE
tLZCE1
0
3
0
0
3
0
0
3
0
3
3
0
3
3
0
3
3
0
OEHIGHto 7C195,
5
5
7
7
9
9
11
11
25
15
15
35
15
15
45
High Z[8]
7C196
,
CE LOW to
Low Z[8]
tLZCE2
tHZCE1
tHZCE2
,
CE HIGH to
High Z[8,8]
tPU
tPD
CE LOW to
Power-Up
CE HIGH to
Power-Down
12
15
20
WRITE CYCLE[10]
tWC
tSCE
tAW
Write Cycle Time
12
9
15
10
10
20
15
15
25
18
20
35
22
25
45
22
35
ns
ns
ns
CE LOW to Write End
Address Set-Up to
Write End
9
tHA
tSA
Address Hold from
Write End
0
0
0
0
0
0
0
0
0
0
0
0
ns
ns
Address Set-Up to
Write Start
tPWE
tSD
WE Pulse Width
8
8
9
9
15
10
18
10
22
15
22
15
ns
ns
Data Set-Up to
Write End
tHD
Data Hold from
Write End
0
3
0
3
0
3
0
3
0
0
3
0
0
3
0
ns
ns
ns
tLZWE
WE HIGH to
Low Z[8]
tHZWE
WE LOW to
High Z[8, 9]
7
7
10
13
15
20
Notes:
7. Test conditions assume signal transition time of 3 ns or less for -12 and -15 speeds and 5 ns or less for -20 and slower speeds, timing reference levels of 1.5V,
input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 30-pF load capacitance.
8. tHZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
9. At any given temperature and voltage condition, tHZCE is less than tLZCE and tHZWE is less than tLZWE for any given device.
10. The internal write time of the memory is defined by the overlap of CE1 LOW, CE2 LOW, and WE LOW. All signals must be LOW to initiate a write and any signal can
terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
Document #: 38-05162 Rev. **
Page 4 of 12
CY7C194
CY7C195
CY7C196
Switching Waveforms
Read Cycle No. 1[11, 12]
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
C194-8
[11, 13]
Read Cycle No. 2
t
RC
CE , CE
1
2
t
t
ACE
OE
(7C195 and
7C196)
t
t
HZOE
HZCE
t
DOE
LZOE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA OUT
DATA VALID
t
LZCE
t
PD
t
PU
V
ICC
ISB
CC
SUPPLY
CURRENT
50%
50%
C194-6
Write Cycle No. 1 (CE Controlled)[10, 14, 15]
t
WC
ADDRESS
t
CE
1
SCE
CE
(7C196)
2
t
SA
t
t
HA
AW
WE
t
t
HD
SD
DATA I/O
DATA VALID
C194-7
Notes:
11. WE is HIGH for read cycle.
12. Device is continuously selected: CE1 = VIL, CE2 = VIL (7C196), and OE = VIL (7C195 and 7C196).
13. Address valid prior to or coincident with CE1 and CE2 transition LOW.
14. Data I/O will be high impedance if OE = VIH (7C195 and 7C196).
15. If any CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
Document #: 38-05162 Rev. **
Page 5 of 12
CY7C194
CY7C195
CY7C196
Switching Waveforms (continued)
Write Cycle No. 2 (WE Controlled, OE HIGH During Write for 7C195and 7C196only)[10, 14, 15]
t
WC
ADDRESS
CE
1
(7C196)
CE
2
t
t
HA
AW
t
SA
t
PWE
WE
OE
t
SD
t
HD
DATA I/O
DATA VALID
C194-8
t
HZOE
Write Cycle No. 3 (WE Controlled, OE LOW)[15, 16]
t
WC
ADDRESS
CE
1
CE (7C196)
2
t
t
HA
AW
t
SA
WE
t
t
HD
SD
DATA I/O
DATA VALID
t
t
LZWE
HZWE
C194-9
Note:
16. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD
.
Document #: 38-05162 Rev. **
Page 6 of 12
CY7C194
CY7C195
CY7C196
Typical DC and AC Characteristics
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
OUTPUT SOURCE CURRENT
vs. OUTPUT VOLTAGE
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
120
100
80
1.4
1.2
1.4
1.2
1.0
0.8
0.6
I
CC
I
CC
1.0
0.8
0.6
V
CC
=5.0V
60
T =25°C
A
V
IN
=5.0V
T =25°C
A
40
V
V
IN
=5.0V
=5.0V
0.4
CC
0.4
20
0
0.2
0.0
0.2
0.0
I
SB
I
SB
−55
25
125
0.0
1.0
2.0
3.0
4.0
4.0
4.5
5.0
5.5
6.0
AMBIENT TEMPERATURE(°C)
OUTPUT VOLTAGE(V)
SUPPLY VOLTAGE(V)
NORMALIZED ACCESS TIME
vs. AMBIENT TEMPERATURE
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
NORMALIZED ACCESS TIME
vs. SUPPLY VOLTAGE
140
120
1.6
1.4
1.4
1.3
1.2
100
80
1.2
1.0
1.1
1.0
60
T =25°C
A
V
CC
=5.0V
T =25°C
A
V
CC
=5.0V
40
0.8
20
0
0.9
0.8
0.6
0.0
1.0
2.0
3.0
4.0
−55
25
125
4.0
4.5
5.0
5.5
6.0
AMBIENT TEMPERATURE (°C)
OUTPUT VOLTAGE (V)
SUPPLY VOLTAGE (V)
TYPICAL POWER-ON CURRENT
vs. SUPPLY VOLTAGE
TYPICAL ACCESS TIME CHANGE
vs. OUTPUT LOADING
NORMALIZED I vs.CYCLE TIME
CC
3.0
2.5
2.0
1.5
30.0
25.0
20.0
15.0
1.25
1.00
0.75
0.50
V
=5.0V
CC
T =25°C
A
V
IN
=0.5V
V
=4.5V
1.0
0.5
10.0
5.0
CC
T =25°C
A
0.0
0.0
0.0
1.0
2.0
3.0
4.0
5.0
0
200 400
600 800 1000
10
20
30
40
SUPPLY VOLTAGE (V)
CAPACITANCE (pF)
CYCLE FREQUENCY (MHz)
Document #: 38-05162 Rev. **
Page 7 of 12
CY7C194
CY7C195
CY7C196
7C194 Truth Table
CE
H
WE
X
Data I/O
Mode
Deselect/Power-Down
Read
Power
High Z
Standby (ISB
)
L
H
Data Out
Data In
Active (ICC
)
L
L
Write
Active (ICC)
7C195 Truth Table
CE1
H
WE
X
OE
Data I/O
Mode
Power
X
L
High Z
Deselect/Power-Down
Standby (ISB
Active (ICC
Active (ICC
Active (ICC
)
L
H
Data Out
Data In
High Z
Read
)
L
L
X
H
Write
)
L
H
Deselect
)
7C196 Truth Table
CE1
H
CE2
X
WE
X
OE
Data I/O
Mode
Power
Standby (ISB
X
X
L
High Z
Deselect/Power-Down
)
X
H
X
L
L
H
Data Out
Read
Active (ICC
Active (ICC
Active (ICC)
)
L
L
L
X
H
Data In
High Z
Write
)
L
L
H
Deselect
Document #: 38-05162 Rev. **
Page 8 of 12
CY7C194
CY7C195
CY7C196
Ordering Information
Speed (ns)
Ordering Code
Package Name
P13
Package Type
24-Lead (300-Mil) Molded DIP
24-Lead Molded SOJ
Operating Range
12
CY7C194-12PC
CY7C194-12VC
CY7C194-15PC
CY7C194-15VC
CY7C194-20PC
CY7C194-20VC
CY7C194-25PC
CY7C194-25VC
CY7C194-35PC
CY7C194-35VC
CY7C194-45PC
CY7C194-45VC
Commercial
V13
15
20
25
35
45
P13
24-Lead (300-Mil) Molded DIP
24-Lead Molded SOJ
Commercial
Commercial
Commercial
Commercial
Commercial
V13
P13
24-Lead (300-Mil) Molded DIP
24-Lead Molded SOJ
V13
P13
24-Lead (300-Mil) Molded DIP
24-Lead Molded SOJ
V13
P13
24-Lead (300-Mil) Molded DIP
24-Lead Molded SOJ
V13
P13
24-Lead (300-Mil) Molded DIP
24-Lead Molded SOJ
V13
Speed (ns)
Ordering Code
Package Name
P21
Package Type
28-Lead (300-Mil) Molded DIP
28-Lead Molded SOJ
Operating Range
12
CY7C195-12PC
CY7C195-12VC
CY7C195-15PC
CY7C195-15VC
CY7C195-20PC
CY7C195-20VC
CY7C195-25PC
CY7C195-25VC
CY7C195-35PC
CY7C195-35VC
CY7C195-45PC
CY7C195-45VC
Commercial
V21
15
20
25
35
45
P21
28-Lead (300-Mil) Molded DIP
28-Lead Molded SOJ
Commercial
Commercial
Commercial
Commercial
Commercial
V21
P21
28-Lead (300-Mil) Molded DIP
28-Lead Molded SOJ
V21
P21
28-Lead (300-Mil) Molded DIP
28-Lead Molded SOJ
V21
P21
28-Lead (300-Mil) Molded DIP
28-Lead Molded SOJ
V21
P21
28-Lead (300-Mil) Molded DIP
28-Lead Molded SOJ
V21
)
Speed (ns)
Ordering Code
Package Name
Package Type
28-Lead (300-Mil) Molded DIP
28-Lead Molded SOJ
Operating Range
12
CY7C196-12PC
CY7C196-12VC
CY7C196-15PC
CY7C196-15VC
CY7C196-20PC
CY7C196-20VC
CY7C196-25PC
CY7C196-25VC
CY7C196-35PC
CY7C196-35VC
P21
V21
P21
V21
P21
V21
P21
V21
P21
V21
Commercial
15
20
25
35
28-Lead (300-Mil) Molded DIP
28-Lead Molded SOJ
Commercial
Commercial
Commercial
Commercial
28-Lead (300-Mil) Molded DIP
28-Lead Molded SOJ
28-Lead (300-Mil) Molded DIP
28-Lead Molded SOJ
28-Lead (300-Mil) Molded DIP
28-Lead Molded SOJ
Document #: 38-05162 Rev. **
Page 9 of 12
CY7C194
CY7C195
CY7C196
Package Diagrams
24-Lead (300-Mil) Molded DIP P13/P13A
51-85013-A
28-Lead (300-Mil) Molded DIP P21
51-85014-B
Document #: 38-05162 Rev. **
Page 10 of 12
CY7C194
CY7C195
CY7C196
Package Diagrams (continued)
24-Lead (300-Mil) Molded SOJ V13
51-85030-A
28-Lead (300-Mil) Molded SOJ V21
51-85031-B
Document #: 38-05162 Rev. **
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© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C194
CY7C195
CY7C196
Document Title: CY7C194/CY7C195/CY7C196 64K x 4 Static RAM
Document Number: 38-05162
Issue
ECN NO. Date
Orig. of
Change
REV.
Description of Change
**
110172
09/29/01
SZV
Change from Spec number: 38-00081 to 38-05162
Document #: 38-05162 Rev. **
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