CY7C166-15VCR [CYPRESS]
Standard SRAM, 16KX4, 15ns, CMOS, PDSO24, 0.300 INCH, PLASTIC, SOJ-24;
| 型号： | CY7C166-15VCR |
| 厂家： | 
CYPRESS |
| 描述： | Standard SRAM, 16KX4, 15ns, CMOS, PDSO24, 0.300 INCH, PLASTIC, SOJ-24 |
| 文件： | 总9页 (文件大小：174K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
66
CY7C164
CY7C166
16K x 4 Static RAM
three-state drivers. The CY7C166 has an active LOW Output
Enable (OE) feature. Both devices have an automatic power-
down feature, reducing the power consumption by 65% when
deselected.
Features
• High speed
— 15 ns
Writing to the device is accomplished when the Chip Enable
(CE) and Write Enable (WE) inputs are both LOW (and the
Output Enable (OE) is LOW for the CY7C166). Data on the
four input/output pins (I/O0 through I/O3) is written into the
memory location specified on the address pins (A0 through
A13).
• Output enable (OE) feature (CY7C166)
• CMOS for optimum speed/power
• Low active power
— 633 mW
• Low standby power
Reading the device is accomplished by taking Chip Enable
(CE) LOW (and OE LOW for CY7C166), while Write Enable
(WE) remains HIGH. Under these conditions the contents of
the memory location specified on the address pins will appear
on the four data I/O pins.
— 110 mW
• TTL-compatible inputs and outputs
• Automatic power-down when deselected
Functional Description
The I/O pins stay in a high-impedance state when Chip Enable
(CE) is HIGH (or Output Enable (OE) is HIGH for CY7C166).
A die coat is used to insure alpha immunity.
The CY7C164 and CY7C166 are high-performance CMOS
static RAMs organized as 16,384 by 4 bits. Easy memory ex-
pansion is provided by an active LOW Chip Enable (CE) and
Logic Block Diagram
Pin Configurations
SOJ
Top View
DIP
Top View
A
V
A
V
CC
1
2
3
4
5
6
7
8
9
22
21
20
19
5
CC
5
1
24
A
A
A
A
4
A
3
6
4
6
2
3
4
23
22
21
20
19
18
17
A
A
3
A
7
7
A
8
A
A
A
2
A
1
8
2
A
A
1
A
18
17
16
15
9
9
5
6
7
8
9
10
11
12
7C164
A
A
A
A
A
A
A
A
7C164
A
A
0
10
11
10
11
0
I/O
I/O
I/O
I/O
NC
I/O
3
2
1
0
12
13
12
13
3
I/O
I/O
I/O
14
13
12
16
2
1
0
CE
NC
CE
GND
10
11
15
14
13
WE
INPUT BUFFER
GND
WE
C164–3
C164–2
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
I/O
I/O
3
DIP/SOJ
Top View
2
256 x 64 x 4
ARRAY
A
5
V
CC
1
2
3
24
23
22
I/O
I/O
1
A
6
A
4
A
A
3
7
0
A
4
5
6
7
A
8
21
20
19
18
17
2
A
A
1
9
A
A
A
A
7C166
POWER
DOWN
A
0
10
11
COLUMN
DECODER
NC
I/O
CE
12
13
8
3
I/O
I/O
I/O
9
16
15
14
13
2
1
0
WE
(OE)
(7C166 ONLY)
CE
OE
GND
10
11
12
WE
C166–1
C164–4
]
Selection Guide
7C164-15
7C166-15
7C164-20
7C166-20
7C164-25
7C166-25
7C164-35
7C166-35
Maximum Access Time (ns)
15
115
20
20
115
20
25
105
20
35
105
20
Maximum Operating Current (mA)
Maximum Standby Current (mA)
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Document #: 38-05025 Rev. **
Revised August 24, 2001
CY7C164
CY7C166
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage .......................................... >2001V
(per MIL-STD-883, Method 3015)
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Latch-Up Current.................................................... >200 mA
Power Applied.............................................–55°C to +125°C
Operating Range
Supply Voltage to Ground Potential............... –0.5V to +7.0V
DC Voltage Applied to Outputs
Ambient
Temperature
in High Z State[1]............................................ –0.5V to +7.0V
Range
VCC
DC Input Voltage[1] ........................................ –0.5V to +7.0V
Commercial
0°C to +70°C
5V ± 10%
Electrical Characteristics Over the Operating Range
7C164-15
7C166-15
7C164-20
7C166-20
7C164-25, 35
7C166-25, 35
Parameter
VOH
Description
Output HIGH
Voltage
Test Conditions
VCC = Min.,
IOH = –4.0 mA
Min. Max. Min. Max.
Min.
Max.
Unit
2.4
2.4
2.4
V
VOL
Output LOW
Voltage
VCC = Min.,
IOL = 8.0 mA
0.4
0.4
0.4
V
VIH
VIL
Input HIGH Voltage
2.2
VCC
0.8
2.2
VCC
0.8
2.2
VCC
0.8
V
V
Input LOW
Voltage[1]
–0.5
–0.5
–0.5
IIX
Input Load Current
GND < VI < VCC
–5
–5
+5
+5
–5
–5
+5
+5
–5
–5
+5
+5
µA
µA
IOZ
Output Leakage
Current
GND < VO < VCC
Output Disabled
,
IOS
ICC
ISB1
ISB2
Output Short
VCC = Max.,
VOUT = GND
–350
115
40
–350
115
40
–350
105
20
mA
mA
mA
mA
Circuit Current[2]
VCC Operating
Supply Current
VCC = Max.,
IOUT = 0 mA
Automatic CE
Max. VCC, CE > VIH,
Min. Duty Cycle = 100%
Power-Down Current[3]
Automatic CE
Max. VCC
,
20
20
20
Power-Down Current[3]
CE > VCC – 0.3V,
VIN > VCC – 0.3V
or VIN < 0.3V
Capacitance[4]
Parameter
Description
Test Conditions
Max.
Unit
CIN
Input Capacitance
Output Capacitance
TA = 25°C, f = 1 MHz,
VCC = 5.0V
10
10
pF
pF
COUT
Notes:
1. Minimum voltage is equal to –3.0V for pulse durations less than 30 ns.
2. Not more than 1 output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
3. A pull-up resistor to VCC on the CE input is required to keep the device deselected during VCC power-up, otherwise ISB will exceed values given.
4. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05025 Rev. **
Page 2 of 9
CY7C164
CY7C166
AC Test Loads and Waveforms
R1 481Ω
R1 481Ω
5V
5V
OUTPUT
ALL INPUT PULSES
90%
OUTPUT
3.0V
GND
90%
10%
10%
< 5 ns
R2
255Ω
R2
255Ω
30 pF
5 pF
< 5 ns
INCLUDING
JIG AND
SCOPE
INCLUDING
JIG AND
SCOPE
C164–6
C164–5
(a)
(b)
Equivalent to:
THÉVENIN EQUIVALENT
167Ω
OUTPUT
1.73V
Switching Characteristics Over the Operating Range[5]
7C164-15
7C166-15
7C164-20
7C166-20
7C164-25
7C166-25
7C164-35
7C166-35
Parameter
READ CYCLE
tRC
Description
Min. Max.
Min.
20
5
Max. Min.
Max.
Min. Max. Unit
Read Cycle Time
15
3
25
35
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
Address to Data Valid
15
20
25
35
tOHA
Output Hold from Address Change
CE LOW to Data Valid
5
tACE
15
10
20
10
3
25
12
35
15
tDOE
OE LOW to Data Valid
OE LOW to Low Z
7C166
tLZOE
tHZOE
tLZCE
7C166
7C166
3
3
0
3
5
0
3
5
0
OE HIGH to High Z
8
8
8
10
10
20
12
15
20
CE LOW to Low Z[6]
CE HIGH to High Z[6, 7]
CE LOW to Power-Up
CE HIGH to Power-Down
5
tHZCE
tPU
8
0
tPD
15
20
WRITE CYCLE[8]
tWC
tSCE
tAW
tHA
Write Cycle Time
15
12
12
0
20
15
15
0
20
25
25
25
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CE LOW to Write End
20
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
20
0
tSA
0
0
0
0
tPWE
tSD
12
10
0
15
10
0
15
20
15
0
Data Set-Up to Write End
Data Hold from Write End
WE HIGH to Low Z[6]
10
tHD
0
tLZWE
5
5
5
5
tHZWE
WE LOW to High Z[6, 7]
7
7
7
10
Notes:
5. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and 30-pF load capacitance.
6. At any given temperature and voltage condition, tHZCE is less than tLZCE for any given device. These parameters are guaranteed by design and not 100% tested.
7.
tHZCE and tHZWE are specified with CL = 5 pF as in part (b) in AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
8. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate
a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
Document #: 38-05025 Rev. **
Page 3 of 9
CY7C164
CY7C166
Switching Waveforms
[9, 10]
Read Cycle No.1
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
C164–7
Read CycleNo. 2 [9, 11]
t
RC
CE
t
ACE
OE
7C166
t
t
HZOE
t
DOE
HZCE
t
LZOE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA OUT
DATA VALID
t
LZCE
t
PD
t
PU
V
ICC
ISB
CC
SUPPLY
CURRENT
50%
50%
C164–8
WriteCycleNo.1 (WE Controlled) [8, 12]
t
WC
ADDRESS
CE
t
SCE
t
t
HA
AW
t
SA
t
PWE
WE
t
t
HD
SD
DATA VALID
DATA IN
IN
t
t
LZWE
HZWE
HIGH IMPEDANCE
DATA I/O
DATA UNDEFINED
C164–9
Notes:
9. WE is HIGH for read cycle.
10. Device is continuously selected, CE = VIL. (CY7C166: OE = VIL also).
11. Address valid prior to or coincident with CE transition LOW.
12. CY7C166 only: Data I/O will be high-impedance if OE = VIH
.
Document #: 38-05025 Rev. **
Page 4 of 9
CY7C164
CY7C166
Switching Waveforms (continued)
WriteCycleNo. 2 (CE Controlled) [8, 12, 13]
t
WC
ADDRESS
t
SA
t
SCE
CE
t
t
HA
AW
t
PWE
WE
t
t
HD
SD
DATA IN
DATA VALID
IN
HIGH IMPEDANCE
DATA I/O
C164–10
Note:
13. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
Document #: 38-05025 Rev. **
Page 5 of 9
CY7C164
CY7C166
Typical DC and AC Characteristics
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
OUTPUT SOURCE CURRENT
vs. OUTPUT VOLTAGE
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
120
100
80
1.4
1.2
1.2
1.0
0.8
I
I
CC
CC
1.0
0.8
0.6
V
= 5.0V
CC
0.6
0.4
60
T = 25°C
A
40
V
V
= 5.0V
= 5.0V
CC
0.4
IN
0.2
0.0
20
0
I
0.2
0.0
SB
ISB
–55
25
125
0.0
1.0
2.0
3.0
4.0
4.0
4.5
5.0
5.5
6.0
AMBIENT TEMPERATURE (°C)
OUTPUT VOLTAGE (V)
SUPPLY VOLTAGE (V)
NORMALIZED ACCESS TIME
vs. AMBIENT TEMPERATURE
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
NORMALIZED ACCESS TIME
vs. SUPPLY VOLTAGE
140
120
1.6
1.4
1.4
1.3
1.2
100
80
V
CC
= 5.0V
1.2
1.0
T =25°C
A
1.1
1.0
60
T = 25°C
A
V
CC
=5.0V
40
0.8
20
0
0.9
0.8
0.6
–55
0.0
1.0
2.0
3.0
4.0
25
125
4.0
4.5
5.0
5.5
6.0
AMBIENT TEMPERATURE (°C)
OUTPUT VOLTAGE (V)
SUPPLY VOLTAGE (V)
TYPICAL POWER-ON CURRENT
vs. SUPPLY VOLTAGE
TYPICAL ACCESS TIME CHANGE
vs. OUTPUT LOADING
NORMALIZED I vs. CYCLETIME
CC
3.0
2.5
2.0
1.5
30.0
25.0
20.0
15.0
1.25
1.00
0.75
0.50
V
= 5.0V
CC
T = 25°C
A
V
IN
= 0.5V
1.0
0.5
0.0
10.0
5.0
V
= 4.5V
CC
T = 25°C
A
0.0
0.0
1.0
2.0
3.0
4.0
5.0
0
200 400
600 800 1000
10
20
30
40
SUPPLY VOLTAGE (V)
CAPACITANCE (pF)
CYCLE FREQUENCY (MHz)
Document #: 38-05025 Rev. **
Page 6 of 9
CY7C164
CY7C166
CY7C164 Truth Table
Address Designators
CE WE
Input/Output
High Z
Mode
Deselect/Power-Down
Read
Address
Name
Address CY 7C164 Pin CY7C166 Pin
Function
Number
Number
H
L
L
X
H
L
A5
A6
X3
1
2
1
2
Data Out
Data In
X4
Write
A7
X5
3
3
A8
X6
4
4
CY7C166 Truth Table
A9
X7
5
5
CE WE OE
Input/Output
Mode
A10
A11
A12
A13
A0
Y5
6
6
H
L
L
L
X
H
L
X
L
High Z
Deselect/Power-Down
Y4
7
7
Data Out
Data In
High Z
Read
Write
Write
Y0
8
8
H
H
Y1
9
9
H
Y2
17
18
19
20
21
19
20
21
22
23
A1
Y3
A2
X0
A3
X1
A4
X2
Ordering Information
Speed
(ns)
Package
Name
Operating
Range
Ordering Code
Package Type
15
20
25
35
CY7C164-15PC
CY7C164-15VC
CY7C164-20PC
CY7C164-20VC
CY7C164-25PC
CY7C164-25VC
CY7C164-35PC
CY7C164-35VC
P9
22-Lead (300-Mil) Molded DIP
24-Lead Molded SOJ
Commercial
V13
P9
22-Lead (300-Mil) Molded DIP
24-Lead Molded SOJ
Commercial
Commercial
Commercial
V13
P9
22-Lead (300-Mil) Molded DIP
24-Lead Molded SOJ
V13
P9
22-Lead (300-Mil) Molded DIP
24-Lead Molded SOJ
V13
Speed
(ns)
Package
Name
Operating
Ordering Code
Package Type
24-Lead (300-Mil) Molded DIP
24-Lead Molded SOJ
Range
15
20
25
35
CY7C166-15PC
CY7C166-15VC
CY7C166-20PC
CY7C166-20VC
CY7C166-25PC
CY7C166-25VC
CY7C166-35PC
CY7C166-35VC
P13
V13
P13
V13
P13
V13
P13
V13
Commercial
24-Lead (300-Mil) Molded DIP
24-Lead Molded SOJ
Commercial
Commercial
Commercial
24-Lead (300-Mil) Molded DIP
24-Lead Molded SOJ
24-Lead (300-Mil) Molded DIP
24-Lead Molded SOJ
Document #: 38-05025 Rev. **
Page 7 of 9
CY7C164
CY7C166
Package Diagrams
22-Lead (300-Mil) Molded DIP P9
51-85012-A
24-Lead (300-Mil) Molded DIP P13/P13A
51-85013-A
24-Lead (300-Mil) Molded SOJ V13
51-85030-A
Document #: 38-05025 Rev. **
Page 8 of 9
© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C164
CY7C166
Document Title: CY7C164, CY7C166 16K x 4 Static RAM
Document Number: 38-05025
Issue
Date
Orig. of
Change
REV.
ECN NO.
Description of Change
Change from Spec number: 38-00032 to 38-05025
**
106811
09/10/01
SZV
Document #: 38-05025 Rev. **
Page 9 of 9
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