CY7C164_06 [CYPRESS]
16K x 4 Static RAM; 16K ×4静态RAM
| 型号： | CY7C164_06 |
| 厂家： | 
CYPRESS |
| 描述： | 16K x 4 Static RAM |
| 文件： | 总9页 (文件大小：265K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C164
CY7C166
16K x 4 Static RAM
Features
Functional Description
The CY7C164 and CY7C166 are high-performance CMOS
static RAMs organized as 16,384 by 4 bits. Easy memory
expansion is provided by an active LOW Chip Enable (CE) and
tri-state drivers. The CY7C166 has an active LOW Output
Enable (OE) feature. Both devices have an automatic power-
down feature, reducing the power consumption by 65% when
deselected.
• High speed
— 15 ns
• Output enable (OE) feature (CY7C166)
• CMOS for optimum speed/power
• Low active power
Writing to the device is accomplished when the Chip Enable
(CE) and Write Enable (WE) inputs are both LOW (and the
Output Enable (OE) is LOW for the CY7C166). Data on the
four input/output pins (I/O0 through I/O3) is written into the
memory location specified on the address pins (A0 through
— 633 mW
• Low standby power
— 110 mW
• TTL-compatible inputs and outputs
• Automatic power-down when deselected
A13).
Reading the device is accomplished by taking Chip Enable
(CE) LOW (and OE LOW for CY7C166), while Write Enable
(WE) remains HIGH. Under these conditions the contents of
the memory location specified on the address pins will appear
on the four data I/O pins.
• CY7C164 is available in non Pb-free 22-pin (300-Mil)
MoldedDIP, CY7C166innonPb-free24-pinMoldedSOJ
The I/O pins stay in a high-impedance state when Chip Enable
(CE) is HIGH (or Output Enable (OE) is HIGH for CY7C166).
A die coat is used to insure alpha immunity.
Logic Block Diagram
Pin Configurations
DIP
SOJ
Top View
Top View
A
A
A
A
A
V
CC
1
2
3
4
5
6
7
8
9
22
21
20
19
5
A
V
CC
1
2
3
4
5
6
7
8
5
24
23
22
A
A
6
7
8
9
4
A
6
A
4
3
A
A
3
7
A
2
A
1
A
8
A
21
20
19
18
17
2
A
A
1
18
17
16
15
9
INPUT BUFFER
A
10
A
11
A
10
A
11
7C166
7C164
A
0
A
0
I/O
I/O
I/O
I/O
NC
I/O
3
2
1
0
A
A
12
A
13
I/O
I/O
A
12
A
13
1
3
3
A
2
I/O
9
14
13
12
2
16
15
14
13
A
3
2
I/O
1
CE
OE
GND
10
11
12
16K x 4
ARRAY
CE
GND
10
11
A
4
A
I/O
0
WE
5
6
I/O
I/O
A
1
WE
A
7
8
A
0
POWER
DOWN
COLUMN
DECODER
CE
WE
(OE)
(7C166 ONLY)
Cypress Semiconductor Corporation
Document #: 38-05025 Rev. *A
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised August 3, 2006
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CY7C164
CY7C166
Selection Guide
CY7C164-15
CY7C166-15
CY7C164-25
CY7C166-25
Maximum Access Time (ns)
15
115
20
25
105
20
Maximum Operating Current (mA)
Maximum CMOS Standby Current (mA)
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage........................................... >2001V
(per MIL-STD-883, Method 3015)
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Latch-Up Current.................................................... >200 mA
Power Applied.............................................–55°C to +125°C
Operating Range
Supply Voltage to Ground Potential............... –0.5V to +7.0V
DC Voltage Applied to Outputs
Ambient
Temperature
in High Z State[1] ............................................ –0.5V to +7.0V
Range
VCC
DC Input Voltage[1]......................................... –0.5V to +7.0V
Commercial
0°C to +70°C
5V ± 10%
Electrical Characteristics Over the Operating Range
–15
–25
Parameter
VOH
VOL
VIH
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage[1]
Input Leakage Current
Output Leakage Current
VCC Operating Supply Current
Test Conditions
Min.
Max.
Min.
Max.
Unit
VCC = Min., IOH = –4.0 mA
VCC = Min., IOL = 8.0 mA
2.4
2.4
V
V
0.4
VCC
0.8
+5
0.4
VCC
0.8
+5
2.2
–0.5
–5
2.2
–0.5
–5
V
VIL
V
IIX
GND < VI < VCC
µA
µA
mA
mA
IOZ
GND < VO < VCC, Output Disabled
VCC = Max., IOUT = 0 mA
–5
+5
–5
+5
ICC
115
40
105
20
ISB1
Automatic CE
Max. VCC, CE > VIH,
Min. Duty Cycle = 100%
Power-Down Current[2]
ISB2
Automatic CE
Max. VCC, CE > VCC – 0.3V,
VIN > VCC – 0.3V or VIN < 0.3V
20
20
mA
Power-Down Current[2]
Capacitance[3]
Parameter
Description
Input Capacitance
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
CC = 5.0V
Max.
Unit
CIN
10
10
pF
pF
V
COUT
Notes:
1. Minimum voltage is equal to –3.0V for pulse durations less than 30 ns.
2. A pull-up resistor to V on the CE input is required to keep the device deselected during V power-up, otherwise I will exceed values given.
CC
CC
SB
3. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05025 Rev. *A
Page 2 of 9
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CY7C164
CY7C166
AC Test Loads and Waveforms
R1 481Ω
R1 481Ω
5V
5V
OUTPUT
ALL INPUT PULSES
OUTPUT
3.0V
GND
90%
10%
90%
10%
< 5 ns
R2
255Ω
R2
255Ω
30 pF
5 pF
< 5 ns
INCLUDING
JIG AND
SCOPE
INCLUDING
JIG AND
SCOPE
C164–6
C164–5
(a)
(b)
Equivalent to:
THÉVENIN EQUIVALENT
167Ω
OUTPUT
1.73V
Switching Characteristics Over the Operating Range[4]
CY7C164-15
CY7C166-15
CY7C164-25
CY7C166-25
Parameter
Description
Min.
Max.
Min.
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
15
3
25
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
Address to Data Valid
Output Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
15
25
tOHA
tACE
15
10
25
12
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
tPU
7C166
7C166
7C166
3
3
0
3
5
0
OE HIGH to High Z
CE LOW to Low Z[5]
CE HIGH to High Z[5, 6]
CE LOW to Power-Up
CE HIGH to Power-Down
8
8
10
10
20
tPD
15
WRITE CYCLE[7]
tWC
Write Cycle Time
15
12
12
0
20
20
20
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSCE
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
tAW
tHA
tSA
0
0
tPWE
tSD
12
10
0
15
10
0
Data Set-Up to Write End
Data Hold from Write End
WE HIGH to Low Z[5]
tHD
tLZWE
tHZWE
5
5
WE LOW to High Z[5, 6]
7
7
Notes:
4. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
/I and 30-pF load capacitance.
OL OH
5. At any given temperature and voltage condition, t
is less than t
for any given device. These parameters are guaranteed by design and not 100% tested.
HZCE
LZCE
6. t
and t
are specified with C = 5 pF as in part (b) in AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
HZCE
HZWE L
7. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate a
write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
Document #: 38-05025 Rev. *A
Page 3 of 9
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CY7C164
CY7C166
Switching Waveforms
Read Cycle No. 1[8,9]
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
C164–7
Read Cycle No. 2[8,10]
t
RC
CE
t
ACE
OE
7C166
t
t
HZOE
t
DOE
HZCE
t
LZOE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA OUT
DATA VALID
t
LZCE
t
PD
t
PU
V
ICC
CC
SUPPLY
CURRENT
50%
50%
ISB
C164–8
Notes:
8. WE is HIGH for read cycle.
9. Device is continuously selected, CE = V . (CY7C166: OE = V also).
IL
IL
10. Address valid prior to or coincident with CE transition LOW.
Document #: 38-05025 Rev. *A
Page 4 of 9
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CY7C164
CY7C166
Switching Waveforms (continued)
Write Cycle No. 1(WE Controlled)[7,11]
t
WC
ADDRESS
CE
t
SCE
t
t
HA
AW
t
SA
t
PWE
WE
t
t
HD
SD
DATA VALID
DATA IN
IN
t
t
LZWE
HZWE
HIGH IMPEDANCE
DATA I/O
DATA UNDEFINED
C164–9
Write Cycle No. 2(CE Controlled)[7,11,12]
t
WC
ADDRESS
t
SA
t
SCE
CE
t
t
HA
AW
t
PWE
WE
t
t
HD
SD
DATA IN
DATA VALID
IN
HIGH IMPEDANCE
DATA I/O
C164–10
Notes:
11. CY7C166 only: Data I/O will be high-impedance if OE = V
.
IH
12. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
Document #: 38-05025 Rev. *A
Page 5 of 9
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CY7C164
CY7C166
Typical DC and AC Characteristics
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
OUTPUT SOURCE CURRENT
vs. OUTPUT VOLTAGE
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
120
100
80
1.4
1.2
1.2
1.0
0.8
I
I
CC
CC
1.0
0.8
0.6
V
= 5.0V
CC
0.6
0.4
60
T = 25°C
A
40
V
V
= 5.0V
= 5.0V
CC
IN
0.4
0.2
0.0
20
0
I
0.2
0.0
SB
ISB
–55
25
125
0.0
1.0
2.0
3.0
4.0
4.0
4.5
5.0
5.5
6.0
AMBIENT TEMPERATURE (°C)
OUTPUT VOLTAGE (V)
SUPPLY VOLTAGE (V)
NORMALIZED ACCESS TIME
vs. AMBIENT TEMPERATURE
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
NORMALIZED ACCESS TIME
vs. SUPPLY VOLTAGE
140
120
1.6
1.4
1.4
1.3
1.2
100
80
V
= 5.0V
CC
1.2
1.0
T =25°C
A
1.1
1.0
60
T = 25°C
A
V
CC
=5.0V
40
0.8
20
0
0.9
0.8
0.6
–55
0.0
1.0
2.0
3.0
4.0
25
125
4.0
4.5
5.0
5.5
6.0
AMBIENT TEMPERATURE (°C)
OUTPUT VOLTAGE (V)
SUPPLY VOLTAGE (V)
TYPICAL POWER-ON CURRENT
vs. SUPPLY VOLTAGE
TYPICAL ACCESS TIME CHANGE
vs. OUTPUT LOADING
NORMALIZED I vs. CYCLETIME
CC
3.0
2.5
2.0
1.5
30.0
25.0
20.0
15.0
1.25
1.00
0.75
0.50
V
= 5.0V
CC
T = 25°C
A
V
IN
= 0.5V
1.0
0.5
0.0
10.0
5.0
V
= 4.5V
CC
T = 25°C
A
0.0
0.0
1.0
2.0
3.0
4.0
5.0
0
200 400
600 800 1000
10
20
30
40
SUPPLY VOLTAGE (V)
CAPACITANCE (pF)
CYCLE FREQUENCY (MHz)
Document #: 38-05025 Rev. *A
Page 6 of 9
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CY7C164
CY7C166
CY7C164 Truth Table
CE
H
WE
X
Input/Output
Mode
Deselect/Power-Down
Read
Power
Standby (ISB
Active (ICC
Active (ICC
High Z
)
L
H
Data Out
Data In
)
L
L
Write
)
CY7C166 Truth Table
CE
H
L
WE
X
OE
X
Input/Output
High Z
Mode
Deselect/Power-Down
Read
Power
Standby (ISB
Active (ICC
Active (ICC
Active (ICC
)
H
L
Data Out
Data In
High Z
)
L
L
H
Write
)
L
H
H
Select/Output Disabled
)
Address Designators
Address
Name
Address CY 7C164 Pin CY7C166 Pin
Function
Number
Number
A5
A6
X3
1
2
1
2
X4
A7
X5
3
3
A8
X6
4
4
A9
X7
5
5
A10
A11
A12
A13
A0
Y5
6
6
Y4
7
7
Y0
8
8
Y1
9
9
Y2
17
18
19
20
21
19
20
21
22
23
A1
Y3
A2
X0
A3
X1
A4
X2
Ordering Information
Speed
Package
Diagram
Operating
Range
(ns)
Ordering Code
CY7C164-15PC
Package Type
15
51-85012 22-pin (300-Mil) Molded DIP
51-85030 24-pin (300-Mil) Molded SOJ
51-85012 22-pin (300-Mil) Molded DIP
51-85030 24-pin (300-Mil) Molded SOJ
Commercial
CY7C166-15VC
CY7C164-25PC
CY7C166-25VC
25
Commercial
Document #: 38-05025 Rev. *A
Page 7 of 9
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CY7C164
CY7C166
Package Diagrams
22-pin (300-Mil) PDIP (51-85012)
11
1
MIN.
DIMENSIONS IN INCHES
MAX.
0.250
0.270
12
22
0.030
0.065
1.070
1.120
SEATING PLANE
0.280
0.325
0.120
0.140
0.140
0.190
0.009
0.012
0.115
0.160
3° MIN.
0.015
0.060
0.055
0.065
0.310
0.385
0.090
0.110
0.015
0.020
51-85012-*A
24-pin (300-mil) SOJ (51-85030)
PIN 1 ID
12
1
MIN.
MAX.
DIMENSIONS IN INCHES[MM]
REFERENCE JEDEC MO-088
PACKAGE WEIGHT 0.75gms
0.291[7.39]
0.330[8.38]
0.300[7.62]
0.350[8.89]
PART #
V24.3
STANDARD PKG.
LEAD FREE PKG.
13
24
VZ24.3
0.597[15.16]
0.613[15.57]
SEATING PLANE
0.120[3.05]
0.140[3.55]
0.007[0.17]
0.013[0.33]
0.004[0.10]
0.262[6.65]
0.272[6.91]
0.050[1.27]
TYP.
0.025[0.63] MIN.
0.013[0.33]
0.019[0.48]
51-85030-*B
Document #: 38-05025 Rev. *A
Page 8 of 9
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
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CY7C164
CY7C166
Document History Page
Document Title: CY7C164/CY7C166 16K x 4 Static RAM
Document Number: 38-05025
Issue
Orig. of
Change
REV.
**
*A
ECN NO. Date
Description of Change
106811
486744
09/10/01
See ECN
SZV
NXR
Change from Spec number: 38-00032 to 38-05025
Removed 20 ns and 35 ns speed bin from Product offering
Removed 24-pin (300-Mil) Molded DIP package
Changed the description of IIX from Input Load Current to Input Leakage
Current in DC Electrical Characteristics table
Removed IOS parameter from DC Electrical Characteristics table
Updated the ordering information table
Document #: 38-05025 Rev. *A
Page 9 of 9
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