CY7C1566V18-333BZXI [CYPRESS]
72-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency); 72兆位的DDR -II + SRAM 2字突发架构（ 2.5周期读延迟）
| 型号： | CY7C1566V18-333BZXI |
| 厂家： | 
CYPRESS |
| 描述： | 72-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency) |
| 文件： | 总27页 (文件大小：1198K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C1566V18
CY7C1577V18
CY7C1568V18
CY7C1570V18
72-Mbit DDR-II+ SRAM 2-Word Burst
Architecture (2.5 Cycle Read Latency)
Features
Functional Description
■ 72-Mbit density (8M x 8, 8M x 9, 4M x 18, 2M x 36)
■ 300 MHz to 400 MHz clock for high bandwidth
■ 2-word burst for reducing address bus frequency
The CY7C1566V18, CY7C1577V18, CY7C1568V18, and
CY7C1570V18 are 1.8V Synchronous Pipelined SRAM
equipped with DDR-II+ architecture. The DDR-II+ consists of an
SRAM core with advanced synchronous peripheral circuitry.
Addresses for read and write are latched on alternate rising
edges of the input (K) clock. Write data is registered on the rising
edges of both K and K. Read data is driven on the rising edges
of both K and K. Each address location is associated with two
8-bit words (CY7C1566V18), 9-bit words (CY7C1577V18),
18-bit words (CY7C1568V18), or 36-bit words (CY7C1570V18)
that burst sequentially into or out of the device.
■ Double Data Rate (DDR) interfaces
(data transferred at 800 MHz) at 400 MHz
■ Read latency of 2.5 clock cycles
■ Two input clocks (K and K) for precise DDR timing
❐ SRAM uses rising edges only
Asynchronous inputs include output impedance matching input
■ Echo clocks (CQ and CQ) simplify data capture in high speed
systems
(ZQ). Synchronous data outputs (Q, that share the same
physical pins with the data inputs, D) are tightly matched to the
two output echo clocks CQ/CQ, eliminating the need to capture
data separately from individual DDR SRAMs in the system
design.
■ Data valid pin (QVLD) to indicate valid data on the output
■ Synchronous internally self-timed writes
[1]
■ Core VDD = 1.8V ± 0.1V; IO VDDQ = 1.4V to VDD
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the K or K input clocks. Writes are
conducted with on-chip synchronous self-timed write circuitry.
■ HSTL inputs and Variable drive HSTL output buffers
■ Available in 165-Ball FBGA package (15 x 17 x 1.4 mm)
■ Offered in both Pb-free and non Pb-free packages
■ JTAG 1149.1 compatible test access port
■ Delay Lock Loop (DLL) for accurate data placement
Configurations
With Read Cycle Latency of 2.5 cycles:
CY7C1566V18 – 8M x 8
CY7C1577V18 – 8M x 9
CY7C1568V18 – 4M x 18
CY7C1570V18 – 2M x 36
Selection Guide
400 MHz
400
375 MHz
375
333 MHz
333
300 MHz
300
Unit
MHz
mA
Maximum Operating Frequency
Maximum Operating Current
x8
x9
1400
1400
1400
1400
1300
1300
1300
1300
1200
1200
1200
1200
1100
1100
x18
x36
1100
1100
Note
1. The QDR consortium specification for V
is 1.5V + 0.1V. The Cypress QDR devices exceed the QDR consortium specification and are capable of supporting V
DDQ
DDQ
= 1.4V to V
.
DD
Cypress Semiconductor Corporation
Document Number: 001-06551 Rev. *D
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised August 07, 2007
CY7C1566V18
CY7C1577V18
CY7C1568V18
CY7C1570V18
Logic Block Diagram (CY7C1566V18)
Write
Reg
Write
Reg
22
A
(21:0)
Address
Register
LD
8
K
K
Output
Logic
Control
CLK
Gen.
R/W
DOFF
Read Data Reg.
16
CQ
CQ
V
8
REF
8
8
Reg.
Reg.
Reg.
Control
Logic
R/W
8
DQ
[7:0]
8
NWS
[1:0]
QVLD
Logic Block Diagram (CY7C1577V18)
Write
Reg
Write
Reg
22
A
(21:0)
Address
Register
LD
9
K
K
Output
Logic
Control
CLK
Gen.
R/W
DOFF
Read Data Reg.
18
CQ
CQ
V
9
REF
9
9
Reg.
Reg.
Reg.
Control
Logic
R/W
9
DQ
[8:0]
9
BWS
[0]
QVLD
Document Number: 001-06551 Rev. *D
Page 2 of 27
CY7C1566V18
CY7C1577V18
CY7C1568V18
CY7C1570V18
Logic Block Diagram (CY7C1568V18)
Write
Reg
Write
Reg
21
A
(20:0)
Address
Register
LD
18
K
K
Output
Logic
Control
CLK
Gen.
R/W
DOFF
Read Data Reg.
36
CQ
CQ
V
18
REF
18
18
Reg.
Reg.
Reg.
Control
Logic
R/W
DQ
[17:0]
18
BWS
18
[1:0]
QVLD
Logic Block Diagram (CY7C1570V18)
Write
Reg
Write
Reg
20
A
(19:0)
Address
Register
LD
36
K
K
Output
Logic
Control
CLK
Gen.
R/W
DOFF
Read Data Reg.
72
36
CQ
CQ
V
REF
36
36
Reg.
Reg.
Reg.
Control
Logic
R/W
DQ
[35:0]
36
BWS
36
[3:0]
QVLD
Document Number: 001-06551 Rev. *D
Page 3 of 27
CY7C1566V18
CY7C1577V18
CY7C1568V18
CY7C1570V18
Pin Configuration
The Pin Configuration for CY7C1566V18, CY7C1577V18, CY7C1568V18, and CY7C1570V18 follows.[2]
165-Ball FBGA (15 x 17 x 1.4 mm) Pinout
CY7C1566V18 (8M x 8)
1
CQ
NC
NC
NC
NC
NC
NC
DOFF
NC
NC
NC
NC
NC
NC
TDO
2
A
3
A
4
5
NWS1
NC/288M
A
6
7
NC/144M
NWS0
A
8
9
A
10
A
11
CQ
DQ3
NC
NC
DQ2
NC
NC
ZQ
A
B
C
D
E
F
R/W
A
K
LD
NC
NC
NC
NC
NC
NC
VREF
NC
NC
DQ6
NC
NC
NC
TCK
NC
NC
NC
DQ4
NC
DQ5
VDDQ
NC
NC
NC
NC
NC
DQ7
A
K
A
NC
NC
NC
NC
NC
NC
VDDQ
NC
NC
NC
NC
NC
NC
A
NC
NC
NC
NC
NC
NC
VREF
DQ1
NC
NC
NC
NC
NC
TMS
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
A
A
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
A
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
A
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
A
G
H
J
NC
NC
DQ0
NC
NC
NC
TDI
K
L
M
N
P
R
A
C
A
A
A
C
A
A
CY7C1577V18 (8M x 9)
1
CQ
NC
NC
NC
NC
NC
NC
DOFF
NC
NC
NC
NC
NC
NC
TDO
2
A
3
A
4
5
NC
6
K
7
NC/144M
BWS0
A
8
9
A
10
A
11
CQ
DQ3
NC
A
B
C
D
E
F
R/W
A
LD
NC
NC
NC
NC
NC
NC
VREF
NC
NC
DQ6
NC
NC
NC
TCK
NC
NC
NC
DQ4
NC
DQ5
VDDQ
NC
NC
NC
NC
NC
DQ7
A
NC/288M
A
K
A
NC
NC
NC
NC
NC
NC
VDDQ
NC
NC
NC
NC
NC
NC
A
NC
NC
NC
NC
NC
NC
VREF
DQ1
NC
NC
NC
NC
NC
TMS
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
A
A
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
A
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
A
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
A
NC
DQ2
NC
G
H
J
NC
ZQ
NC
K
L
NC
DQ0
NC
M
N
P
R
NC
A
QVLD
NC
A
DQ8
TDI
A
A
A
A
Note
2. NC/144M and NC/288M are not connected to the die and can be tied to any voltage level.
Document Number: 001-06551 Rev. *D
Page 4 of 27
CY7C1566V18
CY7C1577V18
CY7C1568V18
CY7C1570V18
Pin Configuration
The Pin Configuration for CY7C1566V18, CY7C1577V18, CY7C1568V18, and CY7C1570V18 follows.[2] (continued)
165-Ball FBGA (15 x 17 x 1.4 mm) Pinout
CY7C1568V18 (4M x 18)
1
CQ
NC
NC
NC
NC
NC
NC
DOFF
NC
NC
NC
NC
NC
NC
TDO
2
A
3
4
5
BWS1
NC/288M
A
6
K
7
NC/144M
BWS0
A
8
9
A
10
A
11
CQ
A
B
C
D
E
F
A
R/W
A
LD
DQ9
NC
NC
K
A
NC
NC
NC
NC
NC
NC
VDDQ
NC
NC
NC
NC
NC
NC
A
NC
DQ8
NC
NC
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
A
NC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
A
DQ7
NC
NC
DQ10
DQ11
NC
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
A
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
A
NC
NC
NC
DQ6
DQ5
NC
DQ12
NC
NC
G
H
J
DQ13
VDDQ
NC
NC
VREF
NC
VREF
DQ4
NC
ZQ
NC
K
L
NC
DQ14
NC
DQ3
DQ2
NC
DQ15
NC
NC
M
N
P
R
NC
DQ1
NC
NC
DQ16
DQ17
A
NC
NC
A
QVLD
NC
A
NC
DQ0
TDI
TCK
A
A
A
A
TMS
CY7C1570V18 (2M x 36)
1
CQ
NC
NC
NC
NC
NC
NC
DOFF
NC
NC
NC
NC
NC
NC
TDO
2
NC/144M
DQ27
NC
3
4
5
BWS2
BWS3
A
6
K
7
BWS1
BWS0
A
8
9
A
10
A
11
A
B
C
D
E
F
A
R/W
A
LD
CQ
DQ18
DQ28
DQ19
DQ20
DQ21
DQ22
VDDQ
DQ32
DQ23
DQ24
DQ34
DQ25
DQ26
A
K
A
NC
NC
NC
NC
NC
NC
VDDQ
NC
NC
NC
NC
NC
NC
A
NC
DQ8
DQ7
DQ16
DQ6
DQ5
DQ14
ZQ
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
A
NC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
A
DQ17
NC
DQ29
NC
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
A
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
A
DQ15
NC
DQ30
DQ31
VREF
NC
G
H
J
NC
VREF
DQ13
DQ12
NC
DQ4
DQ3
DQ2
DQ1
DQ10
DQ0
TDI
K
L
NC
DQ33
NC
M
N
P
R
DQ11
NC
DQ35
NC
A
QVLD
NC
A
DQ9
TMS
TCK
A
A
A
A
Document Number: 001-06551 Rev. *D
Page 5 of 27
CY7C1566V18
CY7C1577V18
CY7C1568V18
CY7C1570V18
Pin Definitions
Pin Name
IO
Pin Description
Data Input and Output Signals. Inputs are sampled on the rising edge of K and K clocks during
valid write operations. These pins drive out the requested data during a read operation. Valid data is
driven out on the rising edge of both the K and K clocks during read operations. When read access
is deselected, Q[x:0] are automatically tri-stated.
DQ[x:0]
Input and
Output
Synchronous
CY7C1566V18 − DQ[7:0]
CY7C1577V18 − DQ[8:0]
CY7C1568V18 − DQ[17:0]
CY7C1570V18 − DQ[35:0]
LD
Input
Synchronous Load. Sampled on the rising edge of the K clock. This input is brought LOW when a
Synchronous bus cycle sequence is defined. This definition includes address and read or write direction. All trans-
actions operate on a burst of 2 data. LD must meet the setup and hold times around edge of K.
NWS0, NWS1 Input
Nibble Write Select 0, 1, Active LOW (CY7C1566V18 only). Sampled on the rising edge of the K
Synchronous and K clocks during write operations. Used to select the nibble that is written into the device during
the current portion of the write operations. Nibbles not written remain unaltered.
NWS0 controls D[3:0] and NWS1 controls D[7:4]
.
All the Nibble Write Selects are sampled on the same edge as the data. Deselecting a Nibble Write
Select ignores the corresponding nibble of data and does not write into the device.
BWS0 BWS
BWS2, BWS3
Input
Byte Write Select 0, 1, 2, and 3, Active LOW. Sampled on the rising edge of the K and K clocks
,
,
1
Synchronous during write operations. Used to select which byte is written into the device during the current portion
of the write operations. Bytes not written remain unaltered.
CY7C1577V18 − BWS0 controls D[8:0]
CY7C1568V18 − BWS0 controls D[8:0] and BWS1 controls D[17:9].
CY7C1570V18 − BWS0 controls D[8:0], BWS1 controls D[17:9], BWS2 controls D[26:18] and BWS3
controls D[35:27]
.
All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write Select
ignores the corresponding byte of data and does not write into the device.
A
Input
Address Inputs. Sampled on the rising edge of the K clock during active read and write operations.
Synchronous These address inputs are multiplexed for both read and write operations. Internally, the device is
organized as 8M x 8 (2 arrays each of 4M x 8) for CY7C1566V18, 8M x 9 (2 arrays each of 4M x 9)
for CY7C1577V18, 4M x 18 (2 arrays each of 2M x 18) for CY7C1568V18, and 2M x 36 (2 arrays
each of 1M x 36) for CY7C1570V18.
R/W
Input
Synchronous Read/Write Input. When LD is LOW, this input designates the access type (read
Synchronous when R/W is HIGH, write when R/W is LOW) for loaded address. R/W must meet the setup and hold
times around edge of K.
QVLD
K
Valid Output Valid Output Indicator. The Q Valid indicates valid output data. QVLD is edge aligned with CQ and
Indicator
CQ.
Input Clock Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the device
and to drive out data through Q[x:0] when in single clock mode. All accesses are initiated on the rising
edge of K.
K
Input Clock Negative Input Clock Input. K is used to capture synchronous data presented to the device and to
drive out data through Q[x:0] when in single clock mode.
CQ
Clock Output Synchronous Echo Clock Outputs. This is a free running clock and is synchronized to the input
clock (K) of the DDR-II+. The timing for the echo clocks is shown in “Switching Characteristics” on
page 22.
CQ
Synchronous Echo Clock Outputs. This is a free running clock and is synchronized to the input
clock (K) of the DDR-II+. The timing for the echo clocks is shown in “Switching Characteristics” on
page 22.
Clock Output
Document Number: 001-06551 Rev. *D
Page 6 of 27
CY7C1566V18
CY7C1577V18
CY7C1568V18
CY7C1570V18
Pin Definitions (continued)
Pin Name
ZQ
IO
Pin Description
Input
Output Impedance Matching Input. This input is used to tune the device outputs to the system data
bus impedance. CQ, CQ, and Q[x:0] output impedance are set to 0.2 x RQ, where RQ is a resistor
connected between ZQ and ground. Alternatively, this pin is connected directly to VDDQ that enables
the minimum impedance mode. This pin is not connected directly to GND or is left unconnected.
DOFF
Input
DLL Turn Off, Active LOW. Connecting this pin to ground turns off the DLL inside the device. The
timing in the DLL turned off operation is different from that listed in this datasheet. For normal
operation, this pin is connected to a pull up through a 10 Kohm or less pull up resistor. The device
behaves in DDR-I mode when the DLL is turned off. In this mode, the device is operated at a
frequency of up to 167 MHz with DDR-I timing.
TDO
Output
Input
Input
Input
N/A
TDO for JTAG.
TCK
TCK Pin for JTAG.
TDI
TDI Pin for JTAG.
TMS
TMS Pin for JTAG.
NC
Not Connected to the Die. Is tied to any voltage level.
Not Connected to the Die. Is tied to any voltage level.
Not Connected to the Die. Is tied to any voltage level.
Not Connected to the Die. Is tied to any voltage level.
Reference Voltage Input. Static input is used to set the reference level for HSTL inputs, outputs,
NC/72M
NC/144M
NC/288M
VREF
N/A
N/A
N/A
Input
Reference and AC measurement points.
VDD
VSS
Power Supply Power Supply Inputs to the Core of the Device.
Ground
Ground for the Device.
VDDQ
Power Supply Power Supply Inputs for the Outputs of the Device.
Document Number: 001-06551 Rev. *D
Page 7 of 27
CY7C1566V18
CY7C1577V18
CY7C1568V18
CY7C1570V18
Byte Write Operations
Functional Overview
Byte write operations are supported by the CY7C1568V18. A
write operation is initiated as described in the Write Operations
section. The bytes that are written are determined by BWS0 and
BWS1, that are sampled with each set of 18-bit data words.
Asserting the appropriate Byte Write Select input during the data
portion of a write enables to present the data to be latched and
written into the device. Deasserting the Byte Write Select input
during the data portion of a write enables the data stored in the
device for that byte to remain unaltered. This feature is used to
simplify read, modify, and write operations to a byte write
operation.
The CY7C1566V18, CY7C1577V18, CY7C1568V18, and
CY7C1570V18 are synchronous pipelined Burst SRAMs
equipped with a DDR interface.
Accesses for both ports are initiated on the Positive Input Clock
(K). All synchronous input and output timing refer to the rising
edge of the input clocks (K and K).
All synchronous data inputs (D[x:0]) pass through input registers
controlled by the rising edge of the input clocks (K and K). All
synchronous data outputs (Q[x:0]) pass through output registers
controlled by the rising edge of the input clocks (K and K).
All synchronous control (R/W, LD, NWS[0:X], BWS[0:X]) inputs
pass through input registers controlled by the rising edge of the
input clock (K\K).
Double Date Rate Operation
The CY7C1568V18 enables high performance operation
through high clock frequencies (achieved through pipelining) and
DDR mode of operation. The CY7C1568V18 requires two No
Operation (NOP) cycles when transitioning from a read to a write
cycle. At higher frequencies, some applications require a third
NOP cycle to avoid contention.
CY7C1568V18 is described in the following sections. The same
basic descriptions apply to CY7C1566V18, CY7C1577V18, and
CY7C1570V18.
Read Operations
If a read occurs after a write cycle, address and data for the write
are stored in registers. The write information is stored because
the SRAM cannot perform the last word write to the array without
conflicting with the read. The data stays in this register until the
next write cycle occurs. On the first write cycle after the read(s),
the stored data from the earlier write is written into the SRAM
array. This is called a Posted Write.
The CY7C1568V18 is organized internally as two arrays of 4M x
18. Accesses are completed in a burst of two sequential 18-bit
data words. Read operations are initiated by asserting R/W
HIGH and LD LOW at the rising edge of the positive input clock
(K). Following the next two K clock rising edges, the corre-
sponding 18-bit word of data from this address location is driven
onto the Q[17:0] using K as the output timing reference. On the
subsequent rising edge of K, the next 18-bit data word is driven
onto the Q[17:0]. The requested data is valid 0.45 ns from the
rising edge of the input clock (K and K). To maintain the internal
logic, each read access is allowed to complete. Read accesses
are initiated on every rising edge of the positive input clock (K).
If a read is performed on the same address where a write is
performed in the previous cycle, the SRAM reads out the most
current data. The SRAM does this by bypassing the memory
array and reading the data from the registers.
Depth Expansion
When read access is deselected, the CY7C1568V18 completes
the pending read transactions. Synchronous internal circuitry
automatically tri-states the outputs following the next rising edge
of the negative input clock (K). This enables a seamless
transition between devices without the insertion of wait states in
a depth expanded memory.
Depth expansion requires replicating the LD control signal for
each bank. All other control signals are common between banks
as appropriate.
Programmable Impedance
An external resistor, RQ, is connected between the ZQ pin on the
SRAM and VSS to enable the SRAM to adjust its output driver
impedance. The value of RQ is 5x the value of the intended line
impedance driven by the SRAM. The allowable range of RQ to
guarantee impedance, matching with a tolerance of ±15%, is
between 175Ω and 350Ω with VDDQ = 1.5V. The output
impedance is adjusted every 1024 cycles upon power up to
account for drifts in supply voltage and temperature.
Write Operations
Write operations are initiated by asserting R/W LOW and LD
LOW at the rising edge of the positive input clock (K). The
address presented to Address inputs is stored in the Write
Address register. On the following K clock rise, the data
presented to D[17:0] is latched and stored into the 18-bit Write
Data register, provided BWS[1:0] are both asserted active. On the
subsequent rising edge of the Negative Input Clock (K), the infor-
mation presented to D[17:0] is also stored into the Write Data
register, provided BWS[1:0] are both asserted active. The 36 bits
of data is then written into the memory array at the specified
location. Write accesses are initiated on every rising edge of the
positive input clock (K). This pipelines the data flow such that 18
bits of data is transferred into the device on every rising edge of
the input clocks (K and K).
Echo Clocks
Echo clocks are provided on the DDR-II+ to simplify data capture
on high speed systems. Two echo clocks are generated by the
DDR-II+. CQ is referenced with respect to K and CQ is refer-
enced with respect to K. These are free running clocks and are
synchronized to the input clock of the DDR-II+. The timing for the
echo clocks is shown in “Switching Characteristics” on page 22.
When write access is deselected, the device ignores all inputs
after the pending write operations are completed.
Document Number: 001-06551 Rev. *D
Page 8 of 27
CY7C1566V18
CY7C1577V18
CY7C1568V18
CY7C1570V18
Valid Data Indicator (QVLD)
DLL
QVLD is provided on the DDR-II+ to simplify data capture on high
speed systems. The QVLD is generated by the DDR-II+ device
along with data output. This signal is also edge aligned with the
echo clock and follows the timing of any data pin. This signal is
asserted half a cycle before valid data arrives.
These chips use a DLL that is designed to function between 120
MHz and the specified maximum clock frequency. The DLL is
disabled by applying ground to the DOFF pin. When the DLL is
turned off, the device behaves in DDR-I mode (with 1.0 cycle
latency and a longer access time). For more information, refer to
the
application
note,
DLL
Considerations
in
QDRII/DDRII/QDRII+/DDRII+. The DLL is also reset by slowing
or stopping the input clocks K and K for a minimum of 30 ns.
However, it is not necessary to reset the DLL to lock at the
desired frequency. During power up, when the DOFF is tied
HIGH, the DLL gets locked after 2048 cycles of stable clock.
Application Example
Figure 1. Application Example
ZQ
CQ/CQ
K
K
ZQ
CQ/CQ
K
K
SRAM#1
LD R/W
SRAM#2
DQ
DQ
R = 250ohms
R = 250ohms
LD R/W
A
A
DQ
Addresses
Cycle Start
R/W
Source CLK
Source CLK
BUS
MASTER
(CPU or ASIC)
Echo Clock1/Echo Clock1
Echo Clock2/Echo Clock2
Truth Table
The truth table for CY7C1566V18, CY7C1577V18, CY7C1568V18, and CY7C1570V18 follows. [3, 4, 5, 6, 7, 8]
Operation
K
LD
R/W
DQ
DQ
Write Cycle:
Load address; wait one cycle;
L-H
L
L
D(A) at K(t + 1) ↑
D(A+1) at K(t + 1) ↑
input write data on consecutive K and K rising edges.
Read Cycle: (2.5 cycle Latency)
Load address; wait two and half cycle;
read data on consecutive K and K rising edges.
L-H
L
H
Q(A) at K(t + 2) ↑
Q(A+1) at K(t + 3) ↑
NOP: No Operation
L-H
H
X
X
X
High Z
High Z
Standby: Clock Stopped
Stopped
Previous State
Previous State
Notes
3. X = “Don’t Care,” H = Logic HIGH, L = Logic LOW, ↑ represents rising edge.
4. Device powers up deselected with the outputs in a tri-state condition.
5. “A” represents address location latched by the devices when transaction was initiated. A + 1 represents the address sequence in the burst.
6. “t” represents the cycle at which a read/write operation is started. t + 1 and t + 2 are the first and second clock cycles succeeding the “t” clock cycle.
7. Data inputs are registered at K and K rising edges. Data outputs are delivered on K and K rising edges.
8. Cypress recommends that K = K = HIGH when clock is stopped. This is not essential but permits most rapid restart by overcoming transmission line charging
symmetrically.
Document Number: 001-06551 Rev. *D
Page 9 of 27
CY7C1566V18
CY7C1577V18
CY7C1568V18
CY7C1570V18
Write Cycle Descriptions
The write cycle description table for CY7C1566V18 and CY7C1568V18 follows. [3, 9]
BWS0/ BWS1/
K
Comments
K
NWS0 NWS1
L
L
L–H
–
During the data portion of a write sequence :
CY7C1566V18 − both nibbles (D[7:0]) are written into the device,
CY7C1568V18 − both bytes (D[17:0]) are written into the device.
L
L
–
L–H
–
L-H During the data portion of a write sequence :
CY7C1566V18 − both nibbles (D[7:0]) are written into the device,
CY7C1568V18 − both bytes (D[17:0]) are written into the device.
L
H
H
L
–
During the data portion of a write sequence :
CY7C1566V18 − only the lower nibble (D[3:0]) is written into the device, D[7:4] remains unaltered.
CY7C1568V18 − only the lower byte (D[8:0]) is written into the device, D[17:9] remains unaltered.
L
L–H During the data portion of a write sequence :
CY7C1566V18 − only the lower nibble (D[3:0]) is written into the device, D[7:4] remains unaltered.
CY7C1568V18 − only the lower byte (D[8:0]) is written into the device, D[17:9] remains unaltered.
H
H
L–H
–
–
During the data portion of a write sequence :
CY7C1566V18 − only the upper nibble (D[7:4]) is written into the device, D[3:0] remains unaltered.
CY7C1568V18 − only the upper byte (D[17:9]) is written into the device, D[8:0] remains unaltered.
L
L–H During the data portion of a write sequence :
CY7C1566V18 − only the upper nibble (D[7:4]) is written into the device, D[3:0] remains unaltered.
CY7C1568V18 − only the upper byte (D[17:9]) is written into the device, D[8:0] remains unaltered.
H
H
H
H
L–H
–
–
No data is written into the devices during this portion of a write operation.
L–H No data is written into the devices during this portion of a write operation.
Write Cycle Descriptions
The write cycle description table for CY7C1577V18 follows. [3, 9]
BWS0
K
L–H
–
K
L
L
–
During the data portion of a write sequence, the single byte (D[8:0]) is written into the device.
L–H During the data portion of a write sequence, the single byte (D[8:0]) is written into the device.
No data is written into the device during this portion of a write operation.
L–H No data is written into the device during this portion of a write operation.
H
H
L–H
–
–
Note
9. Assumes a write cycle is initiated per the Write Cycle Descriptions table. NWS , NWS , BWS , BWS , BWS , and BWS are altered on different portions of a write
0
1
0
1
2
3
cycle, as long as the setup and hold requirements are met.
Document Number: 001-06551 Rev. *D
Page 10 of 27
CY7C1566V18
CY7C1577V18
CY7C1568V18
CY7C1570V18
Write Cycle Descriptions
The write cycle description table for CY7C1570V18 follows. [3, 9]
BWS0 BWS1 BWS2 BWS3
K
K
Comments
L
L
L
L
L–H
–
During the data portion of a write sequence, all four bytes (D[35:0]) are written into
the device.
L
L
L
L
–
L–H
–
L–H During the data portion of a write sequence, all four bytes (D[35:0]) are written into
the device.
L
H
H
L
H
H
H
H
L
H
H
H
H
H
H
L
–
During the data portion of a write sequence, only the lower byte (D[8:0]) is written
into the device. D[35:9] remains unaltered.
L
L–H During the data portion of a write sequence, only the lower byte (D[8:0]) is written
into the device. D[35:9] remains unaltered.
H
H
H
H
H
H
L–H
–
–
During the data portion of a write sequence, only the byte (D[17:9]) is written into
the device. D[8:0] and D[35:18] remain unaltered.
L
L–H During the data portion of a write sequence, only the byte (D[17:9]) is written into
the device. D[8:0] and D[35:18] remain unaltered.
H
H
H
H
L–H
–
–
During the data portion of a write sequence, only the byte (D[26:18]) is written into
the device. D[17:0] and D[35:27] remain unaltered.
L
L–H During the data portion of a write sequence, only the byte (D[26:18]) is written into
the device. D[17:0] and D[35:27] remain unaltered.
H
H
L–H
–
–
During the data portion of a write sequence, only the byte (D[35:27]) is written into
the device. D[26:0] remains unaltered.
L
L–H During the data portion of a write sequence, only the byte (D[35:27]) is written into
the device. D[26:0] remains unaltered.
H
H
H
H
H
H
H
H
L–H
–
–
No data is written into the device during this portion of a write operation.
L–H No data is written into the device during this portion of a write operation.
Document Number: 001-06551 Rev. *D
Page 11 of 27
CY7C1566V18
CY7C1577V18
CY7C1568V18
CY7C1570V18
Instruction Register
IEEE 1149.1 Serial Boundary Scan (JTAG)
Three-bit instructions are serially loaded into the Instruction
register. This register is loaded when it is placed between the TDI
and TDO pins as shown in “TAP Controller Block Diagram” on
page 15. Upon power up, the Instruction register is loaded with
the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as described
in the Performing a TAP Reset section.
These SRAMs incorporate a serial boundary scan test access
port (TAP) in the FBGA package. This part is fully compliant with
IEEE Standard 1149.1-2001. The TAP operates using JEDEC
standard 1.8V IO logic levels.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, tie TCK LOW (VSS) to
prevent device clocking. TDI and TMS are internally pulled up
and are unconnected. They are alternately connected to VDD
through a pull up resistor. TDO is left unconnected. Upon power
up, the device comes up in a reset state and does not interfere
with the operation of the device.
When the TAP controller is in the Capture-IR state, the two least
significant bits are loaded with a binary ‘01’ pattern. This enables
fault isolation of the board level serial test path.
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The Bypass
register is a single-bit register that is placed between TDI and
TDO pins. This enables to shift data through the SRAM with
minimal delay. The Bypass register is set LOW (VSS) when the
BYPASS instruction is executed.
Test Access Port—Test Clock
The test clock is used only with the TAP controller. All inputs are
captured on the rising edge of TCK. All outputs are driven from
the falling edge of TCK.
Boundary Scan Register
Test Mode Select
The Boundary Scan register is connected to all of the input and
output pins on the SRAM. Several no connect (NC) pins are also
included in the Scan register to reserve pins for higher density
devices.
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. Leave this pin uncon-
nected if the TAP is not used. The pin is pulled up internally,
resulting in a logic HIGH level.
The Boundary Scan register is loaded with the contents of the
RAM input and output ring when the TAP controller is in the
Capture-DR state. It is then placed between the TDI and TDO
pins when the controller is moved to the Shift-DR state. The
EXTEST, SAMPLE/PRELOAD, and SAMPLE Z instructions are
used to capture the contents of the input and output ring.
Test Data In (TDI)
The TDI pin is used to serially input information into the registers
and is connected to the input of any of the registers. The register
between TDI and TDO is selected by the instruction that is
loaded into the TAP Instruction register. For information about
loading the instruction register, see “TAP Controller State
Diagram” on page 14. TDI is internally pulled up and is uncon-
nected if the TAP is unused in an application. TDI is connected
to the most significant bit (MSb) on any register.
“Boundary Scan Order” on page 18 shows the order of the bits
that are connected. Each bit corresponds to one of the bumps on
the SRAM package. The MSb of the register is connected to TDI
and the LSb is connected to TDO.
Identification (ID) Register
Test Data Out (TDO)
The ID register is loaded with a vendor specific 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the Instruction register. The IDCODE is hardwired into
the SRAM and is shifted out when the TAP controller is in the
Shift-DR state. The ID register has a vendor code and other infor-
mation described in “Identification Register Definitions” on
page 17.
The TDO output pin is used to serially clock data-out from the
registers.The active output depends on the current state of the
TAP state machine (see “Instruction Codes” on page 17). The
output changes on the falling edge of TCK. TDO is connected to
the least significant bit (LSb) of any register.
Performing a TAP Reset
A reset is performed by forcing TMS HIGH (VDD) for five rising
edges of TCK. This RESET does not affect the operation of the
SRAM and is performed while the SRAM is operating. At power
up, the TAP is reset internally to ensure that TDO comes up in a
High Z state.
TAP Instruction Set
Eight different instructions are possible with the three-bit
Instruction register. All combinations are listed in “Instruction
Codes” on page 17. Three of these instructions are listed as
RESERVED and are not used. The other five instructions are
described in this section.
TAP Registers
Instructions are loaded into the TAP controller during the Shift-IR
state when the Instruction register is placed between TDI and
TDO. During this state, instructions are shifted through the
Instruction register through the TDI and TDO pins. To execute
the instruction after it is shifted in, the TAP controller is moved
into the Update-IR state.
Registers are connected between the TDI and TDO pins. This
enables scanning of data into and out of the SRAM test circuitry.
Only one register is selected at a time through the instruction
registers. Data is serially loaded into the TDI pin on the rising
edge of TCK. Data is output on the TDO pin on the falling edge
of TCK.
Document Number: 001-06551 Rev. *D
Page 12 of 27
CY7C1566V18
CY7C1577V18
CY7C1568V18
CY7C1570V18
IDCODE
The shifting of data for the SAMPLE and PRELOAD phases
occurs concurrently when required — that is, while data captured
is shifted out, the preloaded data is shifted in.
The IDCODE instruction is loaded with a vendor specific 32-bit
code into the Instruction register. It also places the Instruction
register between the TDI and TDO pins. This enables to shift the
IDCODE out of the device when the TAP controller enters the
Shift-DR state. The IDCODE instruction is loaded into the
Instruction register up on power up or whenever the TAP
controller is in a Test-Logic-Reset state.
BYPASS
When the BYPASS instruction is loaded in the Instruction
register and the TAP is placed in a Shift-DR state, the Bypass
register is placed between the TDI and TDO pins. The advantage
of the BYPASS instruction is that it shortens the boundary scan
path when multiple devices are connected together on a board.
SAMPLE Z
The SAMPLE Z instruction enables the Boundary Scan register
to connect between the TDI and TDO pins when the TAP
controller is in a Shift-DR state. The SAMPLE Z command puts
the output bus into a High Z state until the next command is
issued during the Update-IR state.
EXTEST
The EXTEST instruction enables to drive the preloaded data out
through the system output pins. This instruction also selects the
Boundary Scan register to connect, for serial access, between
the TDI and TDO in the Shift-DR controller state.
SAMPLE/PRELOAD
EXTEST Output Bus Tri-State
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When
the SAMPLE/PRELOAD instructions are loaded into the
Instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and output pins is
captured in the Boundary Scan register.
IEEE Standard 1149.1 mandates that the TAP controller puts the
output bus into a tri-state mode.
The Boundary Scan register has a special bit located at bit 108
called the “extest output bus tri-state”. When this scan cell is
latched into the Preload register during the Update-DR state in
the TAP controller, it directly controls the state of the output
(Q-bus) pins, when the EXTEST is entered as the current
instruction. When HIGH, it enables the output buffers to drive the
output bus. When LOW, this bit places the output bus into a High
Z condition.
Note that the TAP controller clock operates only at a frequency
up to 20 MHz, while the SRAM clock operates more than an
order of magnitude faster. Because there is a large difference in
the clock frequencies, it is possible that during the Capture-DR
state, an input or output undergoes a transition. The TAP then
tries to capture a signal while in transition (metastable state).
This does not harm the device, but there is no guarantee as to
the value that is captured. Repeatable results are not possible.
This bit is set by entering the SAMPLE/PRELOAD or EXTEST
command and then shifting the desired bit into that cell, during
the Shift-DR state. During Update-DR, the value loaded into that
shift-register cell latches into the Preload register. When the
EXTEST instruction is entered, this bit directly controls the output
Q-bus pins. Note that this bit is preset HIGH to enable the output
when the device is powered up, and also when the TAP controller
is in the Test-Logic-Reset state.
To guarantee that the Boundary Scan register captures the
correct value of a signal, the SRAM signal is stabilized long
enough to meet the TAP controller's capture setup plus hold
times (tCS and tCH). The SRAM clock input are not captured
correctly if there is no way in a design to stop (or slow) the clock
during a SAMPLE/PRELOAD instruction. If this is an issue, it is
still possible to capture all other signals and simply ignore the
value of the CK and CK captured in the Boundary Scan register.
Reserved
After the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the Boundary
Scan register between the TDI and TDO pins.
These instructions are not implemented but are reserved for
future use. Do not use these instructions
PRELOAD enables to place an initial data pattern at the latched
parallel outputs of the Boundary Scan register cells before the
selection of another boundary scan test operation.
Document Number: 001-06551 Rev. *D
Page 13 of 27
CY7C1566V18
CY7C1577V18
CY7C1568V18
CY7C1570V18
TAP Controller State Diagram
The state diagram for the TAP controller follows. [10]
TEST LOGIC
1
RESET
0
1
1
1
TEST LOGIC/
IDLE
SELECT
SELECT
0
DR-SCAN
IR-SCAN
0
0
1
1
CAPTURE-DR
CAPTURE-IR
0
0
SHIFT-DR
0
SHIFT-IR
0
1
1
EXIT1-DR
0
1
EXIT1-IR
0
1
0
0
PAUSE-DR
1
PAUSE-IR
1
0
0
EXIT2-DR
1
EXIT2-IR
1
UPDATE-DR
UPDATE-IR
1
1
0
0
Note
10. The 0/1 next to each state represents the value at TMS at the rising edge of TCK.
Document Number: 001-06551 Rev. *D
Page 14 of 27
CY7C1566V18
CY7C1577V18
CY7C1568V18
CY7C1570V18
TAP Controller Block Diagram
0
Bypass Register
2
1
0
Selection
Selection
Instruction Register
TDO
TDI
Circuitry
Circuitry
29
Identification Register
31 30
.
.
2
1
1
0
0
.
.
.
.
2
108
Boundary Scan Register
TCK
TMS
TAP Controller
TAP Electrical Characteristics
Over the Operating Range [11, 12, 13]
Parameter
VOH1
Description
Output HIGH Voltage
Test Conditions
IOH = −2.0 mA
Min
1.4
1.6
Max
Unit
V
V
VOH2
VOL1
VOL2
VIH
Output HIGH Voltage
Output LOW Voltage
Output LOW Voltage
Input HIGH Voltage
IOH = −100 µA
IOL = 2.0 mA
IOL = 100 µA
0.4
0.2
V
V
0.65VDD VDD + 0.3
V
VIL
Input LOW Voltage
–0.3
–5
0.35VDD
5
V
IX
Input and Output Load Current
GND ≤ VI ≤ VDD
µA
Notes
11. These characteristics apply to the TAP inputs (TMS, TCK, TDI, and TDO). Parallel load levels are specified in “Electrical Characteristics” on page 20.
12. Overshoot: V (AC) < V + 0.3V (pulse width less than t /2).
/2). Undershoot: V (AC) > − 0.3V (pulse width less than t
IH
DDQ
CYC
IL
CYC
13. All voltage refers to ground.
Document Number: 001-06551 Rev. *D
Page 15 of 27
CY7C1566V18
CY7C1577V18
CY7C1568V18
CY7C1570V18
TAP AC Switching Characteristics
Over the Operating Range [14, 15]
Parameter
Description
Min
Max
Unit
ns
tTCYC
TCK Clock Cycle Time
TCK Clock Frequency
TCK Clock HIGH
50
tTF
20
MHz
ns
tTH
20
20
tTL
TCK Clock LOW
ns
Setup Times
tTMSS
tTDIS
TMS Setup to TCK Clock Rise
TDI Setup to TCK Clock Rise
Capture Setup to TCK Rise
5
5
5
ns
ns
ns
tCS
Hold Times
tTMSH
tTDIH
TMS Hold After TCK Clock Rise
TDI Hold After Clock Rise
5
5
5
ns
ns
ns
tCH
Capture Hold After Clock Rise
Output Times
tTDOV
tTDOX
TCK Clock LOW to TDO Valid
TCK Clock LOW to TDO Invalid
10
ns
ns
0
TAP Timing and Test Conditions
Figure 2. TAP Timing and Test Conditions [15]
0.9V
ALL INPUT PULSES
50Ω
1.8V
TDO
0.9V
0V
Z = 50
Ω
0
C = 20 pF
L
GND
(a)
t
TL
t
TH
Test Clock
TCK
t
TCYC
t
TMSH
t
TMSS
Test Mode Select
TMS
t
TDIS
t
TDIH
Test Data In
TDI
Test Data Out
TDO
t
TDOV
t
TDOX
Notes
14. t and t refer to the setup and hold time requirements of latching data from the boundary scan register.
CS
CH
15. Test conditions are specified using the load in TAP AC Test Conditions. t /t = 1 ns.
R
F
Document Number: 001-06551 Rev. *D
Page 16 of 27
CY7C1566V18
CY7C1577V18
CY7C1568V18
CY7C1570V18
Identification Register Definitions
Value
Instruction Field
Description
CY7C1566V18
CY7C1577V18
000
CY7C1568V18
CY7C1570V18
Revision Number
(31:29)
000
000
000
Version number.
Cypress Device ID 11010111000000100 11010111000001100 11010111000010100 11010111000100100 Defines the type of
(28:12)
SRAM.
Cypress JEDEC ID
(11:1)
00000110100
1
00000110100
1
00000110100
1
00000110100
1
Allows unique
identification of
SRAM vendor.
ID Register
Presence (0)
Indicates the
presence of an ID
register.
Scan Register Sizes
Register Name
Bit Size
Instruction
Bypass
3
1
ID
32
109
Boundary Scan
Instruction Codes
Instruction
EXTEST
Code
000
Description
Captures the input and output ring contents.
IDCODE
001
Loads the ID register with the vendor ID code and places the register between TDI and TDO.
This operation does not affect SRAM operation.
SAMPLE Z
010
Captures the input and output contents. Places the Boundary Scan register between TDI and
TDO. Forces all SRAM output drivers to a High Z state.
RESERVED
011
100
Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD
Captures the input and output ring contents. Places the Boundary Scan register between TDI
and TDO. Does not affect the SRAM operation.
RESERVED
RESERVED
BYPASS
101
110
111
Do Not Use: This instruction is reserved for future use.
Do Not Use: This instruction is reserved for future use.
Places the Bypass register between TDI and TDO. This operation does not affect SRAM
operation.
Document Number: 001-06551 Rev. *D
Page 17 of 27
CY7C1566V18
CY7C1577V18
CY7C1568V18
CY7C1570V18
Boundary Scan Order
Bit Number
Bump ID
6R
Bit Number
28
Bump ID
10G
9G
Bit Number
56
Bump ID
6A
5B
5A
4A
5C
4B
3A
2A
1A
2B
3B
1C
1B
3D
3C
1D
2C
3E
2D
2E
1E
2F
Bit Number
Bump ID
1J
0
1
84
85
6P
29
57
2J
2
6N
30
11F
11G
9F
58
86
3K
3
7P
31
59
87
3J
4
7N
32
60
88
2K
5
7R
33
10F
11E
10E
10D
9E
61
89
1K
6
8R
34
62
90
2L
7
8P
35
63
91
3L
8
9R
36
64
92
1M
1L
9
11P
10P
10N
9P
37
65
93
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
38
10C
11D
9C
66
94
3N
39
67
95
3M
1N
40
68
96
10M
11N
9M
41
9D
69
97
2M
3P
42
11B
11C
9B
70
98
43
71
99
2N
9N
44
72
100
101
102
103
104
105
106
107
108
2P
11L
11M
9L
45
10B
11A
10A
9A
73
1P
46
74
3R
47
75
4R
10L
11K
10K
9J
48
76
4P
49
8B
77
5P
50
7C
78
3F
5N
51
6C
79
1G
1F
5R
9K
52
8A
80
Internal
10J
11J
11H
53
7A
81
3G
2G
1H
54
7B
82
55
6B
83
Document Number: 001-06551 Rev. *D
Page 18 of 27
CY7C1566V18
CY7C1577V18
CY7C1568V18
CY7C1570V18
DLL Constraints
■ DLL uses K clock as its synchronizing input. The input has low
Power Up Sequence in DDR-II+ SRAM
DDR-II+ SRAMs are powered up and initialized in a pre-defined
manner to prevent undefined operations. During power up, when
the DOFF is tied HIGH, the DLL is locked after 2048 cycles of
stable clock.
phase jitter that is specified as tKC Var
.
■ The DLL functions at frequencies down to 120 MHz.
■ If the input clock is unstable and the DLL is enabled, then the
DLL locks on to an incorrect frequency. This causes unstable
SRAM behavior. To avoid this, provide 2048 cycles stable clock
to relock to the desired clock frequency.
Power Up Sequence
■ Apply power with DOFF tied HIGH (All other inputs are HIGH
or LOW)
❐ Apply VDD before VDDQ
❐ Apply VDDQ before VREF or at the same time as VREF
■ Provide stable power and clock (K, K) for 2048 cycles to lock
the DLL.
Power Up Waveforms
Figure 3. Power Up Waveforms
K
K
Start Normal
Operation
Unstable Clock
> 2048 Stable Clock
Clock Start (Clock Starts after V /V
DD DDQ
is Stable)
V
/V
+
/V Stable (< 0.1V DC per 50 ns)
DD DDQ
V
DD DDQ
Fix HIGH (tie to V
DDQ
)
DOFF
Document Number: 001-06551 Rev. *D
Page 19 of 27
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CY7C1570V18
Current into Outputs (LOW) ........................................ 20 mA
Static Discharge Voltage (MIL-STD-883, M. 3015)... >2001V
Latch up Current..................................................... >200 mA
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with Power Applied.. –55°C to +125°C
Supply Voltage on VDD Relative to GND........–0.5V to +2.9V
Supply Voltage on VDDQ Relative to GND.......–0.5V to +VDD
DC Applied to Outputs in High Z ........ –0.5V to VDDQ + 0.3V
DC Input Voltage[12]............................... –0.5V to VDD + 0.3V
Operating Range
Ambient
[16]
[16]
Range
VDD
VDDQ
Temperature (TA)
Commercial
Industrial
0°C to +70°C
1.8 ± 0.1V
1.4V to
VDD
–40°C to +85°C
Electrical Characteristics
Over the Operating Range [13]
DC Electrical Characteristics
Parameter
VDD
Description
Power Supply Voltage
IO Supply Voltage
Test Conditions
Min
1.7
Typ
Max
1.9
Unit
1.8
1.5
V
V
VDDQ
VOH
1.4
VDD
Output HIGH Voltage
Output LOW Voltage
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Note 17
Note 18
VDDQ/2 – 0.12
VDDQ/2 – 0.12
VDDQ – 0.2
VSS
VDDQ/2 + 0.12
VDDQ/2 + 0.12
VDDQ
0.2
V
VOL
V
VOH(LOW)
VOL(LOW)
VIH
IOH = –0.1 mA, Nominal Impedance
IOL = 0.1 mA, Nominal Impedance
V
V
VREF + 0.1
–0.15
VDDQ + 0.15
VREF – 0.1
2
V
VIL
V
IX
Input Leakage Current
GND ≤ VI ≤ VDDQ
–2
µA
µA
V
IOZ
Output Leakage Current
Input Reference Voltage[19] Typical Value = 0.75V
GND ≤ VI ≤ VDDQ, Output Disabled
–2
2
VREF
0.68
0.75
0.95
I
I
I
I
DD (x8)
DD (x9)
DD (x18)
DD (x36)
VDD Operating Supply
VDD Operating Supply
VDD Operating Supply
VDD Operating Supply
VDD = Max,
OUT = 0 mA,
f = fMAX = 1/tCYC
300 MHz
333 MHz
375 MHz
400 MHz
300 MHz
333 MHz
375 MHz
400 MHz
300 MHz
333 MHz
375 MHz
400 MHz
300 MHz
333 MHz
375 MHz
400 MHz
1100
mA
I
1200
1300
1400
VDD = Max,
OUT = 0 mA,
1100
mA
mA
mA
I
1200
f = fMAX = 1/tCYC
1300
1400
VDD = Max,
IOUT = 0 mA,
f = fMAX = 1/tCYC
1100
1200
1300
1400
VDD = Max,
1100
I
OUT = 0 mA,
1200
f = fMAX = 1/tCYC
1300
1400
Notes
16. Power up: assumes a linear ramp from 0V to V (min) within 200 ms. During this time V < V and V
< V .
DD
DD
IH
DD
DDQ
17. Outputs are impedance controlled. I = –(V
/2)/(RQ/5) for values of 175Ω < RQ < 350Ω.
OH
DDQ
18. Outputs are impedance controlled. I = (V
/2)/(RQ/5) for values of 175Ω < RQ < 350Ω.
OL
DDQ
19. V
(min) = 0.68V or 0.46V
, whichever is larger. V
(max) = 0.95V or 0.54V
, whichever is smaller.
DDQ
REF
DDQ
REF
Document Number: 001-06551 Rev. *D
Page 20 of 27
CY7C1566V18
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Electrical Characteristics
Over the Operating Range [13]
DC Electrical Characteristics
Parameter
Description
Test Conditions
Min
Typ
Max
450
500
525
550
Unit
ISB1
Automatic Power Down
Current
Max VDD
,
300 MHz
333 MHz
375 MHz
400 MHz
mA
Both Ports Deselected,
VIN ≥ VIH or VIN ≤ VIL
f = fMAX = 1/tCYC, Inputs Static
AC Electrical Characteristics
Over the Operating Range[12]
Parameter
Description
Input HIGH Voltage
Input LOW Voltage
Test Conditions
Min
VREF + 0.2
–0.24
Typ
–
Max
Unit
V
VIH
VIL
VDDQ + 0.24
VREF – 0.2
–
V
Capacitance
Tested initially and after any design or process change that may affect these parameters.
Parameter
CIN
Description
Input Capacitance
Test Conditions
TA = 25°C, f = 1 MHz, VDD = 1.8V, VDDQ = 1.5V
Max
Unit
5.5
8.5
8
pF
pF
pF
CCLK
Clock Input Capacitance
Output Capacitance
CO
Thermal Resistance
Tested initially and after any design or process change that may affect these parameters.
165 FBGA
Package
Parameter
Description
Test Conditions
Unit
ΘJA
Thermal Resistance
(Junction to Ambient)
Test conditions follow standard test methods and
procedures for measuring thermal impedance, per
EIA/JESD51.
11.82
°C/W
°C/W
ΘJC
Thermal Resistance
(Junction to Case)
2.33
AC Test Loads and Waveforms
Figure 4. AC Test Loads and Waveforms
V
REF = 0.75V
0.75V
VREF
VREF
0.75V
R = 50Ω
OUTPUT
[20]
ALL INPUT PULSES
Z = 50Ω
0
OUTPUT
1.25V
Device
R = 50Ω
L
0.75V
Under
Device
Under
0.25V
Test
5 pF
VREF = 0.75V
Slew Rate = 2 V/ns
ZQ
Test
ZQ
RQ =
RQ =
250Ω
250Ω
INCLUDING
JIG AND
SCOPE
(a)
(b)
Note
20. Unless otherwise noted, test conditions assume signal transition time of 2V/ns, timing reference levels of 0.75V, V
= 0.75V, RQ = 250Ω, V
= 1.5V, input pulse
DDQ
REF
levels of 0.25V to 1.25V, output loading of the specified I /I , and load capacitance shown in (a) of AC Test Loads and Waveforms.
OL OH
Document Number: 001-06551 Rev. *D
Page 21 of 27
CY7C1566V18
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Switching Characteristics
Over the Operating Range [20, 21]
400 MHz
375 MHz
333 MHz
300 MHz
Cypress Consortium
Parameter Parameter
Description
Unit
Min Max Min Max Min Max Min Max
tPOWER
tCYC
tKH
VDD(Typical) to the First Access[22]
K Clock Cycle Time
1
–
1
–
1
–
1
–
ms
tKHKH
tKHKL
tKLKH
tKHKH
2.50 8.40 2.66 8.40 3.0 8.40 3.3 8.40 ns
Input Clock (K/K) HIGH
Input Clock (K/K) LOW
0.4
0.4
–
–
–
0.4
0.4
–
–
–
0.4
0.4
–
–
–
0.4
0.4
–
–
–
tCYC
tCYC
ns
tKL
tKHKH
K Clock Rise to K Clock Rise
(rising edge to rising edge)
1.06
1.13
1.28
1.40
Setup Times
tSA
tAVKH
tIVKH
tIVKH
Address Setup to K Clock Rise
0.4
0.4
–
–
–
0.4
0.4
–
–
–
0.4
0.4
–
–
–
0.4
0.4
–
–
–
ns
ns
ns
tSC
Control Setup to K Clock Rise (LD, R/W)
tSCDDR
Double Data Rate Control Setup to Clock (K/K) 0.28
Rise (BWS0, BWS1, BWS2, BWS3)
0.28
0.28
0.28
tSD
tDVKH
D[X:0] Setup to Clock (K/K) Rise
0.28
–
0.28
–
0.28
–
0.28
–
ns
Hold Times
tHA
tKHAX
tKHIX
tKHIX
0.4
0.4
–
–
–
0.4
0.4
–
–
–
0.4
0.4
–
–
–
0.4
0.4
–
–
–
ns
ns
ns
Address Hold After K Clock Rise
tHC
Control Hold After K Clock Rise (LD, R/W)
tHCDDR
Double Data Rate Control Hold After Clock (K/K) 0.28
Rise (BWS0, BWS1, BWS2, BWS3)
0.28
0.28
0.28
tHD
tKHDX
D[X:0] Hold After Clock (K/K) Rise
0.28
–
0.28
–
0.28
–
0.28
–
ns
Output Times
tCO
tCHQV
K/K Clock Rise to Data Valid
–
0.45
–
–
0.45
–
–
0.45
–
–
0.45 ns
ns
tDOH
tCHQX
Data Output Hold After K/K Clock Rise
(Active to Active)
–0.45
–0.45
–0.45
–0.45
–
tCCQO
tCQOH
tCQD
tCHCQV
tCHCQX
tCQHQV
tCQHQX
tCQHCQL
K/K Clock Rise to Echo Clock Valid
Echo Clock Hold After K/K Clock Rise
Echo Clock High to Data Valid
–
0.45
–
–
0.45
–
–
0.45
–
–
0.45 ns
–0.45
–
–0.45
–
–0.45
–
–0.45
–
–
0.2
–
ns
ns
ns
ns
ns
0.2
–
0.2
–
0.2
–
tCQDOH
tCQH
Echo Clock High to Data Invalid
Output Clock (CQ/CQ) HIGH[23]
CQ Clock Rise to CQ Clock Rise[23]
–0.2
0.81
0.81
–0.2
0.88
0.88
–0.2
1.03
1.03
–0.2
1.15
1.15
–
–
–
–
tCQHCQH tCQHCQH
–
–
–
–
(rising edge to rising edge)
tCHZ
tCLZ
tCHQZ
tCHQX1
tQVLD
Clock (K/K) Rise to High Z (Active to High Z) [24, 25]
Clock (K/K) Rise to Low Z [24, 25]
Echo Clock High to QVLD Valid [26]
–
0.45
–
–
0.45
–
–
0.45
–
–
0.45 ns
ns
–0.45
–0.45
–0.45
–0.45
–
tQVLD
–0.20 0.20 –0.20 0.20 –0.20 0.20 –0.20 0.20 ns
DLL Timing
tKC Var tKC Var
tKC lock tKC lock
Clock Phase Jitter
–
0.20
–
–
0.20
–
–
0.20
–
–
0.20 ns
DLL Lock Time (K)
K Static to DLL Reset [27]
2048
30
2048
30
2048
30
2048
30
–
–
Cycles
ns
tKC Reset tKC Reset
–
–
–
Notes
21. When a part with a maximum frequency above 300 MHz is operating at a lower clock frequency, it requires the input timings of the frequency range in which it is operated
and outputs data with the output timings of that frequency range.
22. This part has a voltage regulator internally; t
is the time that the power is supplied above V minimum initially before a read or write operation is initiated.
DD
POWER
23. These parameters are extrapolated from the input timing parameters (t
- 250 ps, where 250 ps is the internal jitter. An input jitter of 200 ps (t
) is already
KHKH
KC Var
included in the t
). These parameters are only guaranteed by design and are not tested in production
KHKH
24. t
, t
, are specified with a load capacitance of 5 pF as in (b) of AC Test Loads and Waveforms. Transition is measured ±100 mV from steady state voltage.
CHZ CLZ
25. At any given voltage and temperature, t
is less than t
and t
less than t
.
CO
CHZ
CLZ
CHZ
26. t
specification is applicable for both rising and falling edges of QVLD signal.
QVLD
27. Hold to >V or <V .
IH
IL
Document Number: 001-06551 Rev. *D
Page 22 of 27
CY7C1566V18
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Switching Waveforms
Read/Write/Deselect Sequence [28, 29]
Figure 5. Waveform for 2.5 Cycle Read Latency
NOP
1
READ
2
READ
3
NOP
5
NOP
6
WRITE
7
WRITE
8
NOP
11
NOP
4
READ
9
NOP
10
12
K
t
t
t
t
KH
KL
KHKH
CYC
K
LD
t
t
HC
SC
R/W
A
A2
A3
A0
A4
A1
t
QVLD
t
t
t
t
SA HA
QVLD
QVLD
QVLD
t
t
HD
HD
SD
t
t
SD
D21 D30 D31
Q00 Q01 Q10 Q11
D20
Q40
DQ
t
t
DOH
t
CHZ
CLZ
t
t
t
CO
CQD
(Read Latency = 2.5 Cycles)
t
CQDOH
CCQO
CQOH
t
CQ
CQ
t
CQH
t
CQHCQH
t
CCQO
t
CQOH
DON’T CARE
UNDEFINED
Notes
28. Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, that is, A0 + 1.
29. Outputs are disabled (High Z) one clock cycle after a NOP.
Document Number: 001-06551 Rev. *D
Page 23 of 27
CY7C1566V18
CY7C1577V18
CY7C1568V18
CY7C1570V18
Ordering Information
Not all of the speed, package, and temperature ranges are available. Contact your local sales representative or
visit www.cypress.com for actual products offered.
Speed
(MHz)
Package
Diagram
Operating
Range
Package Type
Ordering Code
375 CY7C1566V18-375BZC
CY7C1577V18-375BZC
CY7C1568V18-375BZC
CY7C1570V18-375BZC
CY7C1566V18-375BZXC
CY7C1577V18-375BZXC
CY7C1568V18-375BZXC
CY7C1570V18-375BZXC
CY7C1566V18-375BZI
CY7C1577V18-375BZI
CY7C1568V18-375BZI
CY7C1570V18-375BZI
CY7C1566V18-375BZXI
CY7C1577V18-375BZXI
CY7C1568V18-375BZXI
CY7C1570V18-375BZXI
333 CY7C1566V18-333BZC
CY7C1577V18-333BZC
CY7C1568V18-333BZC
CY7C1570V18-333BZC
CY7C1566V18-333BZXC
CY7C1577V18-333BZXC
CY7C1568V18-333BZXC
CY7C1570V18-333BZXC
CY7C1566V18-333BZI
CY7C1577V18-333BZI
CY7C1568V18-333BZI
CY7C1570V18-333BZI
CY7C1566V18-333BZXI
CY7C1577V18-333BZXI
CY7C1568V18-333BZXI
CY7C1570V18-333BZXI
51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm)
51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free
51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm)
51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free
51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm)
51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free
51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm)
51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free
Commercial
Industrial
Commercial
Industrial
Document Number: 001-06551 Rev. *D
Page 24 of 27
CY7C1566V18
CY7C1577V18
CY7C1568V18
CY7C1570V18
Ordering Information (continued)
Not all of the speed, package, and temperature ranges are available. Contact your local sales representative or
visit www.cypress.com for actual products offered.
Speed
(MHz)
Package
Diagram
Operating
Range
Package Type
Ordering Code
300 CY7C1566V18-300BZC
CY7C1577V18-300BZC
CY7C1568V18-300BZC
CY7C1570V18-300BZC
CY7C1566V18-300BZXC
CY7C1577V18-300BZXC
CY7C1568V18-300BZXC
CY7C1570V18-300BZXC
CY7C1566V18-300BZI
CY7C1577V18-300BZI
CY7C1568V18-300BZI
CY7C1570V18-300BZI
CY7C1566V18-300BZXI
CY7C1577V18-300BZXI
CY7C1568V18-300BZXI
CY7C1570V18-300BZXI
51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm)
51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free
51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm)
51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free
Commercial
Industrial
Document Number: 001-06551 Rev. *D
Page 25 of 27
CY7C1566V18
CY7C1577V18
CY7C1568V18
CY7C1570V18
Package Diagram
Figure 6. 165-Ball FBGA (15 x 17 x 1.40 mm)
"/44/- 6)%7
4/0 6)%7
0). ꢀ #/2.%2
ꢃꢂꢃꢄ - #
ꢃꢂꢈꢄ - # ! "
ꢍꢃꢂꢀꢉ
0). ꢀ #/2.%2
ꢃꢂꢄꢃ
ꢅꢀꢆꢄ8ꢇ
ꢎꢃꢂꢃꢆ
ꢀ
ꢈ
ꢊ
ꢉ
ꢄ
ꢆ
ꢁ
ꢋ
ꢌ
ꢀꢃ
ꢀꢀ
ꢀꢀ ꢀꢃ
ꢌ
ꢋ
ꢁ
ꢆ
ꢄ
ꢉ
ꢊ
ꢈ
ꢀ
!
"
!
"
#
$
#
$
%
%
&
&
'
'
(
*
(
*
+
+
,
,
-
-
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.
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ꢀꢂꢃꢃ
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"
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ꢃꢂꢀꢄꢅꢉ8ꢇ
./4%3 ꢏ
3/,$%2 0!$ 490% ꢏ./. 3/,$%2 -!3+ $%&).%$ ꢅ.3-$ꢇ
0!#+!'% 7%)'(4 ꢏꢃꢂꢆꢄG
*%$%# 2%&%2%.#% ꢏ-/ꢎꢈꢀꢆ ꢐ $%3)'. ꢉꢂꢆ#
0!#+!'% #/$% ꢏ""ꢃ!$
3%!4).' 0,!.%
#
51-85195-*A
Document Number: 001-06551 Rev. *D
Page 26 of 27
CY7C1566V18
CY7C1577V18
CY7C1568V18
CY7C1570V18
Document History Page
Document Title: CY7C1566V18/CY7C1577V18/CY7C1568V18/CY7C1570V18, 72-Mbit DDR-II+ SRAM 2-Word Burst Architec-
ture (2.5 Cycle Read Latency)
Document Number: 001-06551
Issue
Date
Orig. of
Change
REV. ECN No.
Description of Change
**
432718 See ECN
437000 See ECN
461934 See ECN
NXR
IGS
New datasheet
*A
*B
ECN to show on web
NXR
Changed tTH and tTL from 40 ns to 20 ns, changed tTMSS, tTDIS, tCS, tTMSH, tTDIH, tCH
from 10 ns to 5 ns, and changed tTDOV from 20 ns to 10 ns in TAP AC Switching
Characteristics table
Modified power up waveform
*C
497567 See ECN
NXR
Changed the VDDQ operating voltage to 1.4V to VDD in the Features section, Operating
Range table, and the DC Electrical Characteristics table
Added foot note in page 1
Changed the Maximum rating of ambient temperature with power applied from –10°C
to +85°C to –55°C to +125°C
Changed VREF (Max) specification from 0.85V to 0.95V in the DC Electrical Character-
istics table and in the note below the table
Updated footnote 18 to specify overshoot and undershoot specification
Updated IDD and ISB values
Updated ΘJA and ΘJC values
Removed x9 part and its related information
Updated footnote 25
*D
1351504 See ECN VKN/AESA Converted from preliminary to final
Added x8 and x9 parts
Updated logic block diagram for x18 and x36 parts
Changed tCYC max spec to 8.4 ns for all speed bins
Updated footnote# 21
Updated Ordering Information table
© Cypress Semiconductor Corporation, 2006-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used
for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use
as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support
systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-06551 Rev. *D
Revised August 07, 2007
Page 27 of 27
QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress, IDT, NEC, Renesas, and Samsung. All product and company names mentioned in this document
are the trademarks of their respective holders.
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