CY7C1470BV25_13_技术文档

CY7C1470BV25

CY7C1472BV25

72-Mbit (2 M × 36/4 M × 18)

Pipelined SRAM with NoBL™ Architecture

72-Mbit (2

M × 36/4 M × 18) Pipelined SRAM with NoBL™ Architecture

Features

Functional Description

■ Pin-compatible and functionally equivalent to ZBT™

The CY7C1470BV25 and CY7C1472BV25 are 2.5 V,

2 M × 36/4 M × 18 synchronous pipelined burst SRAMs with No

Bus Latency™ (NoBL logic, respectively. They are designed

to support unlimited true back-to-back read or write operations

with no wait states. The CY7C1470BV25 and CY7C1472BV25

are equipped with the advanced (NoBL) logic required to enable

consecutive read or write operations with data being transferred

on every clock cycle. This feature dramatically improves the

throughput of data in systems that require frequent read or write

transitions. The CY7C1470BV25 and CY7C1472BV25 are

pin-compatible and functionally equivalent to ZBT devices.

■ Supports 250 MHz bus operations with zero wait states

❐ Available speed grades are 250, 200, and 167 MHz

■ Internally self-timed output buffer control to eliminate the need

to use asynchronous OE

■ Fully registered (inputs and outputs) for pipelined operation

■ Byte Write capability

■ Single 2.5 V power supply

All synchronous inputs pass through input registers controlled by

the rising edge of the clock. All data outputs pass through output

registers controlled by the rising edge of the clock. The clock

input is qualified by the Clock Enable (CEN) signal, which when

deasserted suspends operation and extends the previous clock

cycle. Write operations are controlled by the Byte Write Selects

(BW_a–BW_dfor CY7C1470BV25 and BW_a–BW_bfor

CY7C1472BV25) and a Write Enable (WE) input. All writes are

conducted with on-chip synchronous self-timed write circuitry.

■ 2.5 V I/O supply (V_DDQ

)

■ Fast clock-to-output times

❐ 3.0 ns (for 250-MHz device)

■ Clock Enable (CEN) pin to suspend operation

■ Synchronous self-timed writes

■ CY7C1470BV25 available in JEDEC-standard Pb-free 100-pin

TQFP and Pb-free 165-ball FBGA package. CY7C1472BV25

available in JEDEC-standard Pb-free 100-pin TQFP

Three synchronous Chip Enables (CE₁, CE₂, CE₃) and an

asynchronous Output Enable (OE) provide for easy bank

selection and output tri-state control. To avoid bus contention,

the output drivers are synchronously tri-stated during the data

portion of a write sequence.

■ IEEE 1149.1 JTAG Boundary Scan compatible

■ Burst capability – linear or interleaved burst order

■ “ZZ” Sleep Mode option and Stop Clock option

Selection Guide

Description

Maximum Access Time

250 MHz

3.0

200 MHz

3.0

167 MHz Unit

3.4

400

120

ns

Maximum Operating Current

450

mA

Maximum CMOS Standby Current

120

Cypress Semiconductor Corporation

Document Number: 001-15032 Rev. *K

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised February 25, 2013

CY7C1470BV25

CY7C1472BV25

Logic Block Diagram – CY7C1470BV25

ADDRESS

REGISTER

A0, A1,

A

0

A1

A0

A1'

A0'

D1

D0

Q1

Q0

BURST

LOGIC

MODE

ADV/LD

CLK

CEN

C

WRITE ADDRESS

REGISTER

WRITE ADDRESS

REGISTER 2

1

O

U

T

O

U

T

S

E

D

A

T

P

U

T

N

S

P

U

T

ADV/LD

A

E

WRITE REGISTRY

AND DATA COHERENCY

CONTROL LOGIC

R

E

G

I

MEMORY

ARRAY

B

U

F

E

R

S

T

E

R

I

DQ s

WRITE

DRIVERS

BW

a

DQ P

a

b

c

A

M

P

BW

b

c

S

T

E

R

S

d

S

WE

E

N

G

INPUT

REGISTER

INPUT

REGISTER 0

E

1

OE

READ LOGIC

CE1

CE2

CE3

SLEEP

CONTROL

ZZ

Logic Block Diagram – CY7C1472BV25

ADDRESS

REGISTER

A0, A1,

A

0

A1

A0

A1'

A0'

D1

D0

Q1

Q0

BURST

LOGIC

MODE

ADV/LD

CLK

CEN

C

WRITE ADDRESS

REGISTER

WRITE ADDRESS

REGISTER 2

1

O

U

T

O

U

T

P

U

T

S

E

P

U

T

D

A

T

ADV/LD

N

S

WRITE REGISTRY

AND DATA COHERENCY

CONTROL LOGIC

A

R

E

G

I

MEMORY

ARRAY

E

B

U

F

E

R

S

DQ s

DQ P

WRITE

DRIVERS

BW

a

S

T

E

R

I

A

M

P

a

b

S

T

E

R

S

b

S

N

G

WE

E

INPUT

REGISTER

INPUT

REGISTER 0

E

1

OE

CE1

CE2

CE3

READ LOGIC

Sleep

Control

ZZ

Document Number: 001-15032 Rev. *K

Page 2 of 29

CY7C1470BV25

CY7C1472BV25

Contents

Pin Configurations ...........................................................4

Pin Definitions ..................................................................6

Functional Overview ........................................................7

Single Read Accesses ................................................7

Burst Read Accesses ..................................................7

Single Write Accesses .................................................7

Burst Write Accesses ..................................................8

Sleep Mode .................................................................8

Linear Burst Address Table .........................................8

Interleaved Burst Address Table .................................8

ZZ Mode Electrical Characteristics ..............................8

Truth Table ........................................................................9

Partial Write Cycle Description .....................................10

IEEE 1149.1 Serial Boundary Scan (JTAG) ..................11

Disabling the JTAG Feature ......................................11

Test Access Port (TAP) .............................................11

Performing a TAP RESET .........................................11

TAP Registers ...........................................................11

TAP Instruction Set ...................................................11

TAP Controller State Diagram .......................................13

TAP Controller Block Diagram ......................................14

TAP Timing ......................................................................14

TAP AC Switching Characteristics ...............................15

2.5 V TAP AC Test Conditions .......................................15

2.5 V TAP AC Output Load Equivalent .........................15

TAP DC Electrical Characteristics and

Operating Conditions .....................................................15

Identification Register Definitions ................................16

Scan Register Sizes .......................................................16

Identification Codes .......................................................16

Boundary Scan Exit Order .............................................17

Maximum Ratings ...........................................................18

Operating Range .............................................................18

Electrical Characteristics ...............................................18

Capacitance ....................................................................19

Thermal Resistance ........................................................19

AC Test Loads and Waveforms .....................................19

Switching Characteristics ..............................................20

Switching Waveforms ....................................................21

Ordering Information ......................................................23

Ordering Code Definitions .........................................23

Package Diagrams ..........................................................24

Acronyms ........................................................................26

Document Conventions .................................................26

Units of Measure .......................................................26

Document History Page .................................................27

Sales, Solutions, and Legal Information ......................29

Worldwide Sales and Design Support .......................29

Products ....................................................................29

PSoC Solutions .........................................................29

Document Number: 001-15032 Rev. *K

Page 3 of 29

CY7C1470BV25

CY7C1472BV25

Pin Configurations

Figure 1. 100-pin TQFP (14 × 20 × 1.4 mm) pinout

DQPc

DQc

1

2

3

4

5

6

7

8

NC

DDQ

1

2

3

4

5

6

7

8

A

NC

78

DQPb

DQb

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

80

79

V

DDQ

V

NC

DQPa

DQa

DDQ

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

DDQ

SS

V

SS

DQc

NC

DQb

DQc

DQb

9

V

SS

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

V

SS

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

V

SS

V

DDQ

V

DQa

V

NC

V

ZZ

DDQ

DQc

NC

DQb

NC

V

SS

V

DD

NC

DD

CY7C1470BV25

(2 M × 36)

CY7C1472BV25

(4 M × 18)

NC

V

DD

V

SS

ZZ

DQa

DQd

DQb

DQa

DQd

V

DDQ

V

DQa

NC

V

DDQ

V

SS

V

SS

DQd

DQa

DQb

DQPb

NC

V

SS

V

SS

V

DDQ

V

DDQ

DQd

DQPd

DQa

DQPa

NC

Document Number: 001-15032 Rev. *K

Page 4 of 29

CY7C1470BV25

CY7C1472BV25

Pin Configurations (continued)

Figure 2. 165-ball FBGA (15 × 17 × 1.4 mm) pinout

CY7C1470BV25 (2 M × 36)

1

2

A

3

4

5

6

7

8

9

A

10

A

11

NC

NC/576M

NC/1G

DQP_c

ADV/LD

A

B

C

D

CE₁

BW_c

BW_d

V_SS

V_DD

BW_b

BW_a

V_SS

CE₃

CLK

V_SS

CEN

WE

A

CE2

V_DDQ

OE

V_SS

V_DD

A

NC

DQ_c

V_SS

V_DDQ

NC

DQ_b

DQP_b

DQ_b

DQ_c

NC

DQ_c

NC

V_DDQ

NC

V_DD

V_SS

V_DD

V_DDQ

NC

DQ_b

NC

DQ_b

ZZ

E

F

G

H

J

DQ_d

V_DDQ

DQ_a

K

L

DQ_d

DQP_d

DQ_d

NC

A

V_DDQ

A

V_DD

V_SS

A

V_SS

NC

V_SS

NC

A1

V_SS

NC

V_DD

V_SS

A

V_DDQ

A

DQ_a

NC

A

DQ_a

DQP_a

M

N

P

NC/144M

TDI

TDO

NC/288M

MODE

A

TMS

A0

TCK

A

R

A

Document Number: 001-15032 Rev. *K

Page 5 of 29

CY7C1470BV25

CY7C1472BV25

Pin Definitions

Pin Name

I/O Type

Pin Description

A₀, A₁, A

Input-

Synchronous

Address Inputs Used to Select One of the Address Locations. Sampled at the rising edge of the CLK.

BW_a, BW_b,

Input-

Byte Write Select Inputs, Active LOW. Qualified with WE to conduct writes to the SRAM. Sampled on

BW_c, BW_dSynchronous the rising edge of CLK. BW_acontrols DQ_aand DQP_a, BW_bcontrols DQ_band DQP_b, BW_ccontrols DQ_c

and DQP_c, BW_dcontrols DQ_dand DQP_d.

WE

Input-

Write Enable Input, Active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This signal

Synchronous must be asserted LOW to initiate a write sequence.

ADV/LD

Input- Advance/Load Input Used to Advance the On-Chip Address Counter or Load a New Address.

Synchronous When HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a new

address can be loaded into the device for an access. After being deselected, ADV/LD must be driven

LOW to load a new address.

CLK

CE₁

CE₂

CE₃

OE

Input-

Clock

Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN. CLK is

only recognized if CEN is active LOW.

Input-

Chip Enable 1 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE₂

Synchronous and CE₃to select/deselect the device.

Input-

Chip Enable 2 Input, Active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE₁

Synchronous and CE₃to select/deselect the device.

Input-

Chip Enable 3 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE₁

Synchronous and CE₂to select/deselect the device.

Input-

Output Enable, Active LOW. Combined with the synchronous logic block inside the device to control

Asynchronous the direction of the I/O pins. When LOW, the I/O pins can behave as outputs. When deasserted HIGH,

I/O pins are tri-stated, and act as input data pins. OE is masked during the data portion of a write

sequence, during the first clock when emerging from a deselected state and when the device has been

deselected.

CEN

DQ_s

Input-

Clock Enable Input, Active LOW. When asserted LOW the clock signal is recognized by the SRAM.

Synchronous When deasserted HIGH the clock signal is masked. Since deasserting CEN does not deselect the device,

CEN can be used to extend the previous cycle when required.

I/O-

Bidirectional Data I/O Lines. As inputs, they feed into an on-chip data register that is triggered by the

Synchronous rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by A_[18:0]

during the previous clock rise of the read cycle. The direction of the pins is controlled by OE and the

internal control logic. When OE is asserted LOW, the pins can behave as outputs. When HIGH, DQ_a–DQ_d

are placed in a tri-state condition. The outputs are automatically tri-stated during the data portion of a write

sequence, during the first clock when emerging from a deselected state, and when the device is deselected,

regardless of the state of OE.

DQP_X

MODE

TDO

TDI

I/O-

Bidirectional Data Parity I/O Lines. Functionally, these signals are identical to DQ_[71:0]. During write

Synchronous sequences, DQP_ais controlled by BW_a, DQP_bis controlled by BW_b, DQP_cis controlled by BW_c, and

DQP_dis controlled by BW_d.

Input Strap Pin Mode Input. Selects the burst order of the device. Tied HIGH selects the interleaved burst order. Pulled

LOW selects the linear burst order. MODE must not change states during operation. When left floating

MODE defaults HIGH, to an interleaved burst order.

JTAG Serial Serial Data Out to the JTAG Circuit. Delivers data on the negative edge of TCK.

Output

Synchronous

JTAG Serial Serial Data In to the JTAG Circuit. Sampled on the rising edge of TCK.

Input

Synchronous

TMS

Test Mode TMS Pin Controls the Test Access Port State Machine. Sampled on the rising edge of TCK.

Select

Synchronous

Document Number: 001-15032 Rev. *K

Page 6 of 29

CY7C1470BV25

CY7C1472BV25

Pin Definitions (continued)

Pin Name

TCK

I/O Type

Pin Description

JTAG Clock Clock Input to the JTAG Circuitry.

V_DD

Power Supply Power Supply Inputs to the Core of the Device.

V_DDQ

I/O Power Power Supply for the I/O Circuitry.

Supply

V_SS

NC

Ground

Ground for the Device. Must be connected to ground of the system.

No Connects. This pin is not connected to the die.

–

NC (144M,

288M,

These Pins are Not Connected. They are used for expansion to the 144M, 288M, 576M, and 1G

densities.

576M, 1G)

ZZ

Input-

ZZ “Sleep” Input. This active HIGH input places the device in a non-time critical “sleep” condition with

Asynchronous data integrity preserved. For normal operation, this pin has must be LOW or left floating. ZZ pin has an

internal pull down.

access the output buffers are controlled by OE and the internal

Functional Overview

control logic. OE must be driven LOW to drive out the requested

data. During the second clock, a subsequent operation (read,

write, or deselect) can be initiated. Deselecting the device is also

pipelined. Therefore, when the SRAM is deselected at clock rise

by one of the chip enable signals, its output tri-states following

the next clock rise.

The

CY7C1470BV25

and

CY7C1472BV25

are

synchronous-pipelined Burst NoBL SRAMs designed

specifically to eliminate wait states during read or write

transitions. All synchronous inputs pass through input registers

controlled by the rising edge of the clock. The clock signal is

qualified with the Clock Enable input signal (CEN). If CEN is

HIGH, the clock signal is not recognized and all internal states

are maintained. All synchronous operations are qualified with

CEN. All data outputs pass through output registers controlled by

the rising edge of the clock. Maximum access delay from the

clock rise (t_CO) is 3.0 ns (250-MHz device).

Burst Read Accesses

The CY7C1470BV25 and CY7C1472BV25 have an on-chip

burst counter that enables the user to supply a single address

and conduct up to four reads without reasserting the address

inputs. ADV/LD must be driven LOW to load a new address into

the SRAM, as described in the Single Read Accesses section.

The sequence of the burst counter is determined by the MODE

input signal. A LOW input on MODE selects a linear burst mode,

a HIGH selects an interleaved burst sequence. Both burst

counters use A0 and A1 in the burst sequence, and wraps

around when incremented sufficiently. A HIGH input on ADV/LD

increments the internal burst counter regardless of the state of

chip enables inputs or WE. WE is latched at the beginning of a

burst cycle. Therefore, the type of access (read or write) is

maintained throughout the burst sequence.

Accesses can be initiated by asserting all three Chip Enables

(CE₁, CE₂, CE₃) active at the rising edge of the clock. If CEN is

active LOW and ADV/LD is asserted LOW, the address

presented to the device is latched. The access can either be a

read or write operation, depending on the status of the Write

Enable (WE). BW_[x]can be used to conduct Byte Write

operations.

Write operations are qualified by the Write Enable (WE). All

writes are simplified with on-chip synchronous self-timed write

circuitry.

Single Write Accesses

Three synchronous Chip Enables (CE₁, CE₂, CE₃) and an

asynchronous Output Enable (OE) simplify depth expansion. All

operations (reads, writes, and deselects) are pipelined. ADV/LD

must be driven LOW after the device is deselected to load a new

address for the next operation.

Write accesses are initiated when the following conditions are

satisfied at clock rise: (1) CEN is asserted LOW, (2) CE₁, CE₂,

and CE₃are ALL asserted active, and (3) the signal WE is

asserted LOW. The address presented to the address inputs is

loaded into the Address Register. The write signals are latched

into the Control Logic block.

Single Read Accesses

A read access is initiated when the following conditions are

satisfied at clock rise: (1) CEN is asserted LOW, (2) CE₁, CE₂,

and CE₃are ALL asserted active, (3) the input signal WE is

deasserted HIGH, and (4) ADV/LD is asserted LOW. The

address presented to the address inputs is latched into the

Address Register and presented to the memory core and control

logic. The control logic determines that a read access is in

progress and allows the requested data to propagate to the input

of the output register. At the rising edge of the next clock the

requested data is allowed to propagate through the output

register and onto the data bus within 2.6 ns (250-MHz device)

provided OE is active LOW. After the first clock of the read

On the subsequent clock rise the data lines are automatically

tri-stated regardless of the state of the OE input signal. This

allows the external logic to present the data on DQ and DQP

(DQ_a,b,c,d/DQP_a,b,c,dfor CY7C1470BV25, DQ_a,b/DQP_a,bfor

CY7C1472BV25). In addition, the address for the subsequent

access (read, write, or deselect) is latched into the Address

Register (provided the appropriate control signals are asserted).

On the next clock rise the data presented to DQ and DQP

(DQ_a,b,c,d/DQP_a,b,c,dfor CY7C1470BV25, DQ_a,b/DQP_a,bfor

CY7C1472BV25) (or a subset for Byte Write operations, see

Partial Write Cycle Description on page 10 for details) inputs is

Document Number: 001-15032 Rev. *K

Page 7 of 29

CY7C1470BV25

CY7C1472BV25

latched into the device and the Write is complete.

Sleep Mode

The data written during the Write operation is controlled by BW

(BW_a,b,c,dfor CY7C1470BV25 and BW_a,bfor CY7C1472BV25)

signals. The CY7C1470BV25 and CY7C1472BV25 provides

Byte Write capability that is described in Partial Write Cycle

Description on page 10. Asserting the WE input with the selected

BW input selectively writes to only the desired bytes. Bytes not

selected during a Byte Write operation remain unaltered. A

synchronous self-timed write mechanism has been provided to

simplify the write operations. Byte Write capability has been

included to greatly simplify read, modify, or write sequences,

which can be reduced to simple Byte Write operations.

The ZZ input pin is an asynchronous input. Asserting ZZ places

the SRAM in a power conservation “sleep” mode. Two clock

cycles are required to enter into or exit from this “sleep” mode.

While in this mode, data integrity is guaranteed. Accesses

pending when entering the “sleep” mode are not considered valid

nor is the completion of the operation guaranteed. The device

must be deselected before entering the “sleep” mode. CE₁, CE₂,

and CE₃, must remain inactive for the duration of t_ZZRECafter the

ZZ input returns LOW.

Linear Burst Address Table

Because the CY7C1470BV25 and CY7C1472BV25 are

common I/O devices, data must not be driven into the device

while the outputs are active. OE can be deasserted HIGH before

presenting data to the DQ and DQP (DQ_a,b,c,d/DQP_a,b,c,dfor

CY7C1470BV25, DQ_a,b/DQP_a,bfor CY7C1472BV25) inputs.

Doing so tri-states the output drivers. As a safety precaution, DQ

(MODE = GND)

First

Address

A1: A0

Second

Address

A1: A0

Third

Address

A1: A0

Fourth

Address

A1: A0

00

01

10

11

01

10

11

00

10

11

00

01

11

00

01

10

and

DQP

(DQ_a,b,c,d/DQP_a,b,c,d

for

CY7C1470BV25,

DQ_a,b/DQP_a,bfor CY7C1472BV25) are automatically tri-stated

during the data portion of a write cycle, regardless of the state of

OE.

Burst Write Accesses

Interleaved Burst Address Table

(MODE = Floating or V_DD

The CY7C1470BV25 and CY7C1472BV25 has an on-chip burst

counter that enables the user to supply a single address and

conduct up to four write operations without reasserting the

address inputs. ADV/LD must be driven LOW to load the initial

address, as described in Single Write Accesses on page 7.

When ADV/LD is driven HIGH on the subsequent clock rise, the

Chip Enables (CE₁, CE₂, and CE₃) and WE inputs are ignored

and the burst counter is incremented. The correct BW (BW_a,b,c,d

for CY7C1470BV25, BW_a,bfor CY7C1472BV25) inputs must be

driven in each cycle of the burst write to write the correct bytes

of data.

)

First

Address

A1: A0

Second

Address

A1: A0

Third

Address

A1: A0

Fourth

Address

A1: A0

00

01

10

11

01

00

11

10

11

00

01

11

10

01

00

ZZ Mode Electrical Characteristics

Parameter

I_DDZZ

Description

Sleep mode standby current

Device operation to ZZ

ZZ recovery time

Test Conditions

Min

Max

120

2t_CYC

–

Unit

mA

ns

ZZ  V_DD 0.2 V

–

t_ZZS

ZZV_DD 0.2 V

ZZ  0.2 V

–

2t_CYC

–

t_ZZREC

t_ZZI

ns

ZZ active to sleep current

This parameter is sampled

2t_CYC

–

ns

t_RZZI

ZZ Inactive to exit sleep current This parameter is sampled

0

ns

Document Number: 001-15032 Rev. *K

Page 8 of 29

CY7C1470BV25

CY7C1472BV25

Truth Table

The truth table for CY7C1470BV25 and CY7C1472BV25 follows. ^{[1, 2, 3, 4, 5, 6, 7]}

Operation

Address Used CE ZZ ADV/LD WE BW_xOE CEN CLK

DQ

Deselect Cycle

None

H

X

L

H

L

H

L

X

H

X

H

X

L

X

L

X

L

H

X

L–H

Tri-State

Continue Deselect Cycle

Read Cycle (Begin Burst)

Read Cycle (Continue Burst)

NOP/Dummy Read (Begin Burst)

Dummy Read (Continue Burst)

Write Cycle (Begin Burst)

Write Cycle (Continue Burst)

NOP/Write Abort (Begin Burst)

Write Abort (Continue Burst)

Ignore Clock Edge (Stall)

Sleep Mode

External

L–H Data Out (Q)

X

L

H

L

External

H

X

L–H

Tri-State

X

L

H

L

External

L–H Data In (D)

X

L

H

L

X

L

None

H

X

L–H

X

Tri-State

–

X

H

X

Current

None

Tri-State

Notes

1. X = “Don't Care”, H = Logic HIGH, L = Logic LOW, CE stands for ALL Chip Enables active. BW = L signifies at least one Byte Write Select is active, BW = Valid

x

signifies that the desired Byte Write Selects are asserted, see Partial Write Cycle Description on page 10 for details.

2. Write is defined by WE and BW

. See Partial Write Cycle Description on page 10 for details.

[a:d]

3. When a write cycle is detected, all IOs are tri-stated, even during Byte Writes.

4. The DQ and DQP pins are controlled by the current cycle and the OE signal.

5. CEN = H inserts wait states.

6. Device powers up deselected with the IOs in a tri-state condition, regardless of OE.

7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles.During a Read cycle DQ and DQP

= tri-state when OE is

[a:d]

s

inactive or when the device is deselected, and DQ = data when OE is active.

s

Document Number: 001-15032 Rev. *K

Page 9 of 29

CY7C1470BV25

CY7C1472BV25

Partial Write Cycle Description

The partial write cycle description for CY7C1470BV25 and CY7C1472BV25 follows. ^{[8, 9, 10, 11]}

Function (CY7C1470BV25)

WE

H

L

BW_d

X

H

L

BW_c

X

H

L

BW_b

X

H

L

BW_a

X

H

L

Read

Write – No bytes written

Write Byte a – (DQ_aand DQP_a)

Write Byte b – (DQ_band DQP_b)

Write Bytes b, a

L

H

L

Write Byte c – (DQ_cand DQP_c)

Write Bytes c, a

L

H

L

H

L

Write Bytes c, b

L

H

L

Write Bytes c, b, a

L

Write Byte d – (DQ_dand DQP_d)

Write Bytes d, a

L

H

L

H

L

H

L

Write Bytes d, b

L

H

L

Write Bytes d, b, a

L

Write Bytes d, c

L

H

L

H

L

Write Bytes d, c, a

L

Write Bytes d, c, b

L

H

L

Write All Bytes

L

Function (CY7C1472BV25)

WE

H

L

BW_b

BW_a

x

Read

x

H

L

Write – No Bytes Written

Write Byte a – (DQ_aand DQP_a)

Write Byte b – (DQ_band DQP_b)

Write Both Bytes

H

L

H

L

Notes

8. X = “Don't Care”, H = Logic HIGH, L = Logic LOW, CE stands for ALL Chip Enables active. BW = L signifies at least one Byte Write Select is active, BW = Valid

x

signifies that the desired Byte Write Selects are asserted, see Partial Write Cycle Description for details.

9. Write is defined by WE and BW

. See Partial Write Cycle Description for details.

[a:d]

10. When a write cycle is detected, all IOs are tri-stated, even during Byte Writes.

11. Table lists only a partial listing of the Byte Write combinations. Any combination of BW

is valid. Appropriate write is based on which Byte Write is active.

[a:d]

Document Number: 001-15032 Rev. *K

Page 10 of 29

CY7C1470BV25

CY7C1472BV25

During power up, the TAP is reset internally to ensure that TDO

comes up in a High Z state.

IEEE 1149.1 Serial Boundary Scan (JTAG)

The CY7C1470BV25 incorporates a serial boundary scan test

access port (TAP). This port operates in accordance with IEEE

Standard 1149.1-1990 but does not have the set of functions

required for full 1149.1 compliance. These functions from the

IEEE specification are excluded because their inclusion places

an added delay in the critical speed path of the SRAM. Note that

the TAP controller functions in a manner that does not conflict

with the operation of other devices using 1149.1 fully compliant

TAPs. The TAP operates using JEDEC-standard 2.5 V I/O logic

levels.

TAP Registers

Registers are connected between the TDI and TDO balls to scan

the data in and out of the SRAM test circuitry. Only one register

can be selected at a time through the instruction register. Data is

serially loaded into the TDI ball on the rising edge of TCK. Data

is output on the TDO ball on the falling edge of TCK.

Instruction Register

Three-bit instructions can be serially loaded into the instruction

register. This register is loaded when it is placed between the TDI

and TDO balls as shown in the TAP Controller Block Diagram on

page 14. During power up, the instruction register is loaded with

the IDCODE instruction. It is also loaded with the IDCODE

instruction if the controller is placed in a reset state as described

in the previous section.

The CY7C1470BV25 contains a TAP controller, instruction

register, boundary scan register, bypass register, and ID register.

Disabling the JTAG Feature

It is possible to operate the SRAM without using the JTAG

feature. To disable the TAP controller, TCK must be tied LOW

(V_SS) to prevent clocking of the device. TDI and TMS are

internally pulled up and may be unconnected. They may

alternately be connected to V_DDthrough a pull up resistor. TDO

must be left unconnected. During power up, the device comes

up in a reset state, which does not interfere with the operation of

the device.

When the TAP controller is in the Capture-IR state, the two least

significant bits are loaded with a binary ‘01’ pattern to enable fault

isolation of the board-level serial test data path.

Bypass Register

To save time when serially shifting data through registers, it is

sometimes advantageous to skip certain chips. The bypass

register is a single-bit register that can be placed between the

TDI and TDO balls. This shifts the data through the SRAM with

minimal delay. The bypass register is set LOW (V_SS) when the

BYPASS instruction is executed.

Test Access Port (TAP)

Test Clock (TCK)

The test clock is used only with the TAP controller. All inputs are

captured on the rising edge of TCK. All outputs are driven from

the falling edge of TCK.

Boundary Scan Register

The boundary scan register is connected to all the input and

bidirectional balls on the SRAM.

Test Mode Select (TMS)

The TMS input is used to give commands to the TAP controller

and is sampled on the rising edge of TCK. It is allowable to leave

this ball unconnected if the TAP is not used. The ball is pulled up

internally, resulting in a logic HIGH level.

The boundary scan register is loaded with the contents of the

RAM I/O ring when the TAP controller is in the Capture-DR state

and is then placed between the TDI and TDO balls when the

controller is moved to the Shift-DR state. The EXTEST,

SAMPLE/PRELOAD and SAMPLE Z instructions can be used to

capture the contents of the I/O ring.

Test Data-In (TDI)

The TDI ball is used to serially input information into the registers

and can be connected to the input of any of the registers. The

register between TDI and TDO is chosen by the instruction that

is loaded into the TAP instruction register. For information about

loading the instruction register, see the TAP Controller State

Diagram. TDI is internally pulled up and can be unconnected if

the TAP is unused in an application. TDI is connected to the most

significant bit (MSB) of any register.

The Boundary Scan Order tables show the order in which the bits

are connected. Each bit corresponds to one of the bumps on the

SRAM package. The MSB of the register is connected to TDI and

the LSB is connected to TDO.

Identification (ID) Register

The ID register is loaded with a vendor-specific, 32-bit code

during the Capture-DR state when the IDCODE command is

loaded in the instruction register. The IDCODE is hardwired into

the SRAM and can be shifted out when the TAP controller is in

the Shift-DR state. The ID register has a vendor code and other

information described in Identification Register Definitions on

page 16.

Test Data-Out (TDO)

The TDO output ball is used to serially clock data-out from the

registers. The output is active depending upon the current state

of the TAP state machine (see Identification Codes on page 16).

The output changes on the falling edge of TCK. TDO is

connected to the least significant bit (LSB) of any register.

TAP Instruction Set

Performing a TAP RESET

Overview

A RESET is performed by forcing TMS HIGH (V_DD) for five rising

edges of TCK. This RESET does not affect the operation of the

SRAM and may be performed while the SRAM is operating.

Eight different instructions are possible with the three-bit

instruction register. All combinations are listed in Identification

Codes on page 16. Three of these instructions are listed as

Document Number: 001-15032 Rev. *K

Page 11 of 29

CY7C1470BV25

CY7C1472BV25

RESERVED and must not be used. The other five instructions

are described in this section in detail.

SAMPLE/PRELOAD

SAMPLE/PRELOAD is a 1149.1 mandatory instruction. The

PRELOAD portion of this instruction is not implemented, so the

device TAP controller is not fully 1149.1 compliant.

The TAP controller used in this SRAM is not fully compliant to the

1149.1 convention because some of the mandatory 1149.1

instructions are not fully implemented.

When the SAMPLE/PRELOAD instruction is loaded into the

instruction register and the TAP controller is in the Capture-DR

state, a snapshot of data on the inputs and bidirectional balls is

captured in the boundary scan register.

The TAP controller cannot be used to load address data or

control signals into the SRAM and cannot preload the I/O buffers.

The SRAM does not implement the 1149.1 commands EXTEST

or INTEST or the PRELOAD portion of SAMPLE/PRELOAD;

rather, it performs a capture of the I/O ring when these

instructions are executed.

The user must be aware that the TAP controller clock can only

operate at a frequency up to 20 MHz, while the SRAM clock

operates more than an order of magnitude faster. Because there

is a large difference in the clock frequencies, it is possible that

during the Capture-DR state, an input or output may undergo a

transition. The TAP may then try to capture a signal while in

transition (metastable state). This does not harm the device, but

there is no guarantee as to the value that is captured.

Repeatable results may not be possible.

Instructions are loaded into the TAP controller during the Shift-IR

state when the instruction register is placed between TDI and

TDO. During this state, instructions are shifted through the

instruction register through the TDI and TDO balls. To execute

the instruction after it is shifted in, the TAP controller must be

moved into the Update-IR state.

To guarantee that the boundary scan register captures the

correct value of a signal, the SRAM signal must be stabilized

long enough to meet the TAP controller’s capture setup plus hold

time (t_CSplus t_CH).

EXTEST

EXTEST is a mandatory 1149.1 instruction which is executed

whenever the instruction register is loaded with all 0s. EXTEST

is not implemented in this SRAM TAP controller, and therefore

this device is not compliant to 1149.1. The TAP controller does

recognize an all-0 instruction.

The SRAM clock input might not be captured correctly if there is

no way in a design to stop (or slow) the clock during a

SAMPLE/PRELOAD instruction. If this is an issue, it is still

possible to capture all other signals and simply ignore the value

of the CLK captured in the boundary scan register.

When an EXTEST instruction is loaded into the instruction

register, the SRAM responds as if a SAMPLE/PRELOAD

instruction has been loaded. There is one difference between the

two instructions. Unlike the SAMPLE/PRELOAD instruction,

EXTEST places the SRAM outputs in a High Z state.

After the data is captured, it is possible to shift out the data by

putting the TAP into the Shift-DR state. This places the boundary

scan register between the TDI and TDO balls.

IDCODE

Note that since the PRELOAD part of the command is not

implemented, putting the TAP to the Update-DR state while

performing a SAMPLE/PRELOAD instruction has the same

effect as the Pause-DR command.

The IDCODE instruction loads a vendor-specific, 32-bit code into

the instruction register. It also places the instruction register

between the TDI and TDO balls and shifts the IDCODE out of the

device when the TAP controller enters the Shift-DR state.

BYPASS

The IDCODE instruction is loaded into the instruction register

during power up or whenever the TAP controller is in a test logic

reset state.

When the BYPASS instruction is loaded in the instruction register

and the TAP is placed in a Shift-DR state, the bypass register is

placed between the TDI and TDO balls. The advantage of the

BYPASS instruction is that it shortens the boundary scan path

when multiple devices are connected together on a board.

SAMPLE Z

The SAMPLE Z instruction connects the boundary scan register

between the TDI and TDO pins when the TAP controller is in a

Shift-DR state. It also places all SRAM outputs into a High Z

state.

Reserved

These instructions are not implemented but are reserved for

future use. Do not use these instructions.

Document Number: 001-15032 Rev. *K

Page 12 of 29

CY7C1470BV25

CY7C1472BV25

TAP Controller State Diagram

TEST-LOGIC

1

RESET

0

1

RUN-TEST/

IDLE

SELECT

DR-SCAN

SELECT

IR-SCAN

0

1

CAPTURE-DR

CAPTURE-IR

0

SHIFT-DR

0

SHIFT-IR

0

1

EXIT1-DR

EXIT1-IR

0

PAUSE-DR

0

PAUSE-IR

1

0

1

0

EXIT2-DR

1

EXIT2-IR

1

UPDATE-DR

UPDATE-IR

1

0

1

0

The 0/1 next to each state represents the value of TMS at the rising edge of TCK.

Document Number: 001-15032 Rev. *K

Page 13 of 29

CY7C1470BV25

CY7C1472BV25

TAP Controller Block Diagram

0

Bypass Register

2

1

Selection

Circuitry

Selection

Circuitry

Instruction Register

31 30 29 .

Identiﬁcation Register

TDI

TDO

.

2

1

0

x

.

. 2 1

0

Boundary Scan Register

TCK

TAP CONTROLLER

TM S

TAP Timing

Figure 3. TAP Timing

1

2

3

4

5

6

Test Clock

(TCK)

t

CYC

TH

TL

t

TM SS

TDIS

TM SH

Test M ode Select

(TM S)

TDIH

Test Data-In

(TDI)

t

TDOV

t

TDOX

Test Data-Out

(TDO)

DON’T CARE

UNDEFINED

Document Number: 001-15032 Rev. *K

Page 14 of 29

CY7C1470BV25

CY7C1472BV25

TAP AC Switching Characteristics

Over the Operating Range

Parameter ^{[12, 13]}

Clock

Description

Min

Max

Unit

t_TCYC

TCK Clock Cycle Time

TCK Clock Frequency

TCK Clock HIGH time

TCK Clock LOW time

50

–

20

–

ns

MHz

ns

t_TF

t_TH

20

t_TL

–

ns

Output Times

t_TDOV

t_TDOX

Setup Times

t_TMSS

t_TDIS

TCK Clock LOW to TDO Valid

TCK Clock LOW to TDO Invalid

–

0

10

–

ns

TMS Setup to TCK Clock Rise

TDI Setup to TCK Clock Rise

Capture Setup to TCK Rise

5

–

ns

t_CS

Hold Times

t_TMSH

t_TDIH

TMS Hold after TCK Clock Rise

TDI Hold after Clock Rise

5

–

ns

t_CH

Capture Hold after Clock Rise

2.5 V TAP AC Test Conditions

2.5 V TAP AC Output Load Equivalent

Input pulse levels ...............................................V_SSto 2.5 V

Input rise and fall time ....................................................1 ns

Input timing reference levels ....................................... 1.25 V

Output reference levels .............................................. 1.25 V

Test load termination supply voltage .......................... 1.25 V

1.25V

50Ω

TDO

Z_O= 50Ω

20pF

TAP DC Electrical Characteristics and Operating Conditions

(0 °C < T_A< +70 °C; V_DD= 2.5 V ± 0.125 V unless otherwise noted)

Parameter ^[14]

Description

Output HIGH Voltage

Output LOW Voltage

Input HIGH Voltage

Input LOW Voltage

Input Load Current

Test Conditions

I_OH= –1.0 mA, V_DDQ= 2.5 V

I_OH= –100 A, V_DDQ= 2.5 V

I_OL= 1.0 mA, V_DDQ= 2.5 V

I_OL= 100 A, V_DDQ= 2.5 V

V_DDQ= 2.5 V

Min

1.7

2.1

–

Max

Unit

V

V_OH1

V_OH2

V_OL1

V_OL2

V_IH

–

0.4

V

–

0.2

V

1.7

–0.3

–5

V_DD+ 0.3

0.7

V

V_IL

V_DDQ= 2.5 V

V

I_X

GND  V_I V_DDQ

5

A

Notes

12. t and t refer to the setup and hold time requirements of latching data from the boundary scan register.

CS

CH

13. Test conditions are specified using the load in TAP AC Test Conditions. t /t = 1 ns.

R

F

14. All voltages refer to V (GND).

SS

Document Number: 001-15032 Rev. *K

Page 15 of 29

CY7C1470BV25

CY7C1472BV25

Identification Register Definitions

Instruction Field

Revision Number (31:29)

CY7C1470BV25 (2 M × 36)

Description

000

01011

Describes the version number

Device Depth (28:24)

Reserved for internal use

Architecture/Memory Type (23:18)

Bus Width/Density (17:12)

001000

100100

00000110100

1

Defines memory type and architecture

Defines width and density

Cypress JEDEC ID Code (11:1)

ID Register Presence Indicator (0)

Allows unique identification of SRAM vendor

Indicates the presence of an ID register

Scan Register Sizes

Register Name

Bit Size (× 36)

Instruction

3

1

Bypass

ID

32

71

Boundary Scan Order – 165-ball FBGA

Identification Codes

Instruction

EXTEST

Code

Description

000

Captures I/O ring contents. Places the boundary scan register between TDI and TDO.

Forces all SRAM outputs to High Z state. This instruction is not 1149.1-compliant.

IDCODE

001

010

Loads the ID register with the vendor ID code and places the register between TDI and TDO.

This operation does not affect SRAM operations.

SAMPLE Z

Captures I/O ring contents. Places the boundary scan register between TDI and TDO.

Forces all SRAM output drivers to a High Z state.

RESERVED

011

100

Do Not Use: This instruction is reserved for future use.

SAMPLE/PRELOAD

Captures I/O ring contents. Places the boundary scan register between TDI and TDO.

Does not affect SRAM operation. This instruction does not implement 1149.1 preload function

and is therefore not 1149.1 compliant.

RESERVED

BYPASS

101

110

111

Do Not Use: This instruction is reserved for future use.

Places the bypass register between TDI and TDO. This operation does not affect SRAM

operations.

Document Number: 001-15032 Rev. *K

Page 16 of 29

CY7C1470BV25

CY7C1472BV25

Boundary Scan Exit Order

(2 M × 36)

Bit #

1

165-ball ID

C1

Bit #

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

165-ball ID

R3

Bit #

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

165-ball ID

J11

Bit #

61

62

63

64

65

66

67

68

69

70

71

165-ball ID

B7

B6

A6

B5

A5

A4

B4

B3

A3

A2

B2

2

D1

P2

K10

J10

H11

G11

F11

E11

D10

D11

C11

G10

F10

E10

A9

3

E1

R4

4

D2

P6

5

E2

R6

6

F1

R8

7

G1

F2

P3

8

P4

9

G2

J1

P8

10

11

12

13

14

15

16

17

18

19

20

P9

K1

P10

R9

L1

J2

R10

R11

N11

M11

L11

M10

L10

K11

M1

N1

B9

K2

A10

B10

A8

L2

M2

R1

B8

R2

A7

Document Number: 001-15032 Rev. *K

Page 17 of 29

CY7C1470BV25

CY7C1472BV25

Current into Outputs (LOW) ........................................ 20 mA

Maximum Ratings

Static Discharge Voltage

(MIL-STD-883, Method 3015) ................................ > 2001 V

Exceeding maximum ratings may impair the useful life of the

device. These user guidelines are not tested.

Latch up Current ................................................... > 200 mA

Storage Temperature ............................... –65 °C to +150 °C

Ambient Temperature with

Power Applied ......................................... –55 °C to +125 °C

Operating Range

Ambient

Supply Voltage on V_DDRelative to GND .....–0.5 V to +3.6 V

Supply Voltage on V_DDQRelative to GND .... –0.5 V to +V_DD

DC to Outputs in Tri-State .................–0.5 V to V_DDQ+ 0.5 V

DC Input Voltage ................................–0.5 V to V_DD+ 0.5 V

Range

V_DD

V_DDQ

Temperature

Commercial 0 °C to +70 °C 2.5 V – 5% / +5% 2.5V–5%to

V_DD

Industrial

–40 °C to +85 °C

Electrical Characteristics

Over the Operating Range

Parameter ^{[15, 16]}

Description

Power Supply Voltage

I/O Supply Voltage

Test Conditions

Min

2.375

2.0

Max

2.625

V_DD

–

Unit

V

V_DD

V_DDQ

V_OH

V_OL

V_IH

For 2.5 V I/O

V

Output HIGH Voltage

Output LOW Voltage

Input HIGH Voltage ^[15]

Input LOW Voltage ^[15]

For 2.5 V I/O, I_OH=1.0 mA

For 2.5 V I/O, I_OL=1.0 mA

For 2.5 V I/O

V

–

0.4

V

1.7

V_DD+ 0.3

0.7

V

V_IL

For 2.5 V I/O

–0.3

–5

V

I_X

Input Leakage Current except ZZ GND  V_I V_DDQ

and MODE

5

A

Input Current of MODE

Input = V_SS

–30

–

5

A

mA

Input = V_DD

Input Current of ZZ

Input = V_SS

–5

–

Input = V_DD

30

5

I_OZ

Output Leakage Current

V_DDOperating Supply

GND  V_I V_DDQ,Output Disabled

–5

–

[17]

I_DD

V_DD= Max, I_OUT= 0 mA,

f = f_MAX= 1/t_CYC

4.0 ns cycle,

250 MHz

450

–

5.0 ns cycle,

200 MHz

6.0 ns cycle,

167 MHz

–

400

200

120

mA

I_SB1

Automatic CE Power Down

Current – TTL Inputs

Max. V_DD, Device Deselected, 4.0 ns cycle,

V_IN V_IHor V_IN V_IL,

250MHz

f = f_MAX= 1/t_CYC

5.0 ns cycle,

200 MHz

6.0 ns cycle,

167 MHz

I_SB2

Automatic CE Power Down

Current – CMOS Inputs

Max. V_DD, Device Deselected, All speed

V_IN 0.3VorV_IN> V_DDQ0.3 V, grades

f = 0

Notes

15. Overshoot: V

< V +1.5 V (pulse width less than t

/2). Undershoot: V

> –2 V (pulse width less than t

/2).

IH(AC)

DD

CYC

IL(AC)

CYC

16. T

: assumes a linear ramp from 0 V to V

within 200 ms. During this time V < V and V

< V

.

Power-up

DD(min)

IH

DD

DDQ

DD

17. The operation current is calculated with 50% read cycle and 50% write cycle.

Document Number: 001-15032 Rev. *K

Page 18 of 29

CY7C1470BV25

CY7C1472BV25

Electrical Characteristics (continued)

Over the Operating Range

Parameter ^{[15, 16]}

Description

Test Conditions

Min

Max

Unit

I_SB3

Automatic CE Power Down

Current – CMOS Inputs

Max. V_DD, Device Deselected, 4.0 ns cycle,

–

200

mA

V_IN 0.3 V or V_IN> V_DDQ0.3 V, 250 MHz

f = f_MAX= 1/t_CYC

5.0 ns cycle,

–

200

135

mA

200 MHz

6.0 ns cycle,

167 MHz

I_SB4

Automatic CE Power Down

Current – TTL Inputs

Max. V_DD, Device Deselected, All speed

V_IN V_IHor V_IN V_IL, f = 0

grades

Capacitance

100-pin TQFP 165-ball FBGA

Parameter ^[18]

Description

Test Conditions

Unit

Max

C_ADDRESS

C_DATA

C_CTRL

C_CLK

Address input capacitance

Data input capacitance

Control input capacitance

Clock input capacitance

Input/Output capacitance

T_A= 25 °C, f = 1 MHz,

6

5

8

6

5

6

5

8

6

5

pF

V_DD= 2.5 V, V_DDQ= 2.5 V

C_IO

Thermal Resistance

100-pin TQFP 165-ballFBGA

Parameter ^[18]

Description

Test Conditions

Unit

Package

_JA

Thermal resistance

(junction to ambient)

Test conditions follow standard test

methods and procedures for measuring

thermal impedance, per EIA/JESD51.

24.63

16.3

C/W

_JC

Thermal resistance

(junction to case)

2.28

2.1

C/W

AC Test Loads and Waveforms

Figure 4. AC Test Loads and Waveforms

2.5 V I/O Test Load

R = 1667 

2.5 V

OUTPUT

ALL INPUT PULSES

90%

V_DDQ

OUTPUT

90%

10%

Z = 50 

0

10%

R = 50 

L

GND

5 pF

R = 1538 

 1 ns

V = 1.25 V

L

INCLUDING

JIG AND

SCOPE

(c)

(a)

(b)

Note

18. Tested initially and after any design or process changes that may affect these parameters.

Document Number: 001-15032 Rev. *K

Page 19 of 29

CY7C1470BV25

CY7C1472BV25

Switching Characteristics

Over the Operating Range

250 MHz

200 MHz

167 MHz

Unit

Parameter ^{[19, 20]}

Description

Min

Max

Min

Max

Min

Max

[21]

t_Power

V_CC(typical) to the first access

Read or Write

1

–

1

–

1

–

ms

Clock

t_CYC

Clock cycle time

Maximum operating frequency

Clock HIGH

4.0

–

250

–

5.0

–

200

–

6.0

–

167

–

ns

MHz

ns

F_MAX

t_CH

2.0

2.2

t_CL

Clock LOW

–

ns

Output Times

t_CO

Data output valid after CLK rise

OE LOW to output valid

–

3.0

–

3.0

–

3.4

–

ns

t_OEV

t_DOH

Data output hold after CLK rise

Clock to high Z ^{[22, 23, 24]}

Clock to low Z ^{[22, 23, 24]}

1.3

–

1.3

–

1.5

–

t_CHZ

3.0

–

3.0

–

3.4

–

t_CLZ

1.3

–

1.3

–

1.5

–

t_EOHZ

OE HIGH to output high Z^{[22, 23,}

3.0

3.4

24]

t_EOLZ

Setup Times

t_AS

OE LOW to output low Z ^{[22, 23, 24]}

0

–

0

–

0

–

ns

Address setup before CLK rise

Data input setup before CLK rise

CEN setup before CLK rise

WE, BW_xsetup before CLK rise

ADV/LD setup before CLK Rise

Chip select setup

1.4

–

1.4

–

1.5

–

ns

t_DS

t_CENS

t_WES

t_ALS

t_CES

Hold Times

t_AH

Address hold after CLK rise

Data input hold after CLK rise

CEN hold after CLK rise

0.4

–

0.4

–

0.5

–

ns

t_DH

t_CENH

t_WEH

WE, BW_xhold after CLK rise

ADV/LD hold after CLK rise

Chip Select hold after CLK rise

t_ALH

t_CEH

Notes

19. Timing reference is 1.25 V when V

= 2.5 V.

DDQ

20. Test conditions shown in (a) of Figure 4 on page 19 unless otherwise noted.

21. This part has a voltage regulator internally; t is the time power is supplied above V

initially, before a read or write operation can be initiated.

DD(minimum)

power

22. t

, t

, and t

are specified with AC test conditions shown in (b) of Figure 4 on page 19. Transition is measured ±200 mV from steady-state voltage.

CHZ CLZ EOLZ

EOHZ

23. At any supplied voltage and temperature, t

is less than t

and t

is less than t

to eliminate bus contention between SRAMs when sharing the same data

CLZ

EOHZ

EOLZ

CHZ

bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve

High Z before Low Z under the same system conditions.

24. This parameter is sampled and not 100% tested.

Document Number: 001-15032 Rev. *K

Page 20 of 29

CY7C1470BV25

CY7C1472BV25

Switching Waveforms

Figure 5. Read/Write Timing ^{[25, 26, 27]}

1

2

3

4

5

6

7

8

9

10

t

CYC

t

CLK

t

CENS

CENH

CL

CH

CEN

t

CES

CEH

CE

ADV/LD

WE

BW

x

A1

A2

A4

CO

A3

A5

A6

A7

ADDRESS

t

DS

DH

t

DOH

OEV

CLZ

CHZ

t

AS

AH

Data

D(A1)

D(A2)

D(A2+1)

Q(A3)

Q(A4)

Q(A4+1)

D(A5)

Q(A6)

In-Out (DQ)

t

OEHZ

t

DOH

t

OELZ

OE

WRITE

D(A1)

WRITE

D(A2)

BURST

WRITE

READ

Q(A3)

READ

Q(A4)

BURST

READ

WRITE

D(A5)

READ

Q(A6)

WRITE

D(A7)

DESELECT

D(A2+1)

Q(A4+1)

DON’T CARE

UNDEFINED

Notes

25. For this waveform ZZ is tied LOW.

26. When CE is LOW, CE is LOW, CE is HIGH, and CE is LOW. When CE is HIGH,CE is HIGH, CE is LOW, or CE is HIGH.

1

2

3

1

2

3

27. Order of the Burst sequence is determined by the status of the MODE (0 = Linear, 1 = Interleaved).Burst operations are optional.

Document Number: 001-15032 Rev. *K

Page 21 of 29

CY7C1470BV25

CY7C1472BV25

Switching Waveforms (continued)

Figure 6. NOP, STALL and DESELECT Cycles ^{[28, 29, 30]}

1

2

3

4

5

6

7

8

9

10

CLK

CEN

CE

ADV/LD

WE

BWx

A1

A2

A3

A4

A5

ADDRESS

t

CHZ

D(A4)

D(A1)

Q(A2)

Q(A3)

Q(A5)

Data

In-Out (DQ)

WRITE

D(A1)

READ

Q(A2)

STALL

READ

Q(A3)

WRITE

D(A4)

STALL

NOP

READ

Q(A5)

DESELECT

CONTINUE

DESELECT

DON’T CARE

UNDEFINED

Figure 7. ZZ Mode Timing ^{[31, 32]}

CLK

t

ZZ

ZZREC

ZZ

t

ZZI

I

SUPPLY

I

DDZZ

t

RZZI

ALL INPUTS

(except ZZ)

DESELECT or READ Only

Outputs (Q)

High-Z

DON’T CARE

Notes

28. For this waveform ZZ is tied LOW.

29. When CE is LOW, CE is LOW, CE is HIGH, and CE is LOW. When CE is HIGH,CE is HIGH, CE is LOW, or CE is HIGH.

1

2

3

1

2

3

30. The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrated CEN being used to create a pause. A write is not performed during this cycle.

31. Device must be deselected when entering ZZ mode. See Truth Table on page 9 for all possible signal conditions to deselect the device.

32. IOs are in High Z when exiting ZZ sleep mode.

Document Number: 001-15032 Rev. *K

Page 22 of 29

CY7C1470BV25

CY7C1472BV25

Ordering Information

Cypress offers other versions of this type of product in many different configurations and features. The below table contains only the

list of parts that are currently available. For a complete listing of all options, visit the Cypress website at www.cypress.com and refer

to the product summary page at http://www.cypress.com/products or contact your local sales representative. Cypress maintains a

worldwide network of offices, solution centers, manufacturer’s representatives and distributors. To find the office closest to you, visit

us at t http://www.cypress.com/go/datasheet/offices.

Speed

(MHz)

Package

Diagram

Operating

Range

Part and Package Type

Ordering Code

167 CY7C1470BV25-167AXC

CY7C1470BV25-167BZXI

200 CY7C1470BV25-200AXC

CY7C1472BV25-200AXC

CY7C1470BV25-200AXI

51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free

51-85165 165-ball FBGA (15 × 17 × 1.4 mm) Pb-free

51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free

Commercial

Industrial

Commercial

Industrial

CY7C1470BV25-200BZXI

250 CY7C1470BV25-250AXC

CY7C1470BV25-250BZXC

CY7C1470BV25-250AXI

51-85165 165-ball FBGA (15 × 17 × 1.4 mm) Pb-free

51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free

51-85165 165-ball FBGA (15 × 17 × 1.4 mm) Pb-free

51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free

Commercial

Industrial

Ordering Code Definitions

CY

7

C 147X B V25 - XXX XX X X

Temperature Range: X = C or I

C = Commercial; I = Industrial

Pb-free

Package Type: XX = A or BZ

AX = 100-pin TQFP

BZX = 165-ball FBGA

Frequency Range: XXX = 167 MHz or 200 MHz or 250 MHz

V_DD: V25 = 2.5 V

Die Revision

147X = 1470 or 1472

1470 = PL, 2 Mb × 36 (72 Mb)

1472 = PL, 4 Mb × 18 (72 Mb)

Technology Code: C = CMOS

Marketing Code: 7 = SRAM

Company ID: CY = Cypress

Document Number: 001-15032 Rev. *K

Page 23 of 29

CY7C1470BV25

CY7C1472BV25

Package Diagrams

Figure 8. 100-pin TQFP (14 × 20 × 1.4 mm) A100RA Package Outline, 51-85050

51-85050 *D

Document Number: 001-15032 Rev. *K

Page 24 of 29

CY7C1470BV25

CY7C1472BV25

Package Diagrams (continued)

Figure 9. 165-ball FBGA (15 × 17 × 1.4 mm) (0.45 Ball Diameter) Package Outline, 51-85165

51-85165 *D

Document Number: 001-15032 Rev. *K

Page 25 of 29

CY7C1470BV25

CY7C1472BV25

Acronyms

Document Conventions

Units of Measure

Acronym

BGA

CMOS

EIA

Description

Ball Grid Array

Symbol

°C

Unit of Measure

Complementary Metal Oxide Semiconductor

Electronic Industries Alliance

Fine-Pitch Ball Grid Array

Input/Output

degree Celsius

microampere

milliampere

millimeter

millisecond

megahertz

nanosecond

ohm

µA

mA

mm

ms

MHz

ns

FBGA

I/O

JEDEC

JTAG

LSB

Joint Electron Devices Engineering Council

Joint Test Action Group

Least Significant Bit

MSB

OE

Most Significant Bit



Output Enable

%

percent

SRAM

TAP

Static Random Access Memory

Test Access Port

pF

V

picofarad

volt

TCK

Test Clock

W

watt

TDI

Test Data-In

TDO

TMS

TQFP

TTL

Test Data-Out

Test Mode Select

Thin Quad Flat Pack

Transistor-Transistor Logic

Write Enable

WE

Document Number: 001-15032 Rev. *K

Page 26 of 29

CY7C1470BV25

CY7C1472BV25

Document History Page

Document Title: CY7C1470BV25/CY7C1472BV25, 72-Mbit (2 M × 36/4 M × 18) Pipelined SRAM with NoBL™ Architecture

Document Number: 001-15032

Orig. of

Change

Rev.

ECN No.

Issue Date

Description of Change

**

1032642

See ECN

VKN /

KKVTMP

New data sheet.

*A

1562503

See ECN

VKN /

AESA

Updated Features (Removed 1.8 V I/O supply information).

Updated IEEE 1149.1 Serial Boundary Scan (JTAG) (Removed 1.8 V I/O

supply information).

Removed the section “1.8 V TAP AC Test Conditions”.

Removed the section “1.8 V TAP AC Output Load Equivalent”.

Updated TAP DC Electrical Characteristics and Operating Conditions

(Removed 1.8 V I/O supply information).

Updated Electrical Characteristics (Removed 1.8 V I/O supply information).

Updated AC Test Loads and Waveforms (Removed 1.8 V I/O supply

information).

Updated Switching Characteristics (Removed 1.8 V I/O supply information).

*B

1897447

See ECN

VKN /

AESA

Updated Electrical Characteristics (Added Note 17 and referred the same note

in I_DDparameter).

*C

*D

2082487

2159486

See ECN

VKN

Changed status from Preliminary to Final.

Minor Change (Moved to the external web).

VKN /

PYRS

*E

*F

2898663

2905460

03/24/2010

04/06/2010

NJY

Updated Ordering Information (Removed inactive parts from Ordering

Information table).

Updated Package Diagrams.

VKN

Updated Ordering Information (Removed inactive part numbers

CY7C1470BV25-167BZC, CY7C1470BV25-167BZI,

CY7C1470BV25-167BZXC, CY7C1470BV25-200BZC,

CY7C1472BV25-250BZC, CY7C1474BV25-167BGC,

CY7C1474BV25-167BGI, CY7C1474BV25-200BGC,

CY7C1474BV25-200BGI, CY7C1474BV25-200BGXI from the ordering

information table).

*G

3061663

10/15/2010

NJY

Updated Ordering Information (Removed pruned parts

CY7C1472BV25-200BZI, CY7C1472BV25-200BZIT from the ordering

information table) and added Ordering Code Definitions.

Updated Package Diagrams.

*H

*I

3207526

3257192

03/28/2011

05/14/2011

NJY

Updated Ordering Information (updated part numbers).

Updated Package Diagrams.

Updated in new template.

Updated Ordering Information (updated part numbers).

Added Acronyms and Units of Measure.

Document Number: 001-15032 Rev. *K

Page 27 of 29

CY7C1470BV25

CY7C1472BV25

Document History Page (continued)

Document Title: CY7C1470BV25/CY7C1472BV25, 72-Mbit (2 M × 36/4 M × 18) Pipelined SRAM with NoBL™ Architecture

Document Number: 001-15032

Orig. of

Change

Rev.

ECN No.

Issue Date

Description of Change

*J

3545503

03/08/2012 PRIT / NJY Updated Features (Removed CY7C1474BV25 related information).

Updated Functional Description (Removed CY7C1474BV25 related

information).

Removed Logic Block Diagram – CY7C1474BV25.

Updated Pin Configurations (Removed CY7C1474BV25 related information).

Updated Functional Overview (Removed CY7C1474BV25 related

information).

Updated Truth Table (Removed CY7C1474BV25 related information).

Updated Partial Write Cycle Description (Removed CY7C1474BV25 related

information).

Updated IEEE 1149.1 Serial Boundary Scan (JTAG) (Removed

CY7C1472BV25 and CY7C1474BV25 related information).

Updated Identification Register Definitions (Removed CY7C1472BV25 and

CY7C1474BV25 related information).

Updated Scan Register Sizes (Removed Bit Size (× 18) and Bit Size (× 72)

columns).

Removed “Boundary Scan Exit Order (4 M × 18)” and “Boundary Scan Exit

Order (1 M × 72)”.

Updated Capacitance (Removed 209-ball FBGA package related information).

Updated Thermal Resistance (Removed 209-ball FBGA package related

information).

Updated Ordering Information (Updated part numbers).

Updated Package Diagrams

Replaced IO with I/O in all instances across the document.

*K

3912915

02/25/2013

PRIT

Updated Ordering Information:

Added part number CY7C1470BV25-250AXI.

Document Number: 001-15032 Rev. *K

Page 28 of 29

CY7C1470BV25

CY7C1472BV25

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office

closest to you, visit us at Cypress Locations.

Products

Automotive

cypress.com/go/automotive

cypress.com/go/clocks

cypress.com/go/interface

cypress.com/go/powerpsoc

cypress.com/go/plc

PSoC Solutions

Clocks & Buffers

Interface

psoc.cypress.com/solutions

PSoC 1 | PSoC 3 | PSoC 5

Lighting & Power Control

Memory

cypress.com/go/memory

cypress.com/go/image

cypress.com/go/psoc

Optical & Image Sensing

PSoC

Touch Sensing

USB Controllers

Wireless/RF

cypress.com/go/touch

cypress.com/go/USB

cypress.com/go/wireless

any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for

medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as

critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems

application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),

United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,

and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress

integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without

the express written permission of Cypress.

Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES

OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not

assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where

a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer

assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

Document Number: 001-15032 Rev. *K

Revised February 25, 2013

Page 29 of 29

NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation. ZBT is a trademark of Integrated Device Technology, Inc. All products and company names mentioned in this

document may be the trademarks of their respective holders.


型号：	CY7C1470BV25_13
厂家：	CYPRESS
描述：	72-Mbit (2 M x 36/4 M x 18) Pipelined SRAM with NoBLâ¢ Architecture 72兆位（2M X 36/4的M× 18 ）流水线SRAM与NoBLâ ?? ¢架构静态存储器
文件：	总29页 (文件大小：935K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CY7C1470BV25_13 [CYPRESS]

相关型号：

CY7C1470BV33

CY7C1470BV33-167AXC

CY7C1470BV33-167AXCT

CY7C1470BV33-167AXI

CY7C1470BV33-167BZC

CY7C1470BV33-167BZCT

CY7C1470BV33-167BZI

CY7C1470BV33-167BZIT

CY7C1470BV33-167BZXC

CY7C1470BV33-167BZXI

CY7C1470BV33-200AXC

CY7C1470BV33-200AXI