CY7C145 [CYPRESS]
8K x 8/9 Dual-Port Static RAM with SEM, INT, BUSY; 8K X 8/9双口静态RAM与SEM ， INT ， BUSY
| 型号： | CY7C145 |
| 厂家： | 
CYPRESS |
| 描述： | 8K x 8/9 Dual-Port Static RAM with SEM, INT, BUSY |
| 文件： | 总20页 (文件大小：609K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C144 CY7C1458K
with SEM, INT, BUSY
x 8/9 Dual-Port Static RAM
CY7C144
CY7C145
8K x 8/9 Dual-Port Static RAM
with SEM, INT, BUSY
are included on the CY7C144/5 to handle situations when
multiple processors access the same piece of data. Two ports
are provided permitting independent, asynchronous access
for reads and writes to any location in memory. The
CY7C144/5 can be utilized as a standalone 64/72-Kbit
dual-port static RAM or multiple devices can be combined in
order to function as a 16/18-bit or wider master/slave dual-port
static RAM. An M/S pin is provided for implementing 16/18-bit
or wider memory applications without the need for separate
master and slave devices or additional discrete logic. Appli-
cation areas include interprocessor/multiprocessor designs,
Features
• TrueDual-Portedmemorycellsthatallowsimultaneous
reads of the same memory location
• 8K x 8 organization (CY7C144)
• 8K x 9 organization (CY7C145)
• 0.65-micron CMOS for optimum speed/power
• High-speed access: 15ns
• Low operating power: ICC = 160 mA (max.)
• Fully asynchronous operation
• Automatic power-down
communications
status
buffering,
and
dual-port
video/graphics memory.
Each port has independent control pins: chip enable (CE),
read or write enable (R/W), and output enable (OE). Two flags,
BUSY and INT, are provided on each port. BUSY signals that
the port is trying to access the same location currently being
accessed by the other port. The interrupt flag (INT) permits
communication between ports or systems by means of a mail
box. The semaphores are used to pass a flag, or token, from
one port to the other to indicate that a shared resource is in
use. The semaphore logic is comprised of eight shared
latches. Only one side can control the latch (semaphore) at
any time. Control of a semaphore indicates that a shared
resource is in use. An automatic power-down feature is
controlled independently on each port by a chip enable (CE)
pin or SEM pin.
• TTL compatible
• Master/Slave select pin allows bus width expansion to
16/18 bits or more
• Busy arbitration scheme provided
• Semaphores included to permit software handshaking
between ports
• INT flag for port-to-port communication
• Available in 68-pin PLCC, 64-pin and 80-pin TQFP
• Pb-Free packages available
Functional Description
The CY7C144 and CY7C145 are high-speed CMOS 8K x 8
and 8K x 9 dual-port static RAMs. Various arbitration schemes
Logic Block Diagram
R/W
L
R/W
R
CE
OE
CE
OE
L
L
R
R
(7C145) I/O
I/O (7C145)
8R
8L
I/O
7L
I/O
7R
I/O
CONTROL
I/O
CONTROL
I/O
0L
I/O
0R
[1, 2]
[1, 2]
BUSY
BUSY
L
R
A
12L
0L
A
A
12R
0R
MEMORY
ARRAY
ADDRESS
DECODER
ADDRESS
DECODER
A
INTERRUPT
SEMAPHORE
ARBITRATION
CE
L
CE
OE
R
R
OE
L
R/W
R/W
L
R
SEM
SEM
R
L
[2]
INT
INT [2]
R
L
M/S
Notes:
1. BUSY is an output in master mode and an input in slave mode.
2. Interrupt: push-pull output and requires no pull-up resistor.
Cypress Semiconductor Corporation
Document #: 38-06034 Rev. *C
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised September 6, 2005
CY7C144
CY7C145
Pin Configurations
68-Pin PLCC
Top View
9
8
7
6
5 4 3 2 1 68 6766 65 64 63 62 61
I/O
I/O
I/O
2L
3L
4L
A
10
11
12
13
14
15
16
17
18
19
20
60
59
58
57
56
55
54
53
52
51
50
49
48
5L
A
4L
A
3L
I/O
5L
A
2L
GND
I/O
A
1L
6L
A
0L
I/O
7L
INT
L
V
CC
BUSY
L
CY7C144/5
GND
GND
M/S
I/O
I/O
0R
1R
2R
BUSY
R
I/O
V
INT
21
22
23
24
25
26
R
A
0R
CC
I/O
3R
4R
5R
A
1R
47
46
45
44
I/O
I/O
I/O
A
2R
A
3R
6R
A
4R
2728 29 30 3132 33 34 35 36 37 38 39 40 41 42 43
64-Pin TQFP
Top View
I/O
I/O
A
48
47
2L
1
2
4L
A
A
3L
3L
4L
I/O
I/O
2L
46
45
3
4
A
A
1L
5L
GND
44
43
42
41
5
6
7
8
9
0L
I/O
6L
INT
L
I/O
7L
BUSY
L
GND
M/S
V
CC
CY7C144
GND
40
39
BUSY
I/O
0R
10
R
I/O
1R
38
37
36
INT
R
11
12
13
I/O
2R
A
0R
A
1R
A
2R
A
3R
V
CC
I/O
3R
35
34
14
15
I/O
4R
I/O
5R
33
A
4R
16
Notes:
3. I/O on the CY7C145.
8R
4. I/O on the CY7C145.
8L
Document #: 38-06034 Rev. *C
Page 2 of 20
CY7C144
CY7C145
Pin Configurations (continued)
80-Pin TQFP
Top View
NC
1
2
3
4
NC
60
59
58
57
/O
A
5L
2L
/O
/O
/O
A
4L
3L
4L
5L
A
3L
A
2L
5
6
7
8
56
55
54
53
A
1L
GND
/O
A
0L
6L
/O
7L
INT
L
BUSY
V
L
9
10
CC
52
51
GND
M/S
CY7C145
NC
GND
/O
11
12
13
14
50
49
48
47
BUSY
0R
R
/O
1R
INT
R
/O
2R
A
0R
V
A
1R
CC
15
16
46
45
O
A
2R
3R
O
A
3R
4R
17
44
O
A
5R
18
19
20
4R
43
42
41
O
6R
NC
NC
NC
Pin Definitions
Left Port Right Port
Description
I/O0L−7L(8L) I/O0R−7R(8R) Data bus Input/Output
A0L−12L
CEL
A0R−12R
CER
Address Lines
Chip Enable
OEL
OER
Output Enable
Read/Write Enable
R/WL
SEML
R/WR
SEMR
Semaphore Enable. When asserted LOW, allows access to eight semaphores. The three least signif-
icant bits of the address lines will determine which semaphore to write or read. The I/O0 pin is used
when writing to a semaphore. Semaphores are requested by writing a 0 into the respective location.
INTL
INTR
Interrupt Flag. INTL is set when right port writes location 1FFE and is cleared when left port reads
location 1FFE. INTR is set when left port writes location 1FFF and is cleared when right port reads
location 1FFF.
BUSYL
M/S
BUSYR
Busy Flag
Master or Slave Select
Power
VCC
GND
Ground
Selection Guide
7C144-15
7C145-15
7C144-25
7C145-25
7C144-35
7C145-35
7C144-55
7C145-55
Unit
ns
Maximum Access Time
15
220
60
25
180
40
35
160
30
55
160
30
Maximum Operating Current
Maximum Standby Current for ISB1
mA
mA
Document #: 38-06034 Rev. *C
Page 3 of 20
CY7C144
CY7C145
Maximum Ratings[5]
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage........................................... >2001V
(per MIL-STD-883, Method 3015)
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Latch-Up Current.................................................... >200 mA
Storage Temperature ..................................... −65°C to +150°C
Ambient Temperature with
Power Applied.................................................. −55°C to +125°C
Operating Range
Ambient
Supply Voltage to Ground Potential .................−0.5V to +7.0V
Range
Commercial
Industrial
Temperature
0°C to +70°C
−40°C to +85°C
VCC
DC Voltage Applied to Outputs
in High Z State .....................................................−0.5V to +7.0V
DC Input Voltage[6]..............................................−0.5V to +7.0V
5V ± 10%
5V ± 10%
Electrical Characteristics Over the Operating Range
7C144-15
7C145-15
7C144-25
7C145-25
Parameter
VOH
VOL
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Leakage Current
Output Leakage Current
Operating Current
Test Conditions
Min.
Max.
Min. Max.
Unit
V
VCC = Min., IOH = −4.0 mA
2.4
2.4
VCC = Min., IOL = 4.0 mA
0.4
0.4
V
VIH
2.2
2.2
V
VIL
0.8
+10
+10
220
0.8
+10
+10
180
190
40
V
IIX
GND < VI < VCC
−10
−10
−10
−10
µA
µA
mA
IOZ
Outputs Disabled, GND < VO < VCC
ICC
VCC = Max., IOUT = 0 mA
Outputs Disabled
Com’l
Ind
ISB1
ISB2
ISB3
Standby Current
(Both Ports TTL Levels)
CEL and CER > VIH,
Com’l
Ind
60
130
15
mA
mA
mA
[7]
f = fMAX
50
Standby Current
(One Port TTL Level)
CEL or CER > VIH,
Com’l
Ind
110
120
15
[7]
f = fMAX
Standby Current
(Both Ports CMOS Levels) CE and CER > VCC – 0.2V,
Both Ports
Com’l
Ind
30
V
IN > VCC – 0.2V
or VIN < 0.2V, f = 0[7]
ISB4
Standby Current
(One Port CMOS Level)
One Port
CEL or CER > VCC – 0.2V,
Com’l
Ind
125
100
115
mA
VIN > VCC – 0.2V or
VIN < 0.2V, Active
Port Outputs, f = fMAX
[7]
Notes:
5. The Voltage on any input or I/O pin cannot exceed the power pin during power-up.
6. Pulse width < 20 ns.
7. f
= 1/t = All inputs cycling at f = 1/t (except output enable). f = 0 means no address or control lines change. This applies only to inputs at CMOS level
MAX
RC RC
standby I
.
SB3
Document #: 38-06034 Rev. *C
Page 4 of 20
CY7C144
CY7C145
Electrical Characteristics Over the Operating Range (continued)
7C144-35
7C145-35
7C144-55
7C145-55
Parameter
VOH
VOL
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Leakage Current
Output Leakage Current
Operating Current
Test Conditions
VCC = Min., IOH = −4.0 mA
VCC = Min., IOL = 4.0 mA
Min.
Max.
Min.
Max.
Unit
V
2.4
2.4
0.4
0.4
V
VIH
2.2
2.2
V
VIL
0.8
+10
+10
160
180
30
0.8
+10
+10
160
180
30
V
IIX
GND < VI < VCC
−10
−10
−10
−10
µA
µA
mA
IOZ
Outputs Disabled, GND < VO < VCC
ICC
VCC = Max., IOUT = 0 mA
Outputs Disabled
Com’l
Ind
ISB1
ISB2
ISB3
Standby Current
(Both Ports TTL Levels)
CEL and CER > VIH,
Com’l
Ind
mA
mA
mA
[7]
f = fMAX
40
40
Standby Current
(One Port TTL Level)
CEL or CER > VIH,
Com’l
Ind
100
110
15
100
110
15
[7]
f = fMAX
Standby Current
(Both Ports CMOS Levels) CE and CER > VCC – 0.2V,
Both Ports
Com’l
Ind
30
30
V
IN > VCC – 0.2V
or VIN < 0.2V, f = 0[7]
ISB4
Standby Current
(One Port CMOS Level)
One Port
CEL or CER > VCC – 0.2V,
VIN > VCC – 0.2V or
Com’l
Ind
90
90
mA
100
100
V
IN < 0.2V, Active
[7]
Port Outputs, f = fMAX
Capacitance[8]
Parameter
Description
Test Conditions
Max.
Unit
CIN
Input Capacitance
Output Capacitance
TA = 25°C, f = 1 MHz,
10
15
pF
pF
V
CC = 5.0V
COUT
Note:
8. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-06034 Rev. *C
Page 5 of 20
CY7C144
CY7C145
AC Test Loads and Waveforms
5V
5V
R1 = 893Ω
R1 = 893Ω
R
TH
= 250Ω
OUTPUT
OUTPUT
C = 30pF
OUTPUT
C = 5 pF
C = 30 pF
R = 347Ω
R2 = 347Ω
V
TH
= 1.4V
(a) Normal Load (Load1)
(b) Thévenin Equivalent (Load 1)
(c) Three-State Delay (Load 3)
ALL INPUT PULSES
OUTPUT
3.0V
GND
90%
90%
10%
10%
C = 30 pF
≤ 3 ns
≤ 3 ns
Load (Load 2)
Switching Characteristics Over the Operating Range[9]
7C144-15
7C145-15
7C144-25
7C145-25
7C144-35
7C145-35
7C144-55
7C145-55
Parameter
Description
Min.
15
3
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
25
3
35
3
55
3
ns
ns
ns
tAA
Address to Data Valid
15
25
35
55
tOHA
Output Hold From Address
Change
tACE
tDOE
CE LOW to Data Valid
OE LOW to Data Valid
OE Low to Low Z
15
10
25
15
35
20
55
25
ns
ns
ns
ns
ns
ns
ns
ns
[10, 11,12]
tLZOE
3
3
0
3
3
0
3
3
0
3
3
0
[10, 11,12]
tHZOE
OE HIGH to High Z
CE LOW to Low Z
10
10
15
15
15
25
20
20
35
25
25
55
[10, 11,12]
tLZCE
[10, 11,12]
tHZCE
CE HIGH to High Z
CE LOW to Power-Up
CE HIGH to Power-Down
[12]
tPU
[12]
tPD
WRITE CYCLE
tWC
tSCE
tAW
tHA
Write Cycle Time
15
12
12
2
25
20
20
2
35
30
30
2
55
45
45
2
ns
ns
ns
ns
ns
ns
CE LOW to Write End
Address Set-Up to Write End
Address Hold From Write End
Address Set-Up to Write Start
Write Pulse Width
tSA
0
0
0
0
tPWE
12
20
25
40
Notes:
9. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
/I and 30-pF load capacitance.
OI OH
10. At any given temperature and voltage condition for any given device, t
is less than t
and t
is less than t
.
LZOE
HZCE
LZCE
HZOE
11. Test conditions used are Load 3.
12. This parameter is guaranteed but not tested.
Document #: 38-06034 Rev. *C
Page 6 of 20
CY7C144
CY7C145
Switching Characteristics Over the Operating Range[9] (continued)
7C144-15
7C145-15
7C144-25
7C145-25
7C144-35
7C145-35
7C144-55
7C145-55
Parameter
tSD
Description
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
ns
Data Set-Up to Write End
Data Hold From Write End
R/W LOW to High Z
10
0
15
0
15
0
25
0
tHD
ns
[11,12]
[11,12]
tHZWE
10
15
20
25
ns
tLZWE
R/W HIGH to Low Z
3
3
3
3
ns
[13]
tWDD
Write Pulse to Data Delay
30
25
50
30
60
35
70
40
ns
[13]
tDDD
Write Data Valid to Read Data
Valid
ns
BUSY TIMING[14]
tBLA BUSY LOW from Address
15
15
20
20
20
20
30
30
ns
ns
Match
tBHA
BUSY HIGH from Address
Mismatch
tBLC
tBHC
tPS
BUSY LOW from CE LOW
BUSY HIGH from CE HIGH
Port Set-Up for Priority
15
15
20
20
20
20
30
30
ns
ns
ns
ns
ns
ns
5
0
5
0
5
0
5
0
tWB
tWH
tBDD
R/W LOW after BUSY LOW
R/W HIGH after BUSY HIGH
BUSY HIGH to Data Valid
13
20
30
30
15
25
35
55
INTERRUPT TIMING[14]
tINS INT Set Time
tINR INT Reset Time
SEMAPHORE TIMING
15
15
25
25
25
25
35
35
ns
ns
tSOP
SEM Flag Update Pulse (OE
or SEM)
10
10
15
20
ns
tSWRD
tSPS
SEM Flag Write to Read Time
5
5
5
5
5
5
5
5
ns
ns
SEM Flag Contention
Window
Notes:
13. For information on part-to-part delay through RAM cells from writing port to reading port, refer to Read Timing with Port-to-Port Delay waveform.
14. Test conditions used are Load 2.
Document #: 38-06034 Rev. *C
Page 7 of 20
CY7C144
CY7C145
Switching Waveforms
Read Cycle No. 1 (Either Port Address Access)[15, 16]
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Read Cycle No. 2 (Either Port CE/OE Access)[15, 17, 18]
SEM or CE
t
HZCE
t
ACE
OE
t
HZOE
t
DOE
t
LZOE
t
LZCE
DATA VALID
DATA OUT
t
PU
t
PD
I
CC
I
SB
Read Timing with Port-to-Port Delay (M/S=L)[19, 20]
t
WC
ADDRESS
R
MATCH
t
PWE
R/W
R
t
t
SD
HD
DATAIN
VALID
R
ADDRESS
L
MATCH
t
DDD
DATA
VALID
OUTL
t
WDD
Notes:
15. R/W is HIGH for read cycle.
16. Device is continuously selected CE = LOW and OE = LOW. This waveform cannot be used for semaphore reads.
17.Address valid prior to or coincident with CE transition LOW.
18. CE = L, SEM = H when accessing RAM. CE = H, SEM = L when accessing semaphores.
L
19. BUSY = HIGH for the writing port.
20. CE = CE = LOW.
L
R
Document #: 38-06034 Rev. *C
Page 8 of 20
CY7C144
CY7C145
Switching Waveforms (continued)
Write Cycle No. 1: OE Three-State Data I/Os (Either Port)[21, 22, 23]
t
WC
ADDRESS
t
SCE
SEM OR CE
t
t
HA
AW
t
PWE
R/W
t
SA
t
t
HD
SD
DATA IN
DATA VALID
OE
t
t
HZOE
LZOE
HIGH IMPEDANCE
DATA OUT
Write Cycle No. 2: R/W Three-State Data I/Os (Either Port)[21, 23, 24]
t
WC
ADDRESS
t
t
HA
SCE
SEM OR CE
R/W
t
AW
t
SA
t
PWE
t
t
HD
SD
DATAVALID
DATA IN
t
t
LZWE
HZWE
HIGH IMPEDANCE
DATA OUT
Notes:
21.The internal write time of the memory is defined by the overlap of CE or SEM LOW and R/W LOW. Both signals must be LOW to initiate a write, and either signal
can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
22.If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of t
or (t
+ t ) to allow the I/O drivers to turn off and data to
PWE
HZWE SD
be placed on the bus for the required t . If OE is HIGH during a R/W controlled write cycle (as in this example), this requirement does not apply and the write
SD
pulse can be as short as the specified t
.
PWE
23. R/W must be HIGH during all address transitions.
24.Data I/O pins enter high impedance when OE is held LOW during write.
Document #: 38-06034 Rev. *C
Page 9 of 20
CY7C144
CY7C145
Switching Waveforms (continued)
Semaphore Read After Write Timing, Either Side[25]
t
AA
t
OHA
A −A
0
VALID ADDRESS
VALID ADDRESS
2
t
AW
t
ACE
t
HA
SEM
t
t
SOP
SCE
t
SD
I/O
0
DATA VALID
DATA
VALID
IN
OUT
t
HD
t
t
PWE
SA
R/W
OE
t
t
DOE
SWRD
t
SOP
WRITE CYCLE
READ CYCLE
Semaphore Contention[26, 27, 28]
A −A
0L 2L
MATCH
R/W
L
SEM
L
t
SPS
A −A
0R 2R
MATCH
R/W
R
SEM
R
Notes:
25. CE = HIGH for the duration of the above timing (both write and read cycle).
26. I/O = I/O = LOW (request semaphore); CE = CE = HIGH
0R
0L
R
L
27. Semaphores are reset (available to both ports) at cycle start.
28.If t is violated, the semaphore will definitely be obtained by one side or the other, but there is no guarantee which side will control the semaphore.
SPS
Document #: 38-06034 Rev. *C
Page 10 of 20
CY7C144
CY7C145
Switching Waveforms (continued)
Read with BUSY (M/S=HIGH)[20]
t
WC
ADDRESS
R
MATCH
t
PWE
R/W
R
t
t
HD
SD
DATAIN
VALID
R
t
PS
ADDRESS
L
MATCH
t
BLA
t
BHA
BUSY
L
t
BDD
t
DDD
DATA
VALID
OUTL
t
WDD
Write Timing with Busy Input (M/S=LOW)
t
PWE
R/W
t
t
WH
WB
BUSY
Document #: 38-06034 Rev. *C
Page 11 of 20
CY7C144
CY7C145
Switching Waveforms (continued)
Busy Timing Diagram No. 1 (CE Arbitration)[29]
CEL Valid First:
ADDRESSL,R
ADDRESS MATCH
CE
L
t
PS
CE
R
t
t
BHC
BLC
BUSY
R
CER Valid First:
ADDRESSL,R
ADDRESS MATCH
CE
R
t
PS
CE
L
t
t
BHC
BLC
BUSY
L
Busy Timing Diagram No. 2 (Address Arbitration)[29]
Left Address Valid First:
t
or t
WC
RC
ADDRESS
L
ADDRESS MATCH
ADDRESS MISMATCH
t
PS
ADDRESS
BUSY
R
R
t
t
BHA
BLA
Right Address Valid First:
t
or t
WC
RC
ADDRESS
R
ADDRESS MATCH
ADDRESS MISMATCH
t
PS
ADDRESS
L
t
t
BHA
BLA
BUSY
L
Note:
29.If t is violated, the busy signal will be asserted on one side or the other, but there is no guarantee on which side BUSY will be asserted
PS
Document #: 38-06034 Rev. *C
Page 12 of 20
CY7C144
CY7C145
Switching Waveforms (continued)
Interrupt Timing Diagrams
Left Side Sets INTR:
t
WC
ADDRESS
CE
WRITE 1FFF
L
L
[30]
t
HA
R/W
INT
L
R
[31]
t
INS
Right Side Clears INTR:
t
RC
ADDRESS
READ 1FFF
R
CE
R
[31]
t
INR
R/W
OE
R
R
INT
R
Right Side Sets INTL:
t
WC
ADDRESS
WRITE 1FFE
R
[30]
t
HA
CE
R
R
R/W
INT
L
[31]
t
INS
Left Side Clears INTL:
t
RC
ADDRESS
READ 1FFE
R
CE
L
[31]
t
INR
R/W
L
OE
L
INT
L
Notes:
30. t depends on which enable pin (CE or R/W ) is deasserted first.
HA
L
L
31. t
or t
depends on which enable pin (CE or R/W ) is asserted last.
INS
INR L L
Document #: 38-06034 Rev. *C
Page 13 of 20
CY7C144
CY7C145
Master/Slave
Architecture
An M/S pin is provided in order to expand the word width by
configuring the device as either a master or a slave. The BUSY
output of the master is connected to the BUSY input of the
slave. This will allow the device to interface to a master device
with no external components.Writing of slave devices must be
delayed until after the BUSY input has settled. Otherwise, the
slave chip may begin a write cycle during a contention
situation.When presented a HIGH input, the M/S pin allows the
device to be used as a master and therefore the BUSY line is
an output. BUSY can then be used to send the arbitration
outcome to a slave.
The CY7C144/5 consists of a an array of 8K words of 8/9 bits
each of dual-port RAM cells, I/O and address lines, and control
signals (CE, OE, R/W). These control pins permit independent
access for reads or writes to any location in memory. To handle
simultaneous writes/reads to the same location, a BUSY pin is
provided on each port. Two interrupt (INT) pins can be utilized
for port-to-port communication. Two semaphore (SEM) control
pins are used for allocating shared resources. With the M/S
pin, the CY7C144/5 can function as a Master (BUSY pins are
outputs) or as a slave (BUSY pins are inputs). The CY7C144/5
has an automatic power-down feature controlled by CE. Each
port is provided with its own output enable control (OE), which
allows data to be read from the device.
Semaphore Operation
The CY7C144/5 provides eight semaphore latches which are
separate from the dual-port memory locations. Semaphores
are used to reserve resources that are shared between the two
ports.The state of the semaphore indicates that a resource is
in use. For example, if the left port wants to request a given
resource, it sets a latch by writing a 0 to a semaphore location.
The left port then verifies its success in setting the latch by
reading it. After writing to the semaphore, SEM or OE must be
deasserted for tSOP before attempting to read the semaphore.
The semaphore value will be available tSWRD + tDOE after the
rising edge of the semaphore write. If the left port was
successful (reads a 0), it assumes control over the shared
resource, otherwise (reads a 1) it assumes the right port has
control and continues to poll the semaphore.When the right
side has relinquished control of the semaphore (by writing a
1), the left side will succeed in gaining control of the
semaphore. If the left side no longer requires the semaphore,
a 1 is written to cancel its request.
Functional Description
Write Operation
Data must be set up for a duration of tSD before the rising edge
of R/W in order to guarantee a valid write. A write operation is
controlled by either the OE pin (see Write Cycle No.1
waveform) or the R/W pin (see Write Cycle No. 2 waveform).
Data can be written to the device tHZOE after the OE is
deasserted or tHZWE after the falling edge of R/W. Required
inputs for non-contention operations are summarized in
Table 1.
If a location is being written to by one port and the opposite
port attempts to read that location, a port-to-port flowthrough
delay must be met before the data is read on the output;
otherwise the data read is not deterministic. Data will be valid
on the port tDDD after the data is presented on the other port.
Semaphores are accessed by asserting SEM LOW. The SEM
pin functions as a chip enable for the semaphore latches (CE
must remain HIGH during SEM LOW). A0–2 represents the
semaphore address. OE and R/W are used in the same
manner as a normal memory access.When writing or reading
a semaphore, the other address pins have no effect.
Read Operation
When reading the device, the user must assert both the OE
and CE pins. Data will be available tACE after CE or tDOE after
OE are asserted. If the user of the CY7C144/5 wishes to
access a semaphore flag, then the SEM pin must be asserted
instead of the CE pin.
When writing to the semaphore, only I/O0 is used. If a 0 is
written to the left port of an unused semaphore, a 1 will appear
at the same semaphore address on the right port. That
semaphore can now only be modified by the side showing 0
(the left port in this case). If the left port now relinquishes
control by writing a 1 to the semaphore, the semaphore will be
set to 1 for both sides. However, if the right port had requested
the semaphore (written a 0) while the left port had control, the
right port would immediately own the semaphore as soon as
the left port released it. Table 3 shows sample semaphore
operations.
Interrupts
The interrupt flag (INT) permits communications between
ports.When the left port writes to location 1FFF, the right port’s
interrupt flag (INTR) is set. This flag is cleared when the right
port reads that same location. Setting the left port’s interrupt
flag (INTL) is accomplished when the right port writes to
location 1FFE. This flag is cleared when the left port reads
location 1FFE. The message at 1FFF or 1FFE is user-defined.
See Table 2 for input requirements for INT. INTR and INTL are
push-pull outputs and do not require pull-up resistors to
operate.
When reading a semaphore, all eight/nine data lines output the
semaphore value. The read value is latched in an output
register to prevent the semaphore from changing state during
a write from the other port. If both ports attempt to access the
semaphore within tSPS of each other, the semaphore will
definitely be obtained by one side or the other, but there is no
guarantee which side will control the semaphore.
Busy
The CY7C144/5 provides on-chip arbitration to alleviate simul-
taneous memory location access (contention). If both ports’
CEs are asserted and an address match occurs within tPS of
each other the Busy logic will determine which port has
access. If tPS is violated, one port will definitely gain
permission to the location, but it is not guaranteed which one.
BUSY will be asserted tBLA after an address match or tBLC
after CE is taken LOW. BUSYL and BUSYR in master mode
are push-pull outputs and do not require pull-up resistors to
operate.
Initialization of the semaphore is not automatic and must be
reset during initialization program at power-up. All
Semaphores on both sides should have a one written into
them at initialization from both sides to assure that they will be
free when needed.
Document #: 38-06034 Rev. *C
Page 14 of 20
CY7C144
CY7C145
Table 1. Non-Contending Read/Write
Inputs
Outputs
I/O0−7/8
CE
H
R/W
X
OE
X
SEM
Operation
H
L
High Z
Power-Down
H
H
L
Data Out
High Z
Read Data in Semaphore
I/O Lines Disabled
X
X
H
X
L
H
X
Data In
Write to Semaphore
L
L
L
H
L
L
X
X
H
H
L
Data Out
Data In
Read
Write
X
Illegal Condition
Table 2. Interrupt Operation Example (assumes BUSYL = BUSYR = HIGH)
Left Port
Right Port
OE
Function
R/W
X
CE
X
OE
X
A0−12
X
INT
L
R/W
L
CE
L
A0−12
1FFE
X
INT
X
Set Left INT
X
L
X
L
Reset Left INT
Set Right INT
Reset Right INT
X
L
L
1FFE
1FFF
X
H
X
L
X
L
L
X
X
X
X
X
L
X
X
X
X
X
L
1FFF
H
Table 3. Semaphore Operation Example
Function
No action
I/O0-7/8 Left
I/O0-7/8 Right
Status
1
0
0
1
1
0
1
1
1
0
1
1
1
1
0
0
1
1
0
1
1
1
Semaphore free
Left port writes semaphore
Right port writes 0 to semaphore
Left port writes 1 to semaphore
Left port writes 0 to semaphore
Right port writes 1 to semaphore
Left port writes 1 to semaphore
Right port writes 0 to semaphore
Right port writes 1 to semaphore
Left port writes 0 to semaphore
Left port writes 1 to semaphore
Left port obtains semaphore
Right side is denied access
Right port is granted access to semaphore
No change. Left port is denied access
Left port obtains semaphore
No port accessing semaphore address
Right port obtains semaphore
No port accessing semaphore
Left port obtains semaphore
No port accessing semaphore
Document #: 38-06034 Rev. *C
Page 15 of 20
CY7C144
CY7C145
Typical DC and AC Characteristics
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
OUTPUT SOURCE CURRENT
vs. OUTPUT VOLTAGE
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
200
160
120
80
1.4
1.2
1.0
0.8
1.2
ICC
1.0
ICC
ISB3
0.8
0.6
0.4
ISB3
VCC = 5.0V
TA = 25°C
VCC = 5.0V
VIN = 5.0V
0.6
0.4
40
0
0.2
0.6
0.2
0.0
5.0
−55
25
125
0
1.0
2.0
3.0
4.0
4.0
4.5
5.0
5.5
6.0
AMBIENT TEMPERATURE (°C)
OUTPUT VOLTAGE (V)
SUPPLY VOLTAGE (V)
NORMALIZED ACCESS TIME
vs. AMBIENT TEMPERATURE
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
NORMALIZED ACCESS TIME
vs. SUPPLY VOLTAGE
140
120
1.6
1.4
1.4
1.3
1.2
1.1
100
80
1.2
1.0
60
TA = 25°C
VCC = 5.0V
1.0
40
0.8
V
CC = 5.0V
20
0
0.9
0.8
TA = 25°C
0.6
−55
0.0
1.0
2.0
3.0
4.0
25
125
5.0
4.0
4.5
5.0
5.5
6.0
AMBIENT TEMPERATURE (°C)
OUTPUT VOLTAGE (V)
SUPPLY VOLTAGE (V)
TYPICAL POWER-ON CURRENT
vs. SUPPLY VOLTAGE
TYPICAL ACCESS TIME CHANGE
vs. OUTPUT LOADING
NORMALIZED ICC vs. CYCLE TIME
1.25
30.0
25.0
1.00
V
CC = 5.0V
TA = 25°C
IN = 5.0V
V
0.75
0.50
1.0
20.0
15.0
10.0
0.75
0.25
0.0
VCC = 4.5V
TA = 25°C
5.0
0
0.50
40
CYCLE FREQUENCY (MHz)
10
28
66
0
1.0
2.0
3.0
4.0 5.0
0
200 400 600 800 1000
CAPACITANCE (pF)
SUPPLY VOLTAGE (V)
Document #: 38-06034 Rev. *C
Page 16 of 20
CY7C144
CY7C145
Ordering Information
8K x8 Dual-Port SRAM
Speed
(ns)
Package
Name
Operating
Range
Ordering Code
Package Type
15
CY7C144-15AC
CY7C144-15AXC
CY7C144-15JC
CY7C144-15JXC
CY7C144-15AI
CY7C144-15AXI
CY7C144-25AC
CY7C144-25AXC
CY7C144-25JC
CY7C144-25AI
CY7C144-25JI
CY7C144-35AC
CY7C144-35JC
CY7C144-35AI
CY7C144-35JI
CY7C144-55AC
CY7C144-55AXC
CY7C144-55JC
CY7C144-55JXC
CY7C144-55AI
CY7C144-55JI
A65
A65
J81
J81
A65
A65
A65
A65
J81
A65
J81
A65
J81
A65
J81
A65
A65
J81
J81
A65
J81
64-Lead Thin Quad Flat Pack
Commercial
64-Lead Pb-Free Thin Quad Flat Pack
68-Lead Plastic Leaded Chip Carrier
68-Lead Pb-Free Plastic Leaded Chip Carrier
64-Lead Thin Quad Flat Pack
Industrial
64-Lead Pb-Free Thin Quad Flat Pack
64-Lead Thin Quad Flat Pack
25
Commercial
64-Lead Pb-Free Thin Quad Flat Pack
68-Lead Plastic Leaded Chip Carrier
64-Lead Thin Quad Flat Pack
Industrial
68-Lead Plastic Leaded Chip Carrier
64-Lead Thin Quad Flat Pack
35
55
Commercial
Industrial
68-Lead Plastic Leaded Chip Carrier
64-Lead Thin Quad Flat Pack
68-Lead Plastic Leaded Chip Carrier
64-Lead Thin Quad Flat Pack
Commercial
64-Lead Pb-Free Thin Quad Flat Pack
68-Lead Plastic Leaded Chip Carrier
68-Lead Pb-Free Plastic Leaded Chip Carrier
64-Lead Thin Quad Flat Pack
Industrial
68-Lead Plastic Leaded Chip Carrier
8K x9 Dual-Port SRAM
Speed
Package
Name
Operating
Range
(ns)
Ordering Code
Package Type
80-Lead Thin Quad Flat Pack
15
CY7C145-15AC
CY7C145-15AXC
CY7C145-15JC
CY7C145-25AC
CY7C145-25JC
CY7C145-25AI
CY7C145-25JI
CY7C145-35AC
CY7C145-35JC
CY7C145-35JXC
CY7C145-35AI
CY7C145-35JI
CY7C145-55AC
CY7C145-55JC
CY7C145-55AI
CY7C145-55JI
A80
A80
J81
A80
J81
A80
J81
A80
J81
J81
A80
J81
A80
J81
A80
J81
Commercial
80-Lead Pb-Free Thin Quad Flat Pack
68-Lead Plastic Leaded Chip Carrier
80-Lead Thin Quad Flat Pack
25
35
Commercial
Industrial
68-Lead Plastic Leaded Chip Carrier
80-Lead Thin Quad Flat Pack
68-Lead Plastic Leaded Chip Carrier
80-Lead Thin Quad Flat Pack
Commercial
68-Lead Plastic Leaded Chip Carrier
68-Lead Pb-Free Plastic Leaded Chip Carrier
80-Lead Thin Quad Flat Pack
Industrial
68-Lead Plastic Leaded Chip Carrier
80-Lead Thin Quad Flat Pack
55
Commercial
Industrial
68-Lead Plastic Leaded Chip Carrier
80-Lead Thin Quad Flat Pack
68-Lead Plastic Leaded Chip Carrier
Document #: 38-06034 Rev. *C
Page 17 of 20
CY7C144
CY7C145
Package Diagrams
64-Lead Thin Plastic Quad Flat Pack (14 x 14 x 1.4 mm) A65
64-Lead Pb-Free Thin Plastic Quad Flat Pack (14 x 14 x 1.4 mm) A65
51-85046-*B
Document #: 38-06034 Rev. *C
Page 18 of 20
CY7C144
CY7C145
Package Diagrams (continued)
80-Pin Thin Plastic Quad Flat Pack A80
80-Pin Pb-Free Thin Plastic Quad Flat Pack A80
51-85065-*B
68-Lead Plastic Leaded Chip Carrier J81
68-Lead Pb-Free Plastic Leaded Chip Carrier J81
51-85005-*A
All products and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-06034 Rev. *C
Page 19 of 20
© Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY7C144
CY7C145
Document History Page
Document Title: CY7C145, CY7C144 8K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
Document Number: 38-06034
Issue
Orig. of
Change
REV.
**
ECN NO. Date
Description of Change
110175
122285
236752
09/29/01
SZV
RBI
Change from Spec number: 38-00163 to 38-06034
*A
*B
12/27/02
See ECN
Power up requirements added to Maximum Ratings Information
YDT
Removed cross information from features section, added CY7C144-15AI to
ordering information section
*C
393320
See ECN
YIM
Added Pb-Free Logo
Added Pb-Free parts to ordering information:
CY7C144-15AXC, CY7C144-15JXC, CY7C144-15AXI, CY7C144-25AXC,
CY7C144-55AXC, CY7C144-55JXC, CY7C145-15AXC, CY7C145-35JXC
Document #: 38-06034 Rev. *C
Page 20 of 20
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