CY7C145-35JI [CYPRESS]
8K x 8/9 Dual-Port Static RAM with Sem, Int, Busy; 8K X 8/9双口静态RAM与SEM ， INT ， BUSY
| 型号： | CY7C145-35JI |
| 厂家： | 
CYPRESS |
| 描述： | 8K x 8/9 Dual-Port Static RAM with Sem, Int, Busy |
| 文件： | 总19页 (文件大小：391K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
1CY7C144
fax id: 5205
CY7C145
CY7C144
8K x 8/9 Dual-Port Static RAM
with Sem, Int, Busy
are included on the CY7C144/5 to handle situations when mul-
tiple processors access the same piece of data. Two ports are
provided permitting independent, asynchronous access for
reads and writes to any location in memory. The CY7C144/5
can be utilized as a standalone 64/72-Kbit dual-port static
RAM or multiple devices can be combined in order to function
as a 16/18-bit or wider master/slave dual-port static RAM. An
M/S pin is provided for implementing 16/18-bit or wider mem-
ory applications without the need for separate master and
slave devices or additional discrete logic. Application areas
include interprocessor/multiprocessor designs, communica-
tions status buffering, and dual-port video/graphics memory.
Features
• True Dual-Ported memory cells which allow
simultaneous reads of the same memory location
• 8K x 8 organization (CY7C144)
• 8K x 9 organization (CY7C145)
• 0.65-micron CMOS for optimum speed/power
• High-speed access: 15ns
• Low operating power: I = 160 mA (max.)
CC
• Fully asynchronous operation
• Automatic power-down
• TTL compatible
• Master/Slave select pin allows bus width expansion to
16/18 bits or more
• Busy arbitration scheme provided
• Semaphores included to permit software handshaking
between ports
• INT flag for port-to-port communication
• Available in 68-pin PLCC, 64-pin and 80-pin TQFP
• Pin compatible and functionally equivalent to
IDT7005/IDT7015
Each port has independent control pins: chip enable (CE),
read or write enable (R/W), and output enable (OE). Two flags,
BUSYand INT, are provided on each port. BUSY signals that the port
is trying to access the same location currently being accessed by the
other port. The interrupt flag (INT) permits communication between
ports or systems by means of a mail box. The semaphores are used
to pass a flag, or token, from one port to the other to indicate that a
shared resource is in use. The semaphore logic is comprised of eight
shared latches. Only one side can control the latch (semaphore) at
any time. Control of a semaphore indicates that a shared resource is
in use. An automatic power-down feature is controlled independently
on each port by a chip enable (CE) pin or SEM pin.
Functional Description
The CY7C144 and CY7C145 are high-speed CMOS 8K x 8
and 8K x 9 dual-port static RAMs. Various arbitration schemes
Logic Block Diagram
R/W
L
R/W
R
CE
OE
CE
OE
L
L
R
R
(7C145) I/O
I/O (7C145)
8R
8L
I/O
7L
I/O
7R
I/O
CONTROL
I/O
CONTROL
I/O
0L
I/O
0R
[1, 2]
[1, 2]
BUSY
BUSY
L
R
A
12L
0L
A
A
12R
0R
MEMORY
ARRAY
ADDRESS
DECODER
ADDRESS
DECODER
A
INTERRUPT
SEMAPHORE
ARBITRATION
CE
L
CE
OE
R
R
OE
L
R/W
R/W
L
R
SEM
L
SEM
L
R
[2]
[2]
INT
INT
R
C144-1
M/S
Notes:
1. BUSY is an output in master mode and an input in slave mode.
2. Interrupt: push-pull output and requires no pull-up resistor.
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
November 1996
CY7C145
CY7C144
Pin Configurations
68-Pin PLCC
Top View
9
8
7
6
5 4 3 2 1 68 6766 65 64 63 62 61
I/O
I/O
I/O
I/O
2L
3L
4L
5L
A
A
A
10
11
12
13
14
15
16
17
18
19
20
60
59
58
57
56
55
54
53
52
51
50
49
48
5L
4L
3L
A
A
A
2L
GND
1L
I/O
6L
I/O
7L
0L
INT
L
V
CC
BUSY
L
CY7C144/5
GND
GND
M/S
I/O
I/O
I/O
V
0R
1R
2R
BUSY
R
INT
21
22
23
24
25
26
R
A
0R
CC
I/O
3R
4R
5R
6R
A
A
47
46
45
44
1R
I/O
I/O
I/O
2R
A
3R
A
4R
2728 29 30 3132 33 34 35 36 37 38 39 40 41 42 43
C144-2
64-Pin TQFP
Top View
I/O
A
48
47
2L
1
2
4L
A
A
I/O
3L
I/O
4L
I/O
5L
3L
2L
46
45
3
4
A
A
1L
GND
44
43
42
41
5
6
7
8
9
0L
I/O
6L
INT
L
I/O
7L
BUSY
L
GND
M/S
V
CC
CY7C144
GND
40
39
BUSY
I/O
0R
10
R
I/O
1R
38
37
36
INT
R
11
12
13
I/O
2R
A
0R
A
1R
A
2R
A
3R
V
CC
I/O
3R
35
34
14
15
I/O
4R
I/O
5R
33
A
4R
16
C144-3
Notes:
3. I/O8R on the CY7C145.
4. I/O8L on the CY7C145.
2
CY7C145
CY7C144
Pin Configurations (continued)
80-Pin TQFP
Top View
NC
1
2
NC
60
59
I/O
A
5L
2L
I/O
I/O
I/O
A
4L
3
4
3L
4L
5L
58
57
A
A
3L
2L
5
6
7
8
56
55
54
53
A
A
GND
I/O
1L
0L
6L
I/O
7L
INT
L
BUSY
V
L
9
10
CC
52
51
GND
M/S
CY7C145
NC
GND
I/O
11
12
13
14
50
49
48
47
BUSY
0R
R
I/O
1R
INT
R
I/O
2R
A
0R
A
1R
A
2R
A
3R
V
CC
15
16
46
45
I/O
3R
I/O
4R
17
44
I/O
5R
A
18
19
20
4R
43
42
41
I/O
6R
NC
NC
NC
C144-4
Pin Definitions
Left Port
Right Port
Description
I/O
I/O
Data bus Input/Output
Address Lines
0L−7L(8L)
0R−7R(8R)
A
0R−12R
A
0L−12L
CE
CE
Chip Enable
L
R
OE
OE
Output Enable
L
R
R/W
R/W
Read/Write Enable
L
R
SEM
SEM
Semaphore Enable. When asserted LOW, allows access to eight sema-
phores. The three least significant bits of the address lines will determine
L
R
which semaphore to write or read. The I/O pin is used when writing to a
0
semaphore. Semaphores are requested by writing a 0 into the respective
location.
INT
INT
Interrupt Flag. INT is set when right port writes location 1FFE and is
L
L
R
cleared when left port reads location 1FFE. INT is set when left port writes
R
location 1FFF and is cleared when right port reads location 1FFF.
BUSY
M/S
BUSY
Busy Flag
L
R
Master or Slave Select
Power
V
CC
GND
Ground
3
CY7C145
CY7C144
Selection Guide
7C144-15
7C145-15
7C144-25
7C145-25
7C144-35
7C145-35
7C144-55
7C145-55
Maximum Access Time (ns)
15
25
35
55
Maximum Operating
Current (mA)
220
180
160
160
Maximum Standby
60
40
30
30
Current for I
(mA)
SB1
Output Current into Outputs (LOW)............................. 20 mA
Maximum Ratings
Static Discharge Voltage .......................................... >2001V
(per MIL-STD-883, Method 3015)
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Latch-Up Current.................................................... >200 mA
Storage Temperature ..................................... −65°C to +150°C
Ambient Temperature with
Power Applied.................................................. −55°C to +125°C
Operating Range
Ambient
Supply Voltage to Ground Potential .................−0.5V to +7.0V
Range
Commercial
Industrial
Temperature
0°C to +70°C
−40°C to +85°C
V
CC
DC Voltage Applied to Outputs
in High Z State.....................................................−0.5V to +7.0V
5V ± 10%
5V ± 10%
[5]
DC Input Voltage ..............................................−0.5V to +7.0V
Electrical Characteristics Over the Operating Range
7C144-15
7C145-15
7C144-25
7C145-25
Parameter
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Leakage Current
Output Leakage Current
Operating Current
Test Conditions
= Min., I = −4.0 mA
Min.
Max.
Min. Max.
Unit
V
V
V
V
2.4
2.2
2.4
2.2
OH
OL
IH
CC
CC
OH
V
V
V
= Min., I = 4.0 mA
0.4
0.4
V
OL
V
0.8
+10
+10
220
0.8
+10
+10
180
190
40
V
IL
I
I
I
GND < V < V
CC
−10
−10
−10
−10
µA
µA
mA
IX
I
Outputs Disabled, GND < V < V
CC
OZ
CC
O
V
= Max., I
= 0 mA
Com’l
Ind
CC
OUT
Outputs Disabled
I
I
I
Standby Current
(Both Ports TTL Levels)
CE and CE > V ,
Com’l
Ind
60
130
15
mA
mA
mA
SB1
SB2
SB3
L
R
IH
[7]
f = f
MAX
50
Standby Current
(One Port TTL Level)
CE or CE > V ,
Com’l
Ind
110
120
15
L
R
IH
[7]
f = f
MAX
Standby Current
(Both Ports CMOS Levels) CE and CE > V – 0.2V,
Both Ports
Com’l
Ind
R
CC
30
V
> V – 0.2V
IN
CC
[7]
or V < 0.2V, f = 0
IN
I
Standby Current
(One Port CMOS Level)
One Port
Com’l
Ind
125
100
115
mA
SB4
CE or CE > V – 0.2V,
L R CC
V
> V – 0.2V or
IN
CC
V
< 0.2V, Active
IN
[7]
MAX
Port Outputs, f = f
Notes:
5. Pulse width < 20 ns.
6.
7.
T
f
A is the “instant on” case temperature.
MAX = 1/tRC = All inputs cycling at f = 1/tRC (except output enable). f = 0 means no address or control lines change. This applies only to inputs at CMOS
level standby ISB3
.
4
CY7C145
CY7C144
Electrical Characteristics Over the Operating Range (continued)
7C144-35
7C145-35
7C144-55
7C145-55
Parameter
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Leakage Current
Output Leakage Current
Operating Current
Test Conditions
= Min., I = −4.0 mA
Min.
Max.
Min.
Max.
Unit
V
V
V
V
V
V
V
2.4
2.4
OH
OL
IH
CC
CC
OH
= Min., I = 4.0 mA
0.4
0.4
V
OL
2.2
2.2
V
0.8
+10
+10
160
180
30
0.8
+10
+10
160
180
30
V
IL
I
I
I
GND < V < V
CC
−10
−10
−10
−10
µA
µA
mA
IX
I
Outputs Disabled, GND < V < V
CC
OZ
CC
O
V
= Max., I
= 0 mA
Com’l
Ind
CC
OUT
Outputs Disabled
I
I
I
Standby Current
(Both Ports TTL Levels)
CE and CE > V ,
Com’l
Ind
mA
mA
mA
SB1
SB2
SB3
L
R
IH
[7]
f = f
MAX
40
40
Standby Current
(One Port TTL Level)
CE or CE > V ,
Com’l
Ind
100
110
15
100
110
15
L
R
IH
[7]
f = f
MAX
Standby Current
(Both Ports CMOS Levels) CE and CE > V – 0.2V,
Both Ports
Com’l
Ind
R
CC
30
30
V
> V – 0.2V
IN
CC
[7]
or V < 0.2V, f = 0
IN
I
Standby Current
(One Port CMOS Level)
One Port
Com’l
Ind
90
90
mA
SB4
CE or CE > V – 0.2V,
L R CC
100
100
V
> V – 0.2V or
IN
CC
V
< 0.2V, Active
IN
[7]
MAX
Port Outputs, f = f
]
Capacitance[8]
Parameter
Description
Test Conditions
Max.
Unit
C
C
Input Capacitance
Output Capacitance
T = 25°C, f = 1 MHz,
10
15
pF
pF
IN
A
V
= 5.0V
CC
OUT
Note:
8. Tested initially and after any design or process changes that may affect these parameters.
5
CY7C145
CY7C144
AC Test Loads and Waveforms
5V
5V
R1=893Ω
R1=893Ω
R
TH
=250Ω
OUTPUT
OUTPUT
C=30pF
OUTPUT
C = 5 pF
C = 30 pF
R2=347Ω
R2=347Ω
V
TH
=1.4V
(a) Normal Load (Load1)
(b) Thévenin Equivalent (Load 1)
(c) Three-State Delay (Load 3)
C144-5
C144-6
C144-7
ALL INPUT PULSES
90%
OUTPUT
3.0V
GND
90%
10%
10%
C = 30 pF
≤ 3 ns
≤ 3 ns
Load (Load 2)
C144-8
C144-9
[9]
Switching Characteristics Over the Operating Range
7C144-15
7C145-15
7C144-25
7C145-25
7C144-35
7C145-35
7C144-55
7C145-55
Parameter
READ CYCLE
tRC
Description
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
Read Cycle Time
15
25
3
35
3
55
3
ns
ns
ns
t
t
Address to Data Valid
15
25
35
55
AA
Output Hold From Address
Change
3
OHA
t
t
t
t
t
t
t
t
CE LOW to Data Valid
OE LOW to Data Valid
OE Low to Low Z
15
10
25
15
35
20
55
25
ns
ns
ns
ns
ns
ns
ns
ns
ACE
DOE
[10, 11,12]
[10, 11,12]
3
3
0
3
3
0
3
3
0
3
3
0
LZOE
OE HIGH to High Z
CE LOW to Low Z
10
10
15
15
15
25
20
20
35
25
25
55
HZOE
[10, 11,12]
[10, 11,12]
LZCE
CE HIGH to High Z
CE LOW to Power-Up
CE HIGH to Power-Down
HZCE
[12]
[12]
PU
PD
Notes:
9. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
OI/IOH and 30-pF load capacitance.
I
10. At any given temperature and voltage condition for any given device, tHZCE is less than tLZCE and tHZOE is less than tLZOE
.
11. Test conditions used are Load 3.
12. This parameter is guaranteed but not tested.
6
CY7C145
CY7C144
[9]
Switching Characteristics Over the Operating Range (continued)
7C144-15
7C145-15
7C144-25
7C145-25
7C144-35
7C145-35
7C144-55
7C145-55
Parameter
Description
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
WRITE CYCLE
t
t
t
t
Write Cycle Time
15
12
12
2
25
20
20
2
35
30
30
2
55
45
45
2
ns
ns
ns
ns
WC
SCE
AW
HA
CE LOW to Write End
Address Set-Up to Write End
Address Hold From Write
End
t
Address Set-Up to Write
Start
0
0
0
0
ns
SA
t
t
t
t
t
t
t
Write Pulse Width
12
10
0
20
15
0
25
15
0
40
25
0
ns
ns
ns
ns
ns
ns
ns
PWE
Data Set-Up to Write End
Data Hold From Write End
R/W LOW to High Z
SD
HD
[11,12]
10
15
20
25
HZWE
[11,12]
R/W HIGH to Low Z
3
3
3
3
LZWE
[13]
Write Pulse to Data Delay
30
25
50
30
60
35
70
40
WDD
[13]
Write Data Valid to Read
Data Valid
DDD
[14]
BUSY TIMING
t
BUSY LOW from Address
Match
15
15
20
20
20
20
30
30
ns
ns
BLA
t
BUSY HIGH from Address
Mismatch
BHA
t
t
t
t
t
t
BUSY LOW from CE LOW
BUSY HIGH from CE HIGH
Port Set-Up for Priority
15
15
20
20
20
20
30
30
ns
ns
ns
ns
ns
ns
BLC
BHC
PS
5
0
5
0
5
0
5
0
R/W LOW after BUSY LOW
R/W HIGH after BUSY HIGH
WB
13
20
30
30
WH
BDD
BUSY HIGH to Data Valid
15
25
35
55
[14]
INTERRUPT TIMING
t
t
INT Set Time
15
15
25
25
25
25
35
35
ns
ns
INS
INR
INT Reset Time
SEMAPHORE TIMING
t
SEM Flag Update Pulse (OE
or SEM)
10
10
15
20
ns
SOP
t
t
SEM Flag Write to ReadTime
5
5
5
5
5
5
5
5
ns
ns
SWRD
SEM Flag Contention
Window
SPS
Notes:
13. For information on part-to-part delay through RAM cells from writing port to reading port, refer to Read Timing with Port-to-Port Delay waveform.
14. Test conditions used are Load 2.
7
CY7C145
CY7C144
Switching Waveforms
[15, 16]
Read Cycle No. 1 (Either Port Address Access)
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
C144-10
[15, 17, 18]
Read Cycle No. 2 (Either Port CE/OE Access)
SEM or CE
t
HZCE
t
ACE
OE
t
HZOE
t
DOE
t
LZOE
t
LZCE
DATA VALID
DATA OUT
t
PU
t
PD
I
CC
I
SB
C144-11
[19, 20]
Read Timing with Port-to-Port Delay (M/S=L)
t
WC
ADDRESS
R
MATCH
t
PWE
R/W
R
t
t
SD
HD
DATAIN
VALID
R
ADDRESS
L
MATCH
t
DDD
DATA
VALID
OUTL
t
WDD
C144-12
Notes:
15. R/W is HIGH for read cycle.
16. Device is continuously selected CE = LOW and OE = LOW. This waveform cannot be used for semaphore reads.
17. Address valid prior to or coincident with CE transition LOW.
18. CEL = L, SEM = H when accessing RAM. CE = H, SEM = L when accessing semaphores.
19. BUSY = HIGH for the writing port.
20. CEL = CER = LOW.
8
CY7C145
CY7C144
Switching Waveforms (continued)
[21, 22, 23]
Write Cycle No. 1: OE Three-State Data I/Os (Either Port)
t
WC
ADDRESS
t
SCE
SEM OR CE
R/W
t
t
HA
AW
t
PWE
t
SA
t
t
SD
HD
DATA IN
OE
DATA VALID
t
t
HZOE
LZOE
HIGH IMPEDANCE
[21, 23, 24]
DATA OUT
C144-13
Write Cycle No. 2: R/W Three-State Data I/Os (Either Port)
t
WC
ADDRESS
t
t
HA
SCE
SEM OR CE
R/W
t
AW
t
SA
t
PWE
t
t
SD
HD
DATAVALID
DATA IN
t
t
LZWE
HZWE
HIGH IMPEDANCE
DATA OUT
C144-14
Notes:
21. The internal write time of the memory is defined by the overlap of CE or SEM LOW and R/W LOW. Both signals must be LOW to initiate a write, and either
signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates
the write.
22. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tPWE or (tHZWE + tSD) to allow the I/O drivers to turn off and
data to be placed on the bus for the required tSD. If OE is HIGH during a R/W controlled write cycle (as in this example), this requirement does not apply
and the write pulse can be as short as the specified tPWE
23. R/W must be HIGH during all address transitions.
.
24. Data I/O pins enter high impedance when OE is held LOW during write.
9
CY7C145
CY7C144
Switching Waveforms (continued)
[25]
Semaphore Read After Write Timing, Either Side
t
AA
t
OHA
A −A
0
VALID ADDRESS
VALID ADDRESS
2
t
AW
t
ACE
t
HA
SEM
t
t
SOP
SCE
t
SD
I/O
0
DATA VALID
DATA
VALID
IN
OUT
t
HD
t
SA
t
PWE
R/W
OE
t
t
DOE
SWRD
t
SOP
WRITE CYCLE
READ CYCLE
C144-15
[26, 27, 28]
Semaphore Contention
A −A
0L 2L
MATCH
R/W
L
SEM
L
t
SPS
A −A
0R 2R
MATCH
R/W
R
SEM
R
C144-16
Notes:
25. CE = HIGH for the duration of the above timing (both write and read cycle).
26. I/O0R = I/O0L = LOW (request semaphore); CER = CEL = HIGH
27. Semaphores are reset (available to both ports) at cycle start.
28. If tSPS is violated, the semaphore will definitely be obtained by one side or the other, but there is no guarantee which side will control the semaphore.
10
CY7C145
CY7C144
Switching Waveforms (continued)
[20]
Read with BUSY (M/S=HIGH)
t
WC
ADDRESS
R
MATCH
t
PWE
R/W
R
t
t
HD
SD
DATAIN
VALID
R
t
PS
ADDRESS
L
MATCH
t
BLA
t
BHA
BUSY
L
t
BDD
t
DDD
DATA
VALID
OUTL
t
WDD
C144–17
Write Timing with Busy Input (M/S=LOW)
t
PWE
R/W
t
t
WH
WB
BUSY
C144–18
11
CY7C145
CY7C144
Switching Waveforms (continued)
[29]
Busy Timing Diagram No. 1 (CE Arbitration)
CE Valid First:
L
ADDRESS
L,R
ADDRESS MATCH
CE
L
t
PS
CE
R
t
t
BHC
BLC
BUSY
R
C144-19
CE Valid First:
R
ADDRESS
L,R
ADDRESS MATCH
CE
R
t
PS
CE
L
t
t
BHC
BLC
BUSY
L
C144-20
[29]
Busy Timing Diagram No. 2 (Address Arbitration)
Left Address Valid First:
t
or t
WC
RC
ADDRESS
L
ADDRESS MATCH
ADDRESS MISMATCH
t
PS
ADDRESS
BUSY
R
R
t
t
BHA
BLA
C144-21
Right Address Valid First:
t
or t
WC
RC
ADDRESS
R
ADDRESS MATCH
ADDRESS MISMATCH
t
PS
ADDRESS
L
t
t
BHA
BLA
BUSY
L
C144-22
Notes:
29. If tPS is violated, the busy signal will be asserted on one side or the other, but there is no guarantee on which side BUSY will be asserted
12
CY7C145
CY7C144
Switching Waveforms (continued)
Interrupt Timing Diagrams
Left Side Sets INT :
R
t
WC
ADDRESS
L
WRITE 1FFF
[30]
t
HA
CE
L
L
R/W
INT
R
[31]
t
INS
C144-23
Right Side Clears INT
:
R
t
RC
ADDRESS
R
READ 1FFF
CE
R
[31]
t
INR
R/W
OE
R
R
INT
C144-24
R
Right Side Sets INT :
L
t
WC
ADDRESS
R
WRITE 1FFE
[30]
t
HA
CE
R
R
R/W
INT
L
[31]
t
INS
C144-25
Left Side Clears INT :
L
t
RC
ADDRESS
R
READ 1FFE
CE
L
[31]
t
INR
R/W
L
OE
L
INT
L
C144-26
Notes:
30. tHA depends on which enable pin (CEL or R/WL) is deasserted first.
31. INS or tINR depends on which enable pin (CEL or R/WL) is asserted last.
t
13
CY7C145
CY7C144
in master mode are push-pull outputs and do not require pull-up re-
sistors to operate.
Architecture
The CY7C144/5 consists of a an array of 8K words of 8/9 bits
each of dual-port RAM cells, I/O and address lines, and control
signals (CE, OE, R/W). These control pins permit indepen-
dent access for reads or writes to any location in memory. To
handle simultaneous writes/reads to the same location, a
BUSY pin is provided on each port. Two interrupt (INT) pins
can be utilized for port-to-port communication. Two sema-
phore (SEM) control pins are used for allocating shared re-
sources. With the M/S pin, the CY7C144/5 can function as
a Master (BUSY pins are outputs) or as a slave (BUSY pins
are inputs). The CY7C144/5 has an automatic power-down
feature controlled by CE. Each port is provided with its own
output enable control (OE), which allows data to be read
from the device.
Master/Slave
An M/S pin is provided in order to expand the word width by config-
uring the device as either a master or a slave. The BUSY output of
the master is connected to the BUSY input of the slave. This will allow
the device to interface to a master device with no external compo-
nents.Writing of slave devices must be delayed until after the BUSY
input has settled. Otherwise, the slave chip may begin a write cycle
during a contention situation.When presented a HIGH input, the M/S
pin allows the device to be used as a master and therefore the BUSY
line is an output. BUSY can then be used to send the arbitration out-
come to a slave.
Semaphore Operation
The CY7C144/5 provides eight semaphore latches which are
separate from the dual-port memory locations. Semaphores
are used to reserve resources that are shared between the two
ports.The state of the semaphore indicates that a resource is
in use. For example, if the left port wants to request a given
resource, it sets a latch by writing a 0 to a semaphore location.
The left port then verifies its success in setting the latch by
reading it. After writing to the semaphore, SEM or OE must be
Functional Description
Write Operation
Data must be set up for a duration of t
before the rising
SD
edge of R/W in order to guarantee a valid write. A write op-
eration is controlled by either the OE pin (see Write Cycle
No.1 waveform) or the R/W pin (see Write Cycle No. 2 wave-
form). Data can be written to the device t
after the OE
deasserted for t
before attempting to read the semaphore. The
HZOE
SOP
is deasserted or t
after the falling edge of R/W. Re-
semaphore value will be available t
+ t
after the rising edge
HZWE
SWRD DOE
quired inputs for non-contention operations are summarized
in Table 1.
of the semaphore write. If the left port was successful (reads a 0), it
assumes control over the shared resource, otherwise (reads a 1) it
assumes the right port has control and continues to poll the sema-
phore.When the right side has relinquished control of the semaphore
(by writing a 1), the left side will succeed in gaining control of the
semaphore. If the left side no longer requires the semaphore, a 1 is
written to cancel its request.
If a location is being written to by one port and the opposite
port attempts to read that location, a port-to-port flowthrough
delay must be met before the data is read on the output; oth-
erwise the data read is not deterministic. Data will be valid on
the port t
after the data is presented on the other port.
DDD
Semaphores are accessed by asserting SEM LOW. The SEM
pin functions as a chip enable for the semaphore latches (CE must
Read Operation
When reading the device, the user must assert both the OE
remain HIGH during SEM LOW). A
represents the semaphore
0–2
and CE pins. Data will be available t
after CE or t
after
address. OE and R/W are used in the same manner as a normal
memory access.When writing or reading a semaphore, the other ad-
dress pins have no effect.
ACE
DOE
OE are asserted. If the user of the CY7C144/5 wishes to ac-
cess a semaphore flag, then the SEM pin must be asserted
instead of the CE pin.
When writing to the semaphore, only I/O is used. If a 0 is written
0
to the left port of an unused semaphore, a 1 will appear at the same
semaphore address on the right port. That semaphore can now only
be modified by the side showing 0 (the left port in this case). If the left
port now relinquishes control by writing a 1 to the semaphore, the
semaphore will be set to 1 for both sides. However, if the right port
had requested the semaphore (written a 0) while the left port had
control, the right port would immediately own the semaphore as soon
as the left port released it. Table 3 shows sample semaphore oper-
ations.
Interrupts
The interrupt flag (INT) permits communications between
ports.When the left port writes to location 1FFF, the right port’s inter-
rupt flag (INT ) is set. This flag is cleared when the right port reads
R
thatsamelocation. Settingthe left port’sinterrupt flag(INT )isaccom-
L
plished whenthe right port writes to location 1FFE. Thisflagiscleared
when the left port reads location 1FFE. The message at 1FFF or
1FFE is user-defined. See Table 2 for input requirements for INT.
INT and INT are push-pull outputs and do not require pull-up resis-
R
L
When reading a semaphore, all eight/nine data lines output the
semaphore value. The read value is latched in an output reg-
ister to prevent the semaphore from changing state during a
write from the other port. If both ports attempt to access the
tors to operate.
Busy
The CY7C144/5 provides on-chip arbitration to alleviate simul-
taneous memory location access (contention). If both ports’
CEs are asserted and an address match occurs within t of each
other the Busy logic will determine which port has access. If t is
violated, one port will definitely gain permission to the location, but it
is not guaranteed which one. BUSY will be asserted t
address match or t
semaphore within t
of each other, the semaphore will definitely
SPS
be obtained by one side or the other, but there is no guarantee which
side will control the semaphore.
PS
PS
Initialization of the semaphore is not automatic and must be
reset during initialization program at power-up. All Sema-
phores on both sides should have a one written into them at
initialization from both sides to assure that they will be free
when needed.
after an
BLA
after CE is taken LOW. BUSY and BUSY
BLC
L R
14
CY7C145
CY7C144
Table 1. Non-Contending Read/Write.
Inputs
Outputs
I/O
CE R/W OE SEM
Operation
0−7/8
H
H
X
H
X
L
H
L
High Z
Power-Down
Data Out
Read Data in
Semaphore
X
H
X
H
X
X
L
High Z
Data In
I/O Lines Disabled
Write to Semaphore
L
L
L
H
L
L
X
X
H
H
L
Data Out
Data In
Read
Write
X
Illegal Condition
Table 2. Interrupt Operation Example (assumes BUSY =BUSY =HIGH).
L
R
Left Port
Right Port
Function
R/W
X
CE
X
OE
X
A
INT
L
R/W
L
CE
L
OE
X
A
INT
X
0−12
0−12
Set Left INT
X
1FFE
X
Reset Left INT
Set Right INT
Reset Right INT
X
L
L
1FFE
1FFF
X
H
X
L
L
X
L
L
X
X
X
X
X
X
L
X
X
X
X
X
L
L
1FFF
H
Table 3. Semaphore Operation Example.
Function
I/O
Left
I/O
Right
Status
0-7/8
0-7/8
No action
1
0
0
1
1
0
1
1
1
0
1
1
Semaphore free
Left port writes semaphore
Right port writes 0 to semaphore
Left port writes 1 to semaphore
Left port writes 0 to semaphore
Right port writes 1 to semaphore
Left port writes 1 to semaphore
Right port writes 0 to semaphore
Right port writes 1 to semaphore
Left port writes 0 to semaphore
Left port writes 1 to semaphore
1
1
0
0
1
1
0
1
1
1
Left port obtains semaphore
Right side is denied access
Right port is granted access to semaphore
No change. Left port is denied access
Left port obtains semaphore
No port accessing semaphore address
Right port obtains semaphore
No port accessing semaphore
Left port obtains semaphore
No port accessing semaphore
15
CY7C145
CY7C144
Typical DC and AC Characteristics
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
OUTPUT SOURCE CURRENT
vs. OUTPUT VOLTAGE
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
200
160
120
80
1.4
1.2
1.0
I
CC
1.2
I
CC
1.0
I
SB3
0.8
0.6
0.4
I
SB3
0.8
V
=5.0V
CC
V
V
=5.0V
=5.0V
CC
0.6
0.4
T =25°C
A
IN
40
0
0.2
0.6
0.2
0.0
5.0
−55
25
125
0
1.0
2.0
3.0
4.0
4.0
4.5
5.0
5.5
6.0
AMBIENT TEMPERATURE (°C)
OUTPUT VOLTAGE (V)
SUPPLY VOLTAGE (V)
NORMALIZED ACCESS TIME
vs. AMBIENT TEMPERATURE
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
NORMALIZED ACCESS TIME
vs. SUPPLY VOLTAGE
140
120
1.6
1.4
1.4
1.3
1.2
1.1
100
80
1.2
1.0
60
T =25°C
A
V
CC
=5.0V
1.0
40
0.8
V
=5.0V
CC
20
0
0.9
0.8
T =25°C
A
0.6
−55
0.0
1.0
2.0
3.0
4.0
25
125
5.0
4.0
4.5
5.0
5.5
6.0
AMBIENT TEMPERATURE (°C)
OUTPUT VOLTAGE (V)
SUPPLY VOLTAGE (V)
TYPICAL POWER-ON CURRENT
vs. SUPPLY VOLTAGE
TYPICAL ACCESS TIME CHANGE
vs. OUTPUT LOADING
NORMALIZED I
vs. CYCLE TIME
CC
1.25
30.0
25.0
1.00
V
CC
=5.0V
T =25°C
A
V
IN
=0.5V
0.75
0.50
1.0
20.0
15.0
10.0
0.75
0.25
0.0
V
=4.5V
CC
5.0
0
T =25°C
A
0.50
40
66
10
28
0
1.0
2.0
3.0
4.0 5.0
0
200 400 600 800 1000
CAPACITANCE (pF)
CYCLE FREQUENCY (MHz)
SUPPLY VOLTAGE (V)
16
CY7C145
CY7C144
Ordering Information
8K x8 Dual-Port SRAM
Speed
Package
Name
Operating
Range
(ns)
Ordering Code
CY7C144-15AC
CY7C144-15JC
CY7C144-25AC
CY7C144-25JC
CY7C144-25AI
CY7C144-25JI
CY7C144-35AC
CY7C144-35JC
CY7C144-35AI
CY7C144-35JI
CY7C144-55AC
CY7C144-55JC
CY7C144-55AI
CY7C144-55JI
Package Type
15
A65
J81
A65
J81
A65
J81
A65
J81
A65
J81
A65
J81
A65
J81
64-Lead Thin Quad Flat Pack
Commercial
Commercial
Industrial
68-Lead Plastic Leaded Chip Carrier
64-Lead Thin Quad Flat Pack
25
35
55
68-Lead Plastic Leaded Chip Carrier
64-Lead Thin Quad Flat Pack
68-Lead Plastic Leaded Chip Carrier
64-Lead Thin Quad Flat Pack
Commercial
Industrial
68-Lead Plastic Leaded Chip Carrier
64-Lead Thin Quad Flat Pack
68-Lead Plastic Leaded Chip Carrier
64-Lead Thin Quad Flat Pack
Commercial
Industrial
68-Lead Plastic Leaded Chip Carrier
64-Lead Thin Quad Flat Pack
68-Lead Plastic Leaded Chip Carrier
8K x9 Dual-Port SRAM
Speed
(ns)
Package
Name
Operating
Range
Ordering Code
Package Type
15
CY7C145-15AC
CY7C145-15JC
CY7C145-25AC
CY7C145-25JC
CY7C145-25AI
CY7C145-25JI
CY7C145-35AC
CY7C145-35JC
CY7C145-35AI
CY7C145-35JI
CY7C145-55AC
CY7C145-55JC
CY7C145-55AI
CY7C145-55JI
A80
J81
A80
J81
A80
J81
A80
J81
A80
J81
A80
J81
A80
J81
80-Lead Thin Quad Flat Pack
Commercial
Commercial
Industrial
68-Lead Plastic Leaded Chip Carrier
80-Lead Thin Quad Flat Pack
25
35
55
68-Lead Plastic Leaded Chip Carrier
80-Lead Thin Quad Flat Pack
68-Lead Plastic Leaded Chip Carrier
80-Lead Thin Quad Flat Pack
Commercial
Industrial
68-Lead Plastic Leaded Chip Carrier
80-Lead Thin Quad Flat Pack
68-Lead Plastic Leaded Chip Carrier
80-Lead Thin Quad Flat Pack
Commercial
Industrial
68-Lead Plastic Leaded Chip Carrier
80-Lead Thin Quad Flat Pack
68-Lead Plastic Leaded Chip Carrier
17
CY7C145
CY7C144
Package Diagrams
64-Pin Thin PlasticQuad Flat Pack A65
80-PinThin Plastic QuadFlat Pack A80
18
CY7C145
CY7C144
Package Diagrams (continued)
68-Lead Plastic Leaded ChipCarrierJ81
© Cypress Semiconductor Corporation, 1996. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of anycircuitry other than circuitry embodied in a CypressSemiconductor product. Nor does it conveyor imply any license under patent or other rights. CypressSemiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
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