CY7C1442AV25-250AXI [CYPRESS]
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM; 36兆位( 1M ×36 / 2M ×18 / 512K X 72 ),流水线同步SRAM型号: | CY7C1442AV25-250AXI |
厂家: | CYPRESS |
描述: | 36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM |
文件: | 总32页 (文件大小:525K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
CY7C1440AV25
CY7C1442AV25
CY7C1446AV25
36-Mbit (1M x 36/2M x 18/512K x 72)
Pipelined Sync SRAM
Features
Functional Description[1]
• Supports bus operation up to 250 MHz
The CY7C1440AV25/CY7C1442AV25/CY7C1446AV25 SRAM
integrates 1M x 36/2M x 18/512K x 72 SRAM cells with
advanced synchronous peripheral circuitry and a two-bit
• Available speed grades are 250, 200 and 167 MHz
• Registered inputs and outputs for pipelined operation
• 2.5V core power supply
counter for internal burst operation. All synchronous inputs are
gated by registers controlled by a positive-edge-triggered
Clock Input (CLK). The synchronous inputs include all
addresses, all data inputs, address-pipelining Chip Enable
(CE1), depth-expansion Chip Enables (CE2 and CE3), Burst
Control inputs (ADSC, ADSP, and ADV), Write Enables (BWX,
and BWE), and Global Write (GW). Asynchronous inputs
include the Output Enable (OE) and the ZZ pin.
• 2.5V/1.8V I/O powersupply
• Fast clock-to-output times
— 2.6 ns (for 250-MHz device)
• Provide high-performance 3-1-1-1 access rate
• User-selectable burst counter supporting Intel®
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP) or
Address Strobe Controller (ADSC) are active. Subsequent
burst addresses can be internally generated as controlled by
the Advance pin (ADV).
Pentium® interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self-timed writes
• Asynchronous output enable
Address, data inputs, and write controls are registered on-chip
to initiate a self-timed Write cycle.This part supports Byte Write
operations (see Pin Descriptions and Truth Table for further
details). Write cycles can be one to two or four bytes wide as
controlled by the byte write control inputs. GW when active
• Single-cycle Chip Deselect
• CY7C1440AV25, CY7C1442AV25 available in
JEDEC-standard lead-free 100-pin TQFP package,
lead-free and non-lead-free 165-ball FBGA package.
CY7C1446AV25availableinlead-freeandnon-lead-free
209-ball FBGA package
causes all bytes to be written.
LOW
The
CY7C1440AV25/CY7C1442AV25/CY7C1446AV25
operates from a +2.5V core power supply while all outputs
may operate with a +2.5V/1.8V supply. All inputs and outputs
are JEDEC-standard JESD8-5-compatible.
• IEEE 1149.1 JTAG-Compatible Boundary Scan
• “ZZ” Sleep Mode Option
Selection Guide
250 MHz
2.6
200 MHz
3.2
167 MHz
3.4
Unit
ns
Maximum Access Time
Maximum Operating Current
435
385
335
mA
mA
Maximum CMOS Standby Current
120
120
120
Notes:
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
Cypress Semiconductor Corporation
Document #: 38-05350 Rev. *E
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised June 21, 2006
CY7C1440AV25
CY7C1442AV25
CY7C1446AV25
Logic Block Diagram – CY7C1440AV25 (1M x 36)
A0, A1, A
ADDRESS
REGISTER
2
A[1:0]
MODE
Q1
ADV
CLK
BURST
COUNTER
AND
CLR
Q0
LOGIC
ADSC
ADSP
DQ
BYTE
WRITE REGISTER
D ,DQPD
DQ
BYTE
WRITE DRIVER
D ,DQPD
BW
D
DQC ,DQP
BYTE
WRITE DRIVER
C
DQC ,DQP
BYTE
WRITE REGISTER
C
BW
C
OUTPUT
BUFFERS
OUTPUT
REGISTERS
MEMORY
ARRAY
DQ s
SENSE
AMPS
DQPA
DQB ,DQP
BYTE
WRITE DRIVER
B
E
DQB ,DQP
BYTE
WRITE REGISTER
B
DQP
DQP
B
C
BW
BW
B
A
DQPD
DQ
BYTE
WRITE DRIVER
A ,DQPA
DQ
A ,DQPA
BYTE
WRITE REGISTER
BWE
INPUT
REGISTERS
GW
ENABLE
REGISTER
PIPELINED
ENABLE
CE
CE
CE
1
2
3
OE
SLEEP
CONTROL
ZZ
Logic Block Diagram – CY7C1442AV25 (2M x 18)
ADDRESS
A0, A1, A
REGISTER
A[1:0]
2
MODE
Q1
ADV
CLK
BURST
COUNTER AND
LOGIC
CLR
Q0
ADSC
ADSP
DQB,DQP
B
DQB,DQP
WRITE REGISTER
B
WRITE DRIVER
OUTPUT
BUFFERS
BW
B
A
DQs
DQP
DQP
OUTPUT
REGISTERS
SENSE
AMPS
MEMORY
ARRAY
A
B
DQA,DQP
A
E
DQA,DQP
WRITE REGISTER
A
WRITE DRIVER
BW
BWE
GW
INPUT
REGISTERS
ENABLE
REGISTER
CE1
CE2
PIPELINED
ENABLE
CE3
OE
ZZ
SLEEP
CONTROL
Document #: 38-05350 Rev. *E
Page 2 of 32
CY7C1440AV25
CY7C1442AV25
CY7C1446AV25
Logic Block Diagram – CY7C1446AV25 (512K x 72)
ADDRESS
REGISTER
A0, A1,A
A[1:0]
MODE
Q1
ADV
CLK
BINARY
COUNTER
CLR
Q0
ADSC
ADSP
DQ
WRITE DRIVER
H
, DQP
H
DQ
WRITE DRIVER
H, DQPH
BW
BW
H
G
DQG, DQPG
WRITE DRIVER
DQF, DQPF
WRITE DRIVER
DQF, DQPF
WRITE DRIVER
DQF, DQPF
WRITE DRIVER
BW
BW
F
E
DQ E
E
, DQP
WRITE DRIVER
DQE, DQPE
WRITE DRIVER
MEMORY
ARRAY
DQD, DQPD
WRITE DRIVER
DQD, DQPD
WRITE DRIVER
BW
D
DQC, DQPC
WRITE DRIVER
DQC, DQPC
WRITE DRIVER
BW
C
OUTPUT
BUFFERS
OUTPUT
REGISTERS
SENSE
AMPS
DQs
DQP
DQP
DQP
DQP
DQP
DQP
DQP
DQP
A
B
C
D
E
E
DQB, DQPB
WRITE DRIVER
DQB, DQPB
WRITE DRIVER
BW
BW
B
A
DQA, DQPA
WRITE DRIVER
DQ
WRITE DRIVER
A
, DQP
A
F
G
H
BWE
INPUT
REGISTERS
GW
CE1
CE2
CE3
OE
ENABLE
REGISTER
PIPELINED
ENABLE
SLEEP
CONTROL
ZZ
Document #: 38-05350 Rev. *E
Page 3 of 32
CY7C1440AV25
CY7C1442AV25
CY7C1446AV25
Pin Configurations
100-pin TQFP Pinout
DQPC
1
DQPB
DQB
DQB
VDDQ
VSSQ
DQB
DQB
DQB
DQB
VSSQ
VDDQ
DQB
DQB
VSS
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
NC
NC
VDDQ
VSSQ
NC
A
NC
NC
VDDQ
VSSQ
NC
DQPA
DQA
DQA
VSSQ
VDDQ
DQA
DQA
VSS
NC
1
2
3
4
5
6
7
8
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQC
2
DQc
VDDQ
VSSQ
DQC
3
4
5
6
DQC
7
NC
DQC
8
DQB
DQB
VSSQ
VDDQ
DQB
DQB
NC
VDD
NC
VSS
DQB
DQB
VDDQ
VSSQ
DQB
DQB
DQPB
NC
DQC
9
10
11
9
VSSQ
VDDQ
DQC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
12
DQC
13
NC
14
VDD
15
NC
VDD
ZZ
CY7C1442AV25
(2M x 18)
CY7C1440AV25
(1M x 36)
NC
16
VDD
ZZ
VSS
17
DQD
18
DQA
DQA
VDDQ
VSSQ
DQA
DQA
DQA
DQA
VSSQ
VDDQ
DQA
DQA
DQPA
DQA
DQA
VDDQ
VSSQ
DQA
DQA
NC
DQD
19
20
21
VDDQ
VSSQ
DQD
22
DQD
23
DQD
24
DQD
25
26
27
NC
VSSQ
VDDQ
DQD
DQD
29
VSSQ
VDDQ
NC
NC
NC
VSSQ
VDDQ
NC
NC
NC
28
DQPD
30
Document #: 38-05350 Rev. *E
Page 4 of 32
CY7C1440AV25
CY7C1442AV25
CY7C1446AV25
Pin Configurations (continued)
165-ball FBGA (15 x 17 x 1.4 mm) Pinout
CY7C1440AV25 (1M x 36)
1
2
3
4
5
6
7
8
9
10
A
11
NC
NC/288M
NC/144M
DQPC
A
B
C
D
CE1
BWC
BWD
VSS
VDD
BWB
BWA
VSS
VSS
CE3
CLK
VSS
VSS
ADSC
OE
A
BWE
GW
VSS
VSS
ADV
ADSP
VDDQ
VDDQ
A
CE2
VDDQ
VDDQ
A
NC/576M
DQPB
DQB
NC
VSS
VDD
NC/1G
DQB
DQC
DQC
DQC
DQC
DQC
NC
DQC
DQC
DQC
NC
VDDQ
VDDQ
VDDQ
NC
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
NC
DQB
DQB
DQB
NC
DQB
DQB
DQB
ZZ
E
F
G
H
J
DQD
DQD
DQD
DQD
DQD
DQD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
DQA
DQA
DQA
DQA
DQA
DQA
K
L
DQD
DQPD
NC
DQD
NC
VDDQ
VDDQ
A
VDD
VSS
A
VSS
NC
VSS
A
VSS
NC
VDD
VSS
A
VDDQ
VDDQ
A
DQA
NC
A
DQA
DQPA
A
M
N
P
NC/72M
TDI
A1
TDO
A0
MODE
A
A
A
TMS
TCK
A
A
A
A
R
CY7C1442AV25 (2M x 18)
1
2
A
3
4
5
NC
6
7
8
9
10
A
11
A
NC/288M
NC/144M
NC
A
B
C
D
BWB
NC
CE3
CLK
VSS
VSS
CE1
CE2
BWE
GW
VSS
VSS
ADSC
OE
ADV
ADSP
VDDQ
VDDQ
A
BWA
VSS
VSS
A
NC/1G
NC
NC/576M
DQPA
DQA
NC
VDDQ
VDDQ
VSS
VDD
VSS
NC
DQB
VDD
NC
NC
DQB
DQB
DQB
NC
VDDQ
VDDQ
VDDQ
NC
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
NC
NC
NC
DQA
DQA
DQA
ZZ
E
F
NC
NC
G
H
J
NC
NC
DQB
DQB
DQB
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
DQA
DQA
DQA
NC
NC
NC
K
L
NC
NC
DQB
DQPB
NC
NC
NC
VDDQ
VDDQ
A
VDD
VSS
A
VSS
NC
VSS
A
VSS
NC
VDD
VSS
A
VDDQ
VDDQ
A
DQA
NC
A
NC
NC
A
M
N
P
NC/72M
TDI
A1
TDO
MODE
A
A
A
TMS
A0
TCK
A
A
A
A
R
Document #: 38-05350 Rev. *E
Page 5 of 32
CY7C1440AV25
CY7C1442AV25
CY7C1446AV25
Pin Configurations (continued)
209-ball FBGA (14 x 22 x 1.76 mm) Pinout
CY7C1442AV25 (512K x 72)
1
2
3
4
5
6
7
8
9
10
11
DQG
DQG
DQG
A
B
C
D
E
F
DQG
DQG
A
ADSP
ADV
A
CE3
BWSB
BWSE
NC
DQB
DQB
CE2
ADSC
BW
A
DQB
DQB
NC/288M
NC/144M
BWSC
BWSH
VSS
BWSF
BWSG
BWSD
DQG
DQG
NC/576M
GW
CE1
BWSA DQB
DQB
DQB
DQG
NC/1G OE
VSS
NC
DQB
DQPG DQPC
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VDD
VDD
VSS
VDD
DQPF DQPB
DQC
DQC
VSS
DQF
DQF
VSS
VDDQ
VSS
NC
NC
NC
NC
VSS
NC
NC
VSS
G
H
J
DQC
DQC
DQC VDDQ
VDDQ
VSS
VDDQ
VSS
DQF
DQF
DQF
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
NC
A
VSS
DQC
DQF
DQF
NC
VDDQ
DQC
NC
DQC
VDDQ
VDDQ
VDDQ
NC
DQF
NC
K
L
NC
CLK
VDDQ
VSS
NC
NC
DQH
DQH
DQH
VDDQ
VDDQ
VSS
VDDQ
VSS
VDDQ
VSS
DQA
DQA
DQA
M
N
P
R
T
VSS
VDDQ
VSS
VDDQ
NC
DQH
DQH
DQH
VSS
VDD
VSS
DQA
DQA
DQA
VDDQ
DQH
DQH
DQPD
DQD
DQD
VDDQ
VSS
NC
ZZ
DQA
DQA
DQPA
DQE
DQE
VSS
VDDQ
VSS
A
VDDQ
VDD
NC
A
DQPH
DQD
DQD
DQD
DQD
VDDQ
VDD
DQPE
DQE
DQE
DQE
DQE
VSS
NC
A
MODE
A
U
V
W
A
NC/72M
A
A
A1
A
DQD
DQD
A
A
A
A
DQE
DQE
TDI
TDO
TCK
A0
A
TMS
Pin Definitions
Name
I/O
Input-
Synchronous
Description
A0, A1, A
Address Inputs used to select one of the address locations. Sampled at the rising
edge of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, andCE3 [2]are sampled
active. A1: A0 are fed to the two-bit counter.
BWA, BWB, BWC,
BWD, BWE, BWF,
BWG, BWH
Input-
Synchronous
Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes to
the SRAM. Sampled on the rising edge of CLK.
GW
Input-
Synchronous
Global Write Enable Input, active LOW. When asserted LOW on the rising edge of
CLK, a global write is conducted (ALL bytes are written, regardless of the values on BWX
and BWE).
BWE
CLK
CE1
Input-
Synchronous
Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal
must be asserted LOW to conduct a byte write.
Input-
Clock
Clock Input. Used to capture all synchronous inputs to the device. Also used to
increment the burst counter when ADV is asserted LOW, during a burst operation.
Input-
Synchronous
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in
conjunction with CE2 and CE3 to select/deselect the device. ADSP is ignored if CE1 is
HIGH. CE1 is sampled only when a new external address is loaded.
Document #: 38-05350 Rev. *E
Page 6 of 32
CY7C1440AV25
CY7C1442AV25
CY7C1446AV25
Pin Definitions (continued)
Name
I/O
Description
CE2
CE3
Input-
Synchronous
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in
conjunction with CE1 and CE3 to select/deselect the device. CE2 is sampled only when
a new external address is loaded.
Input-
Synchronous
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in
conjunction with CE1 andCE2 to select/deselect the device.Not available for AJ package
version.Not connected for BGA. Where referenced, CE3 is assumed active throughout
this document for BGA. CE3 is sampled only when a new external address is loaded.
OE
Input-
Output Enable, asynchronous input, active LOW. Controls the direction of the I/O
Asynchronous pins. When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are
tri-stated, and act as input data pins. OE is masked during the first clock of a read cycle
when emerging from a deselected state.
ADV
Input-
Synchronous
Advance Input signal, sampled on the rising edge of CLK, active LOW. When
asserted, it automatically increments the address in a burst cycle.
ADSP
Input-
Synchronous
Address Strobe from Processor, sampled on the rising edge of CLK, active LOW.
When asserted LOW, addresses presented to the device are captured in the address
registers. A1: A0 are also loaded into the burst counter. When ADSP and ADSC are both
asserted, only ADSP is recognized. ASDP is ignored when CE1 is deasserted HIGH.
ADSC
ZZ
Input-
Synchronous
Address Strobe from Controller, sampled on the rising edge of CLK, active LOW.
When asserted LOW, addresses presented to the device are captured in the address
registers. A1: A0 are also loaded into the burst counter. When ADSP and ADSC are both
asserted, only ADSP is recognized.
Input-
ZZ “sleep” Input, active HIGH. When asserted HIGH places the device in a
Asynchronous non-time-critical “sleep” condition with data integrity preserved. For normal operation,
this pin has to be LOW or left floating. ZZ pin has an internal pull-down.
I/O-
Synchronous
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is
triggered by the rising edge of CLK. As outputs, they deliver the data contained in the
memory location specified by the addresses presented during the previous clock rise of
the read cycle. The direction of the pins is controlled by OE. When OE is asserted LOW,
the pins behave as outputs. When HIGH, DQs and DQPX are placed in a tri-state
condition.
DQs, DQPs
VDD
Power Supply Power supply inputs to the core of the device.
VSS
Ground
Ground for the core of the device.
Ground for the I/O circuitry.
VSSQ
VDDQ
MODE
I/O Ground
I/O Power Supply Power supply for the I/O circuitry.
Input-
Static
Selects Burst Order. When tied to GND selects linear burst sequence. When tied to
VDD or left floating selects interleaved burst sequence. This is a strap pin and should
remain static during device operation. Mode Pin has an internal pull-up.
TDO
TDI
JTAG serial output Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If the
Synchronous
JTAG feature is not being utilized, this pin should be disconnected. This pin is not
available on TQFP packages.
JTAG serial input Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG
Synchronous
feature is not being utilized, this pin can be disconnected or connected to VDD. This pin
is not available on TQFP packages.
TMS
JTAG serial input Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG
Synchronous
feature is not being utilized, this pin can be disconnected or connected to VDD. This pin
is not available on TQFP packages.
TCK
NC
JTAG-
Clock
Clock input to the JTAG circuitry. If the JTAG feature is not being utilized, this pin must
be connected to VSS. This pin is not available on TQFP packages.
-
-
No Connects. Not internally connected to the die
NC/72M,NC/144M,
NC/288M,
No Connects. Not internally connected to the die. 72M, 144M, 288M, 576M and 1G are
address expansion pins are not internally connected to the die.
NC/576,NC/1G
Document #: 38-05350 Rev. *E
Page 7 of 32
CY7C1440AV25
CY7C1442AV25
CY7C1446AV25
memory array. The Write signals (GW, BWE, and BWX) and
ADV inputs are ignored during this first cycle.
Functional Overview
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock.
Maximum access delay from the clock rise (tCO) is 2.6 ns
(250-MHz device).
ADSP-triggered Write accesses require two clock cycles to
complete. If GW is asserted LOW on the second clock rise, the
data presented to the DQs inputs is written into the corre-
sponding address location in the memory array. If GW is HIGH,
then the Write operation is controlled by BWE and BWX
signals.
The CY7C1440AV25/CY7C1442AV25/CY7C1446AV25 supports
secondary cache in systems utilizing either a linear or inter-
leaved burst sequence. The interleaved burst order supports
Pentium and i486™ processors. The linear burst sequence is
suited for processors that utilize a linear burst sequence. The
burst order is user selectable, and is determined by sampling
the MODE input. Accesses can be initiated with either the
Processor Address Strobe (ADSP) or the Controller Address
Strobe (ADSC). Address advancement through the burst
sequence is controlled by the ADV input. A two-bit on-chip
wraparound burst counter captures the first address in a burst
sequence and automatically increments the address for the
rest of the burst access.
The CY7C1440AV25/CY7C1442AV25/CY7C1446AV25 provides
Byte Write capability that is described in the Write Cycle
Descriptions table. Asserting the Byte Write Enable input
(BWE) with the selected Byte Write (BWX) input, will selec-
tively write to only the desired bytes. Bytes not selected during
a Byte Write operation will remain unaltered. A synchronous
self-timed Write mechanism has been provided to simplify the
Write operations.
Because CY7C1440AV25/CY7C1442AV25/CY7C1446AV25
is a common I/O device, the Output Enable (OE) must be
deasserted HIGH before presenting data to the DQs inputs.
Doing so will tri-state the output drivers. As a safety
precaution, DQs are automatically tri-stated whenever a Write
cycle is detected, regardless of the state of OE.
Byte Write operations are qualified with the Byte Write Enable
(BWE) and Byte Write Select (BWX) inputs. A Global Write
Enable (GW) overrides all Byte Write inputs and writes data to
all four bytes. All writes are simplified with on-chip
synchronous self-timed Write circuitry.
Single Write Accesses Initiated by ADSC
ADSC Write accesses are initiated when the following condi-
tions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is
deserted HIGH, (3) CE1, CE2, CE3 are all asserted active, and
(4) the appropriate combination of the Write inputs (GW, BWE,
and BWX) are asserted active to conduct a Write to the desired
byte(s). ADSC-triggered Write accesses require a single clock
cycle to complete. The address presented to A is loaded into
the address register and the address advancement logic while
being delivered to the memory array. The ADV input is ignored
during this cycle. If a global Write is conducted, the data
presented to the DQs is written into the corresponding address
location in the memory core. If a Byte Write is conducted, only
the selected bytes are written. Bytes not selected during a
Byte Write operation will remain unaltered. A synchronous
self-timed Write mechanism has been provided to simplify the
Write operations.
Three synchronous Chip Selects (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output tri-state control. ADSP is ignored if CE1
is HIGH.
Single Read Accesses
This access is initiated when the following conditions are
satisfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2)
CE1, CE2, CE3 are all asserted active, and (3) the Write
signals (GW, BWE) are all deserted HIGH. ADSP is ignored if
CE1 is HIGH. The address presented to the address inputs (A)
is stored into the address advancement logic and the Address
Register while being presented to the memory array. The
corresponding data is allowed to propagate to the input of the
Output Registers. At the rising edge of the next clock the data
is allowed to propagate through the output register and onto
the data bus within 2.6 ns (250-MHz device) if OE is active
LOW. The only exception occurs when the SRAM is emerging
from a deselected state to a selected state, its outputs are
always tri-stated during the first cycle of the access. After the
first cycle of the access, the outputs are controlled by the OE
signal. Consecutive single Read cycles are supported. Once
the SRAM is deselected at clock rise by the chip select and
either ADSP or ADSC signals, its output will tri-state immedi-
ately.
Because CY7C1440AV25/CY7C1442AV25/CY7C1446AV25
is a common I/O device, the Output Enable (OE) must be
deasserted HIGH before presenting data to the DQs inputs.
Doing so will tri-state the output drivers. As a safety
precaution, DQs are automatically tri-stated whenever a Write
cycle is detected, regardless of the state of OE.
Burst Sequences
The CY7C1440AV25/CY7C1442AV25/CY7C1446AV25 provides
a two-bit wraparound counter, fed by A1: A0, that implements
either an interleaved or linear burst sequence. The interleaved
burst sequence is designed specifically to support Intel
Pentium applications. The linear burst sequence is designed
to support processors that follow a linear burst sequence. The
burst sequence is user selectable through the MODE input.
Single Write Accesses Initiated by ADSP
This access is initiated when both of the following conditions
are satisfied at clock rise: (1) ADSP is asserted LOW, and
(2) CE1, CE2, CE3 are all asserted active. The address
presented to A is loaded into the address register and the
address advancement logic while being delivered to the
Asserting ADV LOW at clock rise will automatically increment
the burst counter to the next address in the burst sequence.
Both Read and Write burst operations are supported.
Document #: 38-05350 Rev. *E
Page 8 of 32
CY7C1440AV25
CY7C1442AV25
CY7C1446AV25
Interleaved Burst Address Table
(MODE = Floating or VDD)
Interleaved Burst Address Table
(MODE = Floating or VDD)
First
Address
A1: A0
Second
Address
A1: A0
Third
Address
A1: A0
Fourth
Address
A1: A0
First
Address
A1: A0
Second
Address
A1: A0
Third
Address
A1: A0
Fourth
Address
A1: A0
11
00
01
10
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CE1, CE2, CE3, ADSP, and ADSC must
remain inactive for the duration of tZZREC after the ZZ input
Linear Burst Address Table (MODE = GND)
First
Address
A1: A0
Second
Address
A1: A0
Third
Address
A1: A0
Fourth
Address
A1: A0
00
01
10
01
10
11
10
11
00
11
00
01
returns LOW
.
ZZ Mode Electrical Characteristics
Parameter
IDDZZ
Description
Sleep mode standby current
Device operation to ZZ
ZZ recovery time
Test Conditions
ZZ > VDD – 0.2V
Min.
Max.
100
Unit
mA
ns
tZZS
ZZ > VDD – 0.2V
2tCYC
tZZREC
tZZI
ZZ < 0.2V
2tCYC
0
ns
ZZ Active to sleep current
This parameter is sampled
This parameter is sampled
2tCYC
ns
tRZZI
ZZ Inactive to exit sleep current
ns
Document #: 38-05350 Rev. *E
Page 9 of 32
CY7C1440AV25
CY7C1442AV25
CY7C1446AV25
Truth Table [2, 3, 4, 5, 6, 7]
Operation
Add. Used CE1 CE2 CE3 ZZ ADSP ADSC ADV WRITE OE CLK
DQ
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Sleep Mode, Power Down
READ Cycle, Begin Burst
READ Cycle, Begin Burst
WRITE Cycle, Begin Burst
READ Cycle, Begin Burst
READ Cycle, Begin Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
WRITE Cycle, Continue Burst
WRITE Cycle, Continue Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
WRITE Cycle, Suspend Burst
None
None
H
L
X
L
X
X
H
X
H
X
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
L
L
X
X
L
X
X
X
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
L
L-H Tri-State
L-H Tri-State
L-H Tri-State
L-H Tri-State
L-H Tri-State
None
L
X
L
L
None
L
H
H
X
L
None
L
X
X
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
L
None
X
L
X
X
X
L
X
Tri-State
Q
External
External
External
External
External
Next
L-H
L
L
L
H
X
L
L-H Tri-State
L
L
H
H
H
H
H
X
X
H
X
H
H
X
X
H
X
L-H
L-H
D
Q
L
L
L
H
H
H
H
H
H
L
L
L
L
H
L
L-H Tri-State
L-H
L-H Tri-State
L-H
L-H Tri-State
X
X
H
H
X
H
X
X
H
H
X
H
X
X
X
X
X
X
X
X
X
X
X
X
H
H
H
H
H
H
H
H
H
H
H
H
Q
Next
L
H
L
Next
L
Q
Next
L
H
X
X
L
Next
L
L-H
L-H
L-H
D
D
Q
Next
L
L
Current
Current
Current
Current
Current
Current
H
H
H
H
H
H
H
H
H
H
L
H
L
L-H Tri-State
L-H
L-H Tri-State
Q
H
X
X
L-H
L-H
D
D
WRITE Cycle, Suspend Burst
L
Notes:
2. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.
3. WRITE = L when any one or more Byte Write enable signals and BWE = L or GW = L. WRITE = H when all Byte write enable signals, BWE, GW = H.
4. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
5. CE , CE , and CE are available only in the TQFP package. BGA package has only two chip selects CE and CE .
1
2
3
1
2
6. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW . Writes may occur only on subsequent clocks
X
after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to tri-state. OE is a
don't care for the remainder of the write cycle.
7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are Tri-State when OE is
inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW).
Document #: 38-05350 Rev. *E
Page 10 of 32
CY7C1440AV25
CY7C1442AV25
CY7C1446AV25
Truth Table for Read/Write[4,8,9]
Function (CY7C1440AV25)
Read
GW
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
BWE
H
L
BWD
X
H
H
H
H
H
H
H
H
L
BWC
X
H
H
H
H
L
BWB
X
H
H
L
BWA
X
H
L
Read
Write Byte A – ( DQA and DQPA )
Write Byte B – ( DQB and DQPB )
Write Bytes B, A
L
L
H
L
L
L
Write Byte C – ( DQC and DQPC )
Write Bytes C, A
L
H
H
L
H
L
L
L
Write Bytes C, B
L
L
H
L
Write Bytes C, B, A
Write Byte D – ( DQD and DQPD )
Write Bytes D, A
L
L
L
L
H
H
H
H
L
H
H
L
H
L
L
L
Write Bytes D, B
L
L
H
L
Write Bytes D, B, A
Write Bytes D, C
L
L
L
L
L
H
H
L
H
L
Write Bytes D, C, A
Write Bytes D, C, B
Write All Bytes
L
L
L
L
L
L
H
L
L
L
L
L
Write All Bytes
X
X
X
X
X
Truth Table for Read/Write[4,8,9]
Function (CY7C1442AV25)
Read
GW
H
BWE
BWB
BWA
H
L
L
L
L
L
X
H
H
L
X
H
L
Read
H
Write Byte A – ( DQA and DQPA )
Write Byte B – ( DQB and DQPB )
Write Bytes B, A
H
H
H
L
H
L
Write All Bytes
H
L
L
Truth Table for Read/Write[4,8,9]
Function (CY7C1446AV25)
GW
H
BWE
BWx
Read
H
L
L
L
X
Read
H
All BW = H
L
Write Byte x – (DQx and DQPx)
H
Write All Bytes
H
All BW = L
Notes:
8. BWx represents any byte write signal. To enable any byte write BW a Logic LOW signal should be applied at clock rise.Any number of bye writes can be enabled
x,
at the same time for any given write.
9. Table only lists a partial listing of the byte write combinations. Any combination of BW is valid. Appropriate write will be done based on which byte write is active.
X
Document #: 38-05350 Rev. *E
Page 11 of 32
CY7C1440AV25
CY7C1442AV25
CY7C1446AV25
Test Data-In (TDI)
IEEE 1149.1 Serial Boundary Scan (JTAG)
The TDI ball is used to serially input information into the
registers and can be connected to the input of any of the
registers. The register between TDI and TDO is chosen by the
instruction that is loaded into the TAP instruction register. For
information on loading the instruction register, see TAP
Controller State Diagram. TDI is internally pulled up and can
be unconnected if the TAP is unused in an application. TDI is
connected to the most significant bit (MSB) of any register.
(See Tap Controller Block Diagram.)
The CY7C1440AV25/CY7C1442AV25/CY7C1446AV25 incor-
porates a serial boundary scan test access port (TAP). This
part is fully compliant with IEEE Standard 1149.1.The TAP
operates using JEDEC-standard 2.5V/1.8V I/O logic level.
The
CY7C1440AV25/CY7C1442AV25/CY7C1446AV25
contains a TAP controller, instruction register, boundary scan
register, bypass register, and ID register.
Disabling the JTAG Feature
Test Data-Out (TDO)
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied
LOW(VSS) to prevent clocking of the device. TDI and TMS are
internally pulled up and may be unconnected. They may alter-
nately be connected to VDD through a pull-up resistor. TDO
should be left unconnected. Upon power-up, the device will
come up in a reset state which will not interfere with the
operation of the device.
The TDO output ball is used to serially clock data-out from the
registers. The output is active depending upon the current
state of the TAP state machine. The output changes on the
falling edge of TCK. TDO is connected to the least significant
bit (LSB) of any register. (See Tap Controller State Diagram.)
TAP Controller Block Diagram
TAP Controller State Diagram
0
Bypass Register
The 0/1 next to each state represents the value of TMS at the
rising edge of TCK.
2
1
0
0
0
Selection
Circuitry
Instruction Register
31 30 29
Identification Register
TEST-LOGIC
1
S
election
TDI
TDO
RESET
0
Circuitr
y
.
.
. 2 1
1
1
1
RUN-TEST/
IDLE
SELECT
DR-SCAN
SELECT
IR-SCAN
0
x
.
.
.
.
. 2 1
0
0
1
1
Boundary Scan Register
CAPTURE-DR
CAPTURE-IR
0
0
SHIFT-DR
0
SHIFT-IR
0
TCK
TMS
1
1
TAP CONTROLLER
1
1
EXIT1-DR
EXIT1-IR
0
0
PAUSE-DR
0
PAUSE-IR
0
Performing a TAP Reset
1
1
0
0
A RESET is performed by forcing TMS HIGH (VDD) for five
rising edges of TCK. This RESET does not affect the operation
of the SRAM and may be performed while the SRAM is
operating.
EXIT2-DR
1
EXIT2-IR
1
UPDATE-DR
UPDATE-IR
At power-up, the TAP is reset internally to ensure that TDO
comes up in a High-Z state.
1
0
1
0
TAP Registers
Registers are connected between the TDI and TDO balls and
allow data to be scanned into and out of the SRAM test
circuitry. Only one register can be selected at a time through
the instruction register. Data is serially loaded into the TDI ball
on the rising edge of TCK. Data is output on the TDO ball on
the falling edge of TCK.
Test Access Port (TAP)
Test Clock (TCK)
The test clock is used only with the TAP controller. All inputs
are captured on the rising edge of TCK. All outputs are driven
from the falling edge of TCK.
Instruction Register
Test MODE SELECT (TMS)
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the
TDI and TDO balls as shown in the Tap Controller Block
Diagram. Upon power-up, the instruction register is loaded
with the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as
described in the previous section.
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. It is allowable to
leave this ball unconnected if the TAP is not used. The ball is
pulled up internally, resulting in a logic HIGH level.
Document #: 38-05350 Rev. *E
Page 12 of 32
CY7C1440AV25
CY7C1442AV25
CY7C1446AV25
When the TAP controller is in the Capture-IR state, the two
least significant bits are loaded with a binary “01” pattern to
allow for fault isolation of the board-level serial test data path.
SAMPLE Z
The SAMPLE Z instruction causes the boundary scan register
to be connected between the TDI and TDO pins when the TAP
controller is in a Shift-DR state. The SAMPLE Z command puts
the output bus into a High-Z state until the next command is
given during the “Update IR” state.
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between the
TDI and TDO balls. This allows data to be shifted through the
SRAM with minimal delay. The bypass register is set LOW
(VSS) when the BYPASS instruction is executed.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When
the SAMPLE/PRELOAD instructions are loaded into the in-
struction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and output pins is cap-
tured in the boundary scan register.
Boundary Scan Register
The boundary scan register is connected to all the input and
bidirectional balls on the SRAM.
The user must be aware that the TAP controller clock can only
operate at a frequency up to 20 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because
there is a large difference in the clock frequencies, it is possi-
ble that during the Capture-DR state, an input or output will
undergo a transition. The TAP may then try to capture a signal
while in transition (metastable state). This will not harm the
device, but there is no guarantee as to the value that will be
captured. Repeatable results may not be possible.
The boundary scan register is loaded with the contents of the
RAM I/O ring when the TAP controller is in the Capture-DR
state and is then placed between the TDI and TDO balls when
the controller is moved to the Shift-DR state. The EXTEST,
SAMPLE/PRELOAD and SAMPLE Z instructions can be used
to capture the contents of the I/O ring.
The Boundary Scan Order tables show the order in which the
bits are connected. Each bit corresponds to one of the bumps
on the SRAM package. The MSB of the register is connected
to TDI, and the LSB is connected to TDO.
To guarantee that the boundary scan register will capture the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller's capture set-up plus
hold times (tCS and tCH). The SRAM clock input might not be
captured correctly if there is no way in a design to stop (or
slow) the clock during a SAMPLE/PRELOAD instruction. If this
is an issue, it is still possible to capture all other signals and
simply ignore the value of the CK and CK# captured in the
boundary scan register.
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired
into the SRAM and can be shifted out when the TAP controller
is in the Shift-DR state. The ID register has a vendor code and
other information described in the Identification Register
Definitions table.
Once the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the bound-
ary scan register between the TDI and TDO pins.
TAP Instruction Set
PRELOAD allows an initial data pattern to be placed at the
latched parallel outputs of the boundary scan register cells
prior to the selection of another boundary scan test operation.
Overview
Eight different instructions are possible with the three bit
instruction register. All combinations are listed in the
Instruction Codes table. Three of these instructions are listed
as RESERVED and should not be used. The other five instruc-
tions are described in detail below.
The shifting of data for the SAMPLE and PRELOAD phases
can occur concurrently when required—that is, while data
captured is shifted out, the preloaded data can be shifted in.
BYPASS
Instructions are loaded into the TAP controller during the
Shift-IR state when the instruction register is placed between
TDI and TDO. During this state, instructions are shifted
through the instruction register through the TDI and TDO balls.
To execute the instruction once it is shifted in, the TAP
controller needs to be moved into the Update-IR state.
When the BYPASS instruction is loaded in the instruction
register and the TAP is placed in a Shift-DR state, the bypass
register is placed between the TDI and TDO pins. The
advantage of the BYPASS instruction is that it shortens the
boundary scan path when multiple devices are connected
together on a board.
IDCODE
EXTEST
The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the instruction register. It also places the
instruction register between the TDI and TDO balls and allows
the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state.
The EXTEST instruction enables the preloaded data to be
driven out through the system output pins. This instruction also
selects the boundary scan register to be connected for serial
access between the TDI and TDO in the shift-DR controller
state.
The IDCODE instruction is loaded into the instruction register
upon power-up or whenever the TAP controller is given a test
logic reset state.
EXTEST OUTPUT BUS TRI-STATE
IEEE Standard 1149.1 mandates that the TAP controller be
able to put the output bus into a tri-state mode.
The boundary scan register has a special bit located at bit #89
(for 165-FBGA package) or bit #138 (for 209-FBGA package).
Document #: 38-05350 Rev. *E
Page 13 of 32
CY7C1440AV25
CY7C1442AV25
CY7C1446AV25
When this scan cell, called the “extest output bus tri-state”, is
latched into the preload register during the “Update-DR” state
in the TAP controller, it will directly control the state of the
output (Q-bus) pins, when the EXTEST is entered as the
current instruction. When HIGH, it will enable the output
buffers to drive the output bus. When LOW, this bit will place
the output bus into a High-Z condition.
loaded into that shift-register cell will latch into the preload
register. When the EXTEST instruction is entered, this bit will
directly control the output Q-bus pins. Note that this bit is
pre-set HIGH to enable the output when the device is
powered-up, and also when the TAP controller is in the
“Test-Logic-Reset” state.
Reserved
This bit can be set by entering the SAMPLE/PRELOAD or
EXTEST command, and then shifting the desired bit into that
cell, during the “Shift-DR” state. During “Update-DR”, the value
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
TAP Timing
1
2
3
4
5
6
Test Clock
(TCK)
t
t
t
CYC
TH
TL
t
t
t
t
TMSS
TDIS
TMSH
Test Mode Select
(TMS)
TDIH
Test Data-In
(TDI)
t
TDOV
t
TDOX
Test Data-Out
(TDO)
DON’T CARE
UNDEFINED
TAP AC Switching Characteristics Over the Operating Range[10, 11]
Parameter
Clock
tTCYC
tTF
Description
Min.
Max.
Unit
TCK Clock Cycle Time
TCK Clock Frequency
TCK Clock HIGH time
TCK Clock LOW time
50
ns
MHz
ns
20
tTH
20
20
tTL
ns
Output Times
tTDOV TCK Clock LOW to TDO Valid
tTDOX TCK Clock LOW to TDO Invalid
Set-up Times
tTMSS TMS Set-up to TCK Clock Rise
tTDIS
10
ns
ns
0
5
5
5
ns
ns
ns
TDI Set-up to TCK Clock Rise
Capture Set-up to TCK Rise
tCS
Hold Times
tTMSH
tTDIH
TMS Hold after TCK Clock Rise
TDI Hold after Clock Rise
5
5
5
ns
ns
ns
tCH
Capture Hold after Clock Rise
Notes:
10. t and t refer to the set-up and hold time requirements of latching data from the boundary scan register.
CS
CH
11. Test conditions are specified using the load in TAP AC test Conditions. t /t = 1 ns.
R
F
Document #: 38-05350 Rev. *E
Page 14 of 32
CY7C1440AV25
CY7C1442AV25
CY7C1446AV25
2.5V TAP AC Test Conditions
1.8V TAP AC Test Conditions
Input pulse levels .............................................. VSS to 2.5V
Input rise and fall time .................................................... 1 ns
Input timing reference levels ........................................1.25V
Output reference levels ................................................1.25V
Test load termination supply voltage............................ 1.25V
Input pulse levels .....................................0.2V to VDDQ – 0.2
Input rise and fall time ....................................................1 ns
Input timing reference levels .......................................... 0.9V
Output reference levels ................................................. 0.9V
Test load termination supply voltage ............................. 0.9V
2.5V TAP AC Output Load Equivalent
1.8V TAP AC Output Load Equivalent
0.9V
1.25V
50Ω
50Ω
TDO
TDO
ZO= 50Ω
20pF
ZO= 50Ω
20pF
TAP DC Electrical Characteristics And Operating Conditions
(0°C < TA < +70°C; VDD = 2.5V ±0.125V unless otherwise noted)[12]
Parameter
VOH1
Description
Test Conditions
VDDQ = 2.5V
VDDQ = 2.5V
DDQ = 1.8V
Min.
2.0
Max.
Unit
V
Output HIGH Voltage IOH = –1.0 mA
Output HIGH Voltage IOH = –100 µA
VOH2
2.1
V
V
1.6
V
VOL1
VOL2
Output LOW Voltage IOL = 1.0 mA
Output LOW Voltage IOL = 100 µA
VDDQ = 2.5V
VDDQ = 2.5V
0.4
0.2
0.2
V
V
VDDQ = 1.8V
V
VIH
VIL
Input HIGH Voltage
Input LOW Voltage
VDDQ = 2.5V
VDDQ = 1.8V
VDDQ = 2.5V
1.7
1.26
–0.3
–0.3
–5
VDD + 0.3
VDD + 0.3
0.7
V
V
V
VDDQ = 1.8V
0.36
V
IX
Input Load Current
GND < VIN < VDDQ
5
µA
Note:
12. All voltages referenced to V (GND).
SS
Document #: 38-05350 Rev. *E
Page 15 of 32
CY7C1440AV25
CY7C1442AV25
CY7C1446AV25
Identification Register Definitions
CY7C1440AV25 CY7C1442AV25 CY7C1446AV25
Instruction Field
Revision Number (31:29)
Device Depth (28:24)
(1M x36)
(2M x18)
(512K x72)
Description
000
000
000
Describes the version number.
01011
01011
01011
Reserved for Internal Use
Architecture/Memory Type(23:18)
Bus Width/Density(17:12)
Cypress JEDEC ID Code (11:1)
000000
100111
000000
010111
000000
110111
Defines memory type and architecture
Defines width and density
00000110100
00000110100
00000110100 Allows unique identification of SRAM
vendor.
ID Register Presence Indicator (0)
1
1
1
Indicates the presence of an ID
register.
Scan Register Sizes
Register Name
Bit Size (x36)
Bit Size (x18)
Bit Size (x72)
Instruction
Bypass
ID
3
1
3
1
3
1
32
89
–
32
89
–
32
–
Boundary Scan Order (165-ball FBGA package)
Boundary Scan Order (209-ball FBGA package)
138
Identification Codes
Instruction
EXTEST
Code
000
Description
Captures I/O ring contents.
IDCODE
001
Loads the ID register with the vendor ID code and places the register between TDI and
TDO. This operation does not affect SRAM operations.
SAMPLE Z
010
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM output drivers to a High-Z state.
RESERVED
011
100
Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Does not affect SRAM operation.
RESERVED
RESERVED
BYPASS
101
110
111
Do Not Use: This instruction is reserved for future use.
Do Not Use: This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does not affect SRAM
operations.
Document #: 38-05350 Rev. *E
Page 16 of 32
CY7C1440AV25
CY7C1442AV25
CY7C1446AV25
165-ball FBGA Boundary Scan Order [13,14]
CY7C1440AV25 (1M x 36), CY7C1442AV25 (2M x 18)
Bit #
1
Ball ID
Bit #
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
Ball ID
E11
D11
G10
F10
E10
D10
C11
A11
B11
A10
B10
A9
Bit #
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
Ball ID
A3
A2
B2
C2
B1
A1
C1
D1
E1
F1
Bit #
76
77
78
79
80
81
82
83
84
85
86
87
88
89
Ball ID
N1
N6
N7
N10
P11
P8
2
N2
3
P1
4
R1
5
R2
6
R8
P3
7
R9
R3
8
P9
P2
9
P10
R10
R11
H11
N11
M11
L11
K11
J11
M10
L10
K10
J10
H9
R4
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
P4
G1
D2
E2
F2
N5
P6
B9
R6
C10
A8
Internal
G2
H1
H3
J1
B8
A7
B7
B6
K1
L1
A6
M1
J2
B5
A5
A4
B4
B3
H10
G11
F11
K2
L2
M2
Notes:
13. Balls which are NC (No Connect) are Pre-Set LOW.
14. Bit# 89 is Pre-Set HIGH.
Document #: 38-05350 Rev. *E
Page 17 of 32
CY7C1440AV25
CY7C1442AV25
CY7C1446AV25
209-ball FBGA Boundary Scan Order [13,15]
CY7C1446AV25 (512K x 72)
Bit #
1
Ball ID
Bit #
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
Ball ID
F6
Bit #
71
Ball ID
Bit #
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
Ball ID
K3
W6
V6
U6
H6
C6
B6
A6
A5
B5
C5
D5
D4
C4
A4
B4
C3
B3
A3
A2
A1
B2
B1
C2
C1
D2
D1
E1
E2
F2
F1
G1
G2
H2
H1
J2
2
K8
72
K4
3
K9
73
K6
4
W7
V7
K10
J11
J10
H11
H10
G11
G10
F11
F10
E10
E11
D11
D10
C11
C10
B11
B10
A11
A10
C9
74
K2
5
75
L2
6
U7
76
L1
7
T7
77
M2
M1
N2
N1
P2
8
V8
78
9
U8
79
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
T8
80
V9
81
U9
82
P1
P6
83
R2
R1
T2
W11
W10
V11
V10
U11
U10
T11
T10
R11
R10
P11
P10
N11
N10
M11
M10
L11
L10
K11
M6
84
85
86
T1
87
U2
U1
V2
88
89
90
V1
91
W2
W1
T6
92
93
B9
94
U3
V3
A9
95
D7
96
T4
C8
97
T5
B8
98
U4
V4
A8
99
D8
100
101
102
103
104
105
5W
5V
C7
B7
5U
Internal
A7
J1
L6
D6
K1
N6
J6
G6
Note:
15. Bit# 138 is Pre-Set HIGH.
Document #: 38-05350 Rev. *E
Page 18 of 32
CY7C1440AV25
CY7C1442AV25
CY7C1446AV25
DC Input Voltage ................................... –0.5V to VDD + 0.5V
Current into Outputs (LOW)......................................... 20 mA
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
Storage Temperature .................................–65°C to +150°C
Latch-up Current.................................................... > 200 mA
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Operating Range
Supply Voltage on VDD Relative to GND........ –0.3V to +3.6V
Supply Voltage on VDDQ Relative to GND ......–0.3V to +VDD
Ambient
Temperature
Range
VDD
VDDQ
DC Voltage Applied to Outputs
Commercial 0°C to +70°C 2.5V + 5%
1.7V to VDD
in Tri-State........................................... –0.5V to VDDQ + 0.5V
Industrial
–40°C to +85°C
Electrical Characteristics Over the Operating Range [16, 17]
DC Electrical Characteristics Over the Operating Range
Parameter
VDD
Description
Power Supply Voltage
I/O Supply Voltage
Test Conditions
Min.
2.375
2.375
1.7
Max.
2.625
2.625
1.9
Unit
V
V
VDDQ
for 2.5V I/O
for 1.8V I/O
V
VOH
VOL
VIH
VIL
IX
Output HIGH Voltage
Output LOW Voltage
for 2.5V I/O, IOH = –1.0 mA
for 1.8V I/O, IOH = –100 µA
for 2.5V I/O, IOL = 1.0 mA
for 1.8V I/O, IOL= 100 µA
2.0
V
1.6
V
0.4
0.2
V
V
Input HIGH Voltage[16] for 2.5V I/O
1.7
1.26
–0.3
–0.3
–5
VDD + 0.3V
V
for 1.8V I/O
V
DD + 0.3V
V
Input LOW Voltage[16]
for 2.5V I/O
for 1.8V I/O
0.7
V
0.36
5
V
Input Leakage Current GND ≤ VI ≤ VDDQ
except ZZ and MODE
µA
Input Current of MODE Input = VSS
Input = VDD
–30
–5
µA
µA
5
Input Current of ZZ
Input = VSS
Input = VDD
µA
30
5
µA
IOZ
IDD
Output Leakage Current GND ≤ VI ≤ VDDQ, Output Disabled
–5
µA
VDD Operating Supply VDD = Max., IOUT = 0 mA,
4-ns cycle, 250 MHz
5-ns cycle, 200 MHz
6-ns cycle, 167 MHz
All speeds
435
385
335
185
mA
mA
mA
mA
Current
f = fMAX = 1/tCYC
ISB1
ISB2
ISB3
Automatic CE
Power-down
Current—TTL Inputs
VDD = Max, Device Deselected,
VIN ≥ VIH or VIN ≤ VIL
f = fMAX = 1/tCYC
Automatic CE
Power-down
Current—CMOS Inputs f = 0
VDD = Max, Device Deselected,
VIN ≤ 0.3V or VIN > VDDQ – 0.3V,
All speeds
120
160
135
mA
mA
mA
Automatic CE
Power-down
Current—CMOS Inputs f = fMAX = 1/tCYC
V
DD = Max, Device Deselected, or All speeds
VIN ≤ 0.3V or VIN > VDDQ – 0.3V
ISB4
Automatic CE
VDD = Max, Device Deselected,
All speeds
Power-down
Current—TTL Inputs
VIN ≥ VIH or VIN ≤ VIL, f = 0
Notes:
16. Overshoot: V (AC) < V +1.5V (Pulse width less than t
/2), undershoot: V (AC) > –2V (Pulse width less than t
/2).
IH
DD
CYC
IL
CYC
17. TPower-up: Assumes a linear ramp from 0V to V (min.) within 200 ms. During this time V < V and V
< V
.
DD
IH
DD
DDQ
DD
Document #: 38-05350 Rev. *E
Page 19 of 32
CY7C1440AV25
CY7C1442AV25
CY7C1446AV25
Capacitance[18]
100 TQFP
Max.
165 FBGA
Max.
209 FBGA
Parameter
Description
Test Conditions
Max
Unit
pF
CIN
Input Capacitance
TA = 25°C, f = 1 MHz,
6.5
3
7
7
6
5
5
7
VDD/VDDQ = 2.5V
CCLK
CI/O
Clock Input Capacitance
Input/Output Capacitance
pF
5.5
pF
Thermal Resistance[18]
100 TQFP
Package
165 FBGA
Package
209 FBGA
Package
Parameter
Description
Test Conditions
Unit
ΘJA
Thermal Resistance
(Junction to Ambient)
Test conditions follow
standard test methods and
procedures for measuring
thermal impedance, per
EIA/JESD51.
25.21
20.8
25.31
°C/W
ΘJC
Thermal Resistance
(Junction to Case)
2.28
3.2
4.48
°C/W
AC Test Loads and Waveforms
2.5V I/O Test Load
R = 1667Ω
2.5V
OUTPUT
OUTPUT
ALL INPUT PULSES
90%
VDDQ
GND
90%
10%
Z = 50Ω
0
R = 50Ω
10%
L
5 pF
R = 1538Ω
≤ 1 ns
≤ 1 ns
INCLUDING
JIG AND
SCOPE
V = 1.25V
T
(a)
(b)
(c)
1.8V I/O Test Load
R = 14 KΩ
1.8V
OUTPUT
R = 50Ω
OUTPUT
ALL INPUT PULSES
90%
VDDQ - 0.2
0.2
90%
10%
Z = 50Ω
0
10%
L
5 pF
R = 14 KΩ
≤ 1 ns
≤ 1 ns
V = 0.9V
(a)T
INCLUDING
JIG AND
SCOPE
(b)
(c)
Note:
18. Tested initially and after any design or process change that may affect these parameters.
Document #: 38-05350 Rev. *E
Page 20 of 32
CY7C1440AV25
CY7C1442AV25
CY7C1446AV25
Switching Characteristics Over the Operating Range[23, 24]
–250
–200
–167
Parameter
tPOWER
Description
VDD(Typical) to the first Access[19]
Min. Max. Min. Max. Min. Max.
Unit
1
1
1
ms
Clock
tCYC
Clock Cycle Time
Clock HIGH
4.0
1.5
1.5
5.0
2.0
2.0
6.0
2.4
2.4
ns
ns
ns
tCH
tCL
Clock LOW
Output Times
tCO
Data Output Valid After CLK Rise
Data Output Hold After CLK Rise
Clock to Low-Z[20, 21, 22]
2.6
3.2
3.4
ns
ns
ns
ns
ns
ns
ns
tDOH
1.0
1.0
1.5
1.3
1.5
1.5
tCLZ
tCHZ
Clock to High-Z[20, 21, 22]
2.6
2.6
3.0
3.0
3.4
3.4
tOEV
OE LOW to Output Valid
tOELZ
tOEHZ
Set-up Times
tAS
OE LOW to Output Low-Z[20, 21, 22]
OE HIGH to Output High-Z[20, 21, 22]
0
0
0
2.6
3.0
3.4
Address Set-up Before CLK Rise
ADSC, ADSP Set-up Before CLK Rise
ADV Set-up Before CLK Rise
1.2
1.2
1.2
1.2
1.2
1.2
1.4
1.4
1.4
1.4
1.4
1.4
1.5
1.5
1.5
1.5
1.5
1.5
ns
ns
ns
ns
ns
ns
tADS
tADVS
tWES
GW, BWE, BWX Set-up Before CLK Rise
Data Input Set-up Before CLK Rise
Chip Enable Set-Up Before CLK Rise
tDS
tCES
Hold Times
tAH
Address Hold After CLK Rise
ADSP, ADSC Hold After CLK Rise
ADV Hold After CLK Rise
0.3
0.3
0.3
0.3
0.3
0.3
0.4
0.4
0.4
0.4
0.4
0.4
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
ns
ns
tADH
tADVH
tWEH
GW, BWE, BWX Hold After CLK Rise
Data Input Hold After CLK Rise
Chip Enable Hold After CLK Rise
tDH
tCEH
Notes:
19. This part has a voltage regulator internally; t
is the time that the power needs to be supplied above V ( minimum) initially before a read or write operation
DD
POWER
can be initiated.
20. t
, t
,t
, and t
are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
CHZ CLZ OELZ
OEHZ
21. At any given voltage and temperature, t
is less than t
and t
is less than t
to eliminate bus contention between SRAMs when sharing the same
CLZ
OEHZ
OELZ
CHZ
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions.
22. This parameter is sampled and not 100% tested.
23. Timing reference level is 1.25V when V
= 2.5V and 0.9V when V
= 1.8V .
DDQ
DDQ
24. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
Document #: 38-05350 Rev. *E
Page 21 of 32
CY7C1440AV25
CY7C1442AV25
CY7C1446AV25
Switching Waveforms
Read Cycle Timing[25]
t
CYC
CLK
t
t
CL
CH
t
t
ADH
ADS
ADSP
ADSC
t
t
ADH
ADS
t
t
AH
AS
A1
A2
A3
ADDRESS
Burst continued with
new base address
t
t
WEH
WES
GW, BWE,
BWx
Deselect
cycle
t
t
CEH
CES
CE
t
t
ADVH
ADVS
ADV
OE
ADV
suspends
burst.
t
t
OEV
CO
t
t
OEHZ
t
OELZ
t
CHZ
DOH
t
CLZ
t
Q(A2)
Q(A2 + 1)
Q(A2 + 2)
Q(A2 + 3)
Q(A2)
Q(A2 + 1)
Q(A1)
Data Out (Q)
High-Z
CO
Burst wraps around
to its initial state
Single READ
BURST READ
DON’T CARE
UNDEFINED
Note:
25. On this diagram, when CE is LOW: CE is LOW, CE is HIGH and CE is LOW. When CE is HIGH: CE is HIGH or CE is LOW or CE is HIGH.
1
2
3
1
2
3
Document #: 38-05350 Rev. *E
Page 22 of 32
CY7C1440AV25
CY7C1442AV25
CY7C1446AV25
Switching Waveforms (continued)
Write Cycle Timing[25, 26]
t
CYC
CLK
t
t
CL
CH
t
t
ADH
ADS
ADSP
ADSC extends burst
t
t
ADH
ADS
t
t
ADH
ADS
ADSC
ADDRESS
BWE,
t
t
AH
AS
A1
A2
A3
Byte write signals are
ignored for first cycle when
ADSP initiates burst
t
t
WEH
WES
BW
X
t
t
WEH
WES
GW
CE
t
t
CEH
CES
t
t
ADVH
ADVS
ADV
OE
ADV suspends burst
t
t
DH
DS
Data In (D)
D(A2)
D(A2 + 1)
D(A2 + 1)
D(A2 + 2)
D(A2 + 3)
D(A3)
D(A3 + 1)
D(A3 + 2)
D(A1)
High-Z
t
OEHZ
Data Out (Q)
BURST READ
Single WRITE
BURST WRITE
Extended BURST WRITE
DON’T CARE
UNDEFINED
Note:
26.
Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW LOW.
X
Document #: 38-05350 Rev. *E
Page 23 of 32
CY7C1440AV25
CY7C1442AV25
CY7C1446AV25
Switching Waveforms (continued)
Read/Write Cycle Timing[25, 27, 28]
t
CYC
CLK
t
t
CL
CH
t
t
ADH
ADS
ADSP
ADSC
t
t
AH
AS
A1
A2
A3
A4
A5
A6
ADDRESS
BWE,
t
t
WEH
WES
BW
X
t
t
CEH
CES
CE
ADV
OE
t
t
DH
t
CO
DS
t
OELZ
Data In (D)
High-Z
High-Z
D(A3)
D(A5)
D(A6)
t
t
OEHZ
CLZ
Data Out (Q)
Q(A1)
Q(A2)
Q(A4)
Q(A4+1)
Q(A4+2)
Q(A4+3)
Back-to-Back READs
Single WRITE
BURST READ
Back-to-Back
WRITEs
DON’T CARE
UNDEFINED
Notes:
27. The data bus (Q) remains in high-Z following a WRITE cycle, unless a new read access is initiated by ADSP or ADSC.
28. GW is HIGH.
Document #: 38-05350 Rev. *E
Page 24 of 32
CY7C1440AV25
CY7C1442AV25
CY7C1446AV25
Switching Waveforms (continued)
ZZ Mode Timing[29, 30]
CLK
t
t
ZZ
ZZREC
ZZ
t
ZZI
I
SUPPLY
I
DDZZ
t
RZZI
ALL INPUTS
(except ZZ)
DESELECT or READ Only
Outputs (Q)
High-Z
DON’T CARE
Notes:
29. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device.
30. DQs are in high-Z when exiting ZZ sleep mode.
Document #: 38-05350 Rev. *E
Page 25 of 32
CY7C1440AV25
CY7C1442AV25
CY7C1446AV25
Ordering Information
Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or
visit www.cypress.com for actual products offered.
Speed
(MHz)
Package
Diagram
Operating
Range
Ordering Code
Part and Package Type
167 CY7C1440AV25-167AXC 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
CY7C1442AV25-167AXC
Commercial
CY7C1440AV25-167BZC 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4mm)
CY7C1442AV25-167BZC
CY7C1440AV25-167BZXC 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4mm) Lead-Free
CY7C1442AV25-167BZXC
CY7C1446AV25-167BGC 51-85167 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm)
CY7C1446AV25-167BGXC
CY7C1440AV25-167AXI
CY7C1442AV25-167AXI
CY7C1440AV25-167BZI
CY7C1442AV25-167BZI
209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Lead-Free
51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
lndustrial
51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4mm)
CY7C1440AV25-167BZXI 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4mm) Lead-Free
CY7C1442AV25-167BZXI
CY7C1446AV25-167BGI
CY7C1446AV25-167BGXI
51-85167 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm)
209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Lead-Free
200 CY7C1440AV25-200AXC 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
CY7C1442AV25-200AXC
Commercial
CY7C1440AV25-200BZC 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4mm)
CY7C1442AV25-200BZC
CY7C1440AV25-200BZXC 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4mm) Lead-Free
CY7C1442AV25-200BZXC
CY7C1446AV25-200BGC 51-85167 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm)
CY7C1446AV25-200BGXC
CY7C1440AV25-200AXI
CY7C1442AV25-200AXI
CY7C1440AV25-200BZI
CY7C1442AV25-200BZI
209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Lead-Free
51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
lndustrial
51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4mm)
CY7C1440AV25-200BZXI 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4mm) Lead-Free
CY7C1442AV25-200BZXI
CY7C1446AV25-200BGI
CY7C1446AV25-200BGXI
51-85167 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm)
209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Lead-Free
Document #: 38-05350 Rev. *E
Page 26 of 32
CY7C1440AV25
CY7C1442AV25
CY7C1446AV25
Ordering Information (continued)
Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or
visit www.cypress.com for actual products offered.
Speed
(MHz)
Package
Diagram
Operating
Range
Ordering Code
Part and Package Type
250 CY7C1440AV25-250AXC 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
CY7C1442AV25-250AXC
Commercial
CY7C1440AV25-250BZC 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4mm)
CY7C1442AV25-250BZC
CY7C1440AV25-250BZXC 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4mm) Lead-Free
CY7C1442AV25-250BZXC
CY7C1446AV25-250BGC 51-85167 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm)
CY7C1446AV25-250BGXC
CY7C1440AV25-250AXI
CY7C1442AV25-250AXI
CY7C1440AV25-250BZI
CY7C1442AV25-250BZI
209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Lead-Free
51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
Industrial
51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4mm)
CY7C1440AV25-250BZXI 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4mm) Lead-Free
CY7C1442AV25-250BZXI
CY7C1446AV25-250BGI
CY7C1446AV25-250BGXI
51-85167 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm)
209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Lead-Free
Document #: 38-05350 Rev. *E
Page 27 of 32
CY7C1440AV25
CY7C1442AV25
CY7C1446AV25
Package Diagrams
100-pin TQFP (14 x 20 x 1.4 mm) (51-85050)
16.00 0.20
1.40 0.05
14.00 0.10
100
81
80
1
0.30 0.08
0.65
TYP.
12° 1°
(8X)
SEE DETAIL
A
30
51
31
50
0.20 MAX.
1.60 MAX.
R 0.08 MIN.
0.20 MAX.
0° MIN.
SEATING PLANE
STAND-OFF
0.05 MIN.
0.15 MAX.
NOTE:
0.25
1. JEDEC STD REF MS-026
GAUGE PLANE
2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH
MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE
R 0.08 MIN.
0.20 MAX.
BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH
3. DIMENSIONS IN MILLIMETERS
0°-7°
0.60 0.15
0.20 MIN.
51-85050-*B
1.00 REF.
DETAIL
A
Document #: 38-05350 Rev. *E
Page 28 of 32
CY7C1440AV25
CY7C1442AV25
CY7C1446AV25
Package Diagrams (continued)
165-ball FBGA (15 x 17 x 1.4 mm) (51-85165)
PIN 1 CORNER
BOTTOM VIEW
TOP VIEW
Ø0.05 M C
PIN 1 CORNER
Ø0.25 M C A B
Ø0.45 0.05(165X)
1
2
3
4
5
6
7
8
9
10
11
11 10
9
8
7
6
5
4
3
2
1
A
B
A
B
C
D
C
D
E
E
F
F
G
G
H
J
H
J
K
K
L
L
M
M
N
P
R
N
P
R
A
1.00
5.00
10.00
B
15.00 0.10
0.15(4X)
SEATING PLANE
51-85165-*A
C
Document #: 38-05350 Rev. *E
Page 29 of 32
CY7C1440AV25
CY7C1442AV25
CY7C1446AV25
Package Diagrams (continued)
209-ball FBGA (14 x 22 x 1.76 mm) (51-85167)
51-85167-**
i486 is a trademark, and Intel and Pentium are registered trademarks of Intel Corporation. PowerPC is a trademark of IBM
Corporation. All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-05350 Rev. *E
Page 30 of 32
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY7C1440AV25
CY7C1442AV25
CY7C1446AV25
Document History Page
Document Title:CY7C1440AV25/CY7C1442AV25/CY7C1446AV25 36-Mbit (1M x 36/2M x 18/512K x 72)
Pipelined Sync SRAM
Document Number: 38-05350
Issue
Date
Orig. of
Change
REV.
**
ECN NO.
Description of Change
124417 03/04/03
254909 See ECN
CJM
SYT
New Data Sheet
*A
Part number changed from previous revision. New and old part number differ by
the letter “A”
Modified Functional Block diagrams
Modified switching waveforms
Added Boundary scan information
Added IDD, IX and ISB values in the DC Electrical Characteristics
Added tPOWER specifications in Switching Characteristics table
Removed 119 PBGA Package
Changed 165 FBGA Package from BB165C (15 x 17 x 1.20 mm) to BB165
(15 x 17 x 1.40 mm)
Changed 209-Lead PBGA BG209 (14 x 22 x 2.20 mm) to BB209A
(14 x 22 x 1.76 mm)
*B
303533 See ECN
SYT
Changed H9 pin from VSSQ to VSS on the Pin Configuration table for 209 FBGA on
Page # 6
Changed the test condition from VDD = Min. to VDD = Max for VOL in the Electrical
Characteristics table
Replaced ΘJA and ΘJC from TBD to respective Thermal Values for All Packages
on the Thermal Resistance Table
Changed IDD from 450, 400 & 350 mA to 435,385 & 335 mA for 250, 200 and 167
Mhz respectively
Changed ISB1 from 190, 180 and 170 mA to 185 mA for 250, 200 and 167 Mhz
respectively
Changed ISB2 from 80 mA to 100 mA for all frequencies
Changed ISB3 from 180, 170 & 160 mA to 160 mA for 250, 200 and 167 Mhz
respectively
Changed ISB4 from 100 mA to 110 mA for all frequencies
Changed CIN, CCLK and CI/O to 6.5, 3 and 5.5 pF from 5, 5 and 7 pF for TQFP
Package
Changed tCO from 3.0 to 3.2 ns and tDOH from 1.3 ns to 1.5 ns for 200 Mhz speed bin
Added lead-free information for 100-pin TQFP, 165 FBGA and 209 FBGA
Packages
*C
331778 See ECN
SYT
Modified Address Expansion balls in the pinouts for 165 FBGA and 209 FBGA
Package as per JEDEC standards and updated the Pin Definitions accordingly
Modified VOL, VOH test conditions
Changed CIN, CCLK and CI/O to 7, 7and 6 pF from 5, 5 and 7 pF for 165 FBGA
Package
Added Industrial Temperature Grade
Changed ISB2 and ISB4 from 100 and 110 mA to 120 and 135 mA respectively
Updated the Ordering Information by Shading and Unshading MPNs as per avail-
ability
*D
417509 See ECN
RXU
Converted from Preliminary to Final
Changed address of Cypress Semiconductor Corporation on Page# 1 from “3901
North First Street” to “198 Champion Court”
Changed IX current value in MODE from –5 & 30 µA to –30 & 5 µA respectively
and also Changed IX current value in ZZ from –30 & 5 µA to –5 & 30 µA respectively
on page# 20
Modified test condition from VIH < VDD to VIH < VDD
Modified “Input Load” to “Input Leakage Current except ZZ and MODE” in the
Electrical Characteristics Table
Replaced Package Name column with Package Diagram in the Ordering
Information table
Replaced Package Diagram of 51-85050 from *A to *B
Updated the Ordering Information Table
Document #: 38-05350 Rev. *E
Page 31 of 32
CY7C1440AV25
CY7C1442AV25
CY7C1446AV25
Document Title:CY7C1440AV25/CY7C1442AV25/CY7C1446AV25 36-Mbit (1M x 36/2M x 18/512K x 72)
Pipelined Sync SRAM
Document Number: 38-05350
Issue
Date
Orig. of
Change
REV.
ECN NO.
Description of Change
*E
473229 See ECN
VKN
Added the Maximum Rating for Supply Voltage on VDDQ Relative to GND
Changed tTH, tTL from 25 ns to 20 ns and tTDOV from 5 ns to 10 ns in TAP AC
Switching Characteristics table
Updated the Ordering Information table.
Document #: 38-05350 Rev. *E
Page 32 of 32
相关型号:
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