CY7C1440AV33-250AXCT [CYPRESS]
Cache SRAM, 1MX36, 2.6ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, MS-026, TQFP-100;型号: | CY7C1440AV33-250AXCT |
厂家: | CYPRESS |
描述: | Cache SRAM, 1MX36, 2.6ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, MS-026, TQFP-100 静态存储器 内存集成电路 |
文件: | 总33页 (文件大小:572K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
CY7C1440AV33
36-Mbit (1 M × 36) Pipelined Sync SRAM
36-Mbit (1
M × 36) Pipelined Sync SRAM
Features
Functional Description
■ Supports bus operation up to 250 MHz
■ Available speed grades are 250 and 167 MHz
■ Registered inputs and outputs for pipelined operation
■ 3.3 V core power supply
The CY7C1440AV33 SRAM integrates 1 M × 36 SRAM cells with
advanced synchronous peripheral circuitry and a two-bit counter
for internal burst operation. All synchronous inputs are gated by
registers controlled by a positive-edge-triggered clock input
(CLK). The synchronous inputs include all addresses, all data
inputs, address-pipelining chip enable (CE1), depth-expansion
chip enables (CE2 and CE3), burst control inputs (ADSC, ADSP,
and ADV), write enables (BWX and BWE), and global write (GW).
Asynchronous inputs include the output enable (OE) and the ZZ
pin.
■ 2.5 V/3.3 V I/O power supply
■ Fast clock-to-output times
❐ 2.6 ns (for 250-MHz device)
Addresses and chip enables are registered at rising edge of
clock when either address strobe processor (ADSP) or address
strobe controller (ADSC) are active. Subsequent burst
addresses can be internally generated as controlled by the
advance pin (ADV).
■ Provide high-performance 3-1-1-1 access rate
■ User-selectable burst counter supporting Intel Pentium
interleaved or linear burst sequences
■ Separate processor and controller address strobes
■ Synchronous self-timed writes
Address, data inputs, and write controls are registered on-chip
to initiate a self-timed write cycle.This part supports byte write
operations (see pin descriptions and truth table for further
details). Write cycles can be one to two or four bytes wide as
■ Asynchronous output enable
■ Single cycle chip deselect
controlled by the byte write control inputs. GW when active
causes all bytes to be written.
LOW
■ CY7C1440AV33 available in Pb-free 100-pin TQFP package,
Pb-free 165-ball FBGA package.
The CY7C1440AV33 operates from a +3.3 V core power supply
while all outputs may operate with either a +2.5 or +3.3 V supply.
■ IEEE 1149.1 JTAG-compatible boundary scan
■ “ZZ” sleep mode option
All
inputs
and
outputs
are
JEDEC-standard
JESD8-5-compatible.
Selection Guide
Description
Maximum access time
250 MHz
2.6
167 MHz Unit
3.4
375
120
ns
Maximum operating current
475
mA
mA
Maximum CMOS standby current
120
Cypress Semiconductor Corporation
Document Number: 38-05383 Rev. *L
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised September 20, 2012
CY7C1440AV33
Logic Block Diagram – CY7C1440AV33
A0, A1, A
ADDRESS
REGISTER
2
A[1:0]
MODE
Q1
ADV
CLK
BURST
COUNTER
AND
CLR
Q0
LOGIC
ADSC
ADSP
DQ
BYTE
WRITE REGISTER
D ,DQPD
DQ
BYTE
WRITE DRIVER
D ,DQPD
BW
D
DQ
BYTE
WRITE DRIVER
C ,DQPC
DQ
BYTE
WRITE REGISTER
C ,DQPC
BW
C
OUTPUT
BUFFERS
OUTPUT
REGISTERS
MEMORY
ARRAY
DQ s
SENSE
AMPS
DQP
DQP
DQP
A
DQ
BYTE
WRITE DRIVER
B ,DQPB
E
DQ
BYTE
WRITE REGISTER
B ,DQPB
B
C
BW
BW
B
A
DQPD
DQ
BYTE
WRITE DRIVER
A ,DQPA
DQ
A ,DQPA
BYTE
WRITE REGISTER
BWE
INPUT
REGISTERS
GW
ENABLE
REGISTER
PIPELINED
ENABLE
CE
CE
CE
1
2
3
OE
SLEEP
CONTROL
ZZ
Document Number: 38-05383 Rev. *L
Page 2 of 33
CY7C1440AV33
Contents
Pin Configurations ...........................................................4
Pin Definitions ..................................................................6
Functional Overview ........................................................7
Single Read Accesses ................................................7
Single Write Accesses Initiated by ADSP ...................7
Single Write Accesses Initiated by ADSC ...................8
Burst Sequences .........................................................8
Sleep Mode .................................................................8
Interleaved Burst Address Table .................................8
Linear Burst Address Table .........................................8
ZZ Mode Electrical Characteristics ..............................8
Truth Table ........................................................................9
Truth Table for Read/Write ............................................10
IEEE 1149.1 Serial Boundary Scan (JTAG) ..................11
Disabling the JTAG Feature ......................................11
Test Access Port (TAP) .............................................11
PERFORMING A TAP RESET ..................................11
TAP REGISTERS ......................................................11
TAP Instruction Set ...................................................11
TAP Controller State Diagram .......................................13
TAP Controller Block Diagram ......................................14
TAP Timing ......................................................................14
TAP AC Switching Characteristics ...............................15
3.3 V TAP AC Test Conditions .......................................15
3.3 V TAP AC Output Load Equivalent .........................15
2.5 V TAP AC Test Conditions .......................................15
2.5 V TAP AC Output Load Equivalent .........................15
TAP DC Electrical Characteristics and
Operating Conditions .....................................................16
Identification Register Definitions ................................17
Scan Register Sizes .......................................................17
Instruction Codes ...........................................................17
Boundary Scan Order ....................................................18
Maximum Ratings ...........................................................19
Operating Range .............................................................19
Electrical Characteristics ...............................................19
Capacitance ....................................................................20
Thermal Resistance ........................................................20
AC Test Loads and Waveforms .....................................20
Switching Characteristics ..............................................21
Switching Waveforms ....................................................22
Ordering Information ......................................................26
Ordering Code Definitions .........................................26
Package Diagrams ..........................................................27
Acronyms ........................................................................29
Document Conventions .................................................29
Units of Measure .......................................................29
Document History Page .................................................30
Sales, Solutions, and Legal Information ......................33
Worldwide Sales and Design Support .......................33
Products ....................................................................33
PSoC Solutions .........................................................33
Document Number: 38-05383 Rev. *L
Page 3 of 33
CY7C1440AV33
Pin Configurations
Figure 1. 100-pin TQFP (14 × 20 × 1.4 mm) pinout
DQPC
DQC
DQc
VDDQ
VSSQ
DQC
DQC
DQC
DQC
VSSQ
VDDQ
DQC
DQC
NC
DQPB
DQB
DQB
VDDQ
VSSQ
DQB
DQB
DQB
DQB
VSSQ
VDDQ
DQB
DQB
VSS
1
2
3
4
5
6
7
8
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
VDD
NC
VSS
NC
VDD
ZZ
CY7C1440AV33
(1 M × 36)
DQD
DQD
VDDQ
VSSQ
DQD
DQD
DQD
DQD
VSSQ
VDDQ
DQD
DQD
DQPD
DQA
DQA
VDDQ
VSSQ
DQA
DQA
DQA
DQA
VSSQ
VDDQ
DQA
DQA
DQPA
Document Number: 38-05383 Rev. *L
Page 4 of 33
CY7C1440AV33
Pin Configurations (continued)
Figure 2. 165-ball FBGA (15 × 17 × 1.4 mm) pinout
CY7C1440AV33 (1 M × 36)
1
2
3
4
5
6
7
8
9
10
A
11
NC
NC/288M
NC/144M
DQPC
A
B
C
D
CE1
BWC
BWD
VSS
VDD
BWB
BWA
VSS
VSS
CE3
CLK
VSS
VSS
ADSC
OE
A
BWE
GW
VSS
VSS
ADV
ADSP
VDDQ
VDDQ
A
CE2
VDDQ
VDDQ
A
NC/576M
DQPB
DQB
NC
VSS
VDD
NC/1G
DQB
DQC
DQC
DQC
DQC
DQC
NC
DQC
DQC
DQC
NC
VDDQ
VDDQ
VDDQ
NC
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
NC
DQB
DQB
DQB
NC
DQB
DQB
DQB
ZZ
E
F
G
H
J
DQD
DQD
DQD
DQD
DQD
DQD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
DQA
DQA
DQA
DQA
DQA
DQA
K
L
DQD
DQPD
NC
DQD
NC
VDDQ
VDDQ
A
VDD
VSS
A
VSS
NC
VSS
A
VSS
NC
VDD
VSS
A
VDDQ
VDDQ
A
DQA
NC
A
DQA
DQPA
A
M
N
P
NC/72M
TDI
A1
TDO
A0
MODE
A
A
A
TMS
TCK
A
A
A
A
R
Document Number: 38-05383 Rev. *L
Page 5 of 33
CY7C1440AV33
Pin Definitions
Name
I/O
Description
A0, A1, A
Input-
Address inputs used to select one of the address locations. Sampled at the rising edge of the CLK
synchronous if ADSP or ADSC is active LOW, and CE1, CE2, and CE3[1]are sampled active. A1:A0 are fed to the
two-bit counter.
BWA, BWB,
BWC, BWD synchronous
Input-
Byte write select inputs, active LOW. Qualified with BWE to conduct byte writes to the SRAM. Sampled
on the rising edge of CLK.
GW
Input-
Global write enable input, active LOW. When asserted LOW on the rising edge of CLK, a global write
synchronous is conducted (all bytes are written, regardless of the values on BWX and BWE).
Input- Byte write enable input, active LOW. Sampled on the rising edge of CLK. This signal must be asserted
synchronous LOW to conduct a byte write.
BWE
CLK
CE1
Input-
clock
Clock input. Used to capture all synchronous inputs to the device. Also used to increment the burst
counter when ADV is asserted LOW, during a burst operation.
Input-
Chip enable 1 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2
synchronous and CE3 to select/deselect the device. ADSP is ignored if CE1 is HIGH. CE1 is sampled only when a
new external address is loaded.
CE2
CE3
Input-
Chip enable 2 input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1
synchronous and CE3 to select/deselect the device. CE2 is sampled only when a new external address is loaded.
Input- Chip enable 3 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1
synchronous and CE2 to select/deselect the device. Not available for AJ package version. Not connected for BGA.
Where referenced, CE3 is assumed active throughout this document for BGA. CE3 is sampled only when
a new external address is loaded.
OE
Input-
Output enable, asynchronous input, active LOW. Controls the direction of the I/O pins. When LOW,
asynchronous the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tri-stated, and act as input data
pins. OE is masked during the first clock of a read cycle when emerging from a deselected state.
ADV
Input-
Advance input signal, sampled on the rising edge of CLK, active LOW. When asserted, it
synchronous automatically increments the address in a burst cycle.
ADSP
Input- Address strobe from processor, sampled on the rising edge of CLK, active LOW. When asserted
synchronous LOW, addresses presented to the device are captured in the address registers. A1:A0 are also loaded
into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP is
ignored when CE1 is deasserted HIGH.
ADSC
ZZ
Input-
Address strobe from controller, sampled on the rising edge of CLK, active LOW. When asserted
synchronous LOW, addresses presented to the device are captured in the address registers. A1:A0 are also loaded
into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized.
Input-
ZZ “sleep” input, active HIGH. When asserted HIGH places the device in a non-time-critical “sleep”
asynchronous condition with data integrity preserved. For normal operation, this pin has to be LOW or left floating. ZZ
pin has an internal pull-down.
I/O-
synchronous rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by the
addresses presented during the previous
Bidirectional data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the
DQs,
DQPX
clock rise of the read cycle. The direction of the pins is
controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQs and DQPX
are placed in a tri-state condition.
VDD
VSS
Power supply Power supply inputs to the core of the device.
Ground
Ground for the core of the device.
VSSQ
I/O ground Ground for the I/O circuitry.
Note
1. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.
Document Number: 38-05383 Rev. *L
Page 6 of 33
CY7C1440AV33
Pin Definitions (continued)
Name
VDDQ
I/O
Description
I/O power Power supply for the I/O circuitry.
supply
MODE
TDO
TDI
Input-
static
Selects burst order. When tied to GND selects linear burst sequence. When tied to VDD or left floating
selects interleaved burst sequence. This is a strap pin and should remain static during device operation.
Mode pin has an internal pull-up.
JTAG serial Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If the JTAG feature is
output
synchronous
not being utilized, this pin should be disconnected. This pin is not available on TQFP packages.
JTAG serial Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature is not being
input
utilized, this pin can be disconnected or connected to VDD. This pin is not available on TQFP packages.
synchronous
TMS
JTAG serial Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature is not being
input
utilized, this pin can be disconnected or connected to VDD. This pin is not available on TQFP packages.
synchronous
TCK
NC
JTAG-
clock
Clock input to the JTAG circuitry. If the JTAG feature is not being utilized, this pin must be connected
to VSS. This pin is not available on TQFP packages.
–
–
No connects. Not internally connected to the die
NC/72M,
NC/144M,
NC/288M,
NC/576M,
NC/1G
No connects. Not internally connected to the die. NC/72M, NC/144M, NC/288M, NC/576M and NC/1G
are address expansion pins are not internally connected to the die.
Single Read Accesses
Functional Overview
This access is initiated when the following conditions are
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. All data outputs pass through output
registers controlled by the rising edge of the clock. Maximum
access delay from the clock rise (tCO) is 2.6 ns (250-MHz
device).
satisfied at clock rise: (1) ADSP or ADSC is asserted LOW,
(2) CE1, CE2, CE3 are all asserted active, and (3) the write
signals (GW, BWE) are all deserted HIGH. ADSP is ignored if
CE1 is HIGH. The address presented to the address inputs (A)
is stored into the address advancement logic and the address
register while being presented to the memory array. The
corresponding data is allowed to propagate to the input of the
output registers. At the rising edge of the next clock the data is
allowed to propagate through the output register and onto the
data bus within 2.6 ns (250-MHz device) if OE is active LOW. The
only exception occurs when the SRAM is emerging from a
deselected state to a selected state, its outputs are always
tri-stated during the first cycle of the access. After the first cycle
of the access, the outputs are controlled by the OE signal.
Consecutive single Read cycles are supported. Once the SRAM
is deselected at clock rise by the chip select and either ADSP or
ADSC signals, its output will tri-state immediately.
The CY7C1440AV33 supports secondary cache in systems
utilizing either a linear or interleaved burst sequence. The
interleaved burst order supports Pentium and i486 processors.
The linear burst sequence is suited for processors that utilize a
linear burst sequence. The burst order is user selectable, and is
determined by sampling the MODE input. Accesses can be
initiated with either the processor address strobe (ADSP) or the
controller address strobe (ADSC). Address advancement
through the burst sequence is controlled by the ADV input. A
two-bit on-chip wraparound burst counter captures the first
address in a burst sequence and automatically increments the
address for the rest of the burst access.
Byte write operations are qualified with the byte write enable
(BWE) and byte write select (BWX) inputs. A global write enable
(GW) overrides all byte write inputs and writes data to all four
bytes. All writes are simplified with on-chip synchronous
self-timed Write circuitry.
Single Write Accesses Initiated by ADSP
This access is initiated when both of the following conditions are
satisfied at clock rise: (1) ADSP is asserted LOW, and (2) CE1,
CE2, CE3 are all asserted active. The address presented to A is
loaded into the address register and the address advancement
logic while being delivered to the memory array. The write signals
(GW, BWE, and BWX) and ADV inputs are ignored during this
first cycle.
Three synchronous chip selects (CE1, CE2, CE3) and an
asynchronous output enable (OE) provide for easy bank
selection and output tri-state control. ADSP is ignored if CE1 is
HIGH.
ADSP-triggered write accesses require two clock cycles to
complete. If GW is asserted LOW on the second clock rise, the
data presented to the DQs inputs is written into the
corresponding address location in the memory array. If GW is
Document Number: 38-05383 Rev. *L
Page 7 of 33
CY7C1440AV33
HIGH, then the write operation is controlled by BWE and BWX
signals.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ places
the SRAM in a power conservation “sleep” mode. Two clock
cycles are required to enter into or exit from this “sleep” mode.
While in this mode, data integrity is guaranteed. Accesses
pending when entering the “sleep” mode are not considered valid
nor is the completion of the operation guaranteed. The device
must be deselected prior to entering
CE3, ADSP, and ADSC must
tZZREC after the ZZ input returns LOW.
The CY7C1440AV33 provides byte write capability that is
described in the Write Cycle Descriptions table. Asserting the
byte write enable input (BWE) with the selected byte write (BWX)
input, will selectively write to only the desired bytes. Bytes not
selected during a byte write operation will remain unaltered. A
synchronous self-timed Write mechanism has been provided to
simplify the write operations.
the
“sleep” mode. CE1, CE2,
remain inactive for the duration of
Because CY7C1440AV33 is a common I/O device, the output
enable (OE) must be deasserted HIGH before presenting data
to the DQs inputs. Doing so will tri-state the output drivers. As a
safety precaution, DQs are automatically tri-stated whenever a
Write cycle is detected, regardless of the state of OE.
Interleaved Burst Address Table
(MODE = Floating or VDD
)
Single Write Accesses Initiated by ADSC
First
Address
A1:A0
Second
Third
Address
A1:A0
Fourth
Address
A1:A0
Address
A1:A0
ADSC Write accesses are initiated when the following conditions
are satisfied: (1) ADSC is asserted LOW, (2) ADSP is deserted
HIGH, (3) CE1, CE2, CE3 are all asserted active, and (4) the
appropriate combination of the Write inputs (GW, BWE, and
BWX) are asserted active to conduct a Write to the desired
byte(s). ADSC-triggered write accesses require a single clock
cycle to complete. The address presented to A is loaded into the
address register and the address advancement logic while being
delivered to the memory array. The ADV input is ignored during
this cycle. If a global Write is conducted, the data presented to
the DQs is written into the corresponding address location in the
memory core. If a byte write is conducted, only the selected bytes
are written. Bytes not selected during a byte write operation will
remain unaltered. A synchronous self-timed write mechanism
has been provided to simplify the Write operations.
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Linear Burst Address Table
(MODE = GND)
First
Address
A1:A0
Second
Address
A1:A0
Third
Address
A1:A0
Fourth
Address
A1:A0
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
Because CY7C1440AV33 is a common I/O device, the output
enable (OE) must be deasserted HIGH before presenting data
to the DQs inputs. Doing so will tri-state the output drivers. As a
safety precaution, DQs are automatically tri-stated whenever a
Write cycle is detected, regardless of the state of OE.
Burst Sequences
The CY7C1440AV33 provides a two-bit wraparound counter, fed
by A1:A0, that implements either an interleaved or linear burst
sequence. The interleaved burst sequence is designed
specifically to support Intel Pentium applications. The linear
burst sequence is designed to support processors that follow a
linear burst sequence. The burst sequence is user selectable
through the MODE input. Asserting ADV LOW at clock rise will
automatically increment the burst counter to the next address in
the burst sequence. Both read and write burst operations are
supported.
ZZ Mode Electrical Characteristics
Parameter
IDDZZ
Description
Sleep mode standby current
Device operation to ZZ
ZZ recovery time
Test Conditions
Min
Max
100
2tCYC
–
Unit
mA
ns
ZZ > VDD– 0.2 V
–
tZZS
ZZ > VDD – 0.2 V
ZZ < 0.2 V
–
2tCYC
–
tZZREC
tZZI
ns
ZZ active to sleep current
This parameter is sampled
2tCYC
–
ns
tRZZI
ZZ inactive to exit sleep current This parameter is sampled
0
ns
Document Number: 38-05383 Rev. *L
Page 8 of 33
CY7C1440AV33
Truth Table
The truth table for CY7C1440AV33 follows. [2, 3, 4, 5, 6, 7]
Operation
Add. Used CE1 CE2 CE3 ZZ ADSP ADSC ADV WRITE OE CLK
DQ
Deselect cycle, power-down
Deselect cycle, power-down
Deselect cycle, power-down
Deselect cycle, power-down
Deselect cycle, power-down
Sleep mode, power-down
READ cycle, begin burst
None
None
H
L
X
L
X
X
H
X
H
X
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
L
L
X
X
L
X
X
X
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
L
L–H Tri-state
L–H Tri-state
L–H Tri-state
L–H Tri-state
L–H Tri-state
None
L
X
L
L
None
L
H
H
X
L
None
L
X
X
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
L
None
X
L
X
X
X
L
X
Tri-state
Q
External
External
External
External
External
Next
L–H
READ cycle, begin burst
L
L
L
H
X
L
L–H Tri-state
WRITE cycle, begin burst
READ cycle, begin burst
L
L
H
H
H
H
H
X
X
H
X
H
H
X
X
H
X
L–H
L–H
D
Q
L
L
L
H
H
H
H
H
H
L
READ cycle, begin burst
L
L
L
H
L
L–H Tri-state
L–H
L–H Tri-state
L–H
L–H Tri-state
READ cycle, continue burst
READ cycle, continue burst
READ cycle, continue burst
READ cycle, continue burst
WRITE cycle, continue burst
WRITE cycle, continue burst
READ cycle, suspend burst
READ cycle, suspend burst
READ cycle, suspend burst
READ cycle, suspend burst
WRITE cycle, suspend burst
WRITE cycle, suspend burst
X
X
H
H
X
H
X
X
H
H
X
H
X
X
X
X
X
X
X
X
X
X
X
X
H
H
H
H
H
H
H
H
H
H
H
H
Q
Next
L
H
L
Next
L
Q
Next
L
H
X
X
L
Next
L
L–H
L–H
L–H
D
D
Q
Next
L
L
Current
Current
Current
Current
Current
Current
H
H
H
H
H
H
H
H
H
H
L
H
L
L–H Tri-state
L–H
L–H Tri-state
Q
H
X
X
L–H
L–H
D
D
L
Notes
2. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.
3. WRITE = L when any one or more byte write enable signals and BWE = L or GW = L. WRITE = H when all byte write enable signals, BWE, GW = H.
4. The DQ pins are controlled by the current cycle and the signal. is asynchronous and is not sampled with the clock.
OE
OE
5. CE , CE , and CE are available only in the TQFP package. BGA package has only 2 chip selects CE and CE .
1
2
3
1
2
6. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW . Writes may occur only on subsequent clocks after the
X
ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to tri-state. OE is a don't care for
the remainder of the write cycle.
7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tri-state when OE is inactive
or when the device is deselected, and all data bits behave as output when OE is active (LOW).
Document Number: 38-05383 Rev. *L
Page 9 of 33
CY7C1440AV33
Truth Table for Read/Write
The truth table for Read/Write for CY7C1440AV33 follows. [8, 9, 10]
Function (CY7C1440AV33)
GW
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
BWE
H
L
BWD
X
H
H
H
H
H
H
H
H
L
BWC
X
H
H
H
H
L
BWB
X
H
H
L
BWA
X
H
L
Read
Read
Write byte A – (DQA and DQPA)
Write byte B – (DQB and DQPB)
Write bytes B, A
L
L
H
L
L
L
Write byte C – (DQC and DQPC)
Write bytes C, A
L
H
H
L
H
L
L
L
Write bytes C, B
L
L
H
L
Write bytes C, B, A
Write byte D – (DQD and DQPD)
Write bytes D, A
L
L
L
L
H
H
H
H
L
H
H
L
H
L
L
L
Write bytes D, B
L
L
H
L
Write bytes D, B, A
Write bytes D, C
L
L
L
L
L
H
H
L
H
L
Write bytes D, C, A
Write bytes D, C, B
Write all bytes
L
L
L
L
L
L
H
L
L
L
L
L
Write all bytes
X
X
X
X
X
Notes
8. The DQ pins are controlled by the current cycle and the
signal.
is asynchronous and is not sampled with the clock.
OE
x
OE
9. BW represents any byte write signal. To enable any byte write BW , a Logic LOW signal should be applied at clock rise. Any number of bye writes can be enabled
x
at the same time for any given write.
10. Table only lists a partial listing of the byte write combinations. Any combination of BW is valid. Appropriate write will be done based on which byte write is active.
X
Document Number: 38-05383 Rev. *L
Page 10 of 33
CY7C1440AV33
instruction register. Data is serially loaded into the TDI ball on the
rising edge of TCK. Data is output on the TDO ball on the falling
edge of TCK.
IEEE 1149.1 Serial Boundary Scan (JTAG)
The CY7C1440AV33 incorporates a serial boundary scan test
access port (TAP). This part is fully compliant with IEEE Standard
1149.1. The TAP operates using JEDEC-standard 3.3 V or 2.5 V
I/O logic levels.
Instruction Register
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the TDI
and TDO balls as shown in the TAP Controller Block Diagram on
page 14. Upon power-up, the instruction register is loaded with
the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as described
in the previous section.
The CY7C1440AV33 contains a TAP controller, instruction
register, boundary scan register, bypass register, and ID register.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(VSS) to prevent clocking of the device. TDI and TMS are
internally pulled up and may be unconnected. They may
alternately be connected to VDD through a pull-up resistor. TDO
should be left unconnected. Upon power-up, the device will
come up in a reset state which will not interfere with the operation
of the device.
When the TAP controller is in the Capture-IR state, the two least
significant bits are loaded with a binary “01” pattern to allow for
fault isolation of the board-level serial test data path.
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between the
TDI and TDO balls. This allows data to be shifted through the
Test Access Port (TAP)
Test Clock (TCK)
SRAM with minimal delay. The bypass register is set LOW (VSS
)
when the BYPASS instruction is executed.
The test clock is used only with the TAP controller. All inputs are
captured on the rising edge of TCK. All outputs are driven from
the falling edge of TCK.
Boundary Scan Register
The boundary scan register is connected to all the input and
bidirectional balls on the SRAM.
Test Mode Select (TMS)
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. It is allowable to leave
this ball unconnected if the TAP is not used. The ball is pulled up
internally, resulting in a logic HIGH level.
The boundary scan register is loaded with the contents of the
RAM I/O ring when the TAP controller is in the Capture-DR state
and is then placed between the TDI and TDO balls when the
controller is moved to the Shift-DR state. The EXTEST,
SAMPLE/PRELOAD and SAMPLE Z instructions can be used to
capture the contents of the I/O ring.
Test Data-In (TDI)
The TDI ball is used to serially input information into the registers
and can be connected to the input of any of the registers. The
register between TDI and TDO is chosen by the instruction that
is loaded into the TAP instruction register. For information about
loading the instruction register, see the TAP Controller State
Diagram on page 13. TDI is internally pulled up and can be
unconnected if the TAP is unused in an application. TDI is
connected to the most significant bit (MSB) of any register.
The Boundary Scan Order tables show the order in which the bits
are connected. Each bit corresponds to one of the bumps on the
SRAM package. The MSB of the register is connected to TDI,
and the LSB is connected to TDO.
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired into
the SRAM and can be shifted out when the TAP controller is in
the Shift-DR state. The ID register has a vendor code and other
information described in the Identification Register Definitions on
page 17.
Test Data-Out (TDO)
The TDO output ball is used to serially clock data-out from the
registers. The output is active, depending upon the current state
of the TAP state machine (see Instruction Codes on page 17).
The output changes on the falling edge of TCK. TDO is
connected to the least significant bit (LSB) of any register.
TAP Instruction Set
Performing a TAP Reset
Overview
A RESET is performed by forcing TMS HIGH (VDD) for five rising
edges of TCK. This RESET does not affect the operation of the
SRAM and may be performed while the SRAM is operating.
Eight different instructions are possible with the three bit
instruction register. All combinations are listed in the Instruction
Codes on page 17. Three of these instructions are listed as
RESERVED and should not be used. The other five instructions
are described in detail below.
At power-up, the TAP is reset internally to ensure that TDO
comes up in a high Z state.
Instructions are loaded into the TAP controller during the Shift-IR
state when the instruction register is placed between TDI and
TDO. During this state, instructions are shifted through the
instruction register through the TDI and TDO balls. To execute
TAP Registers
Registers are connected between the TDI and TDO balls and
allow data to be scanned into and out of the SRAM test circuitry.
Only one register can be selected at a time through the
Document Number: 38-05383 Rev. *L
Page 11 of 33
CY7C1440AV33
the instruction once it is shifted in, the TAP controller needs to be
moved into the Update-IR state.
Once the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the boundary
scan register between the TDI and TDO pins.
IDCODE
PRELOAD allows an initial data pattern to be placed at the
latched parallel outputs of the boundary scan register cells prior
to the selection of another boundary scan test operation.
The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the instruction register. It also places the
instruction register between the TDI and TDO balls and allows
the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state.
The shifting of data for the SAMPLE and PRELOAD phases can
occur concurrently when required – that is, while data captured
is shifted out, the preloaded data can be shifted in.
The IDCODE instruction is loaded into the instruction register
upon power-up or whenever the TAP controller is given a test
logic reset state.
BYPASS
When the BYPASS instruction is loaded in the instruction register
and the TAP is placed in a Shift-DR state, the bypass register is
placed between the TDI and TDO pins. The advantage of the
BYPASS instruction is that it shortens the boundary scan path
when multiple devices are connected together on a board.
SAMPLE Z
The SAMPLE Z instruction causes the boundary scan register to
be connected between the TDI and TDO pins when the TAP
controller is in a Shift-DR state. The SAMPLE Z command puts
the output bus into a high Z state until the next command is given
during the “Update IR” state.
EXTEST
The EXTEST instruction enables the preloaded data to be driven
out through the system output pins. This instruction also selects
the boundary scan register to be connected for serial access
between the TDI and TDO in the shift-DR controller state.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When
the SAMPLE/PRELOAD instructions are loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and output pins is
captured in the boundary scan register.
EXTEST OUTPUT BUS TRI-STATE
IEEE Standard 1149.1 mandates that the TAP controller be able
to put the output bus into a tri-state mode.
The user must be aware that the TAP controller clock can only
operate at a frequency up to 20 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because there
is a large difference in the clock frequencies, it is possible that
during the Capture-DR state, an input or output will undergo a
transition. The TAP may then try to capture a signal while in
transition (metastable state). This will not harm the device, but
there is no guarantee as to the value that will be captured.
Repeatable results may not be possible.
The boundary scan register has a special bit located at, bit #89
(for 165-ball FBGA package). When this scan cell, called the
“extest output bus tri-state”, is latched into the preload register
during the “Update-DR” state in the TAP controller, it will directly
control the state of the output (Q-bus) pins, when the EXTEST is
entered as the current instruction. When HIGH, it will enable the
output buffers to drive the output bus. When LOW, this bit will
place the output bus into a high Z condition.
This bit can be set by entering the SAMPLE/PRELOAD or
EXTEST command, and then shifting the desired bit into that cell,
during the “Shift-DR” state. During “Update-DR”, the value
loaded into that shift-register cell will latch into the preload
register. When the EXTEST instruction is entered, this bit will
directly control the output Q-bus pins. Note that this bit is pre-set
HIGH to enable the output when the device is powered-up, and
also when the TAP controller is in the “Test-Logic-Reset” state.
To guarantee that the boundary scan register will capture the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller’s capture set-up plus
hold times (tCS and tCH). The SRAM clock input might not be
captured correctly if there is no way in a design to stop (or slow)
the clock during a SAMPLE/PRELOAD instruction. If this is an
issue, it is still possible to capture all other signals and simply
ignore the value of the CK and CK captured in the boundary scan
register.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
Document Number: 38-05383 Rev. *L
Page 12 of 33
CY7C1440AV33
TAP Controller State Diagram
TEST-LOGIC
1
RESET
0
1
1
1
RUN-TEST/
IDLE
SELECT
DR-SCAN
SELECT
IR-SCAN
0
0
0
1
1
CAPTURE-DR
CAPTURE-IR
0
0
SHIFT-DR
0
SHIFT-IR
0
1
1
1
1
EXIT1-DR
EXIT1-IR
0
0
PAUSE-DR
0
PAUSE-IR
0
1
1
0
0
EXIT2-DR
1
EXIT2-IR
1
UPDATE-DR
UPDATE-IR
1
0
1
0
The 0/1 next to each state represents the value of TMS at the rising edge of TCK.
Document Number: 38-05383 Rev. *L
Page 13 of 33
CY7C1440AV33
TAP Controller Block Diagram
0
0
Bypass Register
2
1
Selection
Circuitry
Instruction Register
31 30 29 .
S
election
TDI
TDO
Circuitr
y
.
.
2
1
0
Identification Register
x
.
.
.
.
. 2 1 0
Boundary Scan Register
TAP CONTROLLER
TCK
TMS
TAP Timing
1
2
3
4
5
6
Test Clock
(TCK)
t
t
t
CYC
TH
TL
t
t
t
t
TMSS
TDIS
TMSH
Test Mode Select
(TMS)
TDIH
Test Data-In
(TDI)
t
TDOV
t
TDOX
Test Data-Out
(TDO)
DON’T CARE
UNDEFINED
Document Number: 38-05383 Rev. *L
Page 14 of 33
CY7C1440AV33
TAP AC Switching Characteristics
Over the operating Range
Parameter [11, 12]
Clock
Description
Min
Max
Unit
tTCYC
TCK clock cycle time
TCK clock frequency
TCK clock HIGH time
TCK clock LOW time
50
–
–
20
–
ns
MHz
ns
tTF
tTH
20
20
tTL
–
ns
Output Times
tTDOV
TCK clock LOW to TDO valid
TCK clock LOW to TDO invalid
–
0
10
–
ns
ns
tTDOX
Set-up Times
tTMSS
TMS set-up to TCK clock rise
TDI set-up to TCK clock rise
Capture set-up to TCK rise
5
5
5
–
–
–
ns
ns
ns
tTDIS
tCS
Hold Times
tTMSH
tTDIH
TMS hold after TCK clock rise
TDI hold after clock rise
5
5
5
–
–
–
ns
ns
ns
tCH
Capture hold after clock rise
3.3 V TAP AC Test Conditions
2.5 V TAP AC Test Conditions
Input pulse levels ...............................................VSS to 3.3 V
Input rise and fall times....................................................1 ns
Input timing reference levels..........................................1.5 V
Output reference levels .................................................1.5 V
Test load termination supply voltage .............................1.5 V
Input pulse levels................................................VSS to 2.5 V
Input rise and fall time .....................................................1 ns
Input timing reference levels.................. ......................1.25 V
Output reference levels ................. ..............................1.25 V
Test load termination supply voltage ................... ........1.25 V
3.3 V TAP AC Output Load Equivalent
2.5 V TAP AC Output Load Equivalent
1.5V
1.25V
50
50
TDO
TDO
ZO= 50
ZO= 50
20pF
20pF
Notes
11. t and t refer to the set-up and hold time requirements of latching data from the boundary scan register.
CS
CH
12. Test conditions are specified using the load in TAP AC test Conditions. t /t = 1 ns.
R
F
Document Number: 38-05383 Rev. *L
Page 15 of 33
CY7C1440AV33
TAP DC Electrical Characteristics and Operating Conditions
(0 °C < TA < +70 °C; VDD = 3.135 to 3.6 V unless otherwise noted)
Parameter [13]
Description
Test Conditions
Min
2.4
2.0
2.9
2.1
–
Max
Unit
V
VOH1
Output HIGH voltage
IOH = –4.0 mA, VDDQ = 3.3 V
–
I
OH = –1.0 mA, VDDQ = 2.5 V
–
V
VOH2
VOL1
VOL2
VIH
Output HIGH voltage
Output LOW voltage
Output LOW voltage
Input HIGH voltage
Input LOW voltage
Input load current
IOH = –100 µA
VDDQ = 3.3 V
VDDQ = 2.5 V
VDDQ = 3.3 V
VDDQ = 2.5 V
VDDQ = 3.3 V
–
V
–
0.4
V
IOL = 8.0 mA
V
I
OL = 1.0 mA
–
0.4
V
IOL = 100 µA
–
0.2
V
VDDQ = 2.5 V
–
0.2
V
VDDQ = 3.3 V
VDDQ = 2.5 V
VDDQ = 3.3 V
2.0
1.7
–0.3
–0.3
–5
VDD + 0.3
VDD + 0.3
0.8
V
V
VIL
V
VDDQ = 2.5 V
0.7
V
IX
GND < VIN < VDDQ
5
µA
Note
13. All voltages referenced to V (GND).
SS
Document Number: 38-05383 Rev. *L
Page 16 of 33
CY7C1440AV33
Identification Register Definitions
CY7C1440AV33
(1 M × 36)
Instruction Field
Description
Revision number (31:29)
Device depth (28:24) [14]
000
01011
Describes the version number.
Reserved for internal use
Architecture/memory type(23:18)
Bus width/density(17:12)
000000
100111
00000110100
1
Defines memory type and architecture
Defines width and density
Cypress JEDEC ID code (11:1)
ID register presence indicator (0)
Allows unique identification of SRAM vendor.
Indicates the presence of an ID register.
Scan Register Sizes
Register Name
Bit Size (x 36)
Instruction
3
1
Bypass
ID
32
89
Boundary scan order (165-ball FBGA package)
Instruction Codes
Instruction
EXTEST
Code
000
Description
Captures the I/O ring contents.
IDCODE
001
Loads the ID register with the vendor ID code and places the register between TDI and TDO.
This operation does not affect SRAM operations.
SAMPLE Z
010
Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces
all SRAM output drivers to a high Z state.
RESERVED
011
100
Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD
Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Does
not affect SRAM operation.
RESERVED
RESERVED
BYPASS
101
110
111
Do Not Use: This instruction is reserved for future use.
Do Not Use: This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does not affect SRAM
operations.
Note
14. Bit #24 is “1” in the ID Register Definitions for both 2.5 V and 3.3 V versions of this device.
Document Number: 38-05383 Rev. *L
Page 17 of 33
CY7C1440AV33
Boundary Scan Order
165-ball FBGA [15, 16]
CY7C1440AV33 (1 M × 36)
Bit #
1
Ball ID
Bit #
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
Ball ID
E11
D11
G10
F10
E10
D10
C11
A11
B11
A10
B10
A9
Bit #
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
Ball ID
A3
A2
B2
C2
B1
A1
C1
D1
E1
F1
Bit #
76
77
78
79
80
81
82
83
84
85
86
87
88
89
Ball ID
N1
N6
N7
2
N2
3
N10
P11
P8
P1
4
R1
5
R2
6
R8
P3
7
R9
R3
8
P9
P2
9
P10
R10
R11
H11
N11
M11
L11
K11
J11
M10
L10
K10
J10
H9
R4
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
P4
G1
D2
E2
F2
N5
P6
B9
R6
C10
A8
Internal
G2
H1
H3
J1
B8
A7
B7
B6
K1
L1
A6
M1
J2
B5
A5
A4
B4
B3
H10
G11
F11
K2
L2
M2
Notes
15. Balls that are NC (No Connect) are preset LOW.
16. Bit# 89 is preset HIGH.
Document Number: 38-05383 Rev. *L
Page 18 of 33
CY7C1440AV33
DC input voltage ................................. –0.5 V to VDD + 0.5 V
Current into outputs (LOW) ........................................ 20 mA
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Static discharge voltage
(per MIL-STD-883, method 3015) ..........................> 2001 V
Storage temperature ................................ –65 °C to +150 °C
Latch-up current ....................................................> 200 mA
Ambient temperature with
power applied .......................................... –55 °C to +125 °C
Operating Range
Supply voltage on VDD relative to GND .......–0.3 V to +4.6 V
Supply voltage on VDDQ relative to GND ...... –0.3 V to +VDD
Ambient
Range
VDD
VDDQ
Temperature
DC voltage applied to outputs
in tri-state ..........................................–0.5 V to VDDQ + 0.5 V
Commercial 0 °C to +70 °C
Industrial –40 °C to +85 °C
3.3 V– 5% / 2.5 V – 5%
+ 10%
to VDD
Electrical Characteristics
Over the Operating Range
Parameter [17, 18]
Description
Power supply voltage
I/O supply voltage
Test Conditions
Min
3.135
3.135
2.375
2.4
Max
Unit
V
VDD
3.6
VDD
2.625
–
VDDQ
for 3.3 V I/O
for 2.5 V I/O
V
V
VOH
VOL
VIH
VIL
IX
Output HIGH voltage
Output LOW voltage
Input HIGH voltage [17]
Input LOW voltage [17]
for 3.3 V I/O, IOH =4.0 mA
for 2.5 V I/O, IOH =1.0 mA
for 3.3 V I/O, IOL = 8.0 mA
for 2.5 V I/O, IOL = 1.0 mA
for 3.3 V I/O
V
2.0
–
V
–
0.4
V
–
0.4
V
2.0
VDD + 0.3
V
for 2.5 V I/O
1.7
V
DD + 0.3
0.8
V
for 3.3 V I/O
–0.3
–0.3
–5
V
for 2.5 V I/O
0.7
V
Input leakage current except ZZ GND VI VDDQ
and MODE
5
µA
Input current of MODE
Input = VSS
–30
–
–
5
µA
µA
µA
µA
µA
mA
Input = VDD
Input current of ZZ
Input = VSS
–5
–
–
Input = VDD
30
5
IOZ
IDD
Output leakage current
GND VI VDDQ, output disabled
–5
–
VDD operating supply current
VDD = Max, IOUT = 0 mA,
f = fMAX = 1/tCYC
4-ns cycle,
250 MHz
475
6-ns cycle,
167 MHz
–
–
375
225
mA
mA
ISB1
Automatic CE power-down
current – TTL inputs
VDD = Max, device deselected, All speeds
VIN VIH or VIN VIL,
f = fMAX = 1/tCYC
ISB2
Automatic CE power-down
current – CMOS inputs
VDD = Max, device deselected, All speeds
VIN 0.3 V or VIN > VDDQ – 0.3 V,
f = 0
–
120
mA
Notes
17. Overshoot: V
< V + 1.5 V (Pulse width less than t
/2), undershoot: V
> –2 V (Pulse width less than t
/2).
IH(AC)
DD
CYC
IL(AC)
CYC
18. T
: Assumes a linear ramp from 0 V to V
within 200 ms. During this time V < V and V
V
.
Power-up
DD(min)
IH
DD
DDQ
DD
Document Number: 38-05383 Rev. *L
Page 19 of 33
CY7C1440AV33
Electrical Characteristics (continued)
Over the Operating Range
Parameter [17, 18]
Description
Test Conditions
Min
Max
Unit
ISB3
Automatic CE power-down
current – CMOS inputs
VDD = Max, device deselected, or All speeds
VIN 0.3 V or VIN > VDDQ – 0.3 V,
f = fMAX = 1/tCYC
–
200
mA
ISB4
Automatic CE Power-down
current – TTL Inputs
VDD = Max, device deselected, All speeds
VIN VIH or VIN VIL,
f = 0
–
135
mA
Capacitance
100-pin TQFP 165-ballFBGA
Parameter [19]
Description
Test Conditions
Unit
Max
6.5
3
Max
CIN
Input capacitance
TA = 25 C, f = 1 MHz,
DD = 3.3 V, VDDQ = 2.5 V
7
7
6
pF
pF
pF
V
CCLK
CI/O
Clock input capacitance
Input/Output capacitance
5.5
Thermal Resistance
100-pin TQFP 165-ballFBGA
Parameter [19]
Description
Test Conditions
Unit
Package
Package
JA
Thermal resistance
(junction to ambient)
Test conditions follow standard test
methods and procedures for measuring
thermal impedance, per EIA/JESD51.
25.21
20.8
°C/W
JC
Thermal resistance
(junction to case)
2.28
3.2
°C/W
AC Test Loads and Waveforms
Figure 3. AC Test Loads and Waveforms
3.3 V I/O Test Load
R = 317
3.3 V
OUTPUT
ALL INPUT PULSES
90%
VDDQ
OUTPUT
R = 50
90%
10%
Z = 50
0
10%
L
GND
5 pF
R = 351
INCLUDING
1ns
1ns
JIG AND
SCOPE
V = 1.5 V
T
(a)
(b)
(c)
2.5 V I/O Test Load
R = 1667
2.5 V
OUTPUT
R = 50
OUTPUT
ALL INPUT PULSES
90%
VDDQ
GND
90%
10%
Z = 50
0
10%
L
5 pF
R = 1538
INCLUDING
JIG AND
SCOPE
1ns
1ns
V = 1.25 V
T
(a)
(b)
(c)
Note
19. Tested initially and after any design or process change that may affect these parameters.
Document Number: 38-05383 Rev. *L
Page 20 of 33
CY7C1440AV33
Switching Characteristics
Over the Operating Range
-250
-167
Unit
Parameter [20, 21]
Description
Min
Max
Min
Max
tPOWER
Clock
tCYC
VDD(typical) to the first access [22]
1
–
1
–
ms
Clock cycle time
Clock HIGH
4.0
1.5
1.5
–
–
–
6
–
–
–
ns
ns
ns
tCH
2.4
2.4
tCL
Clock LOW
Output Times
tCO
Data output valid after CLK rise
Data output hold after CLK rise
Clock to low Z [23, 24, 25]
–
1.0
1.0
–
2.6
–
–
1.5
1.5
–
3.4
–
ns
ns
ns
ns
ns
ns
ns
tDOH
tCLZ
–
–
tCHZ
Clock to high Z [23, 24, 25]
2.6
2.6
–
3.4
3.4
–
tOEV
OE LOW to output valid
–
–
tOELZ
tOEHZ
Set-up Times
tAS
OE LOW to output low Z [23, 24, 25]
OE HIGH to output high Z [23, 24, 25]
0
0
–
2.6
–
3.4
Address set-up before CLK rise
ADSC, ADSP set-up before CLK rise
ADV set-up before CLK rise
1.2
1.2
1.2
1.2
1.2
1.2
–
–
–
–
–
–
1.5
1.5
1.5
1.5
1.5
1.5
–
–
–
–
–
–
ns
ns
ns
ns
ns
ns
tADS
tADVS
tWES
GW, BWE, BWX set-up before CLK rise
Data input set-up before CLK rise
Chip enable set-up before CLK rise
tDS
tCES
Hold Times
tAH
Address hold after CLK rise
ADSP, ADSC hold after CLK rise
ADV hold after CLK rise
0.3
0.3
0.3
0.3
0.3
0.3
–
–
–
–
–
–
0.5
0.5
0.5
0.5
0.5
0.5
–
–
–
–
–
–
ns
ns
ns
ns
ns
ns
tADH
tADVH
tWEH
GW, BWE, BWX hold after CLK rise
Data input hold after CLK rise
Chip enable hold after CLK rise
tDH
tCEH
Notes
20. Timing reference level is 1.5 V when V
= 3.3 V and is 1.25 V when V
= 2.5 V.
DDQ
DDQ
21. Test conditions shown in (a) of Figure 3 on page 20 unless otherwise noted.
22. This part has a voltage regulator internally; t
is the time that the power needs to be supplied above V
initially before a read or write operation can
POWER
DD(minimum)
be initiated.
23. t
, t
,t
, and t
are specified with AC test conditions shown in (b) of Figure 3 on page 20. Transition is measured ± 200 mV from steady-state voltage.
OEHZ
CHZ CLZ OELZ
24. At any given voltage and temperature, t
is less than t
and t
is less than t
to eliminate bus contention between SRAMs when sharing the same data
OEHZ
OELZ
CHZ
CLZ
bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve
high Z prior to low Z under the same system conditions.
25. This parameter is sampled and not 100% tested.
Document Number: 38-05383 Rev. *L
Page 21 of 33
CY7C1440AV33
Switching Waveforms
Figure 4. Read Cycle Timing [26]
t
CYC
CLK
t
t
CL
CH
t
t
ADH
ADS
ADSP
ADSC
t
t
ADH
ADS
t
t
AH
AS
A1
A2
A3
ADDRESS
Burst continued with
new base address
t
t
WEH
WES
GW, BWE,
BWx
Deselect
cycle
t
t
CEH
CES
CE
t
t
ADVH
ADVS
ADV
OE
ADV
suspends
burst.
t
t
OEV
CO
t
t
OEHZ
t
OELZ
t
CHZ
DOH
t
CLZ
t
Q(A2)
Q(A2 + 1)
Q(A2 + 2)
Q(A2 + 3)
Q(A2)
Q(A2 + 1)
Q(A1)
Data Out (Q)
High-Z
CO
Burst wraps around
to its initial state
Single READ
BURST READ
DON’T CARE
UNDEFINED
Note
26. On this diagram, when CE is LOW: CE is LOW, CE is HIGH and CE is LOW. When CE is HIGH: CE is HIGH or CE is LOW or CE is HIGH.
1
2
3
1
2
3
Document Number: 38-05383 Rev. *L
Page 22 of 33
CY7C1440AV33
Switching Waveforms (continued)
Figure 5. Write Cycle Timing [27, 28]
t
CYC
CLK
t
t
CL
CH
t
t
ADH
ADS
ADSP
ADSC extends burst
t
t
ADH
ADS
t
t
ADH
ADS
ADSC
ADDRESS
BWE,
t
t
AH
AS
A1
A2
A3
Byte write signals are
ignored for first cycle when
ADSP initiates burst
t
t
WEH
WES
BW
X
t
t
WEH
WES
GW
CE
t
t
CEH
CES
t
t
ADVH
ADVS
ADV
OE
ADV suspends burst
t
t
DH
DS
Data In (D)
D(A2)
D(A2 + 1)
D(A2 + 1)
D(A2 + 2)
D(A2 + 3)
D(A3)
D(A3 + 1)
D(A3 + 2)
D(A1)
High-Z
t
OEHZ
Data Out (Q)
BURST READ
Single WRITE
BURST WRITE
Extended BURST WRITE
DON’T CARE
UNDEFINED
Notes
27. On this diagram, when CE is LOW: CE is LOW, CE is HIGH and CE is LOW. When CE is HIGH: CE is HIGH or CE is LOW or CE is HIGH.
1
2
3
1
2
3
28.
Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW LOW.
X
Document Number: 38-05383 Rev. *L
Page 23 of 33
CY7C1440AV33
Switching Waveforms (continued)
Figure 6. Read/Write Cycle Timing [29, 30, 31]
t
CYC
CLK
t
t
CL
CH
t
t
ADH
ADS
ADSP
ADSC
t
t
AH
AS
A1
A2
A3
A4
A5
A6
ADDRESS
t
t
WEH
WES
BWE,
BWX
t
t
CEH
CES
CE
ADV
OE
t
t
DH
t
CO
DS
t
OELZ
Data In (D)
High-Z
High-Z
D(A3)
D(A5)
D(A6)
t
t
OEHZ
CLZ
Data Out (Q)
Q(A1)
Q(A2)
Q(A4)
Q(A4+1)
Q(A4+2)
Q(A4+3)
Back-to-Back READs
Single WRITE
BURST READ
Back-to-Back
WRITEs
DON’T CARE
UNDEFINED
Notes
29. On this diagram, when CE is LOW: CE is LOW, CE is HIGH and CE is LOW. When CE is HIGH: CE is HIGH or CE is LOW or CE is HIGH.
1
2
3
1
2
3
30. The data bus (Q) remains in high Z following a Write cycle, unless a new read access is initiated by ADSP or ADSC.
31. GW is HIGH.
Document Number: 38-05383 Rev. *L
Page 24 of 33
CY7C1440AV33
Switching Waveforms (continued)
Figure 7. ZZ Mode Timing [32, 33]
CLK
t
t
ZZ
ZZREC
ZZ
t
ZZI
I
SUPPLY
I
DDZZ
t
RZZI
ALL INPUTS
(except ZZ)
DESELECT or READ Only
Outputs (Q)
High-Z
DON’T CARE
Notes
32. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device.
33. DQs are in high Z when exiting ZZ sleep mode.
Document Number: 38-05383 Rev. *L
Page 25 of 33
CY7C1440AV33
Ordering Information
Cypress offers other versions of this type of product in different configurations and features. The following table contains only the
list of parts that are currently available.
For a complete listing of all options, visit the Cypress website at www.cypress.com and refer to the product summary page at
http://www.cypress.com/products, or contact your local sales representative.
Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives and distributors. To find the office
closest to you, visit us at http://www.cypress.com/go/datasheet/offices.
Speed
(MHz)
Package
Diagram
Operating
Range
Part and Package Type
Ordering Code
167 CY7C1440AV33-167AXC
250 CY7C1440AV33-250AXC
CY7C1440AV33-250AXI
51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free
51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free
100-pin TQFP (14 × 20 × 1.4 mm) Pb-free
Commercial
Commercial
Industrial
CY7C1440AV33-250BZXI
51-85195 165-ball FBGA (15 × 17 × 1.4 mm) Pb-free
Ordering Code Definitions
CY
7
C
1440 A V33 - XXX XX
X
X
Temperature range: X = C or I
C = Commercial; I = Industrial
Pb-free
Package Type: XX = A or BZ
A = 100-pin TQFP
BZ = 165-ball FBGA
Speed Grade: 167 MHz or 250 MHz
V33 = 3.3 V
Process Technology: A 90 nm
Part Identifier: 1440 = SCD, 1 Mb × 36 (36 Mb)
Technology Code: C = CMOS
Marketing Code: 7 = SRAM
Company ID: CY = Cypress
Document Number: 38-05383 Rev. *L
Page 26 of 33
CY7C1440AV33
Package Diagrams
Figure 8. 100-pin TQFP (14 × 20 × 1.4 mm) A100RA Package Outline, 51-85050
51-85050 *D
Document Number: 38-05383 Rev. *L
Page 27 of 33
CY7C1440AV33
Package Diagrams (continued)
Figure 9. 165-ball FBGA (15 × 17 × 1.40 mm) (0.50 Ball Diameter) Package Outline, 51-85195
51-85195 *C
Document Number: 38-05383 Rev. *L
Page 28 of 33
CY7C1440AV33
Acronyms
Document Conventions
Units of Measure
Acronym
Description
BGA
CE
ball grid array
chip enable
Symbol
°C
Unit of Measure
degree Celsius
megahertz
microampere
milliampere
millisecond
millimeter
nanosecond
ohm
CMOS
EIA
complementary metal oxide semiconductor
electronic industries alliance
fine-pitch ball grid array
input/output
MHz
µA
mA
ms
mm
ns
FBGA
I/O
JEDEC
JTAG
LSB
joint electron devices engineering council
joint test action group
least significant bit
MSB
NoBL
OE
most significant bit
%
percent
No Bus Latency
pF
V
picofarad
volt
output enable
SRAM
TAP
static random access memory
test access port
W
watt
TCK
TMS
TDI
test clock
test mode select
test data-in
TDO
TQFP
TTL
test data-out
thin quad flat pack
transistor-transistor logic
Document Number: 38-05383 Rev. *L
Page 29 of 33
CY7C1440AV33
Document History Page
Document Title: CY7C1440AV33, 36-Mbit (1 M × 36) Pipelined Sync SRAM
Document Number: 38-05383
Orig. of
Change
Rev.
ECN No.
Issue Date
Description of Change
**
124437
254910
03/04/03
See ECN
CJM
New data sheet.
*A
SYT
Updated Logic Block Diagram – CY7C1440AV33.
Updated Logic Block Diagram – CY7C1442AV33.
Updated Logic Block Diagram – CY7C1446AV33.
Updated Identification Register Definitions (Added Note 14 and referred the
same in Device Depth (28:24)).
Added Boundary Scan Order related information.
Updated Electrical Characteristics (Updated values of IDD, IX and ISB
parameters).
Updated Switching Characteristics (Added tPOWER parameter and its details).
Updated Switching Waveforms.
Updated Package Diagrams (Removed 119-ball PBGA package, changed
165-ball FBGA package from BB165C (15 × 17 × 1.20 mm) to BB165
(15 × 17 × 1.40 mm), changed 209-Lead PBGA BG209 (14 × 22 × 2.20 mm)
to BB209A (14 × 22 × 1.76 mm)).
*B
306335
See ECN
SYT
Updated Pin Configurations (Changed H9 pin from VSSQ to VSS for 209-ball
FBGA).
Updated Thermal Resistance (Replaced JA and JC values from TBD to
25.21 C/W and 2.58 C/W respectively for 100-pin TQFP Package, replaced
JA and JC values from TBD to respective Values for 165-ball FBGA and
209-ball FBGA Packages).
Updated Electrical Characteristics (Changed maximum value of IDD parameter
from 450 mA, 400 mA, and 350 mA to 475 mA, 425 mA, and 375 mA for
frequencies of 250 MHz, 200 MHz, and 167 MHz respectively, changed
maximum value of ISB1 parameter from 190 mA, 180 mA, and 170 mA to
225 mA for frequencies of 250 MHz, 200 MHz, and 167 MHz respectively,
changed maximum value of ISB2 from 80 mA to 100 mA, changed maximum
value of ISB3 from 180 mA, 170 mA, and 160 mA to 200 mA for frequencies of
250 MHz, 200 MHz, and 167 MHz respectively, changed maximum value of
ISB4 parameter from 100 mA to 110 mA).
Updated Switching Characteristics (Changed maximum value of tCO
parameter from 3.0 ns to 3.2 ns for 200 MHz frequency, changed minimum
value of tDOH parameter from 1.3 ns to 1.5 ns for 200 MHz frequency).
Updated Ordering Information (Added lead-free information for 100-pin TQFP,
165-ball FBGA and 209-ball FBGA Packages).
*C
332173
See ECN
SYT
Updated Pin Configurations (Modified Address Expansion balls in the pinouts
for 165-ball FBGA and 209-ball FBGA Package as per JEDEC standards).
Updated Operating Range (Added Industrial Temperature Range).
Updated Electrical Characteristics (Updated Test Conditions of VOL, VOH
parameters, changed maximum value of ISB2 and ISB4 parameters from
100 mA and 110 mA to 120 mA and 135 mA respectively).
Updated Capacitance (Changed value of CIN, CCLK and CI/O to 7 pF, 7 pF, and
6 pF from 5 pF, 5 pF, and 7 pF for 165-ball FBGA Package).
Updated Ordering Information (By Shading and Unshading MPNs as per
availability).
Updated Package Diagrams (Included 100-pin TQFP Package Diagram).
Document Number: 38-05383 Rev. *L
Page 30 of 33
CY7C1440AV33
Document History Page (continued)
Document Title: CY7C1440AV33, 36-Mbit (1 M × 36) Pipelined Sync SRAM
Document Number: 38-05383
Orig. of
Rev.
ECN No.
Issue Date
Description of Change
Changed status from Preliminary to Final.
Change
*D
417547
See ECN
RXU
Changed address of Cypress Semiconductor Corporation from “3901 North
First Street” to “198 Champion Court”.
Updated Electrical Characteristics (Updated Note 18 (Changed test condition
from VIH < VDD to VIH VDD), changed “Input Load Current except ZZ and
MODE” to “Input Leakage Current except ZZ and MODE” in the description of
IX parameter, changed minimum value of IX corresponding to Input current of
MODE (Input = VSS) from –5 A to –30 A, changed maximum value of IX
corresponding to Input current of MODE (Input = VDD) from 30 A to 5 A
respectively, changed minimum value of IX corresponding to Input current of
ZZ (Input = VSS) from –30 A to –5 A, changed maximum value of IX
corresponding to Input current of ZZ (Input = VDD) from 5 A to 30 A).
Updated Ordering Information (Updated part numbers, replaced Package
Name column with Package Diagram in the Ordering Information table).
Updated Package Diagrams.
*E
473650
See ECN
VKN
Updated TAP AC Switching Characteristics (Changed minimum value of tTH
,
tTL parameters from 25 ns to 20 ns, changed maximum value of tTDOV
parameter from 5 ns to 10 ns).
Updated Maximum Ratings (Added the Maximum Rating for Supply Voltage
on VDDQ Relative to GND).
Updated Ordering Information (Updated part numbers).
*F
2897278
3044512
03/22/2010
10/01/2010
NJY
NJY
Updated Ordering Information (Removed obsolete part numbers).
Updated Package Diagrams.
*G
Added Ordering Code Definitions.
Added Acronyms and Units of Measure.
Minor edits and updated in new template.
*H
*I
3055212
3357006
10/11/2010
08/29/2011
NJY
Updated Ordering Information (Updated part numbers).
PRIT
Updated Package Diagrams.
Updated in new template.
*J
3424238
11/15/2011
PRIT
Updated Ordering Information (Updated part numbers).
Updated Package Diagrams.
Document Number: 38-05383 Rev. *L
Page 31 of 33
CY7C1440AV33
Document History Page (continued)
Document Title: CY7C1440AV33, 36-Mbit (1 M × 36) Pipelined Sync SRAM
Document Number: 38-05383
Orig. of
Change
Rev.
ECN No.
Issue Date
Description of Change
*K
3616631
05/14/2012
PRIT
Updated Features(Removed200MHzfrequencyrelatedinformation, removed
CY7C1442AV33, CY7C1446AV33 related information, removed 209-ball
FBGA package related information).
Updated Functional Description (Removed CY7C1442AV33, CY7C1446AV33
related information, removed the Note “For best-practices recommendations,
please refer to the Cypress application note System Design Guidelines on
www.cypress.com.” and its reference).
Updated Selection Guide (Removed 200 MHz frequency related information).
Removed Logic Block Diagram – CY7C1442AV33.
Removed Logic Block Diagram – CY7C1446AV33.
Updated Pin Configurations (Updated Figure 1 (Removed CY7C1442AV33
related information), updated Figure 2 (Removed CY7C1442AV33 related
information), removed 209-ball FBGA package related information).
Updated Functional Overview (Removed CY7C1442AV33, CY7C1446AV33
related information).
Updated Truth Table (Removed CY7C1442AV33, CY7C1446AV33 related
information).
Removed Truth Table for Read/Write (Corresponding to CY7C1442AV33).
Removed Truth Table for Read/Write (Corresponding to CY7C1446AV33).
Updated IEEE 1149.1 Serial Boundary Scan (JTAG) (Removed
CY7C1442AV33, CY7C1446AV33 related information).
Updated Identification Register Definitions (Removed CY7C1442AV33,
CY7C1446AV33 related information).
Updated Scan Register Sizes (Removed “Bit Size (× 18)”, “Bit Size (× 72)”
columns).
Updated Boundary Scan Order (Removed CY7C1442AV33 related
information).
Removed Boundary Scan Order (Corresponding to 209-ball FBGA package).
Updated Electrical Characteristics (Removed 200 MHz frequency related
information).
Updated Capacitance (Removed 209-ball FBGA package related information).
Updated Thermal Resistance (Removed 209-ball FBGA package related
information).
Updated Switching Characteristics (Removed 200 MHz frequency related
information).
Updated Package Diagrams (Removed 209-ball FBGA Package related
information (spec 51-85167)).
*L
3749841
09/20/2012
PRIT
No technical updates. Completing sunset review.
Document Number: 38-05383 Rev. *L
Page 32 of 33
CY7C1440AV33
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
Products
Automotive
cypress.com/go/automotive
cypress.com/go/clocks
cypress.com/go/interface
cypress.com/go/powerpsoc
cypress.com/go/plc
PSoC Solutions
Clocks & Buffers
Interface
psoc.cypress.com/solutions
PSoC 1 | PSoC 3 | PSoC 5
Lighting & Power Control
Memory
cypress.com/go/memory
cypress.com/go/image
cypress.com/go/psoc
Optical & Image Sensing
PSoC
Touch Sensing
USB Controllers
Wireless/RF
cypress.com/go/touch
cypress.com/go/USB
cypress.com/go/wireless
© Cypress Semiconductor Corporation, 2003-2012. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 38-05383 Rev. *L
Revised September 20, 2012
Page 33 of 33
i486 is a trademark, and Intel and Pentium are registered trademarks of Intel Corporation. PowerPC is a trademark of IBM Corporation. All products and company names mentioned in this document
may be the trademarks of their respective holders.
相关型号:
CY7C1440KV33-167AXC
Cache SRAM, 1MX36, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, MS-026, TQFP-100
CYPRESS
CY7C1440KV33-250BZXI
Cache SRAM, 1MX36, CMOS, PBGA165, 15 X 17 MM, 1.40 MM HEIGHT, LEAD FREE, FBGA-165
CYPRESS
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