CY7C141-35JC [CYPRESS]
1K x 8 Dual-Port Static Ram; 1K ×8双端口静态RAM型号: | CY7C141-35JC |
厂家: | CYPRESS |
描述: | 1K x 8 Dual-Port Static Ram |
文件: | 总17页 (文件大小:204K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
1CY7C140
fax id: 5200
CY7C130/CY7C131
CY7C140/CY7C141
1K x 8 Dual-Port Static Ram
Features
Functional Description
• True Dual-Ported memory cells which allow simulta-
neous reads of the same memory location
• 1K x 8 organization
• 0.65-micron CMOS for optimum speed/power
• High-speed access: 15 ns
The CY7C130/CY7C131/CY7C140 and CY7C141 are
high-speed CMOS 1K by 8 dual-port static RAMs. Two ports
are provided permitting independent access to any location in
memory. The CY7C130/ CY7C131 can be utilized as either a
standalone 8-bit dual-port static RAM or as a master dual-port
RAM in conjunction with the CY7C140/CY7C141 slave du-
al-port device in systems requiring 16-bit or greater word
widths. It is the solution to applications requiring shared or
buffered data, such as cache memory for DSP, bit-slice, or
multiprocessor designs.
• Low operating power: I = 90 mA (max.)
CC
• Fully asynchronous operation
• Automatic power-down
• Master CY7C130/CY7C131 easily expands data bus
width to 16 or more bits using slave CY7C140/CY7C141
• BUSY output flag on CY7C130/CY7C131; BUSY input
on CY7C140/CY7C141
• INT flag for port-to-port communication
• Availablein 48-pin DIP (CY7C130/140), 52-pin PLCCand
52-pin TQFP
• Pin-compatible and functionally equivalent to
IDT7130/IDT7140
Each port has independent control pins; chip enable (CE),
write enable (R/W), and output enable (OE). Two flags are
provided on each port, BUSY and INT. BUSY signals that the
port is trying to access the same location currently being ac-
cessed by the other port. INT is an interrupt flag indicating that
data has been placed in a unique location (3FF for the left port
and 3FE for the right port). An automatic power-down feature
is controlled independently on each port by the chip enable
(CE) pins.
The CY7C130 and CY7C140 are available in 48-pin DIP. The
CY7C131 and CY7C141 are available in 52-pin PLCC and
PQFP.
Logic Block Diagram
Pin Configurations
R/W
L
R/W
R
CE
L
CE
R
DIP
Top View
OE
L
OE
R
V
48
CE
R/W
BUSY
CC
1
L
L
47
46
45
44
CE
R
R/W
BUSY
INT
2
3
4
5
6
L
R
I/O
I/O
I/O
7L
7R
0R
I/O
CONTROL
I/O
CONTROL
INT
R
L
OE
R
L
I/O
0L
A
0L
OE
A
0R
43
42
R
[1]
A
A
A
BUSY
BUSY
1L
2L
L
R
7
8
9
10
11
12
A
A
A
A
41
40
1R
A
A
A
2R
3L
4L
5L
9L
0L
9R
0R
MEMORY
ARRAY
ADDRESS
DECODER
ADDRESS
DECODER
A
A
39
38
37
36
35
34
3R
4R
A
A
A
6L
5R
7C130
A
A
A
8R
A
A
13 7C140
6R
7L
8L
14
15
16
17
18
19
20
21
22
23
24
7R
A
9L
I/O
A
9R
33
32
31
30
29
28
27
26
25
0L
1L
2L
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
ARBITRATION
LOGIC
7R
6R
(7C130/7C131 ONLY)
AND
3L
4L
5R
CE
L
CE
R
4R
INTERRUPT LOGIC
OE
L
OE
R
3R
5L
6L
7L
2R
R/W
R/W
R
L
I/O
I/O
1R
GND
[2]
L
0R
[2]
INT
INT
R
C130-2
C130-1
Notes:
1. CY7C130/CY7C131 (Master): BUSY is open drain output and requires pull-up resistor
CY7C140/CY7C141 (Slave): BUSY is input.
2. Open drain outputs: pull-up resistor required
s
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
May 1989 – Revised March 27, 1997
CY7C130/CY7C131
CY7C140/CY7C141
Pin Configuration (continued)
PLCC
Top View
PQFP
Top View
7
6
5
4
3
2
1
52 51 50 49 48 47
46
A
A
OE
1L
2L
3L
4L
5L
6L
7L
8L
9L
0L
1L
2L
3L
8
R
A
A
A
A
A
A
9
45
44
43
42
41
40
39
38
37
36
35
34
0R
1R
2R
3R
A
52 5150 49 48 47 4645 44 43 42 41 40
10
11
12
13
14
15
16
17
18
19
20
A
A
A
A
A
A
A
OE
R
1L
2L
3L
4L
5L
6L
1
39
38
37
36
35
34
33
32
31
30
29
28
27
A
0R
A
1R
A
2
A
3
4R
5R
7C131
7C141
A
2R
A
3R
A
4R
A
5R
A
4
A
5
A
6R
A
7R
A
8R
A
9R
A
6
7C131
7C141
A
A
I/O
I/O
I/O
I/O
7L
7
A
A
A
A
8L
6R
8
A
I/O
I/O
9L
0L
1L
7R
9
NC
I/O
8R
9R
10
11
12
13
7R
2122 23 24 25 26 27 28 29 30 31 32 33
I/O
I/O
NC
I/O
2L
3L
C130-3
7R
1415 16 17 18 19 20 21 22 23 24 25 26
C130-4
Selection Guide
7C130-30
7C131-30
7C140-30
7C141-30
7C130-35
7C131-35
7C140-35
7C141-35
7C130-45
7C131-45
7C140-45
7C141-45
7C130-55
7C131-55
7C140-55
7C141-55
[3,4]
[3]
7C131-15
7C131-25
7C141-15
7C141-25
Maximum Access Time (ns)
15
25
30
35
120
170
45
45
90
55
90
Maximum Operating
Current (mA)
Com’l/Ind
Military
190
170
170
120
35
120
35
Maximum Standby
Current (mA)
Com’l/Ind
Military
75
65
65
65
45
45
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Static Discharge Voltage .......................................... >2001V
(per MIL-STD-883, Method 3015)
Storage Temperature ................................. –65°C to +150°C
Latch-Up Current.................................................... >200 mA
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Operating Range
Supply Voltage to Ground Potential
(Pin 48 to Pin 24)........................................... –0.5V to +7.0V
Ambient
Range
Commercial
Industrial
Temperature
V
CC
DC Voltage Applied to Outputs
in High Z State ............................................... –0.5V to +7.0V
0°C to +70°C
5V ± 10%
5V ± 10%
5V ± 10%
–40°C to +85°C
–55°C to +125°C
DC Input Voltage............................................ –3.5V to +7.0V
[5]
Military
Output Current into Outputs (LOW) .............................20 mA
Notes:
3. 15 and 25-ns version available only in PLCC/PQFP packages.
4. Shaded area contains preliminary information.
5.
TA is the “instant on” case temperature
2
CY7C130/CY7C131
CY7C140/CY7C141
Electrical Characteristics Over the Operating Range[6]
[3]
7C130-30
7C130-35 7C130-45,55
7C131-25,30 7C131-35 7C131-45,55
[3,4]
7C131-15
7C141-15
7C140-30
7C140-35 7C140-45,55
7C141-25,30 7C141-35 7C141-45,55
Parameter
Description
Output HIGH
Test Conditions
Min. Max. Min. Max. Min. Max. Min. Max. Unit
V
V
= Min., I = –4.0 mA 2.4
2.4
2.4
2.4
V
OH
CC
OH
Voltage
V
Output LOW
Voltage
I
I
= 4.0 mA
0.4
0.5
0.4
0.5
0.4
0.5
0.4
0.5
V
OL
OL
OL
[7]
= 16.0 mA
V
V
Input HIGH Voltage
Input LOW Voltage
2.2
2.2
2.2
2.2
V
V
IH
IL
0.8
+5
0.8
+5
0.8
+5
0.8
+5
I
I
I
I
Input Leakage
Current
GND < V < V
–5
–5
–5
–5
–5
–5
–5
–5
µA
IX
I
CC
Output Leakage
Current
GND < V < V ,
CC
+5
–350
190
+5
+5
+5
µA
OZ
OS
CC
O
Output Disabled
Output Short
Circuit Current
V
V
= Max.,
–350
170
–350
–350 mA
CC
[8, 9]
= GND
OUT
V
Operating
CE = V ,
Com’l
Mil
120
170
90
mA
mA
mA
CC
IL
Supply Current
Outputs Open,
120
[10]
f = f
MAX
I
I
Standby Current
Both Ports,
TTL Inputs
CE and CE >
R
Com’l
Mil
75
65
45
65
35
45
SB1
SB2
L
[10]
V , f = f
IH
MAX
Standby Current
One Port,
TTL Inputs
CE or CE > V , Com’l
135
115
90
75
90
L
R
IH
Active Port Out-
Mil
115
puts Open,
[10]
f = f
MAX
I
I
Standby Current
Both Ports,
CMOS Inputs
Both Ports CE
Com’l
Mil
15
15
15
15
15
15
mA
mA
SB3
SB4
L
and CE > V
–
R
CC
0.2V,
V
> V – 0.2V
IN
CC
or V < 0.2V, f = 0
IN
Standby Current
One Port,
CMOS Inputs
One Port CE or
Com’l
Mil
125
105
85
70
85
L
CE > V – 0.2V,
R
CC
105
V
> V – 0.2V
IN CC
or V < 0.2V,
IN
Active Port Outputs
Open,
[10]
f = f
MAX
Notes:
6. See the last page of this specification for Group A subgroup testing information.
7. BUSY and INT pins only.
8. Duration of the short circuit should not exceed 30 seconds.
9. This parameter is guaranteed but not tested.
10. At f=fMAX, address and data inputs are cycling at the maximum frequency of read cycle of 1/tRC and using AC Test Waveforms input levels of GND to 3V.
Capacitance[9]
Parameter
Description
Input Capacitance
Output Capacitance
Test Conditions
T = 25°C, f = 1 MHz,
Max.
15
Unit
C
C
pF
pF
IN
A
V
= 5.0V
CC
10
OUT
]
3
CY7C130/CY7C131
CY7C140/CY7C141
AC Test Loads and Waveforms
5V
R1 893Ω
R1 893Ω
5V
5V
OUTPUT
OUTPUT
281Ω
BUSY
R2
347Ω
R2
347Ω
OR
INT
30
30 pF
5 pF
INCLUDING
JIGAND
INCLUDING
JIGAND
pF
C130-5
(a)
(b)
3.0V
SCOPE
SCOPE
BUSY Output Load
(CY7C130/CY7C131 ONLY)
ALL INPUT PULSES
Equivalent to:
THÉVENIN EQUIVALENT
90%
C130-6
10%
90%
10%
250Ω
GND
OUTPUT
1.40V
≤5ns
≤ 5 ns
[6,11]
Switching Characteristics Over the Operating Range
[3]
7C130-25
7C130-30
7C131-30
7C140-30
7C141-30
7C131-25
7C140-25
7C141-25
[3,4]
7C131-15
7C141-15
Parameter
Description
Min.
Max.
Min.
Max.
Min.
Max.
Unit
READ CYCLE
t
t
t
t
t
t
t
t
t
t
t
Read Cycle Time
15
0
25
0
30
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RC
[12]
Address to Data Valid
15
25
30
AA
Data Hold from Address Change
OHA
ACE
DOE
LZOE
HZOE
LZCE
HZCE
PU
[12]
CE LOW to Data Valid
15
10
25
15
30
20
[12]
OE LOW to Data Valid
[9,13, 14]
OE LOW to Low Z
3
3
0
3
5
0
3
5
0
[9,13, 14]
OE HIGH to High Z
10
10
15
15
15
25
15
15
25
[9,13, 14]
CE LOW to Low Z
[9,13, 14]
CE HIGH to High Z
[9]
CE LOW to Power-Up
[9]
CE HIGH to Power-Down
PD
[15]
WRITE CYCLE
t
t
t
t
t
t
t
t
t
t
Write Cycle Time
15
12
12
2
25
20
20
2
30
25
25
2
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
WC
CE LOW to Write End
SCE
AW
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
R/W Pulse Width
HA
0
0
0
SA
12
10
0
15
15
0
25
15
0
PWE
SD
Data Set-Up to Write End
Data Hold from Write End
HD
[14]
R/W LOW to High Z
10
15
15
HZWE
[14]
R/W HIGH to Low Z
0
0
0
LZWE
Notes:
11. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading of the specified
I
OL/IOH, and 30-pF load capacitance.
12. AC Test Conditions use VOH = 1.6V and VOL = 1.4V.
13. At any given temperature and voltage condition for any given device, tHZCE is less than tLZCE and tHZOE is less than tLZOE
.
14.
tLZCE, tLZWE, tHZOE, tLZOE, tHZCE and tHZWE are tested with CL = 5pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady state voltage.
15. The internal write time of the memory is defined by the overlap of CS LOW and R/W LOW. Both signals must be low to initiate a write and either signal can terminate
a write by going high. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write
4
CY7C130/CY7C131
CY7C140/CY7C141
[6,11]
Switching Characteristics Over the Operating Range
(continued)
[3]
7C130-25
7C130-30
7C131-30
7C140-30
7C141-30
7C131-25
7C140-25
7C141-25
[3,4]
7C131-15
7C141-15
Parameter
Description
Min.
Max.
Min.
Max.
Min.
Max.
Unit
BUSY/INTERRUPT TIMING
t
t
t
t
t
t
t
t
t
BUSY LOW from Address Match
BUSY HIGH from Address Mismatch
BUSY LOW from CE LOW
15
15
15
15
20
20
20
20
20
20
20
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
BLA
BHA
BLC
BHC
PS
[16]
[16]
BUSY HIGH from CE HIGH
Port Set Up for Priority
5
0
5
0
5
0
[17]
R/W LOW after BUSY LOW
R/W HIGH after BUSY HIGH
BUSY HIGH to Valid Data
Write Data Valid to Read Data Valid
WB
13
20
30
WH
15
25
30
BDD
DDD
Note
18
Note
18
Note
18
t
Write Pulse to Data Delay
Note
18
Note
18
Note
18
ns
WDD
INTERRUPT TIMING
t
t
t
t
t
t
R/W to INTERRUPT Set Time
15
15
15
15
15
15
25
25
25
25
25
25
25
25
25
25
25
25
ns
ns
ns
ns
ns
ns
WINS
EINS
INS
CE to INTERRUPT Set Time
Address to INTERRUPT Set Time
[16]
OE to INTERRUPT Reset Time
CE to INTERRUPT Reset Time
OINR
EINR
INR
[16]
[16]
Address to INTERRUPT Reset Time
Notes:
16. These parameters are measured from the input signal changing, until the output pin goes to a high-impedance state.
17. CY7C140/CY7C141 only.
18. A write operation on Port A, where Port A has priority, leaves the data on Port B’s outputs undisturbed until one access time after one of the following:
BUSY on Port B goes HIGH.
Port B’s address is toggled.
CE for Port B is toggled.
R/W for Port B is toggled during valid read.
[6,11]
Switching Characteristics Over the Operating Range
7C130-35
7C131-35
7C140-35
7C141-35
7C130-45
7C131-45
7C140-45
7C141-45
7C130-55
7C131-55
7C140-55
7C141-55
Parameter
Description
Min.
Max.
Min.
Max.
Min.
Max.
Unit
READ CYCLE
t
t
t
t
t
t
t
t
t
t
t
Read Cycle Time
35
0
45
0
55
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RC
[12]
Address to Data Valid
35
45
55
AA
Data Hold from Address Change
OHA
ACE
DOE
LZOE
HZOE
LZCE
HZCE
PU
[12]
CE LOW to Data Valid
35
20
45
25
55
25
[12]
OE LOW to Data Valid
[9,13, 14]
OE LOW to Low Z
3
5
0
3
5
0
3
5
0
[9,13, 14]
OE HIGH to High Z
20
20
35
20
20
35
25
25
35
[9,13, 14]
CE LOW to Low Z
[9,13, 14]
CE HIGH to High Z
[9]
CE LOW to Power-Up
[9]
CE HIGH to Power-Down
PD
5
CY7C130/CY7C131
CY7C140/CY7C141
[6,11]
Switching Characteristics Over the Operating Range
(continued)
7C130-35
7C131-35
7C140-35
7C141-35
7C130-45
7C130-55
7C131-55
7C140-55
7C141-55
7C131-45
7C140-45
7C141-45
Parameter
Description
Min.
Max.
Min.
Max.
Min.
Max.
Unit
[15]
WRITE CYCLE
t
t
t
t
t
t
t
t
t
t
Write Cycle Time
35
30
30
2
45
35
35
2
55
40
40
2
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
WC
CE LOW to Write End
SCE
AW
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
R/W Pulse Width
HA
0
0
0
SA
25
15
0
30
20
0
30
20
0
PWE
SD
Data Set-Up to Write End
Data Hold from Write End
HD
[14]
R/W LOW to High Z
20
20
25
HZWE
LZWE
[14]
R/W HIGH to Low Z
0
0
0
BUSY/INTERRUPT TIMING
t
t
t
t
t
t
t
t
t
BUSY LOW from Address Match
20
20
20
20
25
25
25
25
30
30
30
30
ns
ns
ns
ns
ns
ns
ns
ns
ns
BLA
BHA
BLC
BHC
PS
[16]
BUSY HIGH from Address Mismatch
BUSY LOW from CE LOW
[16]
BUSY HIGH from CE HIGH
Port Set Up for Priority
5
0
5
0
5
0
[17]
R/W LOW after BUSY LOW
R/W HIGH after BUSY HIGH
BUSY HIGH to Valid Data
Write Data Valid to Read Data Valid
WB
30
35
35
WH
35
45
45
BDD
DDD
Note
18
Note
18
Note
18
t
Write Pulse to Data Delay
Note
18
Note
18
Note
18
ns
WDD
INTERRUPT TIMING
t
t
t
t
t
t
R/W to INTERRUPT Set Time
25
25
25
25
25
25
35
35
35
35
35
35
45
45
45
45
45
45
ns
ns
ns
ns
ns
ns
WINS
EINS
INS
CE to INTERRUPT Set Time
Address to INTERRUPT Set Time
[16]
OE to INTERRUPT Reset Time
OINR
EINR
INR
[16]
CE to INTERRUPT Reset Time
[16]
Address to INTERRUPT Reset Time
Switching Waveforms
[19, 20]
Either Port Address Access
Read Cycle No.1
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATAVALID
DATA VALID
C130-7
Notes:
19. R/W is HIGH for read cycle.
20. Device is continuously selected, CE = VIL and OE = VIL.
6
CY7C130/CY7C131
CY7C140/CY7C141
Switching Waveforms (continued)
[19, 21]
Read Cycle No. 2
Either Port CE/OE Access
CE
OE
t
HZCE
t
ACE
t
HZOE
t
DOE
t
LZOE
t
LZCE
DATA VALID
DATA OUT
t
PU
t
PD
I
CC
I
SB
C130-8
[20]
Read Cycle No.3
Read with BUSY, Master: CY7C130 and CY7C131
t
RC
ADDRESS
R
ADDRESS MATCH
t
PWE
R/W
R
t
HD
D
INR
VALID
ADDRESS MATCH
ADDRESS
L
t
PS
t
BHA
BUSY
L
t
BLA
t
BDD
DOUT
VALID
L
t
DDD
t
WDD
C130-9
[15, 22]
Write CycleNo.1 (OE Three-States Data I/Os - Either Port)
Either Port
t
WC
ADDRESS
CE
t
SCE
t
t
AW
HA
t
SA
t
PWE
R/W
t
t
HD
SD
DATA
IN
DATA VALID
OE
t
HZOE
HIGH IMPEDANCE
D
OUT
C130-10
Notes:
21. Address valid prior to or coincident with CE transition LOW.
22. If OEis LOW during a R/W controlled write cycle, the write pulse width must be the larger of tPWE or tHZWE + tSD to allow the data I/O pins to enter high impedance and for data
to be placed on the bus for the required tSD
.
7
CY7C130/CY7C131
CY7C140/CY7C141
Switching Waveforms (continued)
[16, 23]
Write Cycle No. 2 (R/W Three-States Data I/Os - Either Port)
Either Port
t
WC
ADDRESS
CE
t
t
HA
SCE
t
AW
t
SA
t
PWE
R/W
t
t
SD
HD
DATA
IN
DATA VALID
t
LZWE
t
HZWE
HIGH IMPEDANCE
DATA
OUT
C130-11
Busy Timing Diagram No. 1 (CE Arbitration)
CE Valid First:
L
ADDRESS
L,R
ADDRESS MATCH
CE
L
t
PS
CE
R
t
t
BHC
BLC
BUSY
R
C130-12
CE Valid First:
R
ADDRESS
L,R
ADDRESS MATCH
CE
R
t
PS
CE
L
t
t
BHC
BLC
BUSY
L
C130-13
Note:
23. If the CE LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high-impedance state
8
CY7C130/CY7C131
CY7C140/CY7C141
Switching Waveforms (continued)
Busy Timing Diagram No. 2 (Address Arbitration)
Left Address Valid First:
t
or t
WC
RC
ADDRESS MATCH
ADDRESS MISMATCH
ADDRESS
L
t
PS
ADDRESS
R
t
t
BHA
BLA
BUSY
R
C130-14
Right Address Valid First:
t
or t
WC
RC
ADDRESS MATCH
ADDRESS MISMATCH
ADDRESS
R
t
PS
ADDRESS
L
t
t
BHA
BLA
BUSY
L
C130-15
Busy Timing Diagram No. 3
Write with BUSY (Slave:CY7C140/CY7C141)
CE
t
PWE
R/W
t
t
WH
WB
BUSY
C130-16
9
CY7C130/CY7C131
CY7C140/CY7C141
Switching Waveforms (continued)
Interrupt Timing Diagrams
Left Side Sets INT
R
t
WC
ADDR
L
WRITE 3FF
t
t
HA
INS
CE
L
t
EINS
R/W
L
t
SA
t
WINS
INT
R
C130-17
Right Side Clears INT
R
t
RC
ADDR
READ 3FF
R
t
t
INT
HA
CE
R
t
EINR
R/W
R
OE
R
t
OINR
INT
R
C130-18
Right Side Sets INT
L
t
WC
ADDR
WRITE 3FE
R
t
t
HA
INS
CE
R
t
EINS
R/W
R
t
SA
t
WINS
INT
L
C130-19
Left Side Clears INT
L
t
RC
ADDR
READ 3FE
R
t
t
INR
HA
CE
L
t
EINR
R/W
L
OE
L
t
OINR
INT
L
C130-20
10
CY7C130/CY7C131
CY7C140/CY7C141
Typical DC and AC Characteristics
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
OUTPUT SOURCE CURRENT
vs. OUTPUT VOLTAGE
NORMALIZED SUPPLY CURRENT
vs.SUPPLYVOLTAGE
120
100
80
1.4
1.2
1.0
I
CC
1.2
I
CC
1.0
0.8
0.8
0.6
0.4
60
V
CC
=5.0V
V
V
=5.0V
=5.0V
CC
0.6
0.4
T =25°C
A
IN
40
0.2
0.6
20
0
I
SB3
I
0.2
0.0
SB3
-55
25
125
0
1.0
2.0
3.0
4.0
4.0
4.5
5.0
5.5
6.0
AMBIENT TEMPERATURE (°C)
OUTPUT VOLTAGE (V)
SUPPLY VOLTAGE (V)
NORMALIZED ACCESS TIME
vs. AMBIENT TEMPERATURE
OUTPUT SINK CURRENT
vs.OUTPUT VOLTAGE
NORMALIZED ACCESS TIME
vs. SUPPLY VOLTAGE
140
120
1.6
1.4
1.4
1.3
1.2
1.1
100
80
1.2
1.0
60
T =25°C
A
V
CC
=5.0V
1.0
40
0.8
V
=5.0V
CC
20
0
0.9
0.8
T =25°C
A
0.6
-55
0.0
1.0
2.0
3.0
4.0
25
125
4.0
4.5
5.0
5.5
6.0
AMBIENT TEMPERATURE (°C)
OUTPUT VOLTAGE (V)
SUPPLYVOLTAGE (V)
TYPICAL POWER -ON CURRENT
vs. SUPPLY VOLTAGE
TYPICAL ACCESS TIME CHANGE
vs. OUTPUT LOADING
NORMALIZED I
vs.CYCLETIME
CC
1.25
30.0
25.0
3.0
2.5
V
CC
=4.5V
T =25°C
A
V
IN
=0.5V
1.0
2.0
20.0
15.0
10.0
1.5
1.0
0.75
V
=4.5V
CC
0.5
0.0
5.0
0
T =25°C
A
0.50
10
20
30
40
0
1.0
2.0
3.0
4.0 5.0
0
200 400 600 800 1000
CAPACITANCE (pF)
CYCLE FREQUENCY (MHz)
SUPPLYVOLTAGE (V)
11
CY7C130/CY7C131
CY7C140/CY7C141
Ordering Information
Speed
Package
Name
Operating
(ns)
Ordering Code
CY7C130-30PC
CY7C130-30PI
CY7C130-35PC
CY7C130-35PI
CY7C130-35DMB
CY7C130-45PC
CY7C130-45PI
CY7C130-45DMB
CY7C130-55PC
CY7C130-55PI
CY7C130-55DMB
Package Type
Range
Commercial
Industrial
Commercial
Industrial
Military
30
P25
P25
P25
P25
D26
P25
P25
D26
P25
P25
D26
48-Lead (600-Mil) Molded DIP
48-Lead (600-Mil) Molded DIP
48-Lead (600-Mil) Molded DIP
48-Lead (600-Mil) Molded DIP
48-Lead (600-Mil) Sidebraze DIP
48-Lead (600-Mil) Molded DIP
48-Lead (600-Mil) Molded DIP
48-Lead (600-Mil) Sidebraze DIP
48-Lead (600-Mil) Molded DIP
48-Lead (600-Mil) Molded DIP
48-Lead (600-Mil) Sidebraze DIP
35
45
55
Commercial
Industrial
Military
Commercial
Industrial
Military
Speed
(ns)
Package
Name
Operating
Range
Ordering Code
CY7C131-15JC
CY7C131-15NC
CY7C131-25JC
CY7C131-25NC
CY7C131-25JI
CY7C131-25NI
CY7C131-30JC
CY7C131-30NC
CY7C131-30JI
CY7C131-35JC
CY7C131-35NC
CY7C131-35JI
CY7C131-35NI
CY7C131-45JC
CY7C131-45NC
CY7C131-45JI
CY7C131-45NI
CY7C131-55JC
CY7C131-55NC
CY7C131-55JI
CY7C131-55NI
Package Type
15
J69
N52
J69
N52
J69
N52
J69
N52
J69
J69
N52
J69
N52
J69
N52
J69
N52
J69
N52
J69
N52
52-Lead Plastic Leaded Chip Carrier Commercial
52-Pin Plastic Quad Flatpack
25
52-Lead Plastic Leaded Chip Carrier Commercial
52-Pin Plastic Quad Flatpack
52-Lead Plastic Leaded Chip Carrier Industrial
52-Pin Plastic Quad Flatpack
30
35
52-Lead Plastic Leaded Chip Carrier Commercial
52-Pin Plastic Quad Flatpack
52-Lead Plastic Leaded Chip Carrier Industrial
52-Lead Plastic Leaded Chip Carrier Commercial
52-Pin Plastic Quad Flatpack
52-Lead Plastic Leaded Chip Carrier Industrial
52-Pin Plastic Quad Flatpack
45
55
52-Lead Plastic Leaded Chip Carrier Commercial
52-Pin Plastic Quad Flatpack
52-Lead Plastic Leaded Chip Carrier Industrial
52-Pin Plastic Quad Flatpack
52-Lead Plastic Leaded Chip Carrier Commercial
52-Pin Plastic Quad Flatpack
52-Lead Plastic Leaded Chip Carrier Industrial
52-Pin Plastic Quad Flatpack
Shaded area contains preliminary information.
12
CY7C130/CY7C131
CY7C140/CY7C141
Ordering Information (continued)
Speed
(ns)
Package
Operating
Ordering Code
CY7C140-30PC
CY7C140-30PI
CY7C140-35PC
CY7C140-35PI
CY7C140-35DMB
CY7C140-45PC
CY7C140-45PI
CY7C140-45DMB
CY7C140-55PC
CY7C140-55PI
CY7C140-55DMB
Name
P25
P25
P25
P25
D26
P25
P25
D26
P25
P25
D26
Package Type
Range
Commercial
Industrial
Commercial
Industrial
Military
30
48-Lead (600-Mil) Molded DIP
48-Lead (600-Mil) Molded DIP
48-Lead (600-Mil) Molded DIP
48-Lead (600-Mil) Molded DIP
48-Lead (600-Mil) Sidebraze DIP
48-Lead (600-Mil) Molded DIP
48-Lead (600-Mil) Molded DIP
48-Lead (600-Mil) Sidebraze DIP
48-Lead (600-Mil) Molded DIP
48-Lead (600-Mil) Molded DIP
48-Lead (600-Mil) Sidebraze DIP
35
45
55
Commercial
Industrial
Military
Commercial
Industrial
Military
Speed
(ns)
Package
Name
Operating
Range
Ordering Code
CY7C141-15JC
CY7C141-15NC
CY7C141-25JC
CY7C141-25NC
CY7C141-25JI
CY7C141-25NI
CY7C141-30JC
CY7C141-30NC
CY7C141-30JI
CY7C141-35JC
CY7C141-35NC
CY7C141-35JI
CY7C141-35NI
CY7C141-45JC
CY7C141-45NC
CY7C141-45JI
CY7C141-45NI
CY7C141-55JC
CY7C141-55NC
CY7C141-55JI
CY7C141-55NI
Package Type
15
J69
N52
J69
N52
J69
N52
J69
N52
J69
J69
N52
J69
N52
J69
N52
J69
N52
J69
N52
J69
N52
52-Lead Plastic Leaded Chip Carrier Commercial
52-Pin Plastic Quad Flatpack
25
52-Lead Plastic Leaded Chip Carrier Commercial
52-Pin Plastic Quad Flatpack
52-Lead Plastic Leaded Chip Carrier Industrial
52-Pin Plastic Quad Flatpack
30
35
52-Lead Plastic Leaded Chip Carrier Commercial
52-Pin Plastic Quad Flatpack
52-Lead Plastic Leaded Chip Carrier Industrial
52-Lead Plastic Leaded Chip Carrier Commercial
52-Pin Plastic Quad Flatpack
52-Lead Plastic Leaded Chip Carrier Industrial
52-Pin Plastic Quad Flatpack
45
55
52-Lead Plastic Leaded Chip Carrier Commercial
52-Pin Plastic Quad Flatpack
52-Lead Plastic Leaded Chip Carrier Industrial
52-Pin Plastic Quad Flatpack
52-Lead Plastic Leaded Chip Carrier Commercial
52-Pin Plastic Quad Flatpack
52-Lead Plastic Leaded Chip Carrier Industrial
52-Pin Plastic Quad Flatpack
Shaded area contains preliminary information.
13
CY7C130/CY7C131
CY7C140/CY7C141
MILITARY SPECIFICATIONS
Switching Characteristics
Group A Subgroup Testing
Parameter
Subgroups
DC Characteristics
READ CYCLE
t
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
Parameter
Subgroups
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
RC
V
t
OH
AA
V
t
OL
ACE
DOE
V
IH
t
V Max.
IL
WRITE CYCLE
I
IX
t
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
WC
I
I
OZ
CC
t
SCE
t
AW
I
I
I
I
SB1
SB2
SB3
SB4
t
HA
t
SA
t
PWE
t
SD
t
HD
Parameter
Subgroups
BUSY/INTERRUPT TIMING
t
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
BLA
t
BHA
t
BLC
t
BHC
t
PS
t
WINS
t
EINS
t
INS
OINR
t
t
EINR
t
INR
BUSY TIMING
[24]
t
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
WB
t
WH
t
BDD
Note:
24. CY7C140/CY7C141 only.
Document #: 38-00027-L
r
14
CY7C130/CY7C131
CY7C140/CY7C141
Package Diagrams
48-Lead (600-Mil) Sidebraze DIP D26
52-Lead Plastic Leaded Chip Carrier J69
15
CY7C130/CY7C131
CY7C140/CY7C141
Package Diagrams (continued)
48-Lead (600-Mil) Molded DIP P25
© Cypress Semiconductor Corporation, 1997. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
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