CY7C1393AV18-167BZC [CYPRESS]
18-Mbit DDR-II SIO SRAM 2-Word Burst Architecture; 18兆位的DDR -II SIO SRAM 2字突发架构
| 型号： | CY7C1393AV18-167BZC |
| 厂家： | 
CYPRESS |
| 描述： | 18-Mbit DDR-II SIO SRAM 2-Word Burst Architecture |
| 文件： | 总21页 (文件大小：332K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C1392AV18
CY7C1393AV18
CY7C1394AV18
PRELIMINARY
18-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
Features
Functional Description
• 18-Mbit density (2M x 8, 1M x 18, 512K x 36)
• 250-MHz clock for high bandwidth
• 2-Word burst for reducing address bus frequency
The CY7C1392AV18/CY7C1393AV18/CY7C1394AV18 are
1.8V Synchronous Pipelined SRAMs equipped with DDR-II
SIO (Double Data Rate Separate I/O) architecture. The DDR-II
SIO consists of two separate ports to access the memory
array. The Read port has dedicated Data outputs and the Write
port has dedicated Data inputs to completely eliminate the
need to “turn around’ the data bus required with common I/O
devices. Access to each port is accomplished using a common
address bus. Addresses for Read and Write are latched on
alternate rising edges of the input (K) clock. Write data is regis-
tered on the rising edges of both K and K. Read data is driven
on the rising edges of C and C if provided, or on the rising edge
of K and K if C/C are not provided. Each address location is
associated with two 8-bit words in the case of
CY7C1392AV18, two 18-bit words in the case of
CY7C1393AV18, and two 36-bit words in the case of
CY7C1394AV18, that burst sequentially into or out of the
device.
• Double Data Rate (DDR) interfaces (data transferred at
500 MHz) @ 250 MHz
• Two input clocks (K and K) for precise DDR timing
— SRAM uses rising edges only
• Two output clocks (C and C) account for clock skew
and flight time mismatching
• Echo clocks (CQ and CQ) simplify data capture in
high-speed systems
• Synchronous internally self-timed writes
• 1.8V core power supply with HSTL inputs and outputs
• Variable drive HSTL output buffers
• Expanded HSTL output voltage (1.4V–VDD
)
Asynchronous inputs include impedance match (ZQ).
Synchronous data outputs are tightly matched to the two
output echo clocks CQ/CQ, eliminating the need for separately
capturing data from each individual DDR-II SIO SRAM in the
system design. Output data clocks (C/C) enable maximum
system clocking and data synchronization flexibility.
• 13 x 15 x 1.4mm 1.0-mm pitch fBGA package, 165 ball
(11 x 15 matrix)
• JTAG 1149.1 compatible test access port
• Delay Lock Loop (DLL) for accurate data placement
All synchronous inputs pass through input registers controlled
by the K/K input clocks. All data outputs pass through output
registers controlled by the C/C input clocks (or K/K in single
clock mode). Writes are conducted with on-chip synchronous
self-timed write circuitry.
Configuration
CY7C1392AV18–2M x 8
CY7C1393AV18–1M x18
CY7C1394AV18–512K x 36
Logic Block Diagram (CY7C1392AV18)
D[7:0]
8
Write
Data Reg
Write
Data Reg
Address
Register
A
(19:0)
20
1M x 8
1M x 8
Memory Memory
Array
Array
K
LD
CLK
Control
Logic
R/W
K
Gen.
C
C
DOFF
Read Data Reg.
16
CQ
CQ
R/W
8
VREF
8
Reg.
Reg.
Reg.
8
Control
Logic
LD
8
BWS0
Q[7:0]
BWS1
8
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Document #: 38-05503 Rev. *A
Revised June 1, 2004
CY7C1392AV18
CY7C1393AV18
CY7C1394AV18
PRELIMINARY
Logic Block Diagram (CY7C1393AV18)
18
D[17:0]
Write
Data Reg
Write
Data Reg
Address
A
Register
(18:0)
19
512K x 18 512K x 18
Memory
Array
Memory
Array
K
LD
CLK
Control
Logic
R/W
K
Gen.
C
C
DOFF
Read Data Reg.
36
CQ
CQ
R/W
18
VREF
18
Reg.
Reg.
Reg.
18
Control
Logic
LD
18
BWS0
Q[17:0]
BWS1
18
Logic Block Diagram (CY7C1394AV18)
36
D[35:0]
Write
Data Reg
Write
Data Reg
Address
A
Register
(17:0)
18
256K x 36 256K x 36
Memory
Array
Memory
Array
K
LD
CLK
Control
Logic
R/W
K
Gen.
C
C
DOFF
Read Data Reg.
72
CQ
CQ
R/W
36
VREF
36
Reg.
Reg.
Reg.
36
Control
Logic
LD
BWS[3:0]
36
Q[35:0]
36
Selection Guide
250 MHz
250
200 MHz
167 MHz
167
Unit
MHz
mA
Maximum Operating Frequency
Maximum Operating Current
200
750
800
700
Document #: 38-05503 Rev. *A
Page 2 of 21
CY7C1392AV18
CY7C1393AV18
CY7C1394AV18
PRELIMINARY
Pin Configurations
CY7C1392AV18 (2M × 8) – 11 × 15 FBGA
1
2
3
4
5
6
7
NC
BWS0
A
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
8
9
10
11
CQ
Q3
D3
NC
CQ
NC
NC
NC
NC
VSS/72M
A
R/W
BWS1
K
LD
A
VSS/36M
A
B
C
D
E
F
G
H
J
K
L
NC
NC
D4
NC
NC
D5
VREF
NC
NC
Q6
NC
NC
NC
Q4
NC
Q5
VDDQ
NC
A
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
A
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
K
A
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
NC
NC
NC
NC
NC
VDDQ
NC
NC
NC
NC
D2
NC
NC
VREF
Q1
Q2
NC
NC
DOFF
NC
NC
NC
NC
NC
ZQ
D1
NC
Q0
NC
D6
NC
NC
NC
NC
NC
NC
NC
NC
D7
NC
NC
NC
Q7
VSS
VSS
VSS
A
A
VSS
A
C
VSS
A
A
VSS
VSS
NC
NC
NC
NC
NC
NC
D0
NC
NC
M
N
P
A
A
A
A
A
A
TDO
TCK
A
C
A
TMS
TDI
R
CY7C1393AV18 (1M × 18) – 11 × 15 FBGA
1
2
3
4
5
6
7
NC
BWS0
A
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
8
9
10
11
CQ
Q8
D8
D7
CQ
NC
NC
NC
VSS/144M NC/36M
R/W
BWS1
K
LD
A
VSS/72M
A
B
C
D
E
F
G
H
J
K
L
Q9
NC
D11
NC
Q12
D13
VREF
NC
D9
D10
Q10
Q11
D12
Q13
VDDQ
D14
Q14
D15
A
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
A
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
K
A
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
NC
NC
NC
NC
NC
VDDQ
NC
NC
Q7
NC
D6
NC
NC
VREF
Q4
NC
NC
NC
DOFF
NC
NC
Q6
Q5
D5
ZQ
D4
Q3
Q2
NC
Q15
NC
NC
D3
NC
NC
NC
NC
NC
NC
D17
NC
D16
Q16
Q17
VSS
VSS
VSS
A
A
VSS
A
C
VSS
A
A
VSS
VSS
NC
NC
NC
Q1
NC
D0
D2
D1
Q0
M
N
P
A
A
A
A
A
A
TDO
TCK
A
C
A
TMS
TDI
R
Document #: 38-05503 Rev. *A
Page 3 of 21
CY7C1392AV18
CY7C1393AV18
CY7C1394AV18
PRELIMINARY
Pin Configurations (continued)
CY7C1394AV18 (512K × 36) – 11 × 15 FBGA
1
2
3
4
5
6
7
8
9
10
11
CQ
Q8
D8
D7
CQ
VSS/288M NC/72M
R/W
BWS2
K
BWS1
BWS0
A
LD
NC/36M VSS/144M
A
B
C
D
E
F
G
H
J
K
L
Q27
D27
D28
Q29
Q30
D30
DOFF
D31
Q32
Q33
Q18
Q28
D20
D29
Q21
D22
VREF
Q31
D32
Q24
D18
D19
Q19
Q20
D21
Q22
VDDQ
D23
Q23
D24
A
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
BWS3
A
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
K
A
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
D17
D16
Q16
Q15
D14
Q13
VDDQ
D12
Q12
D11
Q17
Q7
D15
D6
Q14
D13
VREF
Q4
VSS
VSS
Q6
VDD
VDD
VDD
VDD
VDD
VSS
Q5
D5
ZQ
D4
Q3
Q2
D3
Q11
D33
D34
Q35
Q34
D26
D35
D25
Q25
Q26
VSS
VSS
VSS
A
A
VSS
A
C
VSS
A
A
VSS
VSS
D10
Q10
Q9
Q1
D9
D0
D2
D1
Q0
M
N
P
A
A
A
A
A
A
TDO
TCK
A
C
A
TMS
TDI
R
Pin Definitions
Pin Name
D[x:0]
I/O
Input-
Synchronous operations.
Pin Description
Data Input signals, sampled on the rising edge of K and K clocks during valid Write
CY7C1392AV18 − D[7:0]
CY7C1393AV18 − D[17:0]
CY7C1394AV18 − D[35:0]
LD
Input-
Synchronous Load: This input is brought LOW when a bus cycle sequence is to be defined.
Synchronous This definition includes address and Read/Write direction. All transactions operate on a burst of
2 data (one period of bus activity).
BWS[3:0]
Input-
Byte Write Select 0, 1, 2, and 3 − active LOW. Sampled on the rising edge of the K and K
Synchronous clocks during Write operations. Used to select which byte is written into the device during the
current portion of the Write operations. Bytes not written remain unaltered.
CY7C1392AV18 − BWS0 controls D[3:0] and BWS1 controls D[7:4]
.
CY7C1393AV18 − BWS0 controls D[8:0] and BWS1 controls D[17:9].
CY7C1394AV18 − BWS0 controls D[8:0], BWS1 controls D[17:9], BWS2 controls D[26:18] and
BWS3 controls D[35:27]
All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write
Select will cause the corresponding byte of data to be ignored and not written into the device.
A
Input-
Address Inputs. Sampled on the rising edge of the K clock during active Read and Write
Synchronous operations. These address inputs are multiplexed for both Read and Write operations. Internally,
the device is organized as 2M x 8 (2 arrays each of 1M x 8) for CY7C1392AV18, 1M x 18 (two
arrays each of 512K x 18) for CY7C1393AV18 and 512K x 36 (2 arrays each of 256K x 36) for
CY7C1394AV18. Therefore only 20 address inputs are needed to access the entire memory
array of CY7C1392AV18, 19 address inputs for CY7C1393AV18, and 18 address inputs for
CY7C1394AV18. These inputs are ignored when the appropriate port is deselected.
Q[x:0]
Output-
Data Output signals. These pins drive out the requested data during a Read operation. Valid
Synchronous data is driven out on the rising edge of both the C and C clocks during Read operations or K
and K when in single clock mode. When Read access is deselected, Q[x:0] are automatically
three-stated.
CY7C1392AV18 − Q[7:0]
CY7C1393AV18 − Q[17:0]
CY7C1394AV18 − Q[35:0]
Document #: 38-05503 Rev. *A
Page 4 of 21
CY7C1392AV18
CY7C1393AV18
CY7C1394AV18
PRELIMINARY
Pin Definitions (continued)
Pin Name
R/W
I/O
Input-
Pin Description
Synchronous Read/Write Input: When LD is LOW, this input designates the access type (Read
Synchronous when R/W is HIGH, Write when R/W is LOW) for loaded address. R/W must meet the set-up
and hold times around edge of K.
C
C
K
Input-
Clock
Positive Output Clock Input. C is used in conjunction with C to clock out the Read data from
the device. C and C can be used together to deskew the flight times of various devices on the
board back to the controller. See application example for further details.
Negative Output Clock Input. C is used in conjunction with C to clock out the Read data from
the device. C and C can be used together to deskew the flight times of various devices on the
board back to the controller. See application example for further details.
Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the
device and to drive out data through Q[x:0] when in single clock mode. All accesses are initiated
on the rising edge of K.
Input-
Clock
Input-
Clock
K
Input-
Clock
Negative Input Clock Input. K is used to capture synchronous inputs being presented to the
device and to drive out data through Q[x:0] when in single clock mode.
CQ
Echo Clock
Echo Clock
Input
CQ is referenced with respect to C. This is a free-running clock and is synchronized to the
output clock (C) of the DDR-II. In the single clock mode, CQ is generated with respect to K. The
timings for the echo clocks are shown in the AC timing table.
CQ is referenced with respect to C. This is a free-running clock and is synchronized to the
output clock (C) of the DDR-II. In the single clock mode, CQ is generated with respect to K. The
timings for the echo clocks are shown in the AC timing table.
Output Impedance Matching Input. This input is used to tune the device outputs to the system
data bus impedance. CQ, CQ, and Q[x:0] output impedance are set to 0.2 x RQ, where RQ is a
resistor connected between ZQ and ground. Alternately, this pin can be connected directly to
VDD, which enables the minimum impedance mode. This pin cannot be connected directly to
GND or left unconnected.
CQ
ZQ
DOFF
Input
DLL Turn Off, active LOW. Connecting this pin to ground will turn off the DLL inside the device.
The timings in the DLL turned off operation will be different from those listed in this data sheet.
More details on this operation can be found in the application note DLL Operation in the QDR™-II.
TDO
TCK
TDI
TMS
NC/36M
VSS/36M
NC/72M
VSS/72M
VSS/144M
VSS/288M
VREF
Output
Input
Input
Input
N/A
Input
N/A
Input
Input
Input
TDO for JTAG.
TCK pin for JTAG.
TDI pin for JTAG.
TMS pin for JTAG.
Address expansion for 36M. This is not connected to the die and so can be tied to any voltage level.
Address expansion for 36M. This should be tied LOW.
Address expansion for 72M. This is not connected to the die and so can be tied to any voltage level.
Address expansion for 72M. This must be tied LOW.
Address expansion for 144M. This must be tied LOW.
Address expansion for 288M. This must be tied LOW.
Input-
Reference Voltage Input. Static input used to set the reference level for HSTL inputs and
Reference
Outputs as well as AC measurement points.
VDD
VSS
VDDQ
NC
Power Supply Power supply inputs to the core of the device.
Ground Ground for the device.
Power Supply Power supply inputs for the outputs of the device.
N/A Not connected to the die. Can be tied to any voltage level.
Document #: 38-05503 Rev. *A
Page 5 of 21
CY7C1392AV18
CY7C1393AV18
CY7C1394AV18
PRELIMINARY
mined by BWS0 and BWS1, which are sampled with each set
of 18-bit data words. Asserting the appropriate Byte Write
Select input during the data portion of a write will allow the data
being presented to be latched and written into the device.
Deasserting the Byte Write Select input during the data portion
of a write will allow the data stored in the device for that byte
to remain unaltered. This feature can be used to simplify
Read/Modify/Write operations to a Byte Write operation.
Introduction
Functional Overview
The CY7C1392AV18/CY7C1393AV18/CY7C1394AV18 are
synchronous pipelined Burst SRAMs equipped with a DDR-II
Separate I/O interface.
Accesses are initiated on the rising edge of the positive input
clock (K). All synchronous input timing is referenced from the
rising edge of the input clocks (K and K) and all output timing
is referenced to the rising edge of the output clocks, C/C (or
K/K when in single clock mode).
All synchronous data inputs (D[x:0]) pass through input
registers controlled by the rising edge of input clocks (K and
K). All synchronous data outputs (Q[x:0]) pass through output
registers controlled by the rising edge of the output clocks, C/C
(or K/K when in single clock mode). All synchronous control
(R/W, LD, BWS[x:0]) inputs pass through input registers
controlled by the rising edge of the input clock (K).
CY7C1393AV18 is described in the following sections. The
same basic descriptions apply to CY7C1392AV18 and
CY7C1394AV18.
Single Clock Mode
The CY7C1393AV18 can be used with a single clock that
controls both the input and output registers. In this mode the
device will recognize only a single pair of input clocks (K and
K) that control both the input and output registers. This
operation is identical to the operation if the device had zero
skew between the K/K and C/C clocks. All timing parameters
remain the same in this mode. To use this mode of operation,
the user must tie C and C HIGH at power-on. This function is
a strap option and not alterable during device operation. The
echo clocks are synchronized to input clocks K/K in this mode.
DDR Operation
The CY7C1393AV18 enables high-performance operation
through high clock frequencies (achieved through pipelining)
and double DDR mode of operation. If a Read occurs after a
Write cycle, address and data for the Write are stored in
registers. The write information must be stored because the
SRAM can not perform the last word Write to the array without
conflicting with the Read. The data stays in this register until
the next Write cycle occurs. On the first Write cycle after the
Read(s), the stored data from the earlier Write will be written
into the SRAM array. This is called a Posted Write.
Read Operations
The CY7C1393AV18 is organized internally as two arrays of
512K x 18. Accesses are completed in a burst of two
sequential 18-bit data words. Read operations are initiated by
asserting R/W HIGH and LD LOW at the rising edge of the
positive input clock (K). The address presented to the Address
inputs is stored in the Read address register. Following the
next K clock rise the corresponding lowest-order 18-bit word
of data is driven onto the Q[17:0] using C as the output timing
reference. On the subsequent rising edge of C the next 18-bit
data word is driven onto the Q[17:0]. The requested data will be
valid 0.45 ns from the rising edge of the output clock (C or C,
or K or K when in single clock mode, for 250-MHz and
200-MHz devices). Read accesses can be initiated on every
K clock rise. Doing so will pipeline the data flow such that data
is transferred out of the device on every rising edge of the
output clocks, C/C (or K/K when in single clock mode).
Depth Expansion
Depth expansion requires replicating the LD control signal for
each bank. All other control signals can be common between
banks as appropriate.
Programmable Impedance
An external resistor, RQ, must be connected between the ZQ
pin on the SRAM and VSS to allow the SRAM to adjust its
output driver impedance. The value of RQ must be 5X the
value of the intended line impedance driven by the SRAM. The
allowable range of RQ to guarantee impedance matching with
a tolerance of ±15% is between 175Ω and 350Ω, with
When read access is deselected, the CY7C1393AV18 will first
complete the pending read transactions. Synchronous internal
circuitry will automatically three-state the outputs following the
next rising edge of the positive output clock (C).
V
DDQ = 1.5V. The output impedance is adjusted every 1024
Write Operations
cycles upon power-up to account for drifts in supply voltage
and temperature.
Write operations are initiated by asserting R/W LOW and LD
LOW at the rising edge of the positive input clock (K). On the
following K clock rise the data presented to D[17:0] is latched
and stored into the lower 18-bit Write Data register provided
BWS[1:0] are both asserted active. On the subsequent rising
edge of the negative input clock (K), the information presented
to D[17:0] is also stored into the Write Data register provided
BWS[1:0] are both asserted active. Write accesses can be
initiated on every rising edge of input clock (K). Doing so
pipelines the data flow so that 18 bits of data are written into
the device on every rising edge of both input clocks (K and K).
When write access is deselected, the device will ignore all data
inputs after the pending Write operations have been
completed.
Byte Write Operations
Echo Clocks
Echo clocks are provided on the DDR-II to simplify data
capture on high-speed systems. Two echo clocks are
generated by the DDR-II. CQ is referenced with respect to C
and CQ is referenced with respect to C. These are
free-running clocks and are synchronized to the output clock
of the Separate I/O DDR. In the single clock mode, CQ is
generated with respect to K and CQ is generated with respect
to K. The timings for the echo clocks are shown in the AC
Timing table.
DLL
These chips utilize a Delay Lock Loop (DLL) that is designed
to function between 80 MHz and the specified maximum clock
frequency. The DLL may be disabled by applying ground to the
DOFF pin. The DLL can also be reset by slowing the cycle time
of input clocks K and K to greater than 30 ns.
Byte Write operations are supported by the CY7C1393AV18.
A Write operation is initiated as described in the Write
Operation section above. The bytes that are written are deter-
Document #: 38-05503 Rev. *A
Page 6 of 21
CY7C1392AV18
CY7C1393AV18
CY7C1394AV18
PRELIMINARY
Application Example[1]
SRAM 1
B
SRAM 4
ZQ
ZQ
Q
Q
R = 250 Ohms
R = 250 Ohms
B
Vt
R
CQ
CQ
CQ#
C C# K
K#
W
W
S
#
D
A
D
CQ#
S
LD R/W
LD R/W
#
#
A
#
#
#
C
C#
K
K#
DATA IN
DATA OUT
Address
LD#
Vt
Vt
R
R/W#
BWS#
BUS
SRAM 1 Input CQ
SRAM 1 Input CQ#
SRAM 4 Input CQ
SRAM 4 Input CQ#
MASTER
(CPU
or
ASIC)
Source K
Source K#
Delayed K
Delayed K#
R
R = 50 Ohms
Vt = VREF
Truth Table[2, 3, 4, 5, 6, 7]
Operation
K
LD
R/W
DQ
DQ
Write Cycle:
L-H
L
L
D(A + 0)at K(t + 1) ↑ D(A + 1) at K(t + 1) ↑
Load address; wait one cycle; input write data on
consecutive K and K rising edges.
Read Cycle:
L-H
L
H
Q(A + 0) at C(t + 1)↑ Q(A + 1) at C(t + 2) ↑
Load address; wait one and a half cycle; read data
on consecutive C and C rising edges.
NOP: No Operation
Standby: Clock Stopped
L-H
Stopped
H
X
X
X
High-Z
Previous State
High-Z
Previous State
Write Cycle Descriptions (CY7C1392AV18 and CY7C1393AV18) [2, 8]
BWS0 BWS1
K
K
Comments
L
L
L
L
L-H
-
During the Data portion of a Write sequence:
CY7C1392AV18 − both nibbles (D[7:0]) are written into the device,
CY7C1393AV18 − both bytes (D[17:0]) are written into the device.
L
-
L-H
-
L-H During the Data portion of a Write sequence:
CY7C1392AV18 − both nibbles (D[7:0]) are written into the device,
CY7C1393AV18 − both bytes (D[17:0]) are written into the device.
H
H
-
During the Data portion of a Write sequence:
CY7C1392AV18 − only the lower nibble (D[3:0]) is written into the device. D[7:4] will remain unaltered,
CY7C1393AV18 − only the lower byte (D[8:0]) is written into the device. D[17:9] will remain unaltered.
L
L-H During the Data portion of a Write sequence:
CY7C1392AV18 − only the lower nibble (D[3:0]) is written into the device. D[7:4] will remain unaltered,
CY7C1393AV18 − only the lower byte (D[8:0]) is written into the device. D[17:9] will remain unaltered.
Notes:
1. The above application shows four DDR-II SIO being used.
2. X = “Don't Care,” H = Logic HIGH, L = Logic LOW, ↑ represents rising edge.
3. Device will power-up deselected and the outputs in a three-state condition.
4. “A” represents address location latched by the devices when transaction was initiated. A + 0, A + 1 represents the internal address sequence in the burst.
5. “t” represents the cycle at which a Read/Write operation is started. t+1, t + 2 and t +3 are the first, second and third clock cycles succeeding the “t” clock cycle.
6. Data inputs are registered at K and K rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode.
7. It is recommended that K = K and C = C = HIGH when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line
charging symmetrically.
8. Assumes a Write cycle was initiated per the Write Cycle Description Truth Table. BWS , BWS in the case of CY7C1392AV18 and CY7C1393AV18 and also
0
1
BWS , BWS in the case of CY7C1394AV18 can be altered on different portions of a write cycle, as long as the set-up and hold requirements are achieved.
2
3
Document #: 38-05503 Rev. *A
Page 7 of 21
CY7C1392AV18
CY7C1393AV18
CY7C1394AV18
PRELIMINARY
Write Cycle Descriptions (CY7C1392AV18 and CY7C1393AV18) (continued)[2, 8]
BWS0 BWS1
K
K
Comments
H
L
L-H
–
During the Data portion of a Write sequence:
CY7C1392AV18 − only the upper nibble (D[7:4]) is written into the device. D[3:0] will remain unaltered,
CY7C1393AV18 − only the upper byte (D[17:9]) is written into the device. D[8:0] will remain unaltered.
H
L
–
L-H During the Data portion of a Write sequence:
CY7C1392AV18 − only the upper nibble (D[7:4]) is written into the device. D[3:0] will remain unaltered,
CY7C1393AV18 − only the upper byte (D[17:9]) is written into the device. D[8:0] will remain unaltered.
H
H
H
H
L-H
–
–
No data is written into the devices during this portion of a Write operation.
L-H No data is written into the devices during this portion of a Write operation.
Write Cycle Descriptions (CY7C1394AV18)[2, 8]
BWS0 BWS1 BWS2 BWS3
K
K
Comments
L
L
L
L
L-H
–
During the Data portion of a Write sequence, all four bytes (D[35:0]) are written into
the device.
L
L
L
L
–
L-H
–
L-H During the Data portion of a Write sequence, all four bytes (D[35:0]) are written into
the device.
L
H
H
L
H
H
H
H
L
H
H
H
H
H
H
L
-
During the Data portion of a Write sequence, only the lower byte (D[8:0]) is written
into the device. D[35:9] will remain unaltered.
L
L-H During the Data portion of a Write sequence, only the lower byte (D[8:0]) is written
into the device. D[35:9] will remain unaltered.
H
H
H
H
H
H
L-H
–
–
During the Data portion of a Write sequence, only the byte (D[17:9]) is written into
the device. D[8:0] and D[35:18] will remain unaltered.
L
L-H During the Data portion of a Write sequence, only the byte (D[17:9]) is written into
the device. D[8:0] and D[35:18] will remain unaltered.
H
H
H
H
L-H
–
–
During the Data portion of a Write sequence, only the byte (D[26:18]) is written into
the device. D[17:0] and D[35:27] will remain unaltered.
L
L-H During the Data portion of a Write sequence, only the byte (D[26:18]) is written into
the device. D[17:0] and D[35:27] will remain unaltered.
During the Data portion of a Write sequence, only the byte (D[35:27]) is written into
the device. D[26:0] will remain unaltered.
L-H During the Data portion of a Write sequence, only the byte (D[35:27]) is written into
the device. D[26:0] will remain unaltered.
H
H
L-H
–
L
H
H
H
H
H
H
H
H
L-H
–
–
No data is written into the device during this portion of a Write operation.
L-H No data is written into the device during this portion of a Write operation.
Document #: 38-05503 Rev. *A
Page 8 of 21
CY7C1392AV18
CY7C1393AV18
CY7C1394AV18
PRELIMINARY
Current into Outputs (LOW)......................................... 20 mA
Static Discharge Voltage (MIL-STD-883, M 3015)... > 2001V
Latch-up Current.................................................... > 200 mA
Maximum Ratings
(Above which the useful life may be impaired.)
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with Power Applied..–55°C to +125°C
Supply Voltage on VDD Relative to GND........ –0.5V to +2.9V
Operating Range
Ambient
[10]
[10]
Range
Com’l
Temperature
VDD
VDDQ
1.4V to VDD
DC Voltage Applied to Outputs
0°C to +70°C
1.8 ± 0.1V
in High-Z State .................................... –0.5V to VDDQ + 0.5V
DC Input Voltage[9].............................. –0.5V to VDDQ + 0.5V
Electrical Characteristics Over the Operating Range[11]
DC Electrical Characteristics
Parameter
VDD
Description
Power Supply Voltage
I/O Supply Voltage
Output HIGH Voltage
Test Conditions
Min.
1.7
1.4
Typ.
1.8
1.5
Max.
1.9
VDD
Unit
V
V
VDDQ
VOH
Note 12
Note 13
VDDQ/2 –
VDDQ/2 +
V
0.12
0.12
VOL
Output LOW Voltage
VDDQ/2 –
0.12
VDDQ/2 +
0.12
V
VOH(LOW)
VOL(LOW)
VIH
VIL
VIN
IX
IOZ
VREF
IDD
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage[9]
Input LOW Voltage[9, 14]
Clock Input Voltage
IOH = −0.1 mA, Nominal Impedance VDDQ – 0.2
VDDQ
0.2
VDDQ + 0.3
VREF – 0.1
VDDQ + 0.3
5
V
V
V
V
V
µA
µA
V
mA
mA
mA
mA
mA
mA
IOL = 0.1 mA, Nominal Impedance
VSS
VREF + 0.1
–0.3
–0.3
Input Load Current
GND ≤ VI ≤ VDDQ
–5
Output Leakage Current
GND ≤ VI ≤ VDDQ, Output Disabled
–5
5
Input Reference Voltage[15] Typical Value = 0.75V
0.68
0.75
0.95
700
750
800
450
470
490
VDD Operating Supply
VDD =Max.,IOUT=0mA, 167 MHz
f = fMAX = 1/tCYC
200 MHz
250 MHz
167 MHz
200 MHz
250 MHz
ISB1
Automatic
Power-down
Current
Max. VDD, Both Ports
Deselected, VIN ≥ VIH or
V
IN ≤ VIL,f = fMAX =
1/tCYC, Inputs Static
AC Input Requirements
Parameter
Description
Test Conditions
Min.
VREF + 0.2
–
Typ.
–
–
Max.
–
VREF – 0.2
Unit
V
V
VIH
Input High (Logic 1) Voltage
VIL
Input Low (Logic 0) Voltage
Thermal Resistance[16]
Parameter
Description
Test Conditions
165 FBGA Package Unit
ΘJA
ΘJC
Thermal Resistance (Junction to Ambient) Test conditions follow standard test
16.7
2.5
°C/W
°C/W
methods and procedures for measuring
Thermal Resistance (Junction to Case)
thermal impedance, per EIA / JESD51.
Notes:
9. Overshoot: V (AC) < V +0.85V (Pulse width less than t
/2); Undershoot V (AC) > –1.5V (Pulse width less than t /2).
TCYC
IH
DD
TCYC
IL
10. Power-up: Assumes a linear ramp from 0V to V (Min.) within 200 ms. During this time V < V and V
< V
.
DD
DD
IH
DD
DDQ
11. All voltage referenced to ground.
12. Outputs are impedance controlled. I = –(V
/2)/(RQ/5) for values of 175Ω < RQ < 350Ω.
DDQ
OH
OL
13. Outputs are impedance controlled. I =(V
/2)/(RQ/5) for values of 175Ω < RQ < 350Ω.
DDQ
14. This spec is for all inputs except C and C Clock. For C and C Clock, V (Max.) = V
– 0.2V.
IL
REF
15. V
(Min.) = 0.68V or 0.46V
, whichever is larger, V
(Max.) = 0.95V or 0.54V
, whichever is smaller.
REF
DDQ
REF
DDQ
16. Tested initially and after any design or process change that may affect these parameters.
Document #: 38-05503 Rev. *A
Page 9 of 21
CY7C1392AV18
CY7C1393AV18
CY7C1394AV18
PRELIMINARY
Capacitance[16]
Parameter
Description
Input Capacitance
Clock Input Capacitance
Output Capacitance
Test Conditions
Max.
Unit
pF
pF
CIN
TA = 25°C, f = 1 MHz,
5
6
7
V
DD = 1.8V
CCLK
CO
V
DDQ = 1.5V
pF
AC Test Loads and Waveforms
V
REF = 0.75V
0.75V
VREF
OUTPUT
VREF
OUTPUT
Device
0.75V
R = 50Ω
[15]
ALL INPUT PULSES
Z = 50Ω
0
1.25V
Device
Under
Test
R = 50Ω
L
0.75V
0.25V
5 pF
Under
ZQ
VREF = 0.75V
Slew Rate = 2V / ns
ZQ
Test
RQ =
RQ =
250Ω
250Ω
INCLUDING
JIG AND
SCOPE
(a)
(b)
Switching Characteristics Over the Operating Range [17, 18]
250 MHz
200 MHz
167 MHz
Cypress Consortium
Parameter Parameter
Description
K Clock and C Clock Cycle Time
Input Clock (K/K and C/C) HIGH
Input Clock (K/K and C/C) LOW
Min. Max. Min. Max. Min. Max. Unit
4.0 6.3 5.0 7.9 6.0 8.4
tCYC
tKHKH
tKHKL
tKLKH
tKHKH
ns
ns
ns
ns
tKH
1.6
1.6
–
–
–
2.0
2.0
2.2
–
–
–
2.4
2.4
2.7
–
–
–
tKL
tKHKH
K Clock Rise to K Clock Rise and C to C Rise (rising 1.8
edge to rising edge)
tKHCH
tKHCH
K/K Clock Rise to C/C Clock Rise (rising edge to rising 0.0 1.8 0.0 2.3 0.0 2.8
edge)
ns
Set-up Times
tSA
tSC
tSCDDR
tSA
tSC
tSC
Address Set-up to K Clock Rise
Control Set-up to Clock (K, K) Rise (LD, R/W)
0.5
0.5
–
–
–
0.6
0.6
0.4
–
–
–
0.7
0.7
0.5
–
–
–
ns
ns
ns
Double Data Rate Control Set-up to Clock (K, K) Rise 0.35
(BWS0, BWS1, BWS2, BWS3)
tSD
tSD
D[X:0] Set-up to Clock (K and K) Rise
0.35
–
0.4
–
0.5
–
ns
Hold Times
tHA
tHC
tHA
tHC
tHC
Address Hold after Clock (K and K) Rise
Control Hold after Clock (K and K) Rise (LD, R/W)
0.5
0.5
–
–
–
0.6
0.6
0.4
–
–
–
0.7
0.7
0.5
–
–
–
ns
ns
ns
tHCDDR
Double Data Rate Control Hold after Clock (K and K) 0.35
Rise (BWS0, BWS1, BWS2, BWS3)
tHD
tHD
D[X:0] Hold after Clock (K and K) Rise
0.35
–
0.4
–
0.5
–
ns
Output Times
tCO
tCHQV
C/C Clock Rise (or K/K in single clock mode) to Data
Valid
–
0.45
–
–
0.45
–
–
0.50
–
ns
ns
tDOH
tCHQX
Data Output Hold after Output C/C Clock Rise
–0.45
–0.45
–0.50
(Active to Active)
Notes:
17. All devices can operate at clock frequencies as low as 119 MHz. When a part with a maximum frequency above 133 MHz is operating at a lower clock frequency,
it requires the input timings of the frequency range in which it is being operated and will output data with the output timings of that frequency range.
18. Unless otherwise noted, test conditions assume signal transition time of 2V/ns, timing reference levels of 0.75V, V
= 0.75V, RQ = 250Ω, V
= 1.5V, input
DDQ
REF
pulse levels of 0.25V to 1.25V, and output loading of the specified I /I and load capacitance shown in (a) of AC Test Loads.
OL OH
Document #: 38-05503 Rev. *A
Page 10 of 21
CY7C1392AV18
CY7C1393AV18
CY7C1394AV18
PRELIMINARY
Switching Characteristics Over the Operating Range (continued)[17, 18]
250 MHz
200 MHz
167 MHz
Cypress Consortium
Parameter Parameter
Description
C/C Clock Rise to Echo Clock Valid
Echo Clock Hold after C/C Clock Rise
Echo Clock High to Data Change
Echo Clock High to Data Change
Min. Max. Min. Max. Min. Max. Unit
tCCQO
tCQOH
tCQD
tCQDOH
tCHZ
tCHCQV
tCHCQX
tCQHQV
tCQHQX
tCHZ
–
–0.45
–
–0.30
–
0.45
–
0.30
–
–
–0.45
–
–0.35
–
0.45
–
0.35
–
–
–0.50
–
–0.40
–
0.50
–
0.40
–
ns
ns
ns
ns
ns
Clock (C and C) Rise to High-Z (
0.45
0.45
0.50
Active to High-Z)[19, 20]
tCLZ
tCLZ
Clock (C and C) Rise to Low-Z[19, 20]
–0.45
–
–0.45
–
–0.50
–
ns
DLL Timing
tKC Var
tKC lock
tKC Var
tKC lock
tKC Reset
Clock Phase Jitter
DLL Lock Time (K, C)
K Static to DLL Reset
–
1024
30
0.20
–
–
1024
30
0.20
–
–
1024
30
0.20
–
ns
Cycles
ns
tKC Reset
Notes:
19. t
, t
, are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ± 100 mV from steady-state voltage.
CHZ CLZ
20. At any given voltage and temperature t
is less than t
and t
less than t
.
CO
CHZ
CLZ
CHZ
Document #: 38-05503 Rev. *A
Page 11 of 21
CY7C1392AV18
CY7C1393AV18
CY7C1394AV18
PRELIMINARY
Switching Waveforms[21, 22, 23]
N
O
P
R
E
AD
R
E
AD
W
R
r
I
T
E
W
R
r
I
T
E
R
E
AD
N
7
O
P
(
bu
r
s
t of
2
)
(
bu t of
r
s
2)
(
bu
s
t of
2)
(
bu
s
t of
2)
(
bu
rs
t of 2)
1
8
2
3
4
5
6
K
t
t
t
t
KHKH
KH
KL
CYC
K
#
#
L
D
t
t
SC
HC
R
/W
#
A
A0
A1
A2
A3
A4
t
t
HD
HD
SD
D30
t
t
HA
SA
t
t
SD
D
D20
D21
D31
Qx2
Q
Q00
Q01
Q10
Q11
Q40
Q41
t
t
KHCH
t
t
CO
CO
CQD
t
CLZ
DOH
t
t
DOH
t
t
CLZ
KHCH
C
t
t
KHKH
t
t
CYC
KH
KL
C
#
t
CCQO
t
CQOH
C
Q
t
CCQO
t
CQOH
CQ#
DON’T CARE
UNDEFINED
Notes:
21. Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, i.e., A0+1.
22. Output are disabled (High-Z) one clock cycle after a NOP.
23. In this example, if address A2 = A1,then data Q20 = D10 and Q21 = D11. Write data is forwarded immediately as read results. This note applies to the whole diagram
Document #: 38-05503 Rev. *A
Page 12 of 21
CY7C1392AV18
CY7C1393AV18
CY7C1394AV18
PRELIMINARY
TDI and TDO pins as shown in TAP Controller Block Diagram.
Upon power-up, the instruction register is loaded with the
IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as
described in the previous section.
When the TAP controller is in the Capture IR state, the two
least significant bits are loaded with a binary “01” pattern to
allow for fault isolation of the board level serial test path.
IEEE 1149.1 Serial Boundary Scan (JTAG)
These SRAMs incorporate a serial boundary scan test access
port (TAP) in the FBGA package. This part is fully compliant
with IEEE Standard #1149.1-1900. The TAP operates using
JEDEC standard 1.8V I/O logic levels.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(VSS) to prevent clocking of the device. TDI and TMS are inter-
nally pulled up and may be unconnected. They may alternately
be connected to VDD through a pull-up resistor. TDO should
be left unconnected. Upon power-up, the device will come up
in a reset state which will not interfere with the operation of the
device.
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between TDI
and TDO pins. This allows data to be shifted through the
SRAM with minimal delay. The bypass register is set LOW
(VSS) when the BYPASS instruction is executed.
Test Access Port—Test Clock
The test clock is used only with the TAP controller. All inputs
are captured on the rising edge of TCK. All outputs are driven
from the falling edge of TCK.
Boundary Scan Register
The boundary scan register is connected to all of the input and
output pins on the SRAM. Several no connect (NC) pins are
also included in the scan register to reserve pins for higher
density devices.
Test Mode Select
The boundary scan register is loaded with the contents of the
RAM Input and Output ring when the TAP controller is in the
Capture-DR state and is then placed between the TDI and
TDO pins when the controller is moved to the Shift-DR state.
The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instruc-
tions can be used to capture the contents of the Input and
Output ring.
The Boundary Scan Order tables show the order in which the
bits are connected. Each bit corresponds to one of the bumps
on the SRAM package. The MSB of the register is connected
to TDI, and the LSB is connected to TDO.
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. It is allowable to
leave this pin unconnected if the TAP is not used. The pin is
pulled up internally, resulting in a logic HIGH level.
Test Data-In (TDI)
The TDI pin is used to serially input information into the
registers and can be connected to the input of any of the
registers. The register between TDI and TDO is chosen by the
instruction that is loaded into the TAP instruction register. For
information on loading the instruction register, see the TAP
Controller State Diagram. TDI is internally pulled up and can
be unconnected if the TAP is unused in an application. TDI is
connected to the most significant bit (MSB) on any register.
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired
into the SRAM and can be shifted out when the TAP controller
is in the Shift-DR state. The ID register has a vendor code and
other information described in the Identification Register
Definitions table.
Test Data-Out (TDO)
The TDO output pin is used to serially clock data-out from the
registers. The output is active depending upon the current
state of the TAP state machine (see Instruction codes). The
output changes on the falling edge of TCK. TDO is connected
to the least significant bit (LSB) of any register.
TAP Instruction Set
Performing a TAP Reset
Eight different instructions are possible with the three-bit
instruction register. All combinations are listed in the
Instruction Code table. Three of these instructions are listed
as RESERVED and should not be used. The other five instruc-
tions are described in detail below.
Instructions are loaded into the TAP controller during the
Shift-IR state when the instruction register is placed between
TDI and TDO. During this state, instructions are shifted
through the instruction register through the TDI and TDO pins.
To execute the instruction once it is shifted in, the TAP
controller needs to be moved into the Update-IR state.
A Reset is performed by forcing TMS HIGH (VSS) for five rising
edges of TCK. This RESET does not affect the operation of
the SRAM and may be performed while the SRAM is
operating. At power-up, the TAP is reset internally to ensure
that TDO comes up in a high-Z state.
TAP Registers
Registers are connected between the TDI and TDO pins and
allow data to be scanned into and out of the SRAM test
circuitry. Only one register can be selected at a time through
the instruction registers. Data is serially loaded into the TDI pin
on the rising edge of TCK. Data is output on the TDO pin on
the falling edge of TCK.
IDCODE
The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the instruction register. It also places the
instruction register between the TDI and TDO pins and allows
the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state. The IDCODE instruction
Instruction Register
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the
Document #: 38-05503 Rev. *A
Page 13 of 21
CY7C1392AV18
CY7C1393AV18
CY7C1394AV18
PRELIMINARY
is loaded into the instruction register upon power-up or
whenever the TAP controller is given a test logic reset state.
The shifting of data for the SAMPLE and PRELOAD phases
can occur concurrently when required—that is, while data
captured is shifted out, the preloaded data can be shifted in.
SAMPLE Z
BYPASS
The SAMPLE Z instruction causes the boundary scan register
to be connected between the TDI and TDO pins when the TAP
controller is in a Shift-DR state. The SAMPLE Z command puts
the output bus into a High-Z state until the next command is
given during the “Update IR” state.
When the BYPASS instruction is loaded in the instruction
register and the TAP is placed in a Shift-DR state, the bypass
register is placed between the TDI and TDO pins. The
advantage of the BYPASS instruction is that it shortens the
boundary scan path when multiple devices are connected
together on a board.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When
the SAMPLE/PRELOAD instructions are loaded into the in-
struction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and output pins is cap-
tured in the boundary scan register.
The user must be aware that the TAP controller clock can only
operate at a frequency up to 10 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because
there is a large difference in the clock frequencies, it is possi-
ble that during the Capture-DR state, an input or output will
undergo a transition. The TAP may then try to capture a signal
while in transition (metastable state). This will not harm the
device, but there is no guarantee as to the value that will be
captured. Repeatable results may not be possible.
To guarantee that the boundary scan register will capture the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller's capture set-up plus
hold times (tCS and tCH). The SRAM clock input might not be
captured correctly if there is no way in a design to stop (or
slow) the clock during a SAMPLE/PRELOAD instruction. If this
is an issue, it is still possible to capture all other signals and
simply ignore the value of the CK and CK captured in the
boundary scan register.
EXTEST
The EXTEST instruction enables the preloaded data to be
driven out through the system output pins. This instruction also
selects the boundary scan register to be connected for serial
access between the TDI and TDO in the shift-DR controller
state.
EXTEST Output Bus Three-State
IEEE Standard 1149.1 mandates that the TAP controller be
able to put the output bus into a three-state mode.
The boundary scan register has a special bit located at bit #47.
When this scan cell, called the “extest output bus three-state”,
is latched into the preload register during the “Update-DR”
state in the TAP controller, it will directly control the state of the
output (Q-bus) pins, when the EXTEST is entered as the
current instruction. When HIGH, it will enable the output
buffers to drive the output bus. When LOW, this bit will place
the output bus into a High-Z condition.
This bit can be set by entering the SAMPLE/PRELOAD or
EXTEST command, and then shifting the desired bit into that
cell, during the “Shift-DR” state. During “Update-DR”, the value
loaded into that shift-register cell will latch into the preload
register. When the EXTEST instruction is entered, this bit will
directly control the output Q-bus pins. Note that this bit is
pre-set HIGH to enable the output when the device is
powered-up, and also when the TAP controller is in the
“Test-Logic-Reset” state.
Once the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the bound-
ary scan register between the TDI and TDO pins.
PRELOAD allows an initial data pattern to be placed at the
latched parallel outputs of the boundary scan register cells pri-
or to the selection of another boundary scan test operation.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
Document #: 38-05503 Rev. *A
Page 14 of 21
CY7C1392AV18
CY7C1393AV18
CY7C1394AV18
PRELIMINARY
TAP Controller State Diagram[24]
TEST-LOGIC
RESET
1
0
1
1
1
TEST-LOGIC/
IDLE
SELECT
SELECT
0
DR-SCAN
IR-SCAN
0
0
1
1
CAPTURE-DR
CAPTURE-IR
0
0
SHIFT-DR
0
SHIFT-IR
0
1
1
EXIT1-DR
0
1
EXIT1-IR
0
1
0
0
PAUSE-DR
1
PAUSE-IR
1
0
0
EXIT2-DR
1
EXIT2-IR
1
UPDATE-DR
UPDATE-IR
1
1
0
0
Note:
24. The 0/1 next to each state represents the value at TMS at the rising edge of TCK.
Document #: 38-05503 Rev. *A
Page 15 of 21
CY7C1392AV18
CY7C1393AV18
CY7C1394AV18
PRELIMINARY
TAP Controller Block Diagram
0
Bypass Register
Selection
Circuitry
Selection
Circuitry
2
1
1
0
TDO
TDI
Instruction Register
29
31 30
.
.
2
0
0
Identification Register
.
106 .
.
.
2
1
Boundary Scan Register
TCK
TMS
TAP Controller
TAP Electrical Characteristics Over the Operating Range[11, 9, 25]
Parameter
VOH1
Description
Output HIGH Voltage
Test Conditions
IOH = −2.0 mA
Min.
1.4
Max.
Unit
V
VOH2
VOL1
VOL2
VIH
VIL
IX
Output HIGH Voltage
Output LOW Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input and OutputLoad Current
IOH = −100 µA
IOL = 2.0 mA
IOL = 100 µA
1.6
V
V
V
V
V
µA
0.4
0.2
VDD + 0.3
0.35VDD
5
0.65VDD
–0.3
GND ≤ VI ≤ VDD
–5
TAP AC Switching Characteristics Over the Operating Range [26, 27]
Parameter
tTCYC
tTF
tTH
Description
Min.
100
Max.
Unit
ns
MHz
ns
TCK Clock Cycle Time
TCK Clock Frequency
TCK Clock HIGH
10
40
40
tTL
TCK Clock LOW
ns
Set-up Times
tTMSS
tTDIS
TMS Set-up to TCK Clock Rise
TDI Set-up to TCK Clock Rise
Capture Set-up to TCK Rise
10
10
10
ns
ns
ns
tCS
Notes:
25. These characteristics pertain to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in the Electrical Characteristics Table.
26. t and t refer to the set-up and hold time requirements of latching data from the boundary scan register.
CS
CH
27. Test conditions are specified using the load in TAP AC test conditions. t /t = 1 ns.
R
F
Document #: 38-05503 Rev. *A
Page 16 of 21
CY7C1392AV18
CY7C1393AV18
CY7C1394AV18
PRELIMINARY
TAP AC Switching Characteristics Over the Operating Range (continued)[26, 27]
Parameter
Hold Times
tTMSH
tTDIH
tCH
Description
Min.
Max.
Unit
TMS Hold after TCK Clock Rise
TDI Hold after Clock Rise
Capture Hold after Clock Rise
10
10
10
ns
ns
ns
Output Times
tTDOV
tTDOX
TCK Clock LOW to TDO Valid
TCK Clock LOW to TDO Invalid
20
ns
ns
0
TAP Timing and Test Conditions[27]
0.9V
50Ω
ALL INPUT PULSES
0.9V
TDO
1.8V
Z = 50Ω
0
C = 20 pF
L
0V
(a)
GND
tTL
tTH
Test Clock
TCK
tTCYC
tTMSS
tTMSH
Test Mode Select
TMS
tTDIS
tTDIH
Test Data-In
TDI
Test Data-Out
TDO
tTDOV
tTDOX
Document #: 38-05503 Rev. *A
Page 17 of 21
CY7C1392AV18
CY7C1393AV18
CY7C1394AV18
PRELIMINARY
Identification Register Definitions
Value
CY7C1393AV18
000
Instruction Field
Revision Number (31:29)
CY7C1392AV18
CY7C1394AV18
Description
Version number.
000
000
Cypress Device ID (28:12) 11010100010000101 11010100010010101 11010100010100101 Defines the type of SRAM.
Cypress JEDEC ID (11:1)
00000110100
00000110100
00000110100
Allows unique identification of
SRAM vendor.
ID Register Presence (0)
1
1
1
Indicate the presence of an ID
register.
Scan Register Sizes
Register Name
Bit Size
Instruction
3
Bypass
1
ID
32
107
Boundary Scan
Instruction Codes
Instruction
Code
Description
EXTEST
000
Captures the Input/Output ring contents.
IDCODE
001
Loads the ID register with the vendor ID code and places the register between TDI and TDO.
This operation does not affect SRAM operation.
SAMPLE Z
010
Captures the Input/Output contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM output drivers to a High-Z state.
RESERVED
SAMPLE/PRELOAD
011
100
Do Not Use: This instruction is reserved for future use.
Captures the Input/Output ring contents. Places the boundary scan register between TDI and
TDO. Does not affect the SRAM operation.
RESERVED
RESERVED
BYPASS
101
110
111
Do Not Use: This instruction is reserved for future use.
Do Not Use: This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does not affect SRAM operation.
Boundary Scan Order
Boundary Scan Order (continued)
Bit #
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Bump ID
6R
Bit #
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
Bump ID
9M
9N
6P
6N
7P
7N
7R
8R
8P
9R
11P
10P
10N
9P
10M
11N
11L
11M
9L
10L
11K
10K
9J
9K
10J
11J
11H
10G
9G
Document #: 38-05503 Rev. *A
Page 18 of 21
CY7C1392AV18
CY7C1393AV18
CY7C1394AV18
PRELIMINARY
Boundary Scan Order (continued)
Boundary Scan Order (continued)
Bit #
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
Bump ID
Bit #
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
Bump ID
2D
2E
1E
2F
11F
11G
9F
10F
11E
10E
10D
9E
3F
1G
1F
3G
2G
1J
2J
3K
3J
2K
1K
2L
10C
11D
9C
9D
11B
11C
9B
10B
11A
Internal
9A
8B
7C
6C
8A
7A
7B
6B
6A
5B
5A
4A
5C
4B
3A
1H
1A
2B
3B
1C
1B
3D
3C
1D
2C
3L
1M
1L
3N
3M
1N
2M
3P
2N
2P
1P
3R
4R
4P
5P
5N
5R
3E
Document #: 38-05503 Rev. *A
Page 19 of 21
CY7C1392AV18
CY7C1393AV18
CY7C1394AV18
PRELIMINARY
Ordering Information
Speed
Package
Operating
Range
(MHz)
Ordering Code
Name
Package Type
13 x 15 x 1.4 mm FBGA
250
CY7C1392AV18-250BZC
CY7C1393AV18-250BZC
CY7C1394AV18-250BZC
CY7C1392AV18-200BZC
CY7C1393AV18-200BZC
CY7C1394AV18-200BZC
CY7C1392AV18-167BZC
CY7C1393AV18-167BZC
CY7C1394AV18-167BZC
BB165D
Commercial
Commercial
Commercial
200
167
BB165D
BB165D
13 x 15 x 1.4 mm FBGA
13 x 15 x 1.4 mm FBGA
Package Diagram
165 FBGA 13 x 15 x 1.40 mm BB165D
51-85180-**
QDR SRAMs and Quad Data Rate SRAMs comprise a new family of products developed by Cypress, Hitachi, IDT, Micron,
NEC and Samsung technology. All product and company names mentioned in this document are the trademarks of their respective
holders.
Document #: 38-05503 Rev. *A
Page 20 of 21
© Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C1392AV18
CY7C1393AV18
CY7C1394AV18
PRELIMINARY
Document History Page
Document Title: CY7C1392AV18/CY7C1393AV18/CY7C1394AV18 18-Mb DDR™-II SIO SRAM with 2-Word Burst Archi-
tecture
Document Number: 38-05503
Orig. of
REV.
**
ECN No. Issue Date Change
Description of Change
208408
see ECN
DIM
New Data Sheet
*A
230396
see ECN
VBL
Upload datasheet to the internet
Document #: 38-05503 Rev. *A
Page 21 of 21
相关型号：
©2020 ICPDF网 联系我们和版权申明