CY7C1371DV25-133AC [CYPRESS]
ZBT SRAM, 512KX36, 6.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100;
| 型号： | CY7C1371DV25-133AC |
| 厂家： | 
CYPRESS |
| 描述： | ZBT SRAM, 512KX36, 6.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100 静态存储器 内存集成电路 |
| 文件： | 总31页 (文件大小：724K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C1371DV25
CY7C1373DV25
PRELIMINARY
18-Mbit (512K x 36/1M x 18) Flow-Through
SRAM with NoBL™ Architecture
Functional Description[1]
Features
• No Bus Latency (NoBL) architecture eliminates
The CY7C1371DV25/CY7C1373DV25 is a 2.5V, 512K x 36/
1M x 18 Synchronous Flow-through Burst SRAM designed
specifically to support unlimited true back-to-back Read/Write
operations without the insertion of wait states. The
CY7C1371DV25/CY7C1373DV25 is equipped with the
advanced No Bus Latency (NoBL) logic required to enable
consecutive Read/Write operations with data being trans-
ferred on every clock cycle. This feature dramatically improves
the throughput of data through the SRAM, especially in
systems that require frequent Write-Read transitions.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. The clock input is qualified by
the Clock Enable (CEN) signal, which when deasserted
suspends operation and extends the previous clock cycle.
Maximum access delay from the clock rise is 6.5 ns (133-MHz
device).
dead cycles between write and read cycles
• Can support up to 133-MHz bus operations with zero
wait states
— Data is transferred on every clock
• Pin compatible and functionally equivalent to ZBT™
devices
• Internally self-timed output buffer control to eliminate
the need to use OE
• Registered inputs for flow-through operation
• Byte Write capability
• Single 2.5V power supply
• 2.5V I/O power supply
• Fast clock-to-output times
— 6.5 ns (for 133-MHz device)
— 7.5 ns (for 117-MHz device)
— 8.5 ns (for 100-MHz device)
Write operations are controlled by the two or four Byte Write
Select (BWX) and a Write Enable (WE) input. All writes are
conducted with on-chip synchronous self-timed write circuitry.
Three synchronous Chip Enables (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output tri-state control. In order to avoid bus
contention, the output drivers are synchronously tri-stated
during the data portion of a write sequence.
• Clock Enable (CEN) pin to enable clock and suspend
operation
• Synchronous self-timed writes
• Asynchronous Output Enable
• OfferedinJEDEC-standard100TQFP,119-BallBGAand
165-Ball fBGA packages
• Three chip enables for simple depth expansion
• Automatic Power-down feature available using ZZ
mode or CE deselect
• JTAG boundary scan for BGA and fBGA packages
• Burst Capability—linear or interleaved burst order
• Low standby power
Selection Guide
133 MHz
117 MHz
7.5
100 MHz
8.5
Unit
ns
mA
mA
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
6.5
210
70
190
70
175
70
Notes:
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Document #: 38-05557 Rev. **
Revised August 12, 2004
CY7C1371DV25
CY7C1373DV25
PRELIMINARY
1
Logic Block Diagram – CY7C1371DV25 (512K x 36)
ADDRESS
A0, A1, A
A1
A0
A1'
A0'
REGISTER
D1
D0
Q1
Q0
MODE
C
BURST
LOGIC
CE
ADV/LD
C
CLK
CEN
WRITE ADDRESS
REGISTER
O
U
T
P
U
T
D
A
T
S
E
N
S
ADV/LD
A
B
U
F
MEMORY
ARRAY
BWA
BWB
BWC
BWD
WRITE
DRIVERS
E
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
S
T
E
E
R
I
DQs
DQP
DQP
DQP
DQP
A
B
C
D
A
M
P
F
E
R
S
S
WE
E
N
G
INPUT
REGISTER
E
OE
READ LOGIC
CE1
CE2
CE3
SLEEP
CONTROL
ZZ
2
Logic Block Diagram – CY7C1373DV25 (1M x 18)
ADDRESS
A0, A1, A
A1
A1'
A0'
REGISTER
D1
A0
Q1
Q0
D0
MODE
BURST
LOGIC
CE
ADV/LD
C
CLK
CEN
C
WRITE ADDRESS
REGISTER
O
U
T
P
U
T
D
A
T
S
E
N
S
ADV/LD
A
B
U
F
MEMORY
ARRAY
BW
A
B
WRITE
DRIVERS
E
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
S
T
E
E
R
I
DQs
DQP
DQP
BW
A
B
A
M
P
F
E
R
S
S
WE
E
N
G
INPUT
REGISTER
E
OE
READ LOGIC
CE1
CE2
CE3
SLEEP
ZZ
CONTROL
Document #: 38-05557 Rev. **
Page 2 of 31
CY7C1371DV25
CY7C1373DV25
PRELIMINARY
Pin Configurations
100-lead TQFP
DQPC
DQC
DQC
VDDQ
VSS
80
1
2
3
4
5
6
7
8
DQPB
DQB
DQB
VDDQ
VSS
DQB
DQB
DQB
DQB
VSS
VDDQ
DQB
DQB
VSS
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQC
BYTE C
BYTE B
DQC
DQC
DQC
VSS
VDDQ
DQC
DQC
NC
VDD
NC
VSS
DQD
DQD
VDDQ
VSS
DQD
DQD
DQD
DQD
VSS
VDDQ
DQD
DQD
DQPD
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
CY7C1371DV25
NC
VDD
ZZ
DQA
DQA
VDDQ
VSS
DQA
DQA
DQA
DQA
VSS
VDDQ
DQA
DQA
DQPA
BYTE D
BYTE A
Document #: 38-05557 Rev. **
Page 3 of 31
CY7C1371DV25
CY7C1373DV25
PRELIMINARY
Pin Configurations (continued)
100-lead TQFP
NC
1
80
A
NC
NC
VDDQ
VSS
NC
DQPA
DQA
DQA
VSS
VDDQ
DQA
DQA
VSS
NC
NC
2
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
3
VDDQ
4
VSS
5
NC
6
NC
7
DQB
8
DQB
9
VSS
10
VDDQ
11
DQB
12
DQB
13
CY7C1373DV25
NC
14
BYTE A
VDD
15
BYTE B
NC
VSS
DQB
DQB
VDDQ
VSS
DQB
DQB
DQPB
NC
VSS
VDDQ
NC
NC
NC
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
VDD
ZZ
DQA
DQA
VDDQ
VSS
DQA
DQA
NC
NC
VSS
VDDQ
NC
NC
NC
Document #: 38-05557 Rev. **
Page 4 of 31
CY7C1371DV25
CY7C1373DV25
PRELIMINARY
Pin Configurations (continued)
119-ball BGA (3 Chip Enables with JTAG)
CY7C1371DV25 (512K x 36)
1
2
3
4
5
6
7
A
VDDQ
A
A
A
A
VDDQ
A
B
C
NC
NC
CE2
A
A
A
ADV/LD
VDD
A
A
CE3
A
NC
NC
DQC
DQC
VDDQ
DQC
DQC
VDDQ
DQD
DQPC
DQC
DQC
DQC
DQC
VDD
VSS
VSS
VSS
NC
CE1
OE
A
WE
VDD
CLK
VSS
VSS
VSS
DQPB
DQB
DQB
DQB
DQB
VDD
DQA
DQB
DQB
VDDQ
DQB
DQB
VDDQ
DQA
D
E
F
G
H
J
BWC
VSS
NC
BWB
VSS
NC
DQD
VSS
VSS
K
L
M
N
DQD
VDDQ
DQD
DQD
DQD
DQD
NC
CEN
A1
DQA
DQA
DQA
DQA
VDDQ
DQA
BWD
VSS
VSS
BWA
VSS
VSS
P
R
DQD
NC
DQPD
A
VSS
MODE
A0
VDD
VSS
NC
DQPA
A
DQA
NC
T
U
NC
VDDQ
NC / 72M
TMS
A
TDI
A
TCK
A
TDO
NC / 36M
NC
ZZ
VDDQ
CY7C1373DV25 (1M x 18)
2
A
CE2
A
NC
DQB
NC
1
3
A
A
4
A
5
A
A
6
A
7
A
B
C
D
E
F
G
H
J
VDDQ
NC
NC
DQB
NC
VDDQ
NC
DQB
VDDQ
VDDQ
NC
NC
NC
DQA
VDDQ
DQA
NC
VDDQ
ADV/LD
VDD
NC
CE3
A
DQPA
NC
A
A
VSS
VSS
VSS
BWB
VSS
NC
VSS
VSS
VSS
NC
VSS
NC
CE1
OE
A
DQA
DQB
NC
VDD
NC
DQA
VDD
WE
VDD
NC
DQB
VSS
CLK
NC
CEN
A1
VSS
NC
DQA
NC
DQA
NC
DQA
K
L
M
N
P
DQB
VDDQ
DQB
NC
NC
DQB
NC
NC
VSS
VSS
VSS
NC
VDDQ
NC
BWA
VSS
VSS
VSS
DQPB
A0
DQA
R
T
U
NC
NC / 72M
VDDQ
A
A
TMS
MODE
A
TDI
VDD
NC / 36M
TCK
NC
A
TDO
A
A
NC
NC
ZZ
VDDQ
Document #: 38-05557 Rev. **
Page 5 of 31
CY7C1371DV25
CY7C1373DV25
PRELIMINARY
Pin Configurations (continued)
165-ball fBGA (3 Chip enable with JTAG)
CY7C1371DV25 (512K x 36)
1
NC / 288M
NC
DQPC
DQC
2
A
A
NC
DQC
DQC
DQC
DQC
NC
3
4
5
6
7
8
9
10
11
NC
NC / 144M
DQPB
DQB
A
CE1
BWC
BWB
CE3
CEN
WE
VSS
VSS
VSS
ADV/LD
A
A
B
C
D
E
F
G
H
J
K
L
CE2
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
VDDQ
VDDQ
VDDQ
BWD
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
BWA
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
CLK
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
OE
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
A
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
VDDQ
VDDQ
VDDQ
A
NC
DQB
DQB
DQB
DQB
NC
DQA
DQA
DQA
DQC
DQB
DQC
DQC
NC
DQD
DQD
DQD
VSS
VSS
VSS
VSS
VSS
VSS
DQB
DQB
ZZ
DQA
DQA
DQA
DQD
DQD
DQD
DQD
DQPD
NC
DQD
NC
NC / 72M
VDDQ
VDDQ
A
VDD
VSS
A
VSS
NC
TDI
VSS
NC
A1
VSS
NC
TDO
VDD
VSS
A
VDDQ
VDDQ
A
DQA
NC
A
DQA
DQPA
NC
M
N
P
A0
MODE NC / 36M
A
A
TMS
TCK
A
A
A
A
R
CY7C1373DV25 (1M x 18)
1
NC / 288M
NC
2
A
A
NC
DQB
DQB
DQB
DQB
NC
3
4
5
6
7
8
9
10
11
A
A
CE1
BWB
NC
CE3
CEN
WE
VSS
VSS
ADV/LD
A
A
B
C
D
E
F
G
H
J
K
L
CE2
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
VDDQ
VDDQ
VDDQ
NC
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
BWA
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
CLK
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
OE
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
A
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
VDDQ
VDDQ
VDDQ
A
NC
NC
NC
NC
NC
NC / 144M
DQPA
DQA
NC
NC
NC
NC
NC
VSS
DQA
VSS
VSS
VSS
VSS
VSS
VSS
DQA
DQA
ZZ
NC
NC
NC
NC
DQB
DQB
DQB
NC
NC
NC
DQA
DQA
DQA
NC
DQB
DQPB
NC
NC
NC
NC / 72M
VDDQ
VDDQ
A
VDD
VSS
A
VSS
NC
TDI
VSS
NC
A1
VSS
NC
TDO
VDD
VSS
A
VDDQ
VDDQ
A
DQA
NC
A
NC
NC
NC
M
N
P
A0
MODE NC / 36M
A
A
TMS
TCK
A
A
A
A
R
Document #: 38-05557 Rev. **
Page 6 of 31
CY7C1371DV25
CY7C1373DV25
PRELIMINARY
Pin Definitions
Name
I/O
Description
A0, A1, A
Input-
Address Inputs used to select one of the address locations. Sampled at the
Synchronous
rising edge of the CLK. A[1:0] are fed to the two-bit burst counter.
BWA, BWB
BWC, BWD
Input-
Byte Write Inputs, active LOW. Qualified with WE to conduct writes to the SRAM.
Synchronous
Sampled on the rising edge of CLK.
WE
Input-
Write Enable Input, active LOW. Sampled on the rising edge of CLK if CEN is
Synchronous
active LOW. This signal must be asserted LOW to initiate a write sequence.
ADV/LD
Input-
Advance/Load Input. Used to advance the on-chip address counter or load a new
address. When HIGH (and CEN is asserted LOW) the internal burst counter is
advanced. When LOW, a new address can be loaded into the device for an access.
After being deselected, ADV/LD should be driven LOW in order to load a new
address.
Synchronous
CLK
CE1
CE2
CE3
OE
Input-
Clock
Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified
with CEN. CLK is only recognized if CEN is active LOW.
Input-
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in
Synchronous
conjunction with CE2, and CE3 to select/deselect the device.
Input-
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in
Synchronous
conjunction with CE1 and CE3 to select/deselect the device.
Input-
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in
Synchronous
conjunction with CE1 and CE2 to select/deselect the device.
Input-
Output Enable, asynchronous input, active LOW. Combined with the
synchronous logic block inside the device to control the direction of the I/O pins.
When LOW, the I/O pins are allowed to behave as outputs. When deasserted HIGH,
I/O pins are tri-stated, and act as input data pins. OE is masked during the data
portion of a write sequence, during the first clock when emerging from a deselected
state, when the device has been deselected.
Asynchronous
CEN
Input-
Clock Enable Input, active LOW. When asserted LOW the Clock signal is recog-
nized by the SRAM. When deasserted HIGH the Clock signal is masked. Since
deasserting CEN does not deselect the device, CEN can be used to extend the
previous cycle when required.
Synchronous
ZZ
Input-
ZZ “Sleep” Input. This active HIGH input places the device in a non-time critical
“sleep” condition with data integrity preserved. During normal operation, this pin can
be connected to VSS or left floating.
Asynchronous
I/O-
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that
is triggered by the rising edge of CLK. As outputs, they deliver the data contained
in the memory location specified by the addresses presented during the previous
clock rise of the read cycle. The direction of the pins is controlled by OE. When OE
is asserted LOW, the pins behave as outputs. When HIGH, DQs and DQP[A:D] are
DQs
Synchronous
The outputs are automatically tri-stated during the data
placed in a tri-state condition.
portion of a write sequence, during the first clock when emerging from a deselected
state, and when the device is deselected, regardless of the state of OE.
I/O-
Bidirectional Data Parity I/O Lines. Functionally, these signals are identical to
DQPX
Synchronous
DQs.
MODE
Input Strap Pin
Mode Input. Selects the burst order of the device.
When tied to Gnd selects linear burst sequence. When tied to VDD or left floating
selects interleaved burst sequence.
VDD
VDDQ
VSS
Power Supply
I/O Power Supply
Ground
Power supply inputs to the core of the device.
Power supply for the I/O circuitry.
Ground for the device.
Document #: 38-05557 Rev. **
Page 7 of 31
CY7C1371DV25
CY7C1373DV25
PRELIMINARY
Pin Definitions (continued)
Name
I/O
Description
TDO
TDI
JTAG serial output
Synchronous
Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If
the JTAG feature is not being utilized, this pin should be left unconnected. This pin
is not available on TQFP packages.
JTAG serial
input
Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG
feature is not being utilized, this pin can be left floating or connected to VDD through
a pull-up resistor. This pin is not available on TQFP packages.
Synchronous
TMS
JTAG serial
input
Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG
feature is not being utilized, this pin can be disconnected or connected to VDD. This
pin is not available on TQFP packages.
Synchronous
TCK
NC
JTAG-Clock
-
Clock input to the JTAG circuitry. If the JTAG feature is not being utilized, this pin
must be connected to VSS. This pin is not available on TQFP packages.
No Connects. Not internally connected to the die.
36M, 72M, 144M and 288M are address expansion pins and are not internally
connected to the die.
Document #: 38-05557 Rev. **
Page 8 of 31
CY7C1371DV25
CY7C1373DV25
PRELIMINARY
determined by the MODE input signal. A LOW input on MODE
selects a linear burst mode, a HIGH selects an interleaved
burst sequence. Both burst counters use A0 and A1 in the
burst sequence, and will wrap around when incremented suffi-
ciently. A HIGH input on ADV/LD will increment the internal
burst counter regardless of the state of chip enable inputs or
WE. WE is latched at the beginning of a burst cycle. Therefore,
the type of access (Read or Write) is maintained throughout
the burst sequence.
Functional Overview
The CY7C1371DV25/CY7C1373DV25 is a synchronous
flow-through burst SRAM designed specifically to eliminate
wait states during Write-Read transitions. All synchronous
inputs pass through input registers controlled by the rising
edge of the clock. The clock signal is qualified with the Clock
Enable input signal (CEN). If CEN is HIGH, the clock signal is
not recognized and all internal states are maintained. All
synchronous operations are qualified with CEN. Maximum
access delay from the clock rise (tCDV) is 6.5 ns (133-MHz
device).
Accesses can be initiated by asserting all three Chip Enables
(CE1, CE2, CE3) active at the rising edge of the clock. If Clock
Enable (CEN) is active LOW and ADV/LD is asserted LOW,
the address presented to the device will be latched. The
access can either be a read or write operation, depending on
the status of the Write Enable (WE). BWX can be used to
conduct byte write operations.
Write operations are qualified by the Write Enable (WE). All
writes are simplified with on-chip synchronous self-timed write
circuitry.
Three synchronous Chip Enables (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) simplify depth expansion.
All operations (Reads, Writes, and Deselects) are pipelined.
ADV/LD should be driven LOW once the device has been
deselected in order to load a new address for the next
operation.
Single Write Accesses
Write access are initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,
and CE3 are ALL asserted active, and (3) the write signal WE
is asserted LOW. The address presented to the address bus
is loaded into the Address Register. The write signals are
latched into the Control Logic block. The data lines are
automatically tri-stated regardless of the state of the OE input
signal. This allows the external logic to present the data on
DQs and DQPX.
On the next clock rise the data presented to DQs and DQPX
(or a subset for byte write operations, see truth table for
details) inputs is latched into the device and the write is
complete. Additional accesses (Read/Write/Deselect) can be
initiated on this cycle.
The data written during the Write operation is controlled by
BWX signals. The CY7C1371DV25/CY7C1373DV25 provides
byte write capability that is described in the truth table.
Asserting the Write Enable input (WE) with the selected Byte
Write Select input will selectively write to only the desired
bytes. Bytes not selected during a byte write operation will
remain unaltered. A synchronous self-timed write mechanism
has been provided to simplify the write operations. Byte write
capability has been included in order to greatly simplify
Read/Modify/Write sequences, which can be reduced to
simple byte write operations.
Because the CY7C1371DV25/CY7C1373DV25 is a common
I/O device, data should not be driven into the device while the
outputs are active. The Output Enable (OE) can be deasserted
HIGH before presenting data to the DQs and DQPX inputs.
Doing so will tri-state the output drivers. As a safety
precaution, DQs and DQPX are automatically tri-stated during
the data portion of a write cycle, regardless of the state of OE.
Single Read Accesses
A read access is initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,
and CE3 are ALL asserted active, (3) the Write Enable input
signal WE is deasserted HIGH, and (4) ADV/LD is asserted
LOW. The address presented to the address inputs is latched
into the Address Register and presented to the memory array
and control logic. The control logic determines that a read
access is in progress and allows the requested data to
propagate to the output buffers. The data is available within 6.5
ns (133-MHz device) provided OE is active LOW. After the first
clock of the read access, the output buffers are controlled by
OE and the internal control logic. OE must be driven LOW in
order for the device to drive out the requested data. On the
subsequent clock, another operation (Read/Write/Deselect)
can be initiated. When the SRAM is deselected at clock rise
by one of the chip enable signals, its output will be tri-stated
immediately.
Burst Write Accesses
The CY7C1371DV25/CY7C1373DV25 has an on-chip burst
counter that allows the user the ability to supply a single
address and conduct up to four Write operations without
reasserting the address inputs. ADV/LD must be driven LOW
in order to load the initial address, as described in the Single
Write Access section above. When ADV/LD is driven HIGH on
the subsequent clock rise, the Chip Enables (CE1, CE2, and
CE3) and WE inputs are ignored and the burst counter is incre-
mented. The correct BWX inputs must be driven in each cycle
of the burst write, in order to write the correct bytes of data.
Burst Read Accesses
The CY7C1371DV25/CY7C1373DV25 has an on-chip burst
counter that allows the user the ability to supply a single
address and conduct up to four Reads without reasserting the
address inputs. ADV/LD must be driven LOW in order to load
a new address into the SRAM, as described in the Single Read
Access section above. The sequence of the burst counter is
Document #: 38-05557 Rev. **
Page 9 of 31
CY7C1371DV25
CY7C1373DV25
PRELIMINARY
Sleep Mode
Interleaved Burst Address Table
(MODE = Floating or VDD
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CE1, CE2, and CE3, must remain inactive
for the duration of tZZREC after the ZZ input returns LOW.
)
First
Second
Address
A1: A0
Third
Address
A1: A0
Fourth
Address
A1: A0
Address
A1: A0
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Linear Burst Address Table
(MODE = GND)
First
Second
Address
A1: A0
Third
Address
A1: A0
Fourth
Address
A1: A0
Address
A1: A0
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
ZZ Mode Electrical Characteristics
Parameter
IDDZZ
tZZS
tZZREC
tZZI
Description
Sleep mode standby current
Device operation to ZZ
ZZ recovery time
ZZ active to sleep current
ZZ Inactive to exit sleep current
Test Conditions
ZZ > VDD – 0.2V
ZZ > VDD – 0.2V
ZZ < 0.2V
This parameter is sampled
This parameter is sampled
Min.
Max.
80
2tCYC
Unit
mA
ns
ns
ns
2tCYC
0
2tCYC
tRZZI
ns
Truth Table [2, 3, 4, 5, 6, 7, 8]
Address
Operation
Deselect Cycle
Deselect Cycle
Used CE1 CE2
ZZ ADV/LD WE BWX OE CEN CLK
DQ
CE3
X
H
X
X
L
X
L
X
L
None
None
None
None
External
Next
External
Next
External
Next
H
X
X
X
L
X
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
H
L
H
L
H
L
X
X
X
X
H
X
H
X
L
X
X
X
X
X
X
X
X
L
X
X
X
X
L
L
L
L
L
L
L
L
L
L
L
L
L->H
L->H
L->H
L->H
L->H Data Out (Q)
L->H Data Out (Q)
L->H
L->H
L->H Data In (D)
L->H Data In (D)
Tri-State
Tri-State
Tri-State
Tri-State
Deselect Cycle
Continue Deselect Cycle
Read Cycle (Begin Burst)
Read Cycle (Continue Burst)
NOP/Dummy Read (Begin Burst)
Dummy Read (Continue Burst)
Write Cycle (Begin Burst)
Write Cycle (Continue Burst)
X
H
X
H
X
H
X
H
X
L
L
H
H
X
X
X
Tri-State
Tri-State
X
L
X
L
X
L
X
L
L
H
NOP/Write Abort (Begin Burst)
None
L->H
Tri-State
Notes:
2. X = “Don't Care.” H = Logic HIGH, L = Logic LOW. BW = 0 signifies at least one Byte Write Select is active, BW = Valid signifies that the desired byte write
X
X
selects are asserted, see truth table for details.
3. Write is defined by BW , and WE. See truth table for Read/Write.
X
4. When a write cycle is detected, all I/Os are tri-stated, even during byte writes.
5. The DQs and DQP pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
X
6. CEN = H, inserts wait states.
7. Device will power-up deselected and the I/Os in a tri-state condition, regardless of OE.
8. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQs and DQP = Tri-state when OE
X
is inactive or when the device is deselected, and DQs and DQP = data when OE is active.
X
9. Table only lists a partial listing of the byte write combinations. Any Combination of BW is valid. Appropriate write will be done based on which byte write is active.
X
Document #: 38-05557 Rev. **
Page 10 of 31
CY7C1371DV25
CY7C1373DV25
PRELIMINARY
Truth Table (continued)[2, 3, 4, 5, 6, 7, 8]
Address
Operation
Write Abort (Continue Burst)
Ignore Clock Edge (Stall)
Sleep Mode
Used CE1 CE2
ZZ ADV/LD WE BWX OE CEN CLK
DQ
Tri-State
-
CE3
X
X
Next
Current
None
X
X
X
X
X
X
L
L
H
X
X
X
X
X
H
X
X
X
X
X
L
H
X
L->H
L->H
X
X
H
Tri-State
Partial Truth Table for Read/Write[2, 3, 9]
Function (CY7C1371DV25)
Read
Write No bytes written
Write Byte A – (DQA and DQPA)
Write Byte B – (DQB and DQPB)
Write Byte C – (DQC and DQPC)
Write Byte D – (DQD and DQPD)
Write All Bytes
WE
H
L
L
L
L
L
L
BWA
X
H
L
H
H
H
L
BWB
X
H
H
L
H
H
L
BWC
BWD
X
H
H
H
H
L
L
X
H
H
H
L
H
L
Partial Truth Table for Read/Write[2, 3, 9]
Function (CY7C1373DV25)
Read
Write - No bytes written
Write Byte A – (DQA and DQPA)
Write Byte B – (DQB and DQPB)
Write All Bytes
WE
BWA
BWB
X
H
H
H
H
L
L
L
L
X
H
H
H
L
L
Document #: 38-05557 Rev. **
Page 11 of 31
CY7C1371DV25
CY7C1373DV25
PRELIMINARY
Test Data-In (TDI)
IEEE 1149.1 Serial Boundary Scan (JTAG)
The TDI ball is used to serially input information into the
registers and can be connected to the input of any of the
registers. The register between TDI and TDO is chosen by the
instruction that is loaded into the TAP instruction register. For
information on loading the instruction register, see figure. TDI
is internally pulled up and can be unconnected if the TAP is
unused in an application. TDI is connected to the most signif-
icant bit (MSB) of any register. (See Tap Controller Block
Diagram.)
The CY7C1371DV25/CY7C1373DV25 incorporates a serial
boundary scan test access port (TAP). This part is fully
compliant with 1149.1. The TAP operates using
JEDEC-standard 2.5V I/O logic levels.
The CY7C1371DV25/CY7C1373DV25 contains
a
TAP
controller, instruction register, boundary scan register, bypass
register, and ID register.
Disabling the JTAG Feature
Test Data-Out (TDO)
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(VSS) to prevent clocking of the device. TDI and TMS are inter-
nally pulled up and may be unconnected. They may alternately
be connected to VDD through a pull-up resistor. TDO should be
left unconnected. Upon power-up, the device will come up in
a reset state which will not interfere with the operation of the
device.
The TDO output ball is used to serially clock data-out from the
registers. The output is active depending upon the current
state of the TAP state machine. The output changes on the
falling edge of TCK. TDO is connected to the least significant
bit (LSB) of any register. (See Tap Controller State Diagram.)
TAP Controller Block Diagram
TAP Controller State Diagram
0
Bypass Register
TEST-LOGIC
1
RESET
0
2
1
0
0
0
Selection
Circuitry
1
1
1
Instruction Register
31 30 29
Identification Register
RUN-TEST/
IDLE
SELECT
DR-SCAN
SELECT
IR-SCAN
Selection
0
TDI
TDO
Circuitr
y
.
.
. 2 1
0
0
1
1
CAPTURE-DR
CAPTURE-IR
0
0
x
.
.
.
.
. 2 1
SHIFT-DR
0
SHIFT-IR
0
Boundary Scan Register
1
1
1
1
EXIT1-DR
EXIT1-IR
TCK
TMS
0
0
TAP CONTROLLER
PAUSE-DR
0
PAUSE-IR
0
1
1
0
0
EXIT2-DR
1
EXIT2-IR
1
Performing a TAP Reset
A RESET is performed by forcing TMS HIGH (VDD) for five
rising edges of TCK. This RESET does not affect the operation
of the SRAM and may be performed while the SRAM is
operating.
UPDATE-DR
UPDATE-IR
1
0
1
0
At power-up, the TAP is reset internally to ensure that TDO
comes up in a High-Z state.
The 0/1 next to each state represents the value of TMS at the
rising edge of TCK.
TAP Registers
Registers are connected between the TDI and TDO balls and
allow data to be scanned into and out of the SRAM test
circuitry. Only one register can be selected at a time through
the instruction register. Data is serially loaded into the TDI ball
on the rising edge of TCK. Data is output on the TDO ball on
the falling edge of TCK.
Test Access Port (TAP)
Test Clock (TCK)
The test clock is used only with the TAP controller. All inputs
are captured on the rising edge of TCK. All outputs are driven
from the falling edge of TCK.
Instruction Register
Test Mode Select (TMS)
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the
TDI and TDO balls as shown in the Tap Controller Block
Diagram. Upon power-up, the instruction register is loaded
with the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as
described in the previous section.
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. It is allowable to
leave this ball unconnected if the TAP is not used. The ball is
pulled up internally, resulting in a logic HIGH level.
Document #: 38-05557 Rev. **
Page 12 of 31
CY7C1371DV25
CY7C1373DV25
PRELIMINARY
When the TAP controller is in the Capture-IR state, the two
least significant bits are loaded with a binary “01” pattern to
allow for fault isolation of the board-level serial test data path.
0s. EXTEST is not implemented in this SRAM TAP controller,
and therefore this device is not compliant to 1149.1. The TAP
controller does recognize an all-0 instruction.
When an EXTEST instruction is loaded into the instruction
register, the SRAM responds as if a SAMPLE/PRELOAD
instruction has been loaded. There is one difference between
the two instructions. Unlike the SAMPLE/PRELOAD
instruction, EXTEST places the SRAM outputs in a High-Z
state.
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between the
TDI and TDO balls. This allows data to be shifted through the
SRAM with minimal delay. The bypass register is set LOW
(VSS) when the BYPASS instruction is executed.
IDCODE
The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the instruction register. It also places the
instruction register between the TDI and TDO balls and allows
the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state.
The IDCODE instruction is loaded into the instruction register
upon power-up or whenever the TAP controller is given a test
logic reset state.
Boundary Scan Register
The boundary scan register is connected to all the input and
bidirectional balls on the SRAM.
The boundary scan register is loaded with the contents of the
RAM I/O ring when the TAP controller is in the Capture-DR
state and is then placed between the TDI and TDO balls when
the controller is moved to the Shift-DR state. The EXTEST,
SAMPLE/PRELOAD and SAMPLE Z instructions can be used
to capture the contents of the I/O ring.
SAMPLE Z
The Boundary Scan Order tables show the order in which the
bits are connected. Each bit corresponds to one of the bumps
on the SRAM package. The MSB of the register is connected
to TDI and the LSB is connected to TDO.
The SAMPLE Z instruction causes the boundary scan register
to be connected between the TDI and TDO balls when the TAP
controller is in a Shift-DR state. It also places all SRAM outputs
into a High-Z state.
Identification (ID) Register
SAMPLE/PRELOAD
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired
into the SRAM and can be shifted out when the TAP controller
is in the Shift-DR state. The ID register has a vendor code and
other information described in the Identification Register
Definitions table.
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When
the SAMPLE/PRELOAD instructions are loaded into the in-
struction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and output pins is cap-
tured in the boundary scan register.
The user must be aware that the TAP controller clock can only
operate at a frequency up to 20 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because
there is a large difference in the clock frequencies, it is possi-
ble that during the Capture-DR state, an input or output will
undergo a transition. The TAP may then try to capture a signal
while in transition (metastable state). This will not harm the
device, but there is no guarantee as to the value that will be
captured. Repeatable results may not be possible.
To guarantee that the boundary scan register will capture the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller's capture set-up plus
hold times (tCS and tCH). The SRAM clock input might not be
captured correctly if there is no way in a design to stop (or
slow) the clock during a SAMPLE/PRELOAD instruction. If this
is an issue, it is still possible to capture all other signals and
simply ignore the value of the CK and CK captured in the
boundary scan register.
Once the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the bound-
ary scan register between the TDI and TDO pins.
PRELOAD allows an initial data pattern to be placed at the
latched parallel outputs of the boundary scan register cells pri-
or to the selection of another boundary scan test operation.
The shifting of data for the SAMPLE and PRELOAD phases
can occur concurrently when required—that is, while data
captured is shifted out, the preloaded data can be shifted in.
TAP Instruction Set
Overview
Eight different instructions are possible with the three-bit
instruction register. All combinations are listed in the
Instruction Codes table. Three of these instructions are listed
as RESERVED and should not be used. The other five instruc-
tions are described in detail below.
The TAP controller used in this SRAM is not fully compliant to
the 1149.1 convention because some of the mandatory 1149.1
instructions are not fully implemented.
The TAP controller cannot be used to load address data or
control signals into the SRAM and cannot preload the I/O
buffers. The SRAM does not implement the 1149.1 commands
EXTEST or INTEST or the PRELOAD portion of
SAMPLE/PRELOAD; rather, it performs a capture of the I/O
ring when these instructions are executed.
Instructions are loaded into the TAP controller during the
Shift-IR state when the instruction register is placed between
TDI and TDO. During this state, instructions are shifted
through the instruction register through the TDI and TDO balls.
To execute the instruction once it is shifted in, the TAP
controller needs to be moved into the Update-IR state.
EXTEST
EXTEST is a mandatory 1149.1 instruction which is to be
executed whenever the instruction register is loaded with all
Document #: 38-05557 Rev. **
Page 13 of 31
CY7C1371DV25
CY7C1373DV25
PRELIMINARY
BYPASS
boundary scan path when multiple devices are connected
together on a board.
When the BYPASS instruction is loaded in the instruction
register and the TAP is placed in a Shift-DR state, the bypass
register is placed between the TDI and TDO balls. The
advantage of the BYPASS instruction is that it shortens the
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
TAP Timing
1
2
3
4
5
6
Test Clock
(TCK)
t
t
t
CYC
TH
TL
t
t
t
t
TMSS
TDIS
TMSH
Test Mode Select
(TMS)
TDIH
Test Data-In
(TDI)
t
TDOV
t
TDOX
Test Data-Out
(TDO)
DON’T CARE
UNDEFINED
TAP AC Switching Characteristics Over the Operating Range[10, 11]
Parameter
Clock
tTCYC
tTF
tTH
tTL
Description
Min.
Max.
Unit
TCK Clock Cycle Time
TCK Clock Frequency
TCK Clock HIGH time
TCK Clock LOW time
50
ns
MHz
ns
20
25
25
ns
Output Times
tTDOV TCK Clock LOW to TDO Valid
tTDOX TCK Clock LOW to TDO Invalid
Set-up Times
tTMSS TMS Set-up to TCK Clock Rise
tTDIS
5
ns
ns
0
5
5
5
ns
ns
TDI Set-up to TCK Clock Rise
Capture Set-up to TCK Rise
tCS
Hold Times
tTMSH
tTDIH
TMS hold after TCK Clock Rise
TDI Hold after Clock Rise
Capture Hold after Clock Rise
5
5
5
ns
ns
ns
tCH
Notes:
10. t and t refer to the set-up and hold time requirements of latching data from the boundary scan register.
CS
CH
11. Test conditions are specified using the load in TAP AC test Conditions. t /t = 1 ns.
R
F
Document #: 38-05557 Rev. **
Page 14 of 31
CY7C1371DV25
CY7C1373DV25
PRELIMINARY
2.5V TAP AC Test Conditions
2.5V TAP AC Output Load Equivalent
1.25V
Input pulse levels ............................................... .VSS to 2.5V
Input rise and fall time..................................................... 1 ns
Input timing reference levels.........................................1.25V
Output reference levels.................................................1.25V
Test load termination supply voltage.............................1.25V
50Ω
TDO
ZO= 50Ω
20pF
TAP DC Electrical Characteristics And Operating Conditions
(0°C < TA < +70°C; VDD = 2.5V ±0.125V unless otherwise noted)[12]
Parameter
VOH1
VOH2
VOL1
VOL2
VIH
Description
Test Conditions
Min.
2.0
2.1
Max.
Unit
V
V
V
V
V
V
µA
Output HIGH Voltage IOH = –1.0 mA, VDDQ = 2.5V
Output HIGH Voltage IOH = –100 µA, VDDQ = 2.5V
Output LOW Voltage IOL = 8.0 mA, VDDQ = 2.5V
Output LOW Voltage IOL = 100 µA
Input HIGH Voltage
0.4
0.2
VDD + 0.3
0.7
VDDQ = 2.5V
VDDQ = 2.5V
VDDQ = 2.5V
1.7
–0.3
–5
VIL
IX
Input LOW Voltage
Input Load Current
GND < VIN < VDDQ
5
Note:
12. All voltages referenced to V (GND).
SS
Document #: 38-05557 Rev. **
Page 15 of 31
CY7C1371DV25
CY7C1373DV25
PRELIMINARY
Identification Register Definitions
CY7C1371DV25 CY7C1373DV25
Instruction Field
Revision Number (31:29)
Device Depth (28:24)[13]
(512Kx36)
000
(1Mx18)
000
Description
Describes the version number
Reserved for internal use
01011
01011
001001
100101
00000110100
1
001001
010101
00000110100
1
Device Width (23:18)
Defines memory type and architecture
Defines width and density
Allows unique identification of SRAM vendor
Indicates the presence of an ID register
Cypress Device ID (17:12)
Cypress JEDEC ID Code (11:1)
ID Register Presence Indicator (0)
Scan Register Sizes
Register Name
Bit Size(x36)
Bit Size(x18)
Instruction
Bypass
ID
3
1
32
85
89
3
1
32
85
89
Boundary Scan Order (119-ball BGA package)
Boundary Scan Order (165-ball fBGA package)
Identification Codes
Instruction
Code
Description
EXTEST
000
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM outputs to High-Z state.
IDCODE
001
010
Loads the ID register with the vendor ID code and places the register between TDI and
TDO. This operation does not affect SRAM operations.
SAMPLE Z
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM output drivers to a High-Z state.
RESERVED
SAMPLE/PRELOAD
011
100
Do Not Use: This instruction is reserved for future use.
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Does not affect SRAM operation.
RESERVED
RESERVED
BYPASS
101
110
111
Do Not Use: This instruction is reserved for future use.
Do Not Use: This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does not affect SRAM
operations.
Note:
13. Bit #24 is “1” in the Register Definitions for both 2.5v and 3.3v versions of this device
Document #: 38-05557 Rev. **
Page 16 of 31
CY7C1371DV25
CY7C1373DV25
PRELIMINARY
119-ball BGA Boundary Scan[14, 15]
CY7C1371DV25 (1M x 36)
CY7C1371DV25 (1M x 36)
Bit #
1
2
3
4
5
6
7
8
Ball ID
Bit #
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
Ball ID
B6
D4
B4
F4
Bit #
73
74
75
76
77
78
79
80
81
82
83
84
85
Ball ID
N2
P2
R3
T1
R1
T2
L3
R2
T3
L4
N4
P4
H4
T4
T5
T6
R5
L5
R6
U6
R7
T7
P6
N7
M6
L7
K6
P7
N6
L6
K7
J5
H6
G7
F6
E7
D7
H7
G6
E6
D6
C7
B7
C6
A6
C5
B5
G5
M4
A5
K4
E4
G4
A4
G3
C3
B2
B3
A3
C2
A2
B1
C1
D2
E1
F2
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
Internal
G1
H2
D1
E2
G2
H1
J3
2K
L1
M2
N1
P1
K1
L2
Notes:
14. Balls which are NC (No Connect) are pre-set LOW
15. Bit# 85 is pre-set HIGH
Document #: 38-05557 Rev. **
Page 17 of 31
CY7C1371DV25
CY7C1373DV25
PRELIMINARY
119-ball BGA Boundary Scan Order[14, 15]
CY7C1373DV25 (2M x 18)
CY7C1373DV25 (2M x 18)
Bit #
1
2
3
4
5
6
7
8
Ball ID
Bit #
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
Ball ID
B6
D4
B4
F4
Bit #
73
74
75
76
77
78
79
80
81
82
83
84
85
Ball ID
N2
P2
R3
T1
R1
T2
L3
R2
T3
L4
N4
P4
H4
T4
T5
T6
R5
L5
R6
U6
R7
T7
P6
N7
M6
L7
K6
P7
N6
L6
K7
J5
H6
G7
F6
E7
D7
H7
G6
E6
D6
C7
B7
C6
A6
C5
B5
G5
M4
A5
K4
E4
G4
A4
G3
C3
B2
B3
A3
C2
A2
B1
C1
D2
E1
F2
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
Internal
G1
H2
D1
E2
G2
H1
J3
2K
L1
M2
N1
P1
K1
L2
Document #: 38-05557 Rev. **
Page 18 of 31
CY7C1371DV25
CY7C1373DV25
PRELIMINARY
165-ball fBGA Boundary Scan Order[14, 16]
CY7C1371DV25 (1M x 36)
CY7C1371DV25 (1M x 36)
Bit #
1
2
3
4
5
6
7
8
Ball ID
N6
N7
10N
P11
P8
R8
R9
P9
Bit #
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
Ball ID
A9
B9
C10
A8
B8
A7
B7
B6
A6
B5
A5
A4
B4
B3
A3
A2
B2
C2
B1
A1
C1
D1
E1
F1
G1
D2
E2
F2
G2
H1
H3
J1
K1
L1
M1
J2
Bit #
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
Ball ID
K2
L2
M2
N1
N2
P1
R1
R2
P3
R3
P2
R4
P4
N5
P6
R6
Internal
9
P10
R10
R11
H11
N11
M11
L11
K11
J11
M10
L10
K10
J10
H9
H10
G11
F11
E11
D11
G10
F10
E10
D10
C11
A11
B11
A10
B10
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
Note:
16. Bit# 89 is pre-set HIGH.
Document #: 38-05557 Rev. **
Page 19 of 31
CY7C1371DV25
CY7C1373DV25
PRELIMINARY
165-ball fBGA Boundary Scan Order[14, 16]
CY7C1373DV25 (2M x 18)
CY7C1373DV25 (2M x 18)
Bit #
1
2
3
4
5
6
7
8
Ball ID
N6
N7
10N
P11
P8
R8
R9
P9
Bit #
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
Ball ID
A9
B9
C10
A8
B8
A7
B7
B6
A6
B5
A5
A4
B4
B3
A3
A2
B2
C2
B1
A1
C1
D1
E1
F1
G1
D2
E2
F2
G2
H1
H3
J1
K1
L1
M1
J2
Bit #
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
Ball ID
K2
L2
M2
N1
N2
P1
R1
R2
P3
R3
P2
R4
P4
N5
P6
R6
Internal
9
P10
R10
R11
H11
N11
M11
L11
K11
J11
M10
L10
K10
J10
H9
H10
G11
F11
E11
D11
G10
F10
E10
D10
C11
A11
B11
A10
B10
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
Document #: 38-05557 Rev. **
Page 20 of 31
CY7C1371DV25
CY7C1373DV25
PRELIMINARY
Current into Outputs (LOW)......................................... 20 mA
Maximum Ratings
Static Discharge Voltage........................................... >2001V
(Above which the useful life may be impaired. For user guide-
(per MIL-STD-883, Method 3015)
lines, not tested.)
Latch-up Current..................................................... >200 mA
Storage Temperature .................................–65°C to +150°C
Operating Range
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Ambient
VDD/VDDQ
Range
Commercial
Industrial
Temperature
0°C to +70°C
–40°C to +85°C
Supply Voltage on VDD Relative to GND........ –0.5V to +3.6V
2.5V +_ 5%
DC Voltage Applied to Outputs
in Tri-State........................................... –0.5V to VDDQ + 0.5V
DC Input Voltage....................................–0.5V to VDD + 0.5V
Electrical Characteristics Over the Operating Range[17, 18]
Parameter
VDD
VDDQ
VOH
VOL
VIH
VIL
IX
Description
Test Conditions
Min.
2.375
2.375
2.0
Max.
2.625
VDD
Unit
V
V
V
V
Power Supply Voltage
I/O Supply Voltage
Output HIGH Voltage
Output LOW Voltage
VDD = Min., IOH = −1.0 mA
VDD = Min., IOL= 1.0 mA
0.4
VDD + 0.3V
Input HIGH Voltage[17] VDDQ = 2.5V
Input LOW Voltage[17] VDDQ = 2.5V
Input Load
Input Current of MODE Input = VSS
Input = VDD
Input Current of ZZ
1.7
–0.3
–5
V
V
0.7
5
GND ≤ VI ≤ VDDQ
µA
µA
µA
µA
µA
µA
mA
mA
mA
mA
mA
mA
mA
–5
30
Input = VSS
Input = VDD
–30
–5
5
5
IOZ
IDD
Output Leakage Current GND ≤ VI ≤ VDD, Output Disabled
VDD Operating Supply VDD = Max., IOUT = 0 mA,
7.5-ns cycle, 133 MHz
8.5-ns cycle, 117 MHz
10-ns cycle, 100 MHz
7.5-ns cycle, 133 MHz
8.5-ns cycle, 117 MHz
10-ns cycle, 100 MHz
All speeds
210
190
175
140
130
120
70
Current
f = fMAX = 1/tCYC
ISB1
Automatic CE
VDD = Max, Device Deselected,
Power-down
VIN ≥ VIH or VIN ≤ VIL
Current—TTL Inputs
f = fMAX, inputs switching
ISB2
Automatic CE
Power-down
VDD = Max, Device Deselected,
V
IN ≤ 0.3V or VIN > VDD – 0.3V,
Current—CMOS Inputs f = 0, inputs static
ISB3
Automatic CE
VDD = Max, Device Deselected, or 7.5-ns cycle, 133 MHz
130
120
110
80
mA
mA
mA
mA
Power-down
V
IN ≤ 0.3V or VIN > VDDQ – 0.3V
8.5-ns cycle, 117 MHz
10-ns cycle, 100 MHz
All Speeds
Current—CMOS Inputs f = fMAX, inputs switching
ISB4
Automatic CE
VDD = Max, Device Deselected,
IN ≥ VDD – 0.3V or VIN ≤ 0.3V,
f = 0, inputs static
Power-down
V
Current—TTL Inputs
Notes:
17. Overshoot: V (AC) < V +1.5V (Pulse width less than t
/2), undershoot: V (AC) > –2V (Pulse width less than t
/2).
IH
DD
CYC
IL
CYC
18. T
: Assumes a linear ramp from 0V to V (min.) within 200 ms. During this time V < V and V
< V
.
DD
Power-up
DD
IH
DD
DDQ
Document #: 38-05557 Rev. **
Page 21 of 31
CY7C1371DV25
CY7C1373DV25
PRELIMINARY
Thermal Resistance[19]
TQFP
BGA
fBGA
Parameter
Description
Test Conditions
Package
Package
Package
Unit
ΘJA
Thermal Resistance
Test conditions follow standard
testmethodsandproceduresfor
measuring thermal impedance,
per EIA / JESD51.
31
45
46
°C/W
(Junction to Ambient)
ΘJC
Thermal Resistance
(Junction to Case)
6
7
3
°C/W
Capacitance[19]
TQFP
BGA
fBGA
Parameter
Description
Input Capacitance
Test Conditions
Package
Package
Package
Unit
pF
CIN
TA = 25°C, f = 1 MHz,
5
5
5
8
8
8
9
9
9
V
DD = 2.5V
CCLK
CI/O
Clock Input Capacitance
Input/Output Capacitance
pF
VDDQ = 2.5V
pF
AC Test Loads and Waveforms
2.5V I/O Test Load
R = 1667Ω
2.5V
OUTPUT
ALL INPUT PULSES
90%
VDDQ
GND
OUTPUT
90%
10%
Z = 50Ω
0
R = 50Ω
10%
L
5 pF
R = 1538Ω
≤ 1 ns
≤ 1 ns
V = 1.25V
T
INCLUDING
JIG AND
SCOPE
(c)
(a)
(b)
Note:
19. Tested initially and after any design or process change that may affect these parameters.
Document #: 38-05557 Rev. **
Page 22 of 31
CY7C1371DV25
CY7C1373DV25
PRELIMINARY
Switching Characteristics Over the Operating Range[24, 25]
133 MHz
117 MHz
100 MHz
Parameter
tPOWER
Description
Min.
1
Max.
Min.
1
Max.
Min.
1
Max.
Unit
ms
[20]
Clock
tCYC
tCH
Clock Cycle Time
Clock HIGH
Clock LOW
7.5
2.1
2.1
8.5
2.3
2.3
10
2.5
2.5
ns
ns
ns
tCL
Output Times
tCDV
tDOH
tCLZ
tCHZ
Data Output Valid After CLK Rise
Data Output Hold After CLK Rise
Clock to Low-Z[21, 22, 23]
6.5
7.5
8.5
ns
ns
ns
ns
ns
ns
ns
2.0
2.0
2.0
2.0
2.0
2.0
Clock to High-Z[21, 22, 23]
4.0
3.2
4.0
3.4
5.0
3.8
tOEV
OE LOW to Output Valid
OE LOW to Output Low-Z[21, 22, 23]
OE HIGH to Output High-Z[21, 22, 23]
tOELZ
tOEHZ
Set-up Times
tAS
tALS
tWES
tCENS
tDS
tCES
0
0
0
4.0
4.0
5.0
Address Set-up Before CLK Rise
ADV/LD Set-up Before CLK Rise
WE, BWX Set-up Before CLK Rise
CEN Set-up Before CLK Rise
Data Input Set-up Before CLK Rise
Chip Enable Set-Up Before CLK Rise
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
ns
ns
ns
ns
ns
ns
Hold Times
tAH
tALH
tWEH
tCENH
tDH
Address Hold After CLK Rise
ADV/LD Hold After CLK Rise
WE, BWX Hold After CLK Rise
CEN Hold After CLK Rise
Data Input Hold After CLK Rise
Chip Enable Hold After CLK Rise
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
ns
ns
tCEH
Notes:
20. This part has a voltage regulator internally; t
can be initiated.
is the time that the power needs to be supplied above V (minimum) initially, before a read or write operation
DD
POWER
21. t
, t
,t
, and t
are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
CHZ CLZ OELZ
OEHZ
22. At any given voltage and temperature, t
is less than t
and t
is less than t
to eliminate bus contention between SRAMs when sharing the same
CLZ
OEHZ
OELZ
CHZ
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions.
23. This parameter is sampled and not 100% tested.
24. Timing reference level is 1.25V when V
= 2.5V.
DDQ
25. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
Document #: 38-05557 Rev. **
Page 23 of 31
CY7C1371DV25
CY7C1373DV25
PRELIMINARY
Switching Waveforms
Read/Write Waveforms[26, 27, 28]
t
1
2
3
4
5
6
7
8
9
10
CYC
t
CLK
CEN
t
t
t
t
t
CENS
CES
CENH
CEH
CL
CH
CE
ADV/LD
WE
BW
X
A1
A2
A4
A3
A5
A6
A7
ADDRESS
DQ
t
CDV
t
t
AS
AH
t
t
t
t
CHZ
DOH
OEV
CLZ
D(A1)
t
D(A2)
D(A2+1)
Q(A3)
Q(A4)
Q(A4+1)
D(A5)
Q(A6)
D(A7)
t
OEHZ
t
DS
DH
t
DOH
t
OELZ
OE
COMMAND
WRITE
D(A1)
WRITE
D(A2)
BURST
WRITE
READ
Q(A3)
READ
Q(A4)
BURST
READ
WRITE
D(A5)
READ
Q(A6)
WRITE
D(A7)
DESELECT
D(A2+1)
Q(A4+1)
DON’T CARE
UNDEFINED
Notes:
For this waveform ZZ is tied LOW.
26.
27. When CE is LOW, CE is LOW, CE is HIGH and CE is LOW. When CE is HIGH, CE is HIGH or CE is LOW or CE is HIGH.
1
2
3
1
2
3
28. Order of the Burst sequence is determined by the status of the MODE (0 = Linear, 1= Interleaved). Burst operations are optional.
3
Document #: 38-05557 Rev. **
Page 24 of 31
CY7C1371DV25
CY7C1373DV25
PRELIMINARY
Switching Waveforms (continued)
NOP, STALL AND DESELECT Cycles[26, 27, 29]
t
1
2
3
4
5
6
7
8
9
10
CYC
CLK
CEN
t
t
t
t
t
t
CENS
CES
CENH
CEH
CL
CH
CE
ADV/LD
WE
BW
X
A1
A2
A4
A3
A5
A6
A7
ADDRESS
DQ
t
CDV
t
t
AS
AH
t
t
t
t
CHZ
DOH
OEV
CLZ
D(A1)
t
D(A2)
D(A2+1)
Q(A3)
Q(A4)
Q(A4+1)
D(A5)
Q(A6)
D(A7)
t
OEHZ
t
DS
DH
t
DOH
t
OELZ
OE
COMMAND
WRITE
D(A1)
WRITE
D(A2)
BURST
WRITE
READ
Q(A3)
READ
Q(A4)
BURST
READ
WRITE
D(A5)
READ
Q(A6)
WRITE
D(A7)
DESELECT
D(A2+1)
Q(A4+1)
DON’T CARE
UNDEFINED
Note:
29. The Ignore Clock Edge or Stall cycle (Clock 3) illustrates CEN being used to create a pause. A write is not performed during this cycle.
Document #: 38-05557 Rev. **
Page 25 of 31
CY7C1371DV25
CY7C1373DV25
PRELIMINARY
Switching Waveforms (continued)
ZZ Mode Timing[30, 31]
CLK
t
t
ZZ
ZZREC
ZZ
t
ZZI
I
SUPPLY
I
DDZZ
t
RZZI
ALL INPUTS
(except ZZ)
DESELECT or READ Only
Outputs (Q)
High-Z
DON’T CARE
Notes:
30. Device must be deselected when entering ZZ mode. See truth table for all possible signal conditions to deselect the device.
31. DQs are in high-Z when exiting ZZ sleep mode.
4
Document #: 38-05557 Rev. **
Page 26 of 31
CY7C1371DV25
CY7C1373DV25
PRELIMINARY
Ordering Information
Speed
Package
Operating
Range
(MHz)
Ordering Code
Name
Part and Package Type
133
CY7C1371DV25-133AC
CY7C1373DV25-133AC
A101
100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm)
Commercial
3 Chip Enables
CY7C1371DV25-133AI
CY7C1373DV25-133AI
A101
100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm)
3 Chip Enables
Industrial
CY7C1371DV25-133BGC
CY7C1373DV25-133BGC
CY7C1371DV25-133BGI
CY7C1373DV25-133BGI
CY7C1371DV25-133BZC
CY7C1373DV25-133BZC
CY7C1371DV25-133BZI
CY7C1373DV25-133BZI
CY7C1371DV25-117AC
CY7C1373DV25-117AC
BG119 119-ball (14 x 22 x 2.4 mm) BGA 3 Chip Enables and Commercial
JTAG
BG119 119-ball (14 x 22 x 2.4 mm) BGA 3 Chip Enables and
JTAG
Industrial
BB165D 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4mm) Commercial
3 Chip Enables and JTAG
BB165D 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4mm)
3 Chip Enables and JTAG
Industrial
Commercial
Industrial
117
A101
100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm)
3 Chip Enables
CY7C1371DV25-117AI
A101
100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm)
3 Chip Enables
CY7C1373DV25-117AI
CY7C1371DV25-117BGC
CY7C1373DV25-117BGC
CY7C1371DV25-117BGI
CY7C1373DV25-117BGI
CY7C1371DV25-117BZC
CY7C1373DV25-117BZC
CY7C1371DV25-117BZI
CY7C1373DV25-117BZI
CY7C1371DV25-100AC
CY7C1373DV25-100AC
CY7C1371DV25-100AI
CY7C1373DV25-100AI
CY7C1371DV25-100BGC
CY7C1373DV25-100BGC
CY7C1371DV25-100BGI
ICY7C1373DV25-100BGI
CY7C1371DV25-100BZC
CY7C1373DV25-100BZC
CY7C1371DV25-100BZI
CY7C1373DV25-100BZI
BG119 119-ball (14 x 22 x 2.4 mm) BGA 3 Chip Enables and Commercial
JTAG
BG119 119-ball (14 x 22 x 2.4 mm) BGA 3 Chip Enables and
JTAG
Industrial
BB165D 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4mm) Commercial
3 Chip Enables and JTAG
BB165D 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4mm)
3 Chip Enables and JTAG
Industrial
Commercial
Industrial
100
A101
100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm)
3 Chip Enables
A101
100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm)
3 Chip Enables
BG119 119-ball (14 x 22 x 2.4 mm) BGA 3 Chip Enables and Commercial
JTAG
BG119 119-ball (14 x 22 x 2.4 mm) BGA 3 Chip Enables and
JTAG
Industrial
BB165D 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4mm) Commercial
3 Chip Enables and JTAG
BB165D 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4mm)
3 Chip Enables and JTAG
Industrial
Shaded areas contain advance information. Please contact your local sales representative for availability of these parts.
Document #: 38-05557 Rev. **
Page 27 of 31
CY7C1371DV25
CY7C1373DV25
PRELIMINARY
Package Diagrams
100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101
DIMENSIONS ARE IN MILLIMETERS.
ꢁ6.00 0.20
ꢁ4.00 0.ꢁ0
ꢁ.40 0.05
ꢁ00
ꢀꢁ
ꢀ0
ꢁ
0.30 0.0ꢀ
0.65
TYP.
ꢁ2° ꢁ°
(ꢀX)
SEE DETAIL
A
30
5ꢁ
3ꢁ
50
0.20 MAX.
ꢁ.60 MAX.
R 0.0ꢀ MIN.
0.20 MAX.
0° MIN.
STAND-OFF
0.05 MIN.
0.ꢁ5 MAX.
SEATING PLANE
0.25
GAUGE PLANE
R 0.0ꢀ MIN.
0.20 MAX.
0°-7°
0.60 0.ꢁ5
0.20 MIN.
ꢁ.00 REF.
51-85050-*A
DETAIL
A
Document #: 38-05557 Rev. **
Page 28 of 31
CY7C1371DV25
CY7C1373DV25
PRELIMINARY
Package Diagrams (continued)
119-Lead PBGA (14 x 22 x 2.4 mm) BG119
51-85115-*B
Document #: 38-05557 Rev. **
Page 29 of 31
CY7C1371DV25
CY7C1373DV25
PRELIMINARY
Package Diagrams (continued)
165 FBGA 13 x 15 x 1.40 MM BB165D
51-85180-**
NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation. ZBT is a trademark of Integrated Device
Technologies. All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-05557 Rev. **
Page 30 of 31
© Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C1371DV25
CY7C1373DV25
PRELIMINARY
Document History Page
Document Title: CY7C1371DV25/CY7C1373DV25 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBL™ Archi-
tecture (Preliminary)
Document Number: 38-05557
Orig. of
REV.
ECN NO. Issue Date Change
Description of Change
**
254513
See ECN
RKF
New Data Sheet
Document #: 38-05557 Rev. **
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