CY7C1371DV25-100BGI [CYPRESS]
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBL⑩ Architecture; 18兆位（ 512K ×36 / 1M ×18 ）流通型SRAM与NoBL⑩架构
| 型号： | CY7C1371DV25-100BGI |
| 厂家： | 
CYPRESS |
| 描述： | 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBL⑩ Architecture |
| 文件： | 总28页 (文件大小：445K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C1371DV25
CY7C1373DV25
18-Mbit (512K x 36/1M x 18)
Flow-Through SRAM with NoBL™ Architecture
Functional Description[1]
Features
• No Bus Latency™ (NoBL™) architecture eliminates
The CY7C1371DV25/CY7C1373DV25 is a 2.5V, 512K x
36/1M x 18 Synchronous Flow-through Burst SRAM designed
specifically to support unlimited true back-to-back Read/Write
operations without the insertion of wait states. The
CY7C1371DV25/CY7C1373DV25 is equipped with the
advanced No Bus Latency (NoBL) logic required to enable
consecutive Read/Write operations with data being trans-
ferred on every clock cycle. This feature dramatically improves
the throughput of data through the SRAM, especially in
systems that require frequent Write-Read transitions.
dead cycles between write and read cycles
• Can support up to 133-MHz bus operations with zero
wait states
— Data is transferred on every clock
• Pin compatible and functionally equivalent to ZBT™
devices
• Internally self-timed output buffer control to eliminate
the need to use OE
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. The clock input is qualified by
the Clock Enable (CEN) signal, which when deasserted
suspends operation and extends the previous clock cycle.
Maximum access delay from the clock rise is 6.5 ns (133-MHz
device).
• Registered inputs for flow-through operation
• Byte Write capability
• 2.5V core power supply (VDD
)
• 2.5V I/O power supply (VDDQ
• Fast clock-to-output times
)
Write operations are controlled by the two or four Byte Write
Select (BWX) and a Write Enable (WE) input. All writes are
conducted with on-chip synchronous self-timed write circuitry.
— 6.5 ns (for 133-MHz device)
• Clock Enable (CEN) pin to enable clock and suspend
operation
Three synchronous Chip Enables (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output tri-state control. In order to avoid bus
contention, the output drivers are synchronously tri-stated
during the data portion of a write sequence.
• Synchronous self-timed writes
• Asynchronous Output Enable
• Available in JEDEC-standard lead-free 100-Pin TQFP,
lead-free and non-lead-free 119-Ball BGA and 165- Ball
FBGA package.
• Three chip enables for simple depth expansion
• Automatic Power-down feature available using ZZ
mode or CE deselect
• IEEE 1149.1 JTAG-Compatible Boundary Scan
• Burst Capability—linear or interleaved burst order
• Low standby power
Selection Guide
133 MHz
6.5
100 MHz
8.5
Unit
ns
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
210
175
mA
mA
70
70
Notes:
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
Cypress Semiconductor Corporation
Document #: 38-05557 Rev. *D
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised June 29, 2006
CY7C1371DV25
CY7C1373DV25
1
Logic Block Diagram – CY7C1371DV25 (512K x 36)
ADDRESS
A0, A1, A
A1
A0
A1'
A0'
REGISTER
D1
D0
Q1
Q0
MODE
C
BURST
LOGIC
CE
ADV/LD
C
CLK
CEN
WRITE ADDRESS
REGISTER
O
U
T
P
U
T
D
A
T
S
E
N
S
ADV/LD
A
B
U
F
MEMORY
ARRAY
BWA
BWB
BWC
BWD
WRITE
DRIVERS
E
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
S
T
E
E
R
I
DQs
DQP
DQP
DQP
DQP
A
B
C
D
A
M
P
F
E
R
S
S
WE
E
N
G
INPUT
REGISTER
E
OE
READ LOGIC
CE1
CE2
CE3
SLEEP
CONTROL
ZZ
2
Logic Block Diagram – CY7C1373DV25 (1M x 18)
ADDRESS
A0, A1, A
A1
A1'
A0'
REGISTER
D1
A0
Q1
Q0
D0
MODE
BURST
LOGIC
CE
ADV/LD
C
CLK
CEN
C
WRITE ADDRESS
REGISTER
O
U
T
P
U
T
D
A
T
S
E
N
S
ADV/LD
A
B
U
F
MEMORY
ARRAY
BW
A
B
WRITE
DRIVERS
E
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
S
T
E
E
R
I
DQs
DQP
DQP
BW
A
B
A
M
P
F
E
R
S
S
WE
E
N
G
INPUT
REGISTER
E
OE
READ LOGIC
CE1
CE2
CE3
SLEEP
ZZ
CONTROL
Document #: 38-05557 Rev. *D
Page 2 of 28
CY7C1371DV25
CY7C1373DV25
Pin Configurations
Pinout
100-pin TQFP
DQPC
DQC
DQC
VDDQ
VSS
80
1
DQPB
DQB
DQB
VDDQ
VSS
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
2
3
4
5
DQC
6
DQB
DQB
DQB
DQB
VSS
BYTE C
BYTE B
DQC
DQC
DQC
VSS
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
VDDQ
DQC
DQC
NC
VDDQ
DQB
DQB
VSS
CY7C1371DV25
VDD
NC
NC
VDD
ZZ
VSS
DQD
DQD
VDDQ
VSS
DQA
DQA
VDDQ
VSS
DQD
DQA
DQA
DQA
DQA
VSS
DQD
BYTE D
BYTE A
DQD
DQD
VSS
VDDQ
DQD
DQD
DQPD
VDDQ
DQA
DQA
DQPA
Document #: 38-05557 Rev. *D
Page 3 of 28
CY7C1371DV25
CY7C1373DV25
Pin Configurations (continued)
100-Pin TQFP Pinout
NC
1
80
A
NC
2
NC
3
VDDQ
4
VSS
5
NC
6
NC
7
DQB
8
DQB
9
VSS
10
VDDQ
11
DQB
12
DQB
13
NC
14
VDD
15
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
NC
VDDQ
VSS
NC
DQPA
DQA
DQA
VSS
VDDQ
DQA
DQA
VSS
NC
CY7C1373DV25
BYTE A
BYTE B
NC
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
VDD
ZZ
VSS
DQB
DQB
VDDQ
VSS
DQA
DQA
VDDQ
VSS
DQA
DQA
NC
DQB
DQB
DQPB
NC
NC
VSS
VSS
VDDQ
NC
VDDQ
NC
NC
NC
NC
NC
Document #: 38-05557 Rev. *D
Page 4 of 28
CY7C1371DV25
CY7C1373DV25
Pin Configurations (continued)
119-Ball BGA
Pinout
CY7C1371DV25 (512K x 36)
1
2
3
4
5
6
7
A
A
VDDQ
A
A
A
A
VDDQ
B
C
NC/576M
NC/1G
CE2
A
A
A
ADV/LD
VDD
A
A
CE3
A
NC
NC
D
E
F
DQC
DQC
VDDQ
DQPC
DQC
VSS
VSS
VSS
NC
VSS
VSS
VSS
DQPB
DQB
DQB
DQB
CE1
DQC
DQB
VDDQ
OE
A
G
H
J
DQC
DQC
VDDQ
DQD
DQC
DQC
VDD
DQB
DQB
VDD
DQA
DQB
DQB
VDDQ
DQA
BWC
VSS
NC
BWB
VSS
NC
WE
VDD
K
DQD
VSS
CLK
NC
VSS
L
M
N
DQD
VDDQ
DQD
DQD
DQD
DQD
DQA
DQA
DQA
DQA
VDDQ
DQA
BWD
VSS
VSS
BWA
VSS
VSS
CEN
A1
DQD
DQPD
A
VSS
A0
VSS
NC
DQPA
A
DQA
P
R
NC/144M
MODE
VDD
NC/288M
T
NC
NC/72M
TMS
A
A
A
NC/36M
NC
ZZ
VDDQ
TDI
TCK
TDO
VDDQ
U
CY7C1373DV25 (1M x 18)
2
A
1
VDDQ
NC/576M
NC/1G
DQB
3
A
4
5
A
6
7
A
A
VDDQ
NC
A
B
C
D
E
F
CE2
A
A
A
ADV/LD
VDD
CE3
A
A
A
NC
NC
DQB
NC
VSS
VSS
VSS
NC
VSS
VSS
VSS
DQPA
NC
NC
NC
DQA
VDDQ
CE1
VDDQ
DQA
OE
A
NC
DQB
NC
VDD
NC
VSS
NC
NC
DQA
VDD
DQA
NC
VDDQ
G
H
J
BWB
VSS
NC
DQB
VDDQ
WE
VDD
K
NC
DQB
VSS
CLK
NC
VSS
NC
DQA
L
M
N
P
DQB
VDDQ
DQB
NC
NC
DQB
NC
NC
VSS
VSS
VSS
DQA
NC
NC
VDDQ
NC
BWA
VSS
CEN
A1
VSS
VSS
DQA
NC
DQPB
A0
DQA
R
T
NC/144M
NC/72M
VDDQ
A
A
MODE
A
VDD
NC/36M
TCK
NC
A
A
A
NC/288M
ZZ
TMS
TDI
TDO
NC
VDDQ
U
Document #: 38-05557 Rev. *D
Page 5 of 28
CY7C1371DV25
CY7C1373DV25
Pin Configurations (continued)
165-Ball FBGA Pinout
CY7C1371DV25 (512K x 36)
1
2
A
3
CE1
4
BWC
5
BWB
6
CE3
7
8
9
A
10
A
11
NC
NC/576M
NC/1G
DQPC
DQC
CEN
WE
VSS
VSS
ADV/LD
A
B
C
D
A
CE2
VDDQ
VDDQ
BWD
VSS
BWA
VSS
VSS
CLK
VSS
VSS
OE
VSS
VDD
A
A
NC
NC
DQC
VDDQ
VDDQ
NC
DQPB
DQB
VDD
DQB
DQC
DQC
DQC
DQC
NC
VDDQ
VDDQ
VDDQ
NC
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
NC
DQB
DQB
DQB
NC
DQB
E
F
DQC
DQC
NC
VSS
VSS
VSS
VSS
VSS
VSS
DQB
DQB
ZZ
G
H
J
DQD
DQD
DQD
DQD
DQD
DQD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
DQA
DQA
DQA
DQA
DQA
DQA
K
L
DQD
DQD
NC
VDDQ
VDDQ
A
VDD
VSS
A
VSS
NC
VSS
NC
A1
VSS
NC
VDD
VSS
A
VDDQ
VDDQ
A
DQA
NC
A
DQA
DQPA
M
N
P
DQPD
NC/144M NC/72M
TDI
TDO
NC/288M
A0
MODE
NC/36M
A
A
TMS
TCK
A
A
A
A
R
CY7C1373DV25 (1M x 18)
1
NC/576M
NC/1G
NC
2
A
3
CE1
4
BWB
5
NC
6
CE3
7
8
9
A
10
A
11
A
CEN
WE
VSS
VSS
ADV/LD
A
B
C
D
A
CE2
VDDQ
VDDQ
NC
VSS
VDD
BWA
VSS
VSS
CLK
VSS
VSS
OE
VSS
VDD
A
A
NC
NC
DQB
VDDQ
VDDQ
NC
NC
DQPA
DQA
NC
NC
DQB
DQB
DQB
NC
VDDQ
VDDQ
VDDQ
NC
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
NC
NC
NC
DQA
E
F
NC
NC
VSS
VSS
VSS
VSS
VSS
VSS
DQA
DQA
ZZ
NC
G
H
J
NC
NC
DQB
DQB
DQB
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
DQA
DQA
DQA
NC
NC
NC
K
L
NC
NC
DQB
NC
NC
VDDQ
VDDQ
A
VDD
VSS
A
VSS
NC
VSS
NC
A1
VSS
NC
VDD
VSS
A
VDDQ
VDDQ
A
DQA
NC
A
NC
NC
M
N
P
DQPB
NC/144M NC/72M
MODE NC/36M
TDI
TDO
NC/288M
A0
A
A
TMS
TCK
A
A
A
A
R
Document #: 38-05557 Rev. *D
Page 6 of 28
CY7C1371DV25
CY7C1373DV25
Pin Definitions
Name
I/O
Description
A0, A1, A
Input-
Synchronous
Address Inputs used to select one of the address locations. Sampled at the
rising edge of the CLK. A[1:0] are fed to the two-bit burst counter.
Input-
Synchronous
Byte Write Inputs, active LOW. Qualified with WE to conduct writes to the SRAM.
Sampled on the rising edge of CLK.
BWA, BWB
BWC, BWD
WE
Input-
Synchronous
Write Enable Input, active LOW. Sampled on the rising edge of CLK if CEN is
active LOW. This signal must be asserted LOW to initiate a write sequence.
Input-
Synchronous
Advance/Load Input. Used to advance the on-chip address counter or load a new
address. When HIGH (and CEN is asserted LOW) the internal burst counter is
advanced. When LOW, a new address can be loaded into the device for an access.
After being deselected, ADV/LD should be driven LOW in order to load a new
address.
ADV/LD
CLK
Input-
Clock
Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified
with CEN. CLK is only recognized if CEN is active LOW.
Input-
Synchronous
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in
conjunction with CE2, and CE3 to select/deselect the device.
CE1
CE2
Input-
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in
Synchronous
conjunction with CE1 and CE3 to select/deselect the device.
Input-
Synchronous
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in
conjunction with CE1 and CE2 to select/deselect the device.
CE3
OE
Input-
Asynchronous
Output Enable, asynchronous input, active LOW. Combined with the
synchronous logic block inside the device to control the direction of the I/O pins.
When LOW, the I/O pins are allowed to behave as outputs. When deasserted HIGH,
I/O pins are tri-stated, and act as input data pins. OE is masked during the data
portion of a write sequence, during the first clock when emerging from a deselected
state, when the device has been deselected.
Input-
Synchronous
Clock Enable Input, active LOW. When asserted LOW the Clock signal is recog-
nized by the SRAM. When deasserted HIGH the Clock signal is masked. Since
deasserting CEN does not deselect the device, CEN can be used to extend the
previous cycle when required.
CEN
ZZ
Input-
Asynchronous
ZZ “Sleep” Input. This active HIGH input places the device in a non-time critical
“sleep” condition with data integrity preserved. For normal operation, this pin has to
be LOW or left floating. ZZ pin has an internal pull-down.
I/O-
Synchronous
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that
is triggered by the rising edge of CLK. As outputs, they deliver the data contained
in the memory location specified by the addresses presented during the previous
clock rise of the read cycle. The direction of the pins is controlled by OE. When OE
is asserted LOW, the pins behave as outputs. When HIGH, DQs and DQP[A:D] are
placed in a tri-state condition.The outputs are automatically tri-stated during the data
portion of a write sequence, during the first clock when emerging from a deselected
state, and when the device is deselected, regardless of the state of OE.
DQs
I/O-
Synchronous
Bidirectional Data Parity I/O Lines. Functionally, these signals are identical to
DQs.
DQPX
MODE
Input Strap Pin
Mode Input. Selects the burst order of the device.
When tied to Gnd selects linear burst sequence. When tied to VDD or left floating
selects interleaved burst sequence.
VDD
Power Supply
I/O Power Supply
Ground
Power supply inputs to the core of the device.
Power supply for the I/O circuitry.
Ground for the device.
VDDQ
VSS
TDO
JTAG serial output
Synchronous
Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If
the JTAG feature is not being utilized, this pin should be left unconnected. This pin
is not available on TQFP packages.
Document #: 38-05557 Rev. *D
Page 7 of 28
CY7C1371DV25
CY7C1373DV25
Pin Definitions (continued)
Name
I/O
Description
TDI
JTAG serial input
Synchronous
Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG
feature is not being utilized, this pin can be left floating or connected to VDD through
a pull-up resistor. This pin is not available on TQFP packages.
TMS
JTAG serial input
Synchronous
Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG
feature is not being utilized, this pin can be disconnected or connected to VDD. This
pin is not available on TQFP packages.
TCK
NC
JTAG-
Clock
Clock input to the JTAG circuitry. If the JTAG feature is not being utilized, this pin
must be connected to VSS. This pin is not available on TQFP packages.
–
No Connects. Not internally connected to the die. 36 Mbit, 72 Mbit, 144 Mbit,
288 Mbit, 576 Mbit and 1 Gbit are address expansion pins and are not internally
connected to the die.
Document #: 38-05557 Rev. *D
Page 8 of 28
CY7C1371DV25
CY7C1373DV25
Single Write Accesses
Functional Overview
Write access are initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,
and CE3 are ALL asserted active, and (3) the write signal WE
is asserted LOW. The address presented to the address bus
is loaded into the Address Register. The write signals are
latched into the Control Logic block. The data lines are
automatically tri-stated regardless of the state of the OE input
signal. This allows the external logic to present the data on
DQs and DQPX.
The CY7C1371DV25/CY7C1373DV25 is a synchronous
flow-through burst SRAM designed specifically to eliminate
wait states during Write-Read transitions. All synchronous
inputs pass through input registers controlled by the rising
edge of the clock. The clock signal is qualified with the Clock
Enable input signal (CEN). If CEN is HIGH, the clock signal is
not recognized and all internal states are maintained. All
synchronous operations are qualified with CEN. Maximum
access delay from the clock rise (tCDV) is 6.5 ns (133-MHz
device).
On the next clock rise the data presented to DQs and DQPX
(or a subset for byte write operations, see truth table for
details) inputs is latched into the device and the write is
complete. Additional accesses (Read/Write/Deselect) can be
initiated on this cycle.
Accesses can be initiated by asserting all three Chip Enables
(CE1, CE2, CE3) active at the rising edge of the clock. If Clock
Enable (CEN) is active LOW and ADV/LD is asserted LOW,
the address presented to the device will be latched. The
access can either be a read or write operation, depending on
the status of the Write Enable (WE). BWX can be used to
conduct byte write operations.
The data written during the Write operation is controlled by
BWX signals. The CY7C1371DV25/CY7C1373DV25 provides
byte write capability that is described in the truth table.
Asserting the Write Enable input (WE) with the selected Byte
Write Select input will selectively write to only the desired
bytes. Bytes not selected during a byte write operation will
remain unaltered. A synchronous self-timed write mechanism
has been provided to simplify the write operations. Byte write
capability has been included in order to greatly simplify
Read/Modify/Write sequences, which can be reduced to
simple byte write operations.
Write operations are qualified by the Write Enable (WE). All
writes are simplified with on-chip synchronous self-timed write
circuitry.
Three synchronous Chip Enables (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) simplify depth expansion.
All operations (Reads, Writes, and Deselects) are pipelined.
ADV/LD should be driven LOW once the device has been
deselected in order to load a new address for the next
operation.
Because the CY7C1371DV25/CY7C1373DV25 is a common
I/O device, data should not be driven into the device while the
outputs are active. The Output Enable (OE) can be deasserted
HIGH before presenting data to the DQs and DQPX inputs.
Doing so will tri-state the output drivers. As a safety
precaution, DQs and DQPX are automatically tri-stated during
the data portion of a write cycle, regardless of the state of OE.
Single Read Accesses
A read access is initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,
and CE3 are ALL asserted active, (3) the Write Enable input
signal WE is deasserted HIGH, and (4) ADV/LD is asserted
LOW. The address presented to the address inputs is latched
into the Address Register and presented to the memory array
and control logic. The control logic determines that a read
access is in progress and allows the requested data to
propagate to the output buffers. The data is available within 6.5
ns (133-MHz device) provided OE is active LOW. After the first
clock of the read access, the output buffers are controlled by
OE and the internal control logic. OE must be driven LOW in
order for the device to drive out the requested data. On the
subsequent clock, another operation (Read/Write/Deselect)
can be initiated. When the SRAM is deselected at clock rise
by one of the chip enable signals, its output will be tri-stated
immediately.
Burst Write Accesses
The CY7C1371DV25/CY7C1373DV25 has an on-chip burst
counter that allows the user the ability to supply a single
address and conduct up to four Write operations without
reasserting the address inputs. ADV/LD must be driven LOW
in order to load the initial address, as described in the Single
Write Access section above. When ADV/LD is driven HIGH on
the subsequent clock rise, the Chip Enables (CE1, CE2, and
CE3) and WE inputs are ignored and the burst counter is incre-
mented. The correct BWX inputs must be driven in each cycle
of the burst write, in order to write the correct bytes of data.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CE1, CE2, and CE3, must remain inactive
for the duration of tZZREC after the ZZ input returns LOW.
Burst Read Accesses
The CY7C1371DV25/CY7C1373DV25 has an on-chip burst
counter that allows the user the ability to supply a single
address and conduct up to four Reads without reasserting the
address inputs. ADV/LD must be driven LOW in order to load
a new address into the SRAM, as described in the Single Read
Access section above. The sequence of the burst counter is
determined by the MODE input signal. A LOW input on MODE
selects a linear burst mode, a HIGH selects an interleaved
burst sequence. Both burst counters use A0 and A1 in the
burst sequence, and will wrap around when incremented suffi-
ciently. A HIGH input on ADV/LD will increment the internal
burst counter regardless of the state of chip enable inputs or
WE. WE is latched at the beginning of a burst cycle. Therefore,
the type of access (Read or Write) is maintained throughout
the burst sequence.
Document #: 38-05557 Rev. *D
Page 9 of 28
CY7C1371DV25
CY7C1373DV25
Interleaved Burst Address Table
(MODE = Floating or VDD
Linear Burst Address Table
(MODE = GND)
)
First
Address
A1: A0
Second
Address
A1: A0
Third
Address
A1: A0
Fourth
Address
A1: A0
First
Address
A1: A0
Second
Address
A1: A0
Third
Address
A1: A0
Fourth
Address
A1: A0
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
ZZ Mode Electrical Characteristics
Parameter
IDDZZ
Description
Sleep mode standby current
Device operation to ZZ
ZZ recovery time
Test Conditions
ZZ > VDD – 0.2V
Min.
Max.
Unit
mA
ns
80
tZZS
ZZ > VDD – 0.2V
2tCYC
tZZREC
tZZI
ZZ < 0.2V
2tCYC
0
ns
ZZ active to sleep current
This parameter is sampled
This parameter is sampled
2tCYC
ns
tRZZI
ZZ Inactive to exit sleep current
ns
Truth Table[2, 3, 4, 5, 6, 7, 8]
Address
Operation
Deselect Cycle
Used CE1 CE2
ZZ ADV/LD WE BWX OE CEN CLK
DQ
CE3
X
H
X
X
L
None
None
H
X
X
X
L
X
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
L
X
X
X
X
H
X
H
X
L
X
X
X
X
X
X
X
X
L
X
X
X
X
L
L
L
L
L
L
L
L
L
L
L
L
L
H
X
L->H
L->H
L->H
L->H
Tri-State
Tri-State
Tri-State
Tri-State
Deselect Cycle
Deselect Cycle
None
L
Continue Deselect Cycle
Read Cycle (Begin Burst)
Read Cycle (Continue Burst)
NOP/Dummy Read (Begin Burst)
Dummy Read (Continue Burst)
Write Cycle (Begin Burst)
Write Cycle (Continue Burst)
NOP/Write Abort (Begin Burst)
Write Abort (Continue Burst)
Ignore Clock Edge (Stall)
Sleep Mode
None
X
H
X
H
X
H
X
H
X
X
X
H
L
External
Next
L->H Data Out (Q)
L->H Data Out (Q)
X
L
X
L
H
L
L
External
Next
H
H
X
X
X
X
X
X
L->H
L->H
Tri-State
Tri-State
X
L
X
L
H
L
External
Next
L->H Data In (D)
L->H Data In (D)
X
L
X
L
H
L
X
L
L
None
H
H
X
X
L->H
L->H
L->H
X
Tri-State
Tri-State
-
Next
X
X
X
X
X
X
H
X
X
X
X
X
Current
None
Tri-State
Notes:
2. X = “Don't Care.” H = Logic HIGH, L = Logic LOW. BW = 0 signifies at least one Byte Write Select is active, BW = Valid signifies that the desired byte write
X
X
selects are asserted, see truth table for details.
3. Write is defined by BW , and WE. See truth table for Read/Write.
X
4. When a write cycle is detected, all I/Os are tri-stated, even during byte writes.
5. The DQs and DQP pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
X
6. CEN = H, inserts wait states.
7. Device will power-up deselected and the I/Os in a tri-state condition, regardless of OE.
8. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQs and DQP = Tri-state when OE
X
is inactive or when the device is deselected, and DQs and DQP = data when OE is active.
X
Document #: 38-05557 Rev. *D
Page 10 of 28
CY7C1371DV25
CY7C1373DV25
Partial Truth Table for Read/Write[2, 3, 9]
Function (CY7C1371DV25)
Read
WE
H
L
BWA
X
BWB
X
BWC
X
BWD
X
Write No bytes written
H
H
H
H
Write Byte A – (DQA and DQPA)
Write Byte B – (DQB and DQPB)
Write Byte C – (DQC and DQPC)
Write Byte D – (DQD and DQPD)
Write All Bytes
L
L
H
H
H
L
H
L
H
H
L
H
H
L
H
L
H
H
H
L
L
L
L
L
L
Partial Truth Table for Read/Write[2, 3, 9]
Function (CY7C1373DV25)
Read
WE
BWA
X
BWB
H
L
L
L
L
X
H
H
L
Write - No bytes written
H
Write Byte A – (DQA and DQPA)
Write Byte B – (DQB and DQPB)
Write All Bytes
L
H
L
L
Note:
9. Table only lists a partial listing of the byte write combinations. Any Combination of BW is valid. Appropriate write will be done based on which byte write is active.
X
Document #: 38-05557 Rev. *D
Page 11 of 28
CY7C1371DV25
CY7C1373DV25
Test Data-In (TDI)
IEEE 1149.1 Serial Boundary Scan (JTAG)
The TDI ball is used to serially input information into the
registers and can be connected to the input of any of the
registers. The register between TDI and TDO is chosen by the
instruction that is loaded into the TAP instruction register. For
information on loading the instruction register, see figure. TDI
is internally pulled up and can be unconnected if the TAP is
unused in an application. TDI is connected to the most signif-
icant bit (MSB) of any register. (See Tap Controller Block
Diagram.)
The CY7C1371DV25/CY7C1373DV25 incorporates a serial
boundary scan test access port (TAP).This part is fully
compliant with 1149.1. The TAP operates using
JEDEC-standard 3.3V or 2.5V I/O logic levels.
The CY7C1371DV25/CY7C1373DV25 contains
a
TAP
controller, instruction register, boundary scan register, bypass
register, and ID register.
Disabling the JTAG Feature
Test Data-Out (TDO)
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(VSS) to prevent clocking of the device. TDI and TMS are inter-
nally pulled up and may be unconnected. They may alternately
be connected to VDD through a pull-up resistor. TDO should be
left unconnected. Upon power-up, the device will come up in
a reset state which will not interfere with the operation of the
device.
The TDO output ball is used to serially clock data-out from the
registers. The output is active depending upon the current
state of the TAP state machine. The output changes on the
falling edge of TCK. TDO is connected to the least significant
bit (LSB) of any register. (See Tap Controller State Diagram.)
TAP Controller Block Diagram
TAP Controller State Diagram
0
Bypass Register
TEST-LOGIC
1
RESET
0
2
1
0
0
0
Selection
Circuitry
1
1
1
Instruction Register
31 30 29
Identification Register
RUN-TEST/
IDLE
SELECT
DR-SCAN
SELECT
IR-SCAN
S
election
0
TDI
TDO
Circuitr
y
.
.
. 2 1
0
0
1
1
CAPTURE-DR
CAPTURE-IR
0
0
x
.
.
.
.
. 2 1
SHIFT-DR
0
SHIFT-IR
0
Boundary Scan Register
1
1
1
1
EXIT1-DR
EXIT1-IR
TCK
TMS
0
0
TAP CONTROLLER
PAUSE-DR
0
PAUSE-IR
0
1
1
0
0
EXIT2-DR
1
EXIT2-IR
1
Performing a TAP Reset
A RESET is performed by forcing TMS HIGH (VDD) for five
rising edges of TCK. This RESET does not affect the operation
of the SRAM and may be performed while the SRAM is
operating.
UPDATE-DR
UPDATE-IR
1
0
1
0
At power-up, the TAP is reset internally to ensure that TDO
comes up in a High-Z state.
The 0/1 next to each state represents the value of TMS at the
rising edge of TCK.
TAP Registers
Registers are connected between the TDI and TDO balls and
allow data to be scanned into and out of the SRAM test
circuitry. Only one register can be selected at a time through
the instruction register. Data is serially loaded into the TDI ball
on the rising edge of TCK. Data is output on the TDO ball on
the falling edge of TCK.
Test Access Port (TAP)
Test Clock (TCK)
The test clock is used only with the TAP controller. All inputs
are captured on the rising edge of TCK. All outputs are driven
from the falling edge of TCK.
Instruction Register
Test Mode Select (TMS)
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the
TDI and TDO balls as shown in the Tap Controller Block
Diagram. Upon power-up, the instruction register is loaded
with the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as
described in the previous section.
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. It is allowable to
leave this ball unconnected if the TAP is not used. The ball is
pulled up internally, resulting in a logic HIGH level.
Document #: 38-05557 Rev. *D
Page 12 of 28
CY7C1371DV25
CY7C1373DV25
When the TAP controller is in the Capture-IR state, the two
least significant bits are loaded with a binary “01” pattern to
allow for fault isolation of the board-level serial test data path.
the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state.
The IDCODE instruction is loaded into the instruction register
upon power-up or whenever the TAP controller is given a test
logic reset state.
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between the
TDI and TDO balls. This allows data to be shifted through the
SRAM with minimal delay. The bypass register is set LOW
(VSS) when the BYPASS instruction is executed.
SAMPLE Z
The SAMPLE Z instruction causes the boundary scan register
to be connected between the TDI and TDO balls when the TAP
controller is in a Shift-DR state. It also places all SRAM outputs
into a High-Z state.
Boundary Scan Register
SAMPLE/PRELOAD
The boundary scan register is connected to all the input and
bidirectional balls on the SRAM.
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When
the SAMPLE/PRELOAD instructions are loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and output pins is
captured in the boundary scan register.
The boundary scan register is loaded with the contents of the
RAM I/O ring when the TAP controller is in the Capture-DR
state and is then placed between the TDI and TDO balls when
the controller is moved to the Shift-DR state. The EXTEST,
SAMPLE/PRELOAD and SAMPLE Z instructions can be used
to capture the contents of the I/O ring.
The user must be aware that the TAP controller clock can only
operate at a frequency up to 20 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because
there is a large difference in the clock frequencies, it is
possible that during the Capture-DR state, an input or output
will undergo a transition. The TAP may then try to capture a
signal while in transition (metastable state). This will not harm
the device, but there is no guarantee as to the value that will
be captured. Repeatable results may not be possible.
The Boundary Scan Order tables show the order in which the
bits are connected. Each bit corresponds to one of the bumps
on the SRAM package. The MSB of the register is connected
to TDI and the LSB is connected to TDO.
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired
into the SRAM and can be shifted out when the TAP controller
is in the Shift-DR state. The ID register has a vendor code and
other information described in the Identification Register
Definitions table.
To guarantee that the boundary scan register will capture the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller's capture set-up plus
hold times (tCS and tCH). The SRAM clock input might not be
captured correctly if there is no way in a design to stop (or
slow) the clock during a SAMPLE/PRELOAD instruction. If this
is an issue, it is still possible to capture all other signals and
simply ignore the value of the CK and CK captured in the
boundary scan register.
TAP Instruction Set
Overview
Once the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the
boundary scan register between the TDI and TDO pins.
Eight different instructions are possible with the three bit
instruction register. All combinations are listed in the
Instruction Codes table. Three of these instructions are listed
as RESERVED and should not be used. The other five instruc-
tions are described in detail below.
PRELOAD allows an initial data pattern to be placed at the
latched parallel outputs of the boundary scan register cells
prior to the selection of another boundary scan test operation.
Instructions are loaded into the TAP controller during the
Shift-IR state when the instruction register is placed between
TDI and TDO. During this state, instructions are shifted
through the instruction register through the TDI and TDO balls.
To execute the instruction once it is shifted in, the TAP
controller needs to be moved into the Update-IR state.
The shifting of data for the SAMPLE and PRELOAD phases
can occur concurrently when required—that is, while data
captured is shifted out, the preloaded data can be shifted in.
BYPASS
When the BYPASS instruction is loaded in the instruction
register and the TAP is placed in a Shift-DR state, the bypass
register is placed between the TDI and TDO balls. The
advantage of the BYPASS instruction is that it shortens the
boundary scan path when multiple devices are connected
together on a board.
EXTEST
The EXTEST instruction enables the preloaded data to be
driven out through the system output pins. This instruction also
selects the boundary scan register to be connected for serial
access between the TDI and TDO in the shift-DR controller
state.
EXTEST Output Bus Tri-State
IEEE Standard 1149.1 mandates that the TAP controller be
able to put the output bus into a tri-state mode.
IDCODE
The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the instruction register. It also places the
instruction register between the TDI and TDO balls and allows
The boundary scan register has a special bit located at bit #85
(for 119-BGA package) or bit #89 (for 165-fBGA package).
When this scan cell, called the “extest output bus tri-state,” is
latched into the preload register during the “Update-DR” state
Document #: 38-05557 Rev. *D
Page 13 of 28
CY7C1371DV25
CY7C1373DV25
in the TAP controller, it will directly control the state of the
output (Q-bus) pins, when the EXTEST is entered as the
current instruction. When HIGH, it will enable the output
buffers to drive the output bus. When LOW, this bit will place
the output bus into a High-Z condition.
register. When the EXTEST instruction is entered, this bit will
directly control the output Q-bus pins. Note that this bit is
preset HIGH to enable the output when the device is
powered-up, and also when the TAP controller is in the
“Test-Logic-Reset” state.
This bit can be set by entering the SAMPLE/PRELOAD or
EXTEST command, and then shifting the desired bit into that
cell, during the “Shift-DR” state. During “Update-DR,” the value
loaded into that shift-register cell will latch into the preload
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
TAP Timing
1
2
3
4
5
6
Test Clock
(TCK)
t
t
t
CYC
TH
TL
t
t
t
t
TMSS
TDIS
TMSH
Test Mode Select
(TMS)
TDIH
Test Data-In
(TDI)
t
TDOV
t
TDOX
Test Data-Out
(TDO)
DON’T CARE
UNDEFINED
TAP AC Switching Characteristics Over the Operating Range[10, 11]
Parameter
Clock
tTCYC
tTF
Description
Min.
Max.
Unit
TCK Clock Cycle Time
TCK Clock Frequency
TCK Clock HIGH time
TCK Clock LOW time
50
ns
MHz
ns
20
tTH
20
20
tTL
ns
Output Times
tTDOV TCK Clock LOW to TDO Valid
tTDOX TCK Clock LOW to TDO Invalid
Set-up Times
tTMSS TMS Set-up to TCK Clock Rise
tTDIS
10
ns
ns
0
5
5
5
ns
ns
TDI Set-up to TCK Clock Rise
Capture Set-up to TCK Rise
tCS
Hold Times
tTMSH
tTDIH
TMS hold after TCK Clock Rise
TDI Hold after Clock Rise
5
5
5
ns
ns
ns
tCH
Capture Hold after Clock Rise
Notes:
10. t and t refer to the set-up and hold time requirements of latching data from the boundary scan register.
CS
CH
11. Test conditions are specified using the load in TAP AC test Conditions. t /t = 1 ns.
R
F
Document #: 38-05557 Rev. *D
Page 14 of 28
CY7C1371DV25
CY7C1373DV25
2.5V TAP AC Test Conditions
2.5V TAP AC Output Load Equivalent
1.25V
Input pulse levels ............................................... .VSS to 2.5V
Input rise and fall time..................................................... 1 ns
Input timing reference levels.........................................1.25V
Output reference levels.................................................1.25V
Test load termination supply voltage.............................1.25V
50Ω
TDO
ZO= 50Ω
20pF
TAP DC Electrical Characteristics And Operating Conditions
(0°C < TA < +70°C; VDD = 2.5V ±0.125V unless otherwise noted)[12]
Parameter
VOH1
Description
Test Conditions
Min.
Max.
Unit
V
Output HIGH Voltage IOH = –1.0 mA, VDDQ = 2.5V
Output HIGH Voltage IOH = –100 µA, VDDQ = 2.5V
Output LOW Voltage IOL = 8.0 mA, VDDQ = 2.5V
2.0
2.1
VOH2
VOL1
VOL2
VIH
V
0.4
0.2
V
Output LOW Voltage IOL = 100 µA
Input HIGH Voltage
VDDQ = 2.5V
V
VDDQ = 2.5V
VDDQ = 2.5V
1.7
–0.3
–5
VDD + 0.3
0.7
V
VIL
Input LOW Voltage
V
IX
Input Load Current
GND < VIN < VDDQ
5
µA
Identification Register Definitions
CY7C1371DV25 CY7C1373DV25
Instruction Field
Revision Number (31:29)
Device Depth (28:24)[13]
(512Kx36)
(1Mx18)
Description
000
000
Describes the version number
Reserved for internal use
01011
01011
001001
010101
Device Width (23:18)
001001
100101
00000110100
1
Defines memory type and architecture
Defines width and density
Cypress Device ID (17:12)
Cypress JEDEC ID Code (11:1)
ID Register Presence Indicator (0)
00000110100 Allows unique identification of SRAM vendor
1
Indicates the presence of an ID register
Scan Register Sizes
Register Name
Bit Size (x36)
Bit Size (x18)
Instruction
Bypass
ID
3
3
1
1
32
85
89
32
85
89
Boundary Scan Order (119-ball BGA package)
Boundary Scan Order (165-ball FBGA package)
Notes:
12. All voltages referenced to V (GND).
SS
13. Bit #24 is “1” in the Register Definitions for both 2.5v and 3.3v versions of this device.
Document #: 38-05557 Rev. *D
Page 15 of 28
CY7C1371DV25
CY7C1373DV25
Identification Codes
Instruction
Code
Description
EXTEST
000
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM outputs to High-Z state.
IDCODE
001
010
Loads the ID register with the vendor ID code and places the register between TDI and
TDO. This operation does not affect SRAM operations.
SAMPLE Z
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM output drivers to a High-Z state.
RESERVED
011
100
Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Does not affect SRAM operation.
RESERVED
RESERVED
BYPASS
101
110
111
Do Not Use: This instruction is reserved for future use.
Do Not Use: This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does not affect SRAM
operations.
119-Ball BGA Boundary Scan Order [14, 15]
Bit #
1
Ball ID
Bit #
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
Ball ID
F6
Bit #
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
Ball ID
G4
A4
G3
C3
B2
B3
A3
C2
A2
B1
C1
D2
E1
F2
Bit #
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
Ball ID
L1
H4
T4
T5
T6
R5
L5
2
E7
D7
H7
G6
E6
D6
C7
B7
C6
A6
C5
B5
G5
B6
D4
B4
F4
M2
N1
3
4
P1
5
K1
6
L2
7
R6
U6
R7
T7
P6
N7
M6
L7
N2
P2
8
9
R3
10
11
12
13
14
15
16
17
18
19
20
21
22
T1
R1
T2
L3
R2
K6
P7
N6
L6
G1
H2
D1
E2
G2
H1
J3
T3
L4
N4
P4
K7
J5
M4
A5
K4
E4
Internal
H6
G7
2K
Notes:
14. Balls which are NC (No Connect) are pre-set LOW.
15. Bit# 85 is pre-set HIGH.
Document #: 38-05557 Rev. *D
Page 16 of 28
CY7C1371DV25
CY7C1373DV25
165-Ball BGA Boundary Scan Order [14, 16]
Bit #
1
Ball ID
N6
Bit #
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
Ball ID
D10
C11
A11
B11
A10
B10
A9
Bit #
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
Ball ID
G1
D2
E2
2
N7
3
N10
P11
P8
4
F2
5
G2
H1
H3
J1
6
R8
7
R9
8
P9
B9
9
P10
R10
R11
H11
N11
M11
L11
K11
J11
M10
L10
K10
J10
H9
C10
A8
K1
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
L1
B8
M1
J2
A7
B7
K2
B6
L2
A6
M2
N1
N2
P1
B5
A5
A4
B4
R1
R2
P3
B3
A3
A2
R3
P2
H10
G11
F11
E11
D11
G10
F10
E10
B2
C2
R4
P4
B1
A1
N5
P6
C1
D1
R6
Internal
E1
F1
Note:
16. Bit# 89 is pre-set HIGH.
Document #: 38-05557 Rev. *D
Page 17 of 28
CY7C1371DV25
CY7C1373DV25
DC Input Voltage ................................... –0.5V to VDD + 0.5V
Current into Outputs (LOW)......................................... 20 mA
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Static Discharge Voltage........................................... >2001V
(per MIL-STD-883, Method 3015)
Storage Temperature .................................–65°C to +150°C
Latch-up Current..................................................... >200 mA
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Operating Range
Supply Voltage on VDD Relative to GND........ –0.5V to +3.6V
Supply Voltage on VDDQ Relative to GND ......–0.5V to +VDD
Ambient
VDD/VDDQ
Range
Commercial
Industrial
Temperature
0°C to +70°C
2.5V +_ 5%
DC Voltage Applied to Outputs
in Tri-State........................................... –0.5V to VDDQ + 0.5V
–40°C to +85°C
Electrical Characteristics Over the Operating Range[17, 18]
Parameter
VDD
Description
Test Conditions
Min.
2.375
2.375
2.0
Max.
2.625
VDD
Unit
V
Power Supply Voltage
I/O Supply Voltage
Output HIGH Voltage
Output LOW Voltage
VDDQ
VOH
for 2.5V I/O
V
for 2.5V I/O, IOH = −1.0 mA
V
VOL
for 2.5V I/O, IOL= 1.0 mA
0.4
V
VIH
Input HIGH Voltage[17] for 2.5V I/O
Input LOW Voltage[17] for 2.5V I/O
1.7
–0.3
–5
VDD + 0.3V
V
VIL
0.7
5
V
IX
Input Leakage Current GND ≤ VI ≤ VDDQ
except ZZ and MODE
µA
Input Current of MODE Input = VSS
Input = VDD
–30
–5
µA
µA
5
Input Current of ZZ
Input = VSS
Input = VDD
µA
30
5
µA
IOZ
IDD
Output Leakage Current GND ≤ VI ≤ VDD, Output Disabled
–5
µA
VDD Operating Supply VDD = Max., IOUT = 0 mA,
7.5-ns cycle, 133 MHz
10-ns cycle, 100 MHz
210
175
140
120
mA
mA
mA
mA
Current
f = fMAX = 1/tCYC
ISB1
ISB2
ISB3
ISB4
Automatic CE
Power-down
Current—TTL Inputs
VDD = Max, Device Deselected, 7.5-ns cycle, 133 MHz
VIN ≥ VIH or VIN ≤ VIL
f = fMAX, inputs switching
10-ns cycle, 100 MHz
Automatic CE
Power-down
Current—CMOS Inputs f = 0, inputs static
VDD = Max, Device Deselected, All speeds
VIN ≤ 0.3V or VIN > VDD – 0.3V,
70
mA
Automatic CE
Power-down
Current—CMOS Inputs f = fMAX, inputs switching
VDD = Max, Device Deselected, or 7.5-ns cycle, 133 MHz
VIN ≤ 0.3V or VIN > VDDQ – 0.3V
130
110
mA
mA
10-ns cycle, 100 MHz
Automatic CE
VDD = Max, Device Deselected, All Speeds
80
mA
Power-down
Current—TTL Inputs
VIN ≥ VDD – 0.3V or VIN ≤ 0.3V,
f = 0, inputs static
Notes:
17. Overshoot: V (AC) < V +1.5V (Pulse width less than t
/2), undershoot: V (AC) > –2V (Pulse width less than t
/2).
IH
DD
CYC
IL
CYC
18. T
: Assumes a linear ramp from 0V to V (min.) within 200 ms. During this time V < V and V
< V
.
Power-up
DD
IH
DD
DDQ
DD
Document #: 38-05557 Rev. *D
Page 18 of 28
CY7C1371DV25
CY7C1373DV25
Capacitance[19]
100 TQFP
Package
119 BGA
165 FBGA
Package
Parameter
Description
Test Conditions
Package
Unit
pF
CIN
Input Capacitance
TA = 25°C, f = 1 MHz,
DD = 2.5V
DDQ = 2.5V
5
5
5
8
8
8
9
9
9
V
V
CCLK
CI/O
Clock Input Capacitance
Input/Output Capacitance
pF
pF
Thermal Resistance[19]
100 TQFP 119 BGA 165 FBGA
Parameter
Description
Thermal Resistance
Test Conditions
Test conditions follow standard
Package
Package
Package
Unit
ΘJA
28.66
23.8
20.7
°C/W
(Junction to Ambient) test methods and procedures for
measuring thermal impedance,
ΘJC
Thermal Resistance
per EIA/JESD51.
4.08
6.2
4.0
°C/W
(Junction to Case)
AC Test Loads and Waveforms
2.5V I/O Test Load
R = 1667Ω
2.5V
OUTPUT
ALL INPUT PULSES
90%
VDDQ
OUTPUT
90%
10%
Z = 50Ω
0
10%
R = 50Ω
L
GND
5 pF
R = 1538Ω
≤ 1 ns
≤ 1 ns
V = 1.25V
T
INCLUDING
JIG AND
SCOPE
(c)
(a)
(b)
Note:
19. Tested initially and after any design or process change that may affect these parameters.
Document #: 38-05557 Rev. *D
Page 19 of 28
CY7C1371DV25
CY7C1373DV25
Switching Characteristics Over the Operating Range[24, 25]
133 MHz
100 MHz
Parameter
Description
Min.
Max.
Min.
Max.
Unit
[20]
tPOWER
1
1
ms
Clock
tCYC
Clock Cycle Time
7.5
2.1
2.1
10
2.5
2.5
ns
ns
ns
tCH
Clock HIGH
Clock LOW
tCL
Output Times
tCDV
Data Output Valid After CLK Rise
Data Output Hold After CLK Rise
Clock to Low-Z[21, 22, 23]
6.5
8.5
ns
ns
ns
ns
ns
ns
ns
tDOH
2.0
2.0
2.0
2.0
tCLZ
tCHZ
Clock to High-Z[21, 22, 23]
4.0
3.2
5.0
3.8
tOEV
OE LOW to Output Valid
tOELZ
tOEHZ
Set-up Times
tAS
OE LOW to Output Low-Z[21, 22, 23]
OE HIGH to Output High-Z[21, 22, 23]
0
0
4.0
5.0
Address Set-up Before CLK Rise
ADV/LD Set-up Before CLK Rise
WE, BWX Set-up Before CLK Rise
CEN Set-up Before CLK Rise
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
ns
ns
ns
ns
ns
ns
tALS
tWES
tCENS
tDS
Data Input Set-up Before CLK Rise
Chip Enable Set-Up Before CLK Rise
tCES
Hold Times
tAH
Address Hold After CLK Rise
ADV/LD Hold After CLK Rise
WE, BWX Hold After CLK Rise
CEN Hold After CLK Rise
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
ns
ns
tALH
tWEH
tCENH
tDH
Data Input Hold After CLK Rise
Chip Enable Hold After CLK Rise
tCEH
Notes:
20. This part has a voltage regulator internally; t
is the time that the power needs to be supplied above V (minimum) initially, before a read or write operation
DD
POWER
can be initiated.
21. t
, t
,t
, and t
are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
OEHZ
CHZ CLZ OELZ
22. At any given voltage and temperature, t
is less than t
and t
is less than t
to eliminate bus contention between SRAMs when sharing the same
OEHZ
OELZ
CHZ
CLZ
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions.
23. This parameter is sampled and not 100% tested.
24. Timing reference level is 1.25V when V
= 2.5V.
DDQ
25. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
Document #: 38-05557 Rev. *D
Page 20 of 28
CY7C1371DV25
CY7C1373DV25
Switching Waveforms
Read/Write Waveforms[26, 27, 28]
t
1
2
3
4
5
6
7
8
9
10
CYC
t
CLK
CEN
t
t
t
t
t
CENS
CES
CENH
CEH
CL
CH
CE
ADV/LD
WE
BW
X
A1
A2
A4
A3
A5
A6
A7
ADDRESS
DQ
t
CDV
t
t
AS
AH
t
t
t
t
CHZ
DOH
OEV
CLZ
D(A1)
t
D(A2)
D(A2+1)
Q(A3)
Q(A4)
Q(A4+1)
D(A5)
Q(A6)
D(A7)
t
OEHZ
t
DS
DH
t
DOH
t
OELZ
OE
COMMAND
WRITE
D(A1)
WRITE
D(A2)
BURST
WRITE
READ
Q(A3)
READ
Q(A4)
BURST
READ
WRITE
D(A5)
READ
Q(A6)
WRITE
D(A7)
DESELECT
D(A2+1)
Q(A4+1)
DON’T CARE
UNDEFINED
Notes:
For this waveform ZZ is tied LOW.
26.
27. When CE is LOW, CE is LOW, CE is HIGH and CE is LOW. When CE is HIGH, CE is HIGH or CE is LOW or CE is HIGH.
1
2
3
1
2
3
28. Order of the Burst sequence is determined by the status of the MODE (0 = Linear, 1 = Interleaved). Burst operations are optional.
Document #: 38-05557 Rev. *D
Page 21 of 28
CY7C1371DV25
CY7C1373DV25
Switching Waveforms (continued)
NOP, STALL AND DESELECT Cycles[26, 27, 29]
t
1
2
3
4
5
6
7
8
9
10
CYC
CLK
CEN
t
t
t
t
t
t
CENS
CES
CENH
CEH
CL
CH
CE
ADV/LD
WE
BW
X
A1
A2
A4
A3
A5
A6
A7
ADDRESS
DQ
t
CDV
t
t
AS
AH
t
t
t
t
CHZ
DOH
OEV
CLZ
D(A1)
t
D(A2)
D(A2+1)
Q(A3)
Q(A4)
Q(A4+1)
D(A5)
Q(A6)
D(A7)
t
OEHZ
t
DS
DH
t
DOH
t
OELZ
OE
COMMAND
WRITE
D(A1)
WRITE
D(A2)
BURST
WRITE
READ
Q(A3)
READ
Q(A4)
BURST
READ
WRITE
D(A5)
READ
Q(A6)
WRITE
D(A7)
DESELECT
D(A2+1)
Q(A4+1)
DON’T CARE
UNDEFINED
Note:
29. The Ignore Clock Edge or Stall cycle (Clock 3) illustrates CEN being used to create a pause. A write is not performed during this cycle.
Document #: 38-05557 Rev. *D
Page 22 of 28
CY7C1371DV25
CY7C1373DV25
Switching Waveforms (continued)
ZZ Mode Timing[30, 31]
CLK
t
t
ZZ
ZZREC
ZZ
t
ZZI
I
SUPPLY
I
DDZZ
t
RZZI
ALL INPUTS
(except ZZ)
DESELECT or READ Only
Outputs (Q)
High-Z
DON’T CARE
Notes:
30. Device must be deselected when entering ZZ mode. See truth table for all possible signal conditions to deselect the device.
31. DQs are in high-Z when exiting ZZ sleep mode.
Document #: 38-05557 Rev. *D
Page 23 of 28
CY7C1371DV25
CY7C1373DV25
Ordering Information
Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or
visit www.cypress.com for actual products offered.
Speed
(MHz)
Package
Diagram
Operating
Range
Ordering Code
Part and Package Type
133 CY7C1371DV25-133AXC 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
CY7C1373DV25-133AXC
Commercial
CY7C1371DV25-133BGC 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
CY7C1373DV25-133BGC
CY7C1371DV25-133BGXC 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free
CY7C1373DV25-133BGXC
CY7C1371DV25-133BZC 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)
CY7C1373DV25-133BZC
CY7C1371DV25-133BZXC 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead-Free
CY7C1373DV25-133BZXC
CY7C1371DV25-133AXI
CY7C1373DV25-133AXI
CY7C1371DV25-133BGI
CY7C1373DV25-133BGI
51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
lndustrial
51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
CY7C1371DV25-133BGXI 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free
CY7C1373DV25-133BGXI
CY7C1371DV25-133BZI
CY7C1373DV25-133BZI
51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)
CY7C1371DV25-133BZXI 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead-Free
CY7C1373DV25-133BZXI
100 CY7C1371DV25-100AXC 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
CY7C1373DV25-100AXC
Commercial
CY7C1371DV25-100BGC 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
CY7C1373DV25-100BGC
CY7C1371DV25-100BGXC 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free
CY7C1373DV25-100BGXC
CY7C1371DV25-100BZC 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)
CY7C1373DV25-100BZC
CY7C1371DV25-100BZXC 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead-Free
CY7C1373DV25-100BZXC
CY7C1371DV25-100AXI
CY7C1373DV25-100AXI
CY7C1371DV25-100BGI
CY7C1373DV25-100BGI
51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
lndustrial
51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
CY7C1371DV25-100BGXI 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free
CY7C1373DV25-100BGXI
CY7C1371DV25-100BZI
CY7C1373DV25-100BZI
51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)
CY7C1371DV25-100BZXI 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead-Free
CY7C1373DV25-100BZXI
Document #: 38-05557 Rev. *D
Page 24 of 28
CY7C1371DV25
CY7C1373DV25
Package Diagrams
100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) (51-85050)
16.00 0.20
14.00 0.10
1.40 0.05
100
81
80
1
0.30 0.08
0.65
TYP.
12° 1°
(8X)
SEE DETAIL
A
30
51
31
50
0.20 MAX.
1.60 MAX.
R 0.08 MIN.
0.20 MAX.
0° MIN.
SEATING PLANE
STAND-OFF
0.05 MIN.
0.15 MAX.
NOTE:
1. JEDEC STD REF MS-026
0.25
GAUGE PLANE
2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH
MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE
R 0.08 MIN.
0.20 MAX.
BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH
3. DIMENSIONS IN MILLIMETERS
0°-7°
0.60 0.15
0.20 MIN.
51-85050-*B
1.00 REF.
DETAIL
A
Document #: 38-05557 Rev. *D
Page 25 of 28
CY7C1371DV25
CY7C1373DV25
Package Diagrams (continued)
119-Ball BGA (14 x 22 x 2.4 mm) (51-85115)
Ø0.05 M C
Ø0.25 M C A B
A1 CORNER
Ø0.75 0.15(119X)
Ø1.00(3X) REF.
1
2
3
4
5
6
7
7
6
5
4
3 2 1
A
B
C
D
E
A
B
C
D
E
F
F
G
H
G
H
J
K
L
J
K
L
M
N
P
R
T
M
N
P
R
T
U
U
1.27
0.70 REF.
A
3.81
12.00
7.62
B
14.00 0.20
0.15(4X)
30° TYP.
51-85115-*B
SEATING PLANE
C
Document #: 38-05557 Rev. *D
Page 26 of 28
CY7C1371DV25
CY7C1373DV25
Package Diagrams (continued)
165-Ball FBGA (13 x 15 x 1.4 mm) (51-85180)
BOTTOM VIEW
PIN 1 CORNER
TOP VIEW
Ø0.05 M C
PIN 1 CORNER
Ø0.25 M C A B
-0.06
Ø0.50
(165X)
+0.14
1
2
3
4
5
6
7
8
9
10
11
11 10
9
8
7
6
5
4
3
2
1
A
A
B
B
C
D
C
D
E
E
F
F
G
G
H
J
H
J
K
K
L
L
M
M
N
P
R
N
P
R
A
A
1.00
5.00
10.00
13.00 0.10
B
B
13.00 0.10
0.15(4X)
NOTES :
SOLDER PAD TYPE : NON-SOLDER MASK DEFINED (NSMD)
PACKAGE WEIGHT : 0.475g
JEDECREFERENCE: MO-216 / DESIGN 4.6C
PACKAGE CODE : BB0AC
SEATING PLANE
C
51-85180-*A
NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation. ZBT is a trademark of Integrated Device
Technology, Inc. All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-05557 Rev. *D
Page 27 of 28
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY7C1371DV25
CY7C1373DV25
Document History Page
Document Title: CY7C1371DV25/CY7C1373DV25 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBL™ Archi-
tecture
Document Number: 38-05557
Orig. of
REV.
**
ECN NO. Issue Date Change
Description of Change
254513
288531
See ECN
See ECN
RKF
SYT
New data sheet
*A
Edited description under “IEEE 1149.1 Serial Boundary Scan (JTAG)” for
non-compliance with 1149.1
Removed 117 Mhz Speed Bin
Added lead-free information for 100-Pin TQFP, 119 BGA and 165 FBGA
package
Added comment of ‘Lead-free BG packages availability’ below the Ordering
Information
*B
326078
See ECN
PCI
Address expansion pins/balls in the pinouts for all packages are modified as
per JEDEC standard
Added description on EXTEST Output Bus Tri-State
Changed description on the Tap Instruction Set Overview and Extest
Changed ΘJA and ΘJC for TQFP Package from 31 and 6 °C/W to 28.66 and
4.08 °C/W respectively
Changed ΘJA and ΘJC for BGA Package from 45 and 7 °C/W to 23.8 and 6.2
°C/W respectively
Changed ΘJA and ΘJC for FBGA Package from 46 and 3 °C/W to 20.7 and
4.0 °C/W respectively
Modified VOL, VOH test conditions
Removed comment of ‘Lead-free BG packages availability’ below the
Ordering Information
Updated Ordering Information Table
*C
416321
See ECN
NXR
Converted From Preliminary to Final
Changed address of Cypress Semiconductor Corporation on Page# 1 from
“3901 North First Street” to “198 Champion Court”
Corrected typo in Partial Truth Table for Read/Write of CY7C1373DV25 on
page #11
Changed the description of IX from Input Load Current to Input Leakage
Current on page# 20
Changed the Ix current values of MODE on page # 20 from -5 µA and 30 µA
to -30 µA and 5 µA
Changed the Ix current values of ZZ on page # 20 from -30 µA and 5 µA
to -5 µA and 30 µA
Changed VIH < VDD to VIH < VDDon page # 20
Replaced Package Name column with Package Diagram in the Ordering
Information table
Updated Ordering Information Table
*D
475677
See ECN
VKN
Added the Maximum Rating for Supply Voltage on VDDQ Relative to GND.
Changed tTH, tTL from 25 ns to 20 ns and tTDOV from 5 ns to 10 ns in TAP
AC Switching Characteristics table.
Updated the Ordering Information table.
Document #: 38-05557 Rev. *D
Page 28 of 28
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