CY7C1370D-200AXCT [CYPRESS]
ZBT SRAM, 512KX36, 3ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, MS-026, TQFP-100;
| 型号： | CY7C1370D-200AXCT |
| 厂家： | 
CYPRESS |
| 描述： | ZBT SRAM, 512KX36, 3ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, MS-026, TQFP-100 时钟 静态存储器 内存集成电路 |
| 文件： | 总34页 (文件大小：818K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C1370D
CY7C1372D
18-Mbit (512 K × 36/1 M × 18) Pipelined
SRAM with NoBL™ Architecture
18-Mbit (512
K × 36/1 M × 18) Pipelined SRAM with NoBL™ Architecture
Features
Functional Description
The CY7C1370D and CY7C1372D are 3.3 V, 512 K × 36 and
■ Pin-compatible and functionally equivalent to ZBT™
1 M × 18 synchronous pipelined burst SRAMs with No Bus
Latency™ (NoBL logic, respectively. They are designed to
support unlimited true back-to-back read/write operations with
no wait states. The CY7C1370D and CY7C1372D are equipped
with the advanced (NoBL) logic required to enable consecutive
read/write operations with data being transferred on every clock
cycle. This feature dramatically improves the throughput of data
in systems that require frequent write/read transitions. The
CY7C1370D and CY7C1372D are pin compatible and
functionally equivalent to ZBT devices.
■ Supports 250-MHz bus operations with zero wait states
❐ Available speed grades are 250, 200, and 167 MHz
■ Internally self-timed output buffer control to eliminate the need
to use asynchronous OE
■ Fully registered (inputs and outputs) for pipelined operation
■ Byte write capability
■ 3.3 V core power supply (VDD
)
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. All data outputs pass through output
registers controlled by the rising edge of the clock. The clock
input is qualified by the clock enable (CEN) signal, which when
deasserted suspends operation and extends the previous clock
cycle.
■ 3.3 V/2.5 V I/O power supply (VDDQ
)
■ Fast clock-to-output times
❐ 2.6 ns (for 250 MHz device)
■ Clock enable (CEN) pin to suspend operation
■ Synchronous self-timed writes
Write operations are controlled by the byte write selects
(BWa–BWd for CY7C1370D and BWa–BWb for CY7C1372D)
and a write enable (WE) input. All writes are conducted with
on-chip synchronous self-timed write circuitry.
■ Available in JEDEC-standard Pb-free 100-pin TQFP, Pb-free
and non Pb-free 65-ball FBGA package
■ IEEE 1149.1 JTAG-compatible boundary scan
■ Burst capability – linear or interleaved burst order
■ “ZZ” sleep mode option and stop clock option
Three synchronous chip enables (CE1, CE2, CE3) and an
asynchronous output enable (OE) provide for easy bank
selection and output tri-state control. In order to avoid bus
contention, the output drivers are synchronously tristated during
the data portion of a write sequence.
Selection Guide
Description
Maximum access time
250 MHz
2.6
200 MHz
3.0
167 MHz Unit
3.4
275
70
ns
Maximum operating current
350
300
mA
mA
Maximum CMOS standby current
70
70
Errata: For information on silicon errata, see “Errata” on page 30. Details include trigger conditions, devices affected, and proposed workaround.
Cypress Semiconductor Corporation
Document Number: 38-05555 Rev. *Q
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised October 9, 2013
CY7C1370D
CY7C1372D
Logic Block Diagram – CY7C1370D
ADDRESS
REGISTER
A0, A1,
A
0
A1
A0
A1'
A0'
D1
D0
Q1
Q0
BURST
LOGIC
MODE
ADV/LD
CLK
CEN
C
C
WRITE ADDRESS
REGISTER
WRITE ADDRESS
REGISTER 2
1
O
U
T
O
U
T
S
E
D
A
T
P
U
T
N
S
P
U
T
ADV/LD
A
E
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
R
E
G
I
MEMORY
ARRAY
B
U
F
F
E
R
S
S
T
E
E
R
I
DQ s
DQ P
DQ P
DQ P
DQ P
WRITE
DRIVERS
BW
a
a
b
c
A
M
P
BW
BW
BW
b
c
S
T
E
R
S
d
d
S
WE
E
E
N
G
INPUT
REGISTER
INPUT
REGISTER 0
E
E
1
OE
READ LOGIC
CE1
CE2
CE3
SLEEP
CONTROL
ZZ
Logic Block Diagram – CY7C1372D
ADDRESS
REGISTER
A0, A1,
A
0
A1
A0
A1'
A0'
D1
D0
Q1
Q0
BURST
LOGIC
MODE
ADV/LD
CLK
CEN
C
C
WRITE ADDRESS
REGISTER
WRITE ADDRESS
REGISTER 2
1
O
U
T
O
U
T
P
U
T
S
E
P
U
T
D
A
T
ADV/LD
N
S
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
A
R
E
G
I
MEMORY
ARRAY
E
B
U
F
F
E
R
S
DQ s
DQ P
DQ P
WRITE
DRIVERS
BW
BW
a
S
T
E
E
R
I
A
M
P
a
b
S
T
E
R
S
b
S
N
G
WE
E
E
INPUT
REGISTER
INPUT
REGISTER 0
E
E
1
OE
CE1
CE2
CE3
READ LOGIC
Sleep
Control
ZZ
Document Number: 38-05555 Rev. *Q
Page 2 of 34
CY7C1370D
CY7C1372D
Contents
Pin Configurations ...........................................................4
Pin Definitions ..................................................................6
Functional Overview ........................................................8
Single Read Accesses ................................................8
Burst Read Accesses ..................................................8
Single Write Accesses .................................................8
Burst Write Accesses ..................................................8
Sleep Mode .................................................................9
Interleaved Burst Address Table .................................9
Linear Burst Address Table .........................................9
ZZ Mode Electrical Characteristics ..............................9
Truth Table ......................................................................10
Partial Write Cycle Description .....................................11
IEEE 1149.1 Serial Boundary Scan (JTAG [17]) ...........12
Disabling the JTAG Feature ......................................12
Test Access Port (TAP) .............................................12
PERFORMING A TAP RESET ..................................12
TAP REGISTERS ......................................................12
TAP Instruction Set ...................................................13
TAP Controller State Diagram .......................................14
TAP Controller Block Diagram ......................................15
TAP Timing ......................................................................15
TAP AC Switching Characteristics ...............................16
3.3 V TAP AC Test Conditions .......................................17
3.3 V TAP AC Output Load Equivalent .........................17
2.5 V TAP AC Test Conditions .......................................17
2.5 V TAP AC Output Load Equivalent .........................17
TAP DC Electrical Characteristics and
Identification Codes .......................................................18
Boundary Scan Order ....................................................19
Maximum Ratings ...........................................................20
Operating Range .............................................................20
Neutron Soft Error Immunity .........................................20
Electrical Characteristics ...............................................20
Capacitance ....................................................................21
Thermal Resistance ........................................................21
AC Test Loads and Waveforms .....................................22
Switching Characteristics ..............................................23
Switching Waveforms ....................................................24
Ordering Information ......................................................26
Ordering Code Definitions .........................................26
Package Diagrams ..........................................................27
Acronyms ........................................................................29
Document Conventions .................................................29
Units of Measure .......................................................29
Errata ...............................................................................30
Part Numbers Affected ..............................................30
Product Status ...........................................................30
Ram9 NoBL ZZ Pin & JTAG Issues
Errata Summary ...............................................................30
Document History Page .................................................32
Sales, Solutions, and Legal Information ......................34
Worldwide Sales and Design Support .......................34
Products ....................................................................34
PSoC® Solutions ......................................................34
Cypress Developer Community .................................34
Technical Support .....................................................34
Operating Conditions .....................................................17
Identification Register Definitions ................................18
Scan Register Sizes .......................................................18
Document Number: 38-05555 Rev. *Q
Page 3 of 34
CY7C1370D
CY7C1372D
Pin Configurations
Figure 1. 100-pin TQFP (14 × 20 × 1.4 mm) pinout [1]
DQPc
DQc
DQc
1
2
3
4
5
6
7
8
NC
NC
NC
DDQ
1
2
3
4
5
6
7
8
A
NC
NC
78
DQPb
DQb
DQb
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
80
79
V
V
DDQ
V
V
V
NC
DQPa
DQa
DQa
DDQ
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DDQ
SS
V
V
V
SS
SS
SS
DQc
DQc
NC
NC
DQb
DQb
DQb
DQb
DQb
DQb
DQc
DQc
9
9
V
V
SS
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
V
SS
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
V
SS
SS
V
V
DDQ
DDQ
V
V
DQa
DQa
V
NC
V
ZZ
DDQ
DDQ
DQc
DQc
NC
DQb
DQb
DQb
DQb
NC
V
SS
CY7C1370D
(512 K × 36)
SS
V
V
DD
NC
DD
CY7C1372D
(1 M × 18)
NC
NC
V
DD
DD
V
V
SS
SS
ZZ
DQa
DQa
DQd
DQb
DQb
DQa
DQa
DQd
V
V
DDQ
DDQ
V
V
V
DQa
DQa
NC
NC
V
V
DDQ
DDQ
V
V
SS
V
SS
SS
SS
DQd
DQd
DQd
DQd
DQa
DQa
DQb
DQb
DQa DQPb
DQa
NC
V
SS
V
V
SS
SS
SS
V
V
DDQ
V
DDQ
DDQ
DDQ
DQd
DQd
DQPd
DQa
DQa
DQPa
NC
NC
NC
NC
NC
NC
Note
1. Errata: The ZZ pin (Pin 64) needs to be externally connected to ground. For more information, see “Errata” on page 30.
Document Number: 38-05555 Rev. *Q
Page 4 of 34
CY7C1370D
CY7C1372D
Pin Configurations (continued)
Figure 2. 165-ball FBGA (13 × 15 × 1.4 mm) pinout [2, 3]
CY7C1370D (512 K × 36)
1
2
A
3
4
5
6
7
8
9
A
10
A
11
NC
NC/576M
NC/1G
DQPc
ADV/LD
A
B
C
D
CE1
BWc
BWb
CE3
CLK
VSS
VSS
CEN
WE
VSS
VSS
A
CE2
VDDQ
VDDQ
OE
VSS
VDD
A
A
NC
BWd
VSS
VDD
BWa
VSS
VSS
NC
DQc
VDDQ
VDDQ
NC
DQb
DQPb
DQb
DQc
DQc
DQc
DQc
DQc
NC
VDDQ
VDDQ
VDDQ
NC
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
NC
DQb
DQb
DQb
NC
DQb
E
F
DQc
DQc
NC
VSS
VSS
VSS
VSS
VSS
VSS
DQb
DQb
ZZ
G
H
J
DQd
DQd
DQd
DQd
DQd
DQd
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
DQa
DQa
DQa
DQa
DQa
DQa
K
L
DQd
DQd
NC
VDDQ
VDDQ
A
VDD
VSS
A
VSS
NC
VSS
NC
A1
VSS
NC
VDD
VSS
A
VDDQ
VDDQ
A
DQa
NC
A
DQa
DQPa
M
N
P
DQPd
NC/144M NC/72M
MODE NC/36M
TDI
TDO
NC/288M
A
A
TMS
A0
TCK
A
A
A
A
R
Notes
2. Errata: The ZZ ball (H11) needs to be externally connected to ground. For more information, see “Errata” on page 30.
3. Errata: The JTAG testing should be performed with these devices in BYPASS mode as the JTAG functionality is not guaranteed. For more information, see “Errata”
on page 30.
Document Number: 38-05555 Rev. *Q
Page 5 of 34
CY7C1370D
CY7C1372D
Pin Definitions
Pin Name
I/O Type
Pin Description
A0, A1, A
Input-
synchronous
Address inputs used to select one of the address locations. Sampled at the rising edge of the CLK.
BWa, BWb,
Input-
Byte write select inputs, active LOW. Qualified with WE to conduct writes to the SRAM. Sampled on
BWc, BWd synchronous the rising edge of CLK. BWa controls DQa and DQPa, BWb controls DQb and DQPb, BWc controls DQc
and DQPc, BWd controls DQd and DQPd.
WE
Input-
Write enable input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This signal
synchronous must be asserted LOW to initiate a write sequence.
ADV/LD
Input- Advance/load input used to advance the on-chip address counter or load a new address. When
synchronous HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a new address
can be loaded into the device for an access. After being deselected, ADV/LD should be driven LOW in
order to load a new address.
CLK
CE1
CE2
CE3
OE
Input-clock Clock input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN. CLK is
only recognized if CEN is active LOW.
Input-
Chip enable 1 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2
synchronous and CE3 to select/deselect the device.
Input-
Chip enable 2 input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1
synchronous and CE3 to select/deselect the device.
Input-
Chip enable 3 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1
synchronous and CE2 to select/deselect the device.
Input-
Output enable, active LOW. Combined with the synchronous logic block inside the device to control
asynchronous the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as outputs. When deasserted
HIGH, I/O pins are tristated, and act as input data pins. OE is masked during the data portion of a write
sequence, during the first clock when emerging from a deselected state and when the device has been
deselected.
CEN
DQS
Input-
Clock enable input, active LOW. When asserted LOW the clock signal is recognized by the SRAM.
synchronous When deasserted HIGH the clock signal is masked. Since deasserting CEN does not deselect the device,
CEN can be used to extend the previous cycle when required.
I/O-
Bidirectional data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the
synchronous rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by A[17:0]
during the previous clock rise of the read cycle. The direction of the pins is controlled by OE and the
internal control logic. When OE is asserted LOW, the pins can behave as outputs. When HIGH, DQa–DQd
are placed in a tristate condition. The outputs are automatically tristated during the data portion of a write
sequence, during the first clock when emerging from a deselected state, and when the device is deselected,
regardless of the state of OE.
DQPX
I/O-
Bidirectional data parity I/O lines. Functionally, these signals are identical to DQs. During write
synchronous sequences, DQPa is controlled by BWa, DQPb is controlled by BWb, DQPc is controlled by BWc, and
DQPd is controlled by BWd.
MODE
Input strap pin Mode input. Selects the burst order of the device. Tied HIGH selects the interleaved burst order. Pulled
LOW selects the linear burst order. MODE should not change states during operation. When left floating
MODE will default HIGH, to an interleaved burst order.
Document Number: 38-05555 Rev. *Q
Page 6 of 34
CY7C1370D
CY7C1372D
Pin Definitions (continued)
Pin Name
I/O Type
Pin Description
TDO [4]
JTAG serial Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK.
output
synchronous
TDI [4]
JTAG serial Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK.
input
synchronous
TMS [4]
Test mode This pin controls the test access port state machine. Sampled on the rising edge of TCK.
select
synchronous
TCK [4]
VDD
JTAG-clock Clock input to the JTAG circuitry.
Power supply Power supply inputs to the core of the device.
VDDQ
I/O power Power supply for the I/O circuitry.
supply
VSS
NC
Ground
Ground for the device. Should be connected to ground of the system.
No connects. This pin is not connected to the die.
–
–
NC/(36M,7
2M, 144M,
288M,
These pins are not connected. They will be used for expansion to the 36M, 72M, 144M, 288M, 576M
and 1G densities.
576M, 1G)
ZZ [5]
Input-
ZZ “sleep” input. This active HIGH input places the device in a non-time critical “sleep” condition with
asynchronous data integrity preserved. During normal operation, this pin can be connected to VSS or left floating. ZZ
pin has an internal pull down.
Note
4. Errata: The JTAG testing should be performed with these devices in BYPASS mode as the JTAG functionality is not guaranteed. For more information, see “Errata”
on page 30.
5. Errata: The ZZ pin needs to be externally connected to ground. For more information, see “Errata” on page 30.
Document Number: 38-05555 Rev. *Q
Page 7 of 34
CY7C1370D
CY7C1372D
regardless of the state of chip enables inputs or WE. WE is
latched at the beginning of a burst cycle. Therefore, the type of
access (read or write) is maintained throughout the burst
sequence.
Functional Overview
The CY7C1370D and CY7C1372D are synchronous-pipelined
burst NoBL SRAMs designed specifically to eliminate wait states
during write/read transitions. All synchronous inputs pass
through input registers controlled by the rising edge of the clock.
The clock signal is qualified with the clock enable input signal
(CEN). If CEN is HIGH, the clock signal is not recognized and all
internal states are maintained. All synchronous operations are
qualified with CEN. All data outputs pass through output registers
controlled by the rising edge of the clock. Maximum access delay
from the clock rise (tCO) is 2.6 ns (250-MHz device).
Single Write Accesses
Write access are initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,
and CE3 are all asserted active, and (3) the write signal WE is
asserted LOW. The address presented is loaded into the
address register. The write signals are latched into the control
logic block.
Accesses can be initiated by asserting all three chip enables
(CE1, CE2, CE3) active at the rising edge of the clock. If clock
enable (CEN) is active LOW and ADV/LD is asserted LOW, the
address presented to the device will be latched. The access can
either be a read or write operation, depending on the status of
the write enable (WE). BWX can be used to conduct byte write
operations.
On the subsequent clock rise the data lines are automatically
tristated regardless of the state of the OE input signal. This
allows the external logic to present the data on DQ and DQP
(DQa,b,c,d/DQPa,b,c,d for CY7C1370D and DQa,b/DQPa,b for
CY7C1372D). In addition, the address for the subsequent
access (read/write/deselect) is latched into the address register
(provided the appropriate control signals are asserted).
Write operations are qualified by the write enable (WE). All writes
are simplified with on-chip synchronous self-timed write circuitry.
On the next clock rise the data presented to DQ and DQP
(DQa,b,c,d/DQPa,b,c,d for CY7C1370D & DQa,b/DQPa,b for
CY7C1372D) (or a subset for byte write operations, see Write
Cycle Description table for details) inputs is latched into the
device and the write is complete.
Three synchronous chip enables (CE1, CE2, CE3) and an
asynchronous output enable (OE) simplify depth expansion. All
operations (reads, writes, and deselects) are pipelined. ADV/LD
should be driven LOW once the device has been deselected in
order to load a new address for the next operation.
The data written during the write operation is controlled by BW
(BWa,b,c,d for CY7C1370D and BWa,b for CY7C1372D) signals.
The CY7C1370D/CY7C1372D provides byte write capability that
is described in the Write Cycle Description table. Asserting the
write enable input (WE) with the selected byte write select (BW)
input will selectively write to only the desired bytes. Bytes not
selected during a byte write operation will remain unaltered. A
synchronous self-timed write mechanism has been provided to
simplify the write operations. Byte write capability has been
included in order to greatly simplify read/modify/write
sequences, which can be reduced to simple byte write
operations.
Single Read Accesses
A read access is initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,
and CE3 are all asserted active, (3) the write enable input signal
WE is deasserted HIGH, and (4) ADV/LD is asserted LOW. The
address presented to the address inputs is latched into the
address register and presented to the memory core and control
logic. The control logic determines that a read access is in
progress and allows the requested data to propagate to the input
of the output register. At the rising edge of the next clock the
requested data is allowed to propagate through the output
register and onto the data bus within 2.6 ns (250-MHz device)
provided OE is active LOW. After the first clock of the read
access the output buffers are controlled by OE and the internal
control logic. OE must be driven LOW in order for the device to
drive out the requested data. During the second clock, a
subsequent operation (read/write/deselect) can be initiated.
Deselecting the device is also pipelined. Therefore, when the
SRAM is deselected at clock rise by one of the chip enable
signals, its output will tristate following the next clock rise.
Because the CY7C1370D and CY7C1372D are common I/O
devices, data should not be driven into the device while the
outputs are active. The output enable (OE) can be deasserted
HIGH before presenting data to the DQ and DQP
(DQa,b,c,d/DQPa,b,c,d for CY7C1370D and DQa,b/DQPa,b for
CY7C1372D) inputs. Doing so will tri-state the output drivers. As
a safety precaution, DQ and DQP (DQa,b,c,d/DQPa,b,c,d for
CY7C1370D and DQa,b/DQPa,b for CY7C1372D) are
automatically tristated during the data portion of a write cycle,
regardless of the state of OE.
Burst Write Accesses
Burst Read Accesses
The CY7C1370D/CY7C1372D has an on-chip burst counter that
allows the user the ability to supply a single address and conduct
up to four write operations without reasserting the address
inputs. ADV/LD must be driven LOW in order to load the initial
address, as described in the Single Write Accesses section
above. When ADV/LD is driven HIGH on the subsequent clock
rise, the chip enables (CE1, CE2, and CE3) and WE inputs are
ignored and the burst counter is incremented. The correct BW
(BWa,b,c,d for CY7C1370D and BWa,b for CY7C1372D) inputs
must be driven in each cycle of the burst write in order to write
the correct bytes of data.
The CY7C1370D and CY7C1372D have an on-chip burst
counter that allows the user the ability to supply a single address
and conduct up to four reads without reasserting the address
inputs. ADV/LD must be driven LOW in order to load a new
address into the SRAM, as described in the Single Read
Accesses section above. The sequence of the burst counter is
determined by the MODE input signal. A LOW input on MODE
selects a linear burst mode, a HIGH selects an interleaved burst
sequence. Both burst counters use A0 and A1 in the burst
sequence, and will wrap-around when incremented sufficiently.
A HIGH input on ADV/LD will increment the internal burst counter
Document Number: 38-05555 Rev. *Q
Page 8 of 34
CY7C1370D
CY7C1372D
Sleep Mode
Linear Burst Address Table
The ZZ input pin is an asynchronous input. Asserting ZZ places
the SRAM in a power conservation “sleep” mode. Two clock
cycles are required to enter into or exit from this “sleep” mode.
While in this mode, data integrity is guaranteed. Accesses
pending when entering the “sleep” mode are not considered valid
nor is the completion of the operation guaranteed. The device
must be deselected prior to entering the “sleep” mode. CE1, CE2,
and CE3, must remain inactive for the duration of tZZREC after the
ZZ input returns LOW.
(MODE = GND)
First
Address
A1:A0
Second
Address
A1:A0
Third
Address
A1:A0
Fourth
Address
A1:A0
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
Interleaved Burst Address Table
(MODE = Floating or VDD
)
First
Address
A1:A0
Second
Address
A1:A0
Third
Address
A1:A0
Fourth
Address
A1:A0
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
ZZ Mode Electrical Characteristics
Parameter
IDDZZ
Description
Sleep mode standby current
Device operation to ZZ
ZZ recovery time
Test Conditions
Min
Max
80
Unit
mA
ns
ZZ VDD 0.2 V
–
tZZS
ZZ VDD 0.2 V
ZZ 0.2 V
–
2tCYC
–
2tCYC
–
tZZREC
tZZI
ns
ZZ active to sleep current
This parameter is sampled
2tCYC
–
ns
tRZZI
ZZ Inactive to exit sleep current This parameter is sampled
0
ns
Document Number: 38-05555 Rev. *Q
Page 9 of 34
CY7C1370D
CY7C1372D
Truth Table
The Truth Table for CY7C1370D and CY7C1372D follows. [6, 7, 8, 9, 10, 11, 12]
Operation
Address Used CE ZZ ADV/LD WE BWx OE CEN CLK
DQ
Deselect cycle
None
None
H
X
L
L
L
L
L
L
L
L
L
L
L
L
H
L
H
L
X
X
H
X
H
X
L
X
X
X
X
X
X
L
X
X
L
L
L
L
L
L
L
L
L
L
L
H
X
L–H
L–H
Tri-state
Tri-state
Continue deselect cycle
Read cycle (begin burst)
Read cycle (continue burst)
NOP/dummy read (begin burst)
Dummy read (continue burst)
Write cycle (begin burst)
Write cycle (continue burst)
NOP/write abort (begin burst)
Write abort (continue burst)
Ignore clock edge (stall)
Sleep mode
External
Next
L–H Data out (Q)
L–H Data out (Q)
X
L
H
L
L
External
Next
H
H
X
X
X
X
X
X
L–H
L–H
Tri-state
Tri-state
X
L
H
L
External
Next
L–H Data in (D)
L–H Data in (D)
X
L
H
L
X
L
L
None
H
H
X
X
L–H
L–H
L–H
X
Tri-state
Tri-state
–
Next
X
X
X
H
X
X
X
X
X
Current
None
Tri-state
Notes
6. X = “Don't Care”, H = Logic HIGH, L = Logic LOW, CE stands for ALL Chip Enables active. BWx = L signifies at least one Byte Write Select is active, BWx = Valid
signifies that the desired byte write selects are asserted, see Write Cycle Description table for details.
7. Write is defined by WE and BW . See Write Cycle Description table for details.
X
8. When a write cycle is detected, all I/Os are tristated, even during byte writes.
9. The DQ and DQP pins are controlled by the current cycle and the OE signal.
10. CEN = H inserts wait states.
11. Device will power-up deselected and the I/Os in a tristate condition, regardless of OE.
12. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQ and DQP = Tri-state when OE is
s
X
inactive or when the device is deselected, and DQ = data when OE is active.
s
Document Number: 38-05555 Rev. *Q
Page 10 of 34
CY7C1370D
CY7C1372D
Partial Write Cycle Description
The Partial Write Cycle Description follows. [13, 14, 15, 16]
Function (CY7C1370D)
Read
WE
H
L
BWd
X
H
H
H
H
H
H
H
H
L
BWc
X
H
H
H
H
L
BWb
BWa
X
H
L
X
H
H
L
Write – No bytes written
Write Byte a – (DQa and DQPa)
Write Byte b – (DQb and DQPb)
Write Bytes b, a
L
L
H
L
L
L
Write Byte c – (DQc and DQPc)
Write Bytes c, a
L
H
H
L
H
L
L
L
Write Bytes c, b
L
L
H
L
Write Bytes c, b, a
L
L
L
Write Byte d – (DQd and DQPd)
Write Bytes d, a
L
H
H
H
H
L
H
H
L
H
L
L
L
Write Bytes d, b
L
L
H
L
Write Bytes d, b, a
L
L
L
Write Bytes d, c
L
L
H
H
L
H
L
Write Bytes d, c, a
L
L
L
Write Bytes d, c, b
L
L
L
H
L
Write All Bytes
L
L
L
L
Function (CY7C1372D)
Read
WE
H
L
BWb
X
BWa
X
Write – No Bytes Written
Write Byte a – (DQa and DQPa)
Write Byte b – (DQb and DQPb)
Write Both Bytes
H
H
L
H
L
L
L
H
L
L
L
Notes
13. X = “Don't Care”, H = Logic HIGH, L = Logic LOW, CE stands for ALL Chip Enables active. BWx = L signifies at least one Byte Write Select is active, BWx = Valid
signifies that the desired byte write selects are asserted, see Write Cycle Description table for details.
14. Write is defined by WE and BW . See Write Cycle Description table for details.
X
15. When a write cycle is detected, all I/Os are tristated, even during byte writes.
16. Table only lists a partial listing of the byte write combinations. Any Combination of BW is valid Appropriate write will be done based on which byte write is active.
X
Document Number: 38-05555 Rev. *Q
Page 11 of 34
CY7C1370D
CY7C1372D
IEEE 1149.1 Serial Boundary Scan (JTAG [17]
)
At power-up, the TAP is reset internally to ensure that TDO
comes up in a High Z state.
The CY7C1370D incorporates a serial boundary scan test
access port (TAP). This part is fully compliant with 1149.1. The
TAP operates using JEDEC-standard 3.3 V or 2.5 V I/O logic
levels.
TAP Registers
Registers are connected between the TDI and TDO balls and
allow data to be scanned into and out of the SRAM test circuitry.
Only one register can be selected at a time through the
instruction register. Data is serially loaded into the TDI ball on the
rising edge of TCK. Data is output on the TDO ball on the falling
edge of TCK.
The CY7C1370D contains a TAP controller, instruction register,
boundary scan register, bypass register, and ID register.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(VSS) to prevent clocking of the device. TDI and TMS are
internally pulled up and may be unconnected. They may
alternately be connected to VDD through a pull-up resistor. TDO
should be left unconnected. Upon power-up, the device will
come up in a reset state which will not interfere with the operation
of the device.
Instruction Register
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the TDI
and TDO balls as shown in the TAP Controller Block Diagram on
page 15. Upon power-up, the instruction register is loaded with
the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as described
in the previous section.
The 0/1 next to each state represents the value of TMS at the
rising edge of TCK.
When the TAP controller is in the Capture-IR state, the two least
significant bits are loaded with a binary “01” pattern to allow for
fault isolation of the board-level serial test data path.
Test Access Port (TAP)
Bypass Register
Test Clock (TCK)
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between the
TDI and TDO balls. This allows data to be shifted through the
The test clock is used only with the TAP controller. All inputs are
captured on the rising edge of TCK. All outputs are driven from
the falling edge of TCK.
Test Mode Select (TMS)
SRAM with minimal delay. The bypass register is set LOW (VSS
)
when the BYPASS instruction is executed.
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. It is allowable to leave
this ball unconnected if the TAP is not used. The ball is pulled up
internally, resulting in a logic HIGH level.
Boundary Scan Register
The boundary scan register is connected to all the input and
bidirectional balls on the SRAM.
Test Data-In (TDI)
The boundary scan register is loaded with the contents of the
RAM I/O ring when the TAP controller is in the Capture-DR state
and is then placed between the TDI and TDO balls when the
controller is moved to the Shift-DR state. The EXTEST,
SAMPLE/PRELOAD and SAMPLE Z instructions can be used to
capture the contents of the I/O ring.
The TDI ball is used to serially input information into the registers
and can be connected to the input of any of the registers. The
register between TDI and TDO is chosen by the instruction that
is loaded into the TAP instruction register. TDI is internally pulled
up and can be unconnected if the TAP is unused in an
application. TDI is connected to the most significant bit (MSB) of
any register.
The Boundary Scan Order tables show the order in which the bits
are connected. Each bit corresponds to one of the bumps on the
SRAM package. The MSB of the register is connected to TDI and
the LSB is connected to TDO.
Test Data-Out (TDO)
The TDO output ball is used to serially clock data-out from the
registers. The output is active depending upon the current state
of the TAP state machine. The output changes on the falling edge
of TCK. TDO is connected to the least significant bit (LSB) of any
register.
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired into
the SRAM and can be shifted out when the TAP controller is in
the Shift-DR state. The ID register has a vendor code and other
information described in the Identification Register Definitions
table.
Performing a TAP Reset
A Reset is performed by forcing TMS HIGH (VDD) for five rising
edges of TCK. This Reset does not affect the operation of the
SRAM and may be performed while the SRAM is operating.
Note
17. Errata: The JTAG testing should be performed with these devices in BYPASS mode as the JTAG functionality is not guaranteed. For more information, see “Errata”
on page 30.
Document Number: 38-05555 Rev. *Q
Page 12 of 34
CY7C1370D
CY7C1372D
there is no guarantee as to the value that will be captured.
Repeatable results may not be possible.
TAP Instruction Set
Overview
To guarantee that the boundary scan register will capture the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller’s capture setup plus hold
times (tCS and tCH). The SRAM clock input might not be captured
correctly if there is no way in a design to stop (or slow) the clock
during a SAMPLE/PRELOAD instruction. If this is an issue, it is
still possible to capture all other signals and simply ignore the
value of the CK and CK captured in the boundary scan register.
Eight different instructions are possible with the three bit
instruction register. All combinations are listed in the Instruction
Codes table. Three of these instructions are listed as
RESERVED and should not be used. The other five instructions
are described in detail below.
Instructions are loaded into the TAP controller during the Shift-IR
state when the instruction register is placed between TDI and
TDO. During this state, instructions are shifted through the
instruction register through the TDI and TDO balls. To execute
the instruction once it is shifted in, the TAP controller needs to be
moved into the Update-IR state.
Once the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the boundary
scan register between the TDI and TDO pins.
PRELOAD allows an initial data pattern to be placed at the
latched parallel outputs of the boundary scan register cells prior
to the selection of another boundary scan test operation.
EXTEST
The EXTEST instruction enables the preloaded data to be driven
out through the system output pins. This instruction also selects
the boundary scan register to be connected for serial access
between the TDI and TDO in the shift-DR controller state.
The shifting of data for the SAMPLE and PRELOAD phases can
occur concurrently when required – that is, while data captured
is shifted out, the preloaded data can be shifted in.
BYPASS
IDCODE
When the BYPASS instruction is loaded in the instruction register
and the TAP is placed in a Shift-DR state, the bypass register is
placed between the TDI and TDO balls. The advantage of the
BYPASS instruction is that it shortens the boundary scan path
when multiple devices are connected together on a board.
The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the instruction register. It also places the
instruction register between the TDI and TDO balls and allows
the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state.
The IDCODE instruction is loaded into the instruction register
upon power-up or whenever the TAP controller is given a test
logic reset state.
EXTEST Output Bus Tristate
IEEE Standard 1149.1 mandates that the TAP controller be able
to put the output bus into a tristate mode.
SAMPLE Z
The boundary scan register has a special bit located at bit #85
(for 119-ball BGA package) or bit #89 (for 165-ball FBGA
package). When this scan cell, called the “extest output bus
tristate,” is latched into the preload register during the
“Update-DR” state in the TAP controller, it will directly control the
state of the output (Q-bus) pins, when the EXTEST is entered as
the current instruction. When HIGH, it will enable the output
buffers to drive the output bus. When LOW, this bit will place the
output bus into a High Z condition.
The SAMPLE Z instruction causes the boundary scan register to
be connected between the TDI and TDO balls when the TAP
controller is in a Shift-DR state. It also places all SRAM outputs
into a High Z state.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1-mandatory instruction. When
the SAMPLE/PRELOAD instructions are loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and output pins is
captured in the boundary scan register.
This bit can be set by entering the SAMPLE/PRELOAD or
EXTEST command, and then shifting the desired bit into that cell,
during the “Shift-DR” state. During “Update-DR,” the value
loaded into that shift-register cell will latch into the preload
register. When the EXTEST instruction is entered, this bit will
directly control the output Q-bus pins. Note that this bit is preset
HIGH to enable the output when the device is powered-up, and
also when the TAP controller is in the “Test-Logic-Reset” state.
The user must be aware that the TAP controller clock can only
operate at a frequency up to 20 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because there
is a large difference in the clock frequencies, it is possible that
during the Capture-DR state, an input or output will undergo a
transition. The TAP may then try to capture a signal while in
transition (metastable state). This will not harm the device, but
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
Document Number: 38-05555 Rev. *Q
Page 13 of 34
CY7C1370D
CY7C1372D
TAP Controller State Diagram
TEST-LOGIC
1
RESET
0
1
1
1
RUN-TEST/
0
SELECT
DR-SCAN
SELECT
IR-SCAN
IDLE
0
0
1
1
CAPTURE-DR
CAPTURE-IR
0
0
SHIFT-DR
0
SHIFT-IR
0
1
1
1
1
EXIT1-DR
EXIT1-IR
0
0
PAUSE-DR
0
PAUSE-IR
1
0
1
0
0
EXIT2-DR
1
EXIT2-IR
1
UPDATE-DR
UPDATE-IR
1
0
1
0
Document Number: 38-05555 Rev. *Q
Page 14 of 34
CY7C1370D
CY7C1372D
TAP Controller Block Diagram
0
0
Bypass Register
2
1
Selection
Circuitry
Selection
Circuitry
Instruction Register
31 30 29 .
Identification Register
TDI
TDO
.
.
2
1
0
x
.
.
.
.
. 2 1
0
Boundary Scan Register
TCK
TAP CONTROLLER
TM S
TAP Timing
1
2
3
4
5
6
Test Clock
(TCK)
t
t
t
CYC
TH
TL
t
t
t
t
TM SS
TDIS
TM SH
Test M ode Select
(TM S)
TDIH
Test Data-In
(TDI)
t
TDOV
t
TDOX
Test Data-Out
(TDO)
DON’T CARE
UNDEFINED
Document Number: 38-05555 Rev. *Q
Page 15 of 34
CY7C1370D
CY7C1372D
TAP AC Switching Characteristics
Over the Operating Range
Parameter [18, 19]
Clock
Description
Min
Max
Unit
tTCYC
TCK Clock Cycle Time
TCK Clock Frequency
TCK Clock HIGH time
TCK Clock LOW time
50
–
–
20
–
ns
MHz
ns
tTF
tTH
20
20
tTL
–
ns
Output Times
tTDOV
tTDOX
Setup Times
tTMSS
tTDIS
TCK Clock LOW to TDO Valid
TCK Clock LOW to TDO Invalid
–
0
10
–
ns
ns
TMS Setup to TCK Clock Rise
TDI Setup to TCK Clock Rise
Capture Setup to TCK Rise
5
5
5
–
–
–
ns
ns
ns
tCS
Hold Times
tTMSH
tTDIH
TMS Hold after TCK Clock Rise
TDI Hold after Clock Rise
5
5
5
–
–
–
ns
ns
ns
tCH
Capture Hold after Clock Rise
Notes
18. t and t refer to the setup and hold time requirements of latching data from the boundary scan register.
CS
CH
19. Test conditions are specified using the load in TAP AC test Conditions. t /t = 1 ns.
R
F
Document Number: 38-05555 Rev. *Q
Page 16 of 34
CY7C1370D
CY7C1372D
3.3 V TAP AC Test Conditions
2.5 V TAP AC Test Conditions
Input pulse levels ...............................................VSS to 3.3 V
Input rise and fall times ...................................................1 ns
Input timing reference levels ......................................... 1.5 V
Output reference levels ................................................ 1.5 V
Test load termination supply voltage ............................ 1.5 V
Input pulse levels ...............................................VSS to 2.5 V
Input rise and fall time ....................................................1 ns
Input timing reference levels ....................................... 1.25 V
Output reference levels .............................................. 1.25 V
Test load termination supply voltage .......................... 1.25 V
3.3 V TAP AC Output Load Equivalent
1.5V
2.5 V TAP AC Output Load Equivalent
1.25V
50Ω
50Ω
TDO
TDO
ZO= 50Ω
20pF
ZO= 50Ω
20pF
TAP DC Electrical Characteristics and Operating Conditions
(0 °C < TA < +70 °C; VDD = 3.3 V ± 0.165 V unless otherwise noted)
Parameter [20]
Description
Test Conditions
IOH = –4.0 mA, VDDQ = 3.3 V
IOH = –1.0 mA, VDDQ = 2.5 V
Min
2.4
2.0
2.9
2.1
–
Max
Unit
V
VOH1
Output HIGH Voltage
–
–
V
VOH2
VOL1
VOL2
VIH
Output HIGH Voltage
Output LOW Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Load Current
IOH = –100 µA
VDDQ = 3.3 V
DDQ = 2.5 V
IOL = 8.0 mA, VDDQ = 3.3 V
OL = 8.0 mA, VDDQ = 2.5 V
–
V
V
–
0.4
V
V
I
–
0.4
V
IOL = 100 µA
VDDQ = 3.3 V
VDDQ = 2.5 V
–
0.2
V
–
0.2
V
VDDQ = 3.3 V
2.0
1.7
–0.5
–0.3
–5
VDD + 0.3
VDD + 0.3
0.7
V
V
DDQ = 2.5 V
VDDQ = 3.3 V
DDQ = 2.5 V
GND < VIN < VDDQ
V
VIL
V
V
0.7
V
IX
5
µA
Note
20. All voltages referenced to V (GND)
SS
Document Number: 38-05555 Rev. *Q
Page 17 of 34
CY7C1370D
CY7C1372D
Identification Register Definitions
Instruction Field
CY7C1370D
Description
Revision Number (31:29)
000
Reserved for version number.
Cypress Device ID (28:12) [21]
Cypress JEDEC ID (11:1)
ID Register Presence (0)
01011001000010101 Reserved for future use.
00000110100
1
Allows unique identification of SRAM vendor.
Indicate the presence of an ID register.
Scan Register Sizes
Register Name
Bit Size (× 36)
Instruction
3
1
Bypass
ID
32
89
Boundary Scan Order (165-ball FBGA package)
Identification Codes
Instruction
EXTEST
Code
Description
000
Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces
all SRAM outputs to High Z state.
IDCODE
001
010
Loads the ID register with the vendor ID code and places the register between TDI and TDO.
This operation does not affect SRAM operations.
SAMPLE Z
Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces
all SRAM output drivers to a High Z state.
RESERVED
011
100
Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD
Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Does
not affect SRAM operation.
RESERVED
RESERVED
BYPASS
101
110
111
Do Not Use: This instruction is reserved for future use.
Do Not Use: This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does not affect SRAM
operations.
Note
21. Bit #24 is “1” in the Register Definitions for both 2.5 V and 3.3 V versions of this device.
Document Number: 38-05555 Rev. *Q
Page 18 of 34
CY7C1370D
CY7C1372D
Boundary Scan Order
165-ball FBGA [22, 23]
Bit #
1
Ball ID
N6
Bit #
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
Ball ID
D10
C11
A11
B11
A10
B10
A9
Bit #
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
Ball ID
G1
D2
E2
2
N7
3
N10
P11
P8
4
F2
5
G2
H1
H3
J1
6
R8
7
R9
8
P9
B9
9
P10
R10
R11
H11
N11
M11
L11
K11
J11
M10
L10
K10
J10
H9
C10
A8
K1
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
L1
B8
M1
J2
A7
B7
K2
B6
L2
A6
M2
N1
N2
P1
B5
A5
A4
B4
R1
R2
P3
B3
A3
A2
R3
P2
H10
G11
F11
E11
D11
G10
F10
E10
B2
C2
R4
P4
B1
A1
N5
P6
C1
D1
R6
Internal
E1
F1
Notes
22. Balls which are NC (No Connect) are pre-set LOW.
23. Bit# 89 is preset HIGH.
Document Number: 38-05555 Rev. *Q
Page 19 of 34
CY7C1370D
CY7C1372D
Maximum Ratings
Operating Range
Ambient
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Range
VDD
VDDQ
Temperature
0 °C to +70 °C
–40 °C to +85 °C
Commercial
Industrial
3.3 V – 5% / 2.5 V – 5% to
Storage Temperature ............................... –65 °C to +150 °C
+10%
VDD
Ambient Temperature with
Power Applied ......................................... –55 °C to +125 °C
Supply Voltage on VDD Relative to GND .....–0.5 V to +4.6 V
Supply Voltage on VDDQ Relative to GND .... –0.5 V to +VDD
DC to Outputs in Tristate ..................–0.5 V to VDDQ + 0.5 V
DC Input Voltage ................................–0.5 V to VDD + 0.5 V
Current into Outputs (LOW) ........................................ 20 mA
Neutron Soft Error Immunity
Test
Parameter Description
Conditions
Typ Max* Unit
LSBU
LMBU
SEL
Logical
Single-Bit
Upsets
25 °C
25 °C
85 °C
361 394
FIT/
Mb
Static Discharge Voltage
(per MIL-STD-883, Method 3015) ...........................>2001V
Logical
Multi-Bit
Upsets
0
0
0.01 FIT/
Mb
Latch up Current ....................................................> 200 mA
Single Event
Latch up
0.1
FIT/
Dev
* No LMBU or SEL events occurred during testing; this column represents a
2
statistical , 95% confidence limit calculation. For more details refer to
Application Note AN54908 “Accelerated Neutron SER Testing and Calculation of
Terrestrial Failure Rates”.
Electrical Characteristics
Over the Operating Range
Parameter[24, 25]
Description
Power Supply Voltage
I/O Supply Voltage
Test Conditions
Min
3.135
3.135
2.375
2.4
Max
Unit
V
VDD
3.6
VDDQ
for 3.3 V I/O
for 2.5 V I/O
VDD
V
2.625
V
VOH
VOL
VIH
VIL
IX
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage[24]
Input LOW Voltage[24]
for 3.3 V I/O, IOH = –4.0 mA
for 2.5 V I/O, IOH = –1.0 mA
for 3.3 V I/O, IOL = 8.0 mA
for 2.5 V I/O, IOL = 1.0 mA
for 3.3 V I/O
–
V
2.0
–
0.4
V
–
V
–
0.4
V
2.0
VDD + 0.3 V
V
for 2.5 V I/O
1.7
V
DD + 0.3 V
V
for 3.3 V I/O
–0.3
–0.3
–5
0.8
0.7
5
V
for 2.5 V I/O
V
Input Leakage Current except ZZ GND VI VDDQ
and MODE
A
Input Current of MODE
Input = VSS
–30
–
–
5
A
A
A
A
A
Input = VDD
Input Current of ZZ
Input = VSS
–5
–
–
Input = VDD
30
5
IOZ
Output Leakage Current
GND VI VDDQ, Output Disabled
–5
Notes
24. Overshoot: V
< V + 1.5 V (Pulse width less than t
/2), undershoot: V
> –2 V (Pulse width less than t
/2).
IH(AC)
DD
CYC
IL(AC)
CYC
25. T
: Assumes a linear ramp from 0 V to V
within 200 ms. During this time V < V and V
<V
.
Power-up
DD(min.)
IH
DD
DDQ
DD
Document Number: 38-05555 Rev. *Q
Page 20 of 34
CY7C1370D
CY7C1372D
Electrical Characteristics (continued)
Over the Operating Range
Parameter[24, 25]
Description
Test Conditions
Min
Max
Unit
IDD
VDD Operating Supply
VDD = Max., IOUT = 0 mA,
f = fMAX = 1/tCYC
4-ns cycle,
250 MHz
–
350
mA
5-ns cycle,
200 MHz
–
–
–
–
–
–
300
275
160
150
140
70
mA
mA
mA
mA
mA
mA
6-ns cycle,
167 MHz
ISB1
Automatic CE Power-down
Current – TTL Inputs
Max. VDD, Device Deselected,
VIN VIH or VIN VIL,
f = fMAX = 1/tCYC
4-ns cycle,
250 MHz
5-ns cycle,
200 MHz
6-ns cycle,
167 MHz
ISB2
Automatic CE Power-down
Current – CMOS Inputs
Max. VDD, Device Deselected,
All speed
VIN 0.3 V or VIN > VDDQ 0.3 V, grades
f = 0
ISB3
Automatic CE Power-down
Current – CMOS Inputs
Max. VDD, Device Deselected,
4-ns cycle,
–
–
–
–
135
130
125
80
mA
mA
mA
mA
VIN 0.3 V or VIN > VDDQ 0.3 V, 250 MHz
f = fMAX = 1/tCYC
5-ns cycle,
200 MHz
6-ns cycle,
167 MHz
ISB4
Automatic CE Power-down
Current – TTL Inputs
Max. VDD, Device Deselected,
VIN VIH or VIN VIL, f = 0
All speed
grades
Capacitance
100-pin TQFP 165-ball FBGA
Parameter [26]
Description
Test Conditions
Unit
Max
Max
CIN
Input capacitance
TA = 25C, f = 1 MHz,
VDD = 3.3 V, VDDQ = 2.5 V
5
5
5
9
9
9
pF
pF
pF
CCLK
CI/O
Clock input capacitance
Input/Output capacitance
Thermal Resistance
100-pin TQFP 165-ballFBGA
Parameter [26]
Description
Test Conditions
Unit
Package
Package
JA
Thermal resistance
(junction to ambient)
Test conditions follow standard test
methods and procedures for measuring
thermal impedance, per EIA/JESD51.
28.66
20.7
C/W
JC
Thermal resistance
(junction to case)
4.08
4.0
C/W
Note
26. Tested initially and after any design or process change that may affect these parameters.
Document Number: 38-05555 Rev. *Q
Page 21 of 34
CY7C1370D
CY7C1372D
AC Test Loads and Waveforms
Figure 3. AC Test Loads and Waveforms
3.3V I/O Test Load
R = 317
3.3V
OUTPUT
R = 50
OUTPUT
ALL INPUT PULSES
90%
VDDQ
90%
10%
Z = 50
0
10%
L
GND
5 pF
R = 351
1 ns
1 ns
V = 1.5V
T
INCLUDING
JIG AND
SCOPE
(c)
(a)
(b)
2.5V I/O Test Load
R = 1667
2.5V
OUTPUT
R = 50
OUTPUT
ALL INPUT PULSES
90%
VDDQ
GND
90%
10%
Z = 50
0
10%
L
5 pF
R = 1538
1 ns
1 ns
V = 1.25V
T
INCLUDING
JIG AND
SCOPE
(c)
(a)
(b)
Document Number: 38-05555 Rev. *Q
Page 22 of 34
CY7C1370D
CY7C1372D
Switching Characteristics
Over the Operating Range
-250
-200
-167
Unit
Max
Parameter [27, 28]
Description
Min
Max
Min
Max
Min
[29]
tPower
VCC(typical)tothefirstaccessreador
write
1
–
1
–
1
–
ms
Clock
tCYC
Clock cycle time
Maximum operating frequency
Clock HIGH
4.0
–
–
250
–
5
–
–
200
–
6
–
–
167
–
ns
MHz
ns
FMAX
tCH
1.7
1.7
2.0
2.0
2.2
2.2
tCL
Clock LOW
–
–
–
ns
Output Times
tCO
Data output valid after CLK rise
OE LOW to output valid
–
–
2.6
2.6
–
–
–
3.0
3.0
–
–
–
3.4
3.4
–
ns
ns
ns
ns
ns
ns
ns
tEOV
tDOH
Data output hold after CLK rise
Clock to high Z [30, 31, 32]
Clock to low Z [30, 31, 32]
OE HIGH to output high Z [30, 31, 32]
OE LOW to output low Z [30, 31, 32]
1.0
–
1.3
–
1.3
–
tCHZ
2.6
–
3.0
–
3.4
–
tCLZ
1.0
–
1.3
–
1.3
–
tEOHZ
tEOLZ
Setup Times
tAS
2.6
–
3.0
–
3.4
–
0
0
0
Address setup before CLK rise
Data input setup before CLK rise
CEN setup before CLK rise
WE, BWx setup before CLK rise
ADV/LD setup before CLK rise
Chip select setup
1.2
1.2
1.2
1.2
1.2
1.2
–
–
–
–
–
–
1.4
1.4
1.4
1.4
1.4
1.4
–
–
–
–
–
–
1.5
1.5
1.5
1.5
1.5
1.5
–
–
–
–
–
–
ns
ns
ns
ns
ns
ns
tDS
tCENS
tWES
tALS
tCES
Hold Times
tAH
Address hold after CLK rise
Data input hold after CLK rise
CEN hold after CLK rise
0.3
0.3
0.3
0.3
0.3
0.3
–
–
–
–
–
–
0.4
0.4
0.4
0.4
0.4
0.4
–
–
–
–
–
–
0.5
0.5
0.5
0.5
0.5
0.5
–
–
–
–
–
–
ns
ns
ns
ns
ns
ns
tDH
tCENH
tWEH
WE, BWx hold after CLK rise
ADV/LD hold after CLK rise
Chip select hold after CLK rise
tALH
tCEH
Notes
27. Timing reference is 1.5 V when V
= 3.3 V and is 1.25 V when V
= 2.5 V.
DDQ
DDQ
28. Test conditions shown in (a) of Figure 3 on page 22 unless otherwise noted.
29. This part has a voltage regulator internally; t is the time power needs to be supplied above V minimum initially, before a Read or Write operation can be initiated.
Power
DD
30. t
, t
, t
, and t
are specified with AC test conditions shown in (b) of Figure 3 on page 22. Transition is measured ±200 mV from steady-state voltage.
CHZ CLZ EOLZ
EOHZ
31. At any given voltage and temperature, t
is less than t
and t
is less than t
to eliminate bus contention between SRAMs when sharing the same data
CLZ
EOHZ
EOLZ
CHZ
bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve
High Z prior to Low Z under the same system conditions.
32. This parameter is sampled and not 100% tested.
Document Number: 38-05555 Rev. *Q
Page 23 of 34
CY7C1370D
CY7C1372D
Switching Waveforms
Figure 4. Read/Write/Timing [33, 34, 35]
1
2
3
4
5
6
7
8
9
10
t
CYC
t
CLK
t
t
t
CENS
CENH
CL
CH
CEN
t
t
CES
CEH
CE
ADV/LD
WE
BW
x
A1
A2
A4
CO
A3
A5
A6
A7
ADDRESS
t
t
t
t
DS
DH
t
t
t
DOH
OEV
CLZ
CHZ
t
t
AS
AH
Data
D(A1)
D(A2)
D(A2+1)
Q(A3)
Q(A4)
Q(A4+1)
D(A5)
Q(A6)
In-Out (DQ)
t
OEHZ
t
DOH
t
OELZ
OE
WRITE
D(A1)
WRITE
D(A2)
BURST
WRITE
READ
Q(A3)
READ
Q(A4)
BURST
READ
WRITE
D(A5)
READ
Q(A6)
WRITE
D(A7)
DESELECT
D(A2+1)
Q(A4+1)
DON’T CARE
UNDEFINED
Notes
33. For this waveform ZZ is tied LOW.
34. When CE is LOW, CE is LOW, CE is HIGH and CE is LOW. When CE is HIGH,CE is HIGH or CE is LOW or CE is HIGH.
1
2
3
1
2
3
35. Order of the Burst sequence is determined by the status of the MODE (0 = Linear, 1 = Interleaved).Burst operations are optional.
Document Number: 38-05555 Rev. *Q
Page 24 of 34
CY7C1370D
CY7C1372D
Switching Waveforms (continued)
Figure 5. NOP, STALL, and DESELECT Cycles [36, 37, 38]
1
2
3
4
5
6
7
8
9
10
CLK
CEN
CE
ADV/LD
WE
BWx
A1
A2
A3
A4
A5
ADDRESS
t
CHZ
D(A4)
D(A1)
Q(A2)
Q(A3)
Q(A5)
Data
In-Out (DQ)
WRITE
D(A1)
READ
Q(A2)
STALL
READ
Q(A3)
WRITE
D(A4)
STALL
NOP
READ
Q(A5)
DESELECT
CONTINUE
DESELECT
DON’T CARE
UNDEFINED
Figure 6. ZZ Mode Timing [39, 40]
CLK
t
t
ZZ
ZZREC
ZZ
t
ZZI
I
SUPPLY
I
DDZZ
t
RZZI
ALL INPUTS
(except ZZ)
DESELECT or READ Only
Outputs (Q)
High-Z
DON’T CARE
Notes
36. For this waveform ZZ is tied LOW.
37. When CE is LOW, CE is LOW, CE is HIGH and CE is LOW. When CE is HIGH,CE is HIGH or CE is LOW or CE is HIGH.
1
2
3
1
2
3
38. The Ignore Clock Edge or Stall cycle (Clock 3) illustrated CEN being used to create a pause. A write is not performed during this cycle.
39. Device must be deselected when entering ZZ mode. See cycle description table for all possible signal conditions to deselect the device.
40. I/Os are in High Z when exiting ZZ sleep mode.
Document Number: 38-05555 Rev. *Q
Page 25 of 34
CY7C1370D
CY7C1372D
Ordering Information
Cypress offers other versions of this type of product in many different configurations and features. The following table contains only
the list of parts that are currently available.
For a complete listing of all options, visit the Cypress website at www.cypress.com and refer to the product summary page at
http://www.cypress.com/products or contact your local sales representative.
Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives and distributors. To find the office
closest to you, visit us at http://www.cypress.com/go/datasheet/offices.
Speed
(MHz)
Package
Diagram
Operating
Range
Part and Package Type
Ordering Code
167 CY7C1370D-167AXC
CY7C1372D-167AXC
CY7C1370D-167BZXC
CY7C1370D-167AXI
51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free
Commercial
51-85180 165-ball FBGA (13 × 15 × 1.4 mm) Pb-free
51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free
Industrial
CY7C1372D-167AXI
200 CY7C1370D-200AXC
CY7C1372D-200AXC
CY7C1370D-200BZC
CY7C1370D-200BZI
51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free
51-85180 165-ball FBGA (13 × 15 × 1.4 mm)
Commercial
Industrial
CY7C1370D-200AXI
51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free
51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free
250 CY7C1370D-250AXC
CY7C1370D-250AXI
Commercial
Industrial
Ordering Code Definitions
CY 7 C 13XX D - XXX XX X
X
Temperature Range: X = C or I
C = Commercial = 0 C to +70 C; I = Industrial = –40 C to +85 C
X = Pb-free; X Absent = Leaded
Package Type: XX = A or BZ
A = 100-pin TQFP
BZ = 165-ball FBGA
Speed Grade: XXX = 167 MHz or 200 MHz or 250 MHz
Process Technology: D 90 nm
Part Identifier: 13XX = 1370 or 1372
1370 = PL, 512 Kb × 36 (18 Mb)
1372 = PL, 1 Mb × 18 (18 Mb)
Technology Code: C = CMOS
Marketing Code: 7 = SRAM
Company ID: CY = Cypress
Document Number: 38-05555 Rev. *Q
Page 26 of 34
CY7C1370D
CY7C1372D
Package Diagrams
Figure 7. 100-pin TQFP (14 × 20 × 1.4 mm) A100RA Package Outline, 51-85050
51-85050 *D
Document Number: 38-05555 Rev. *Q
Page 27 of 34
CY7C1370D
CY7C1372D
Package Diagrams (continued)
Figure 8. 165-ball FBGA (13 × 15 × 1.4 mm) BB165D/BW165D (0.5 Ball Diameter) Package Outline, 51-85180
51-85180 *F
Document Number: 38-05555 Rev. *Q
Page 28 of 34
CY7C1370D
CY7C1372D
Acronyms
Document Conventions
Units of Measure
Acronym
Description
CE
Chip Enable
Clock Enable
Symbol
°C
Unit of Measure
CEN
CMOS
FBGA
I/O
degree Celsius
kilohm
Complementary Metal Oxide Semiconductor
Fine-Pitch Ball Grid Array
Input/Output
k
MHz
µA
µs
megahertz
microampere
microsecond
milliampere
millivolt
JTAG
LMBU
LSB
Joint Test Action Group
Logical Multi-Bit Upsets
Least Significant Bit
Logical Single-Bit Upsets
Most Significant Bit
No Bus Latency
mA
mV
mm
ms
ns
LSBU
MSB
NoBL
OE
millimeter
millisecond
nanosecond
ohm
Output Enable
SEL
Single Event Latch-up
Static Random Access Memory
Test Access Port
%
percent
SRAM
TAP
pF
ps
picofarad
picosecond
volt
TCK
TMS
TDI
Test Clock
V
Test Mode Select
W
watt
Test Data-In
TDO
TQFP
TTL
Test Data-Out
Thin Quad Flat Pack
Transistor-Transistor Logic
Write Enable
WE
Document Number: 38-05555 Rev. *Q
Page 29 of 34
CY7C1370D
CY7C1372D
Errata
This section describes the Ram9 NoBL ZZ pin and JTAG issues. Details include trigger conditions, the devices affected, proposed
workaround and silicon revision applicability. Please contact your local Cypress sales representative if you have further questions.
Part Numbers Affected
Density & Revision
Package Type Operating Range
18Mb-Ram9 NoBL SRAMs: CY7C137*D
100-pin TQFP
165-ball FBGA
Commercial/
Industrial
Product Status
All of the devices in the Ram9 18Mb NoBL family are qualified and available in production quantities.
Ram9 NoBL ZZ Pin & JTAG Issues Errata Summary
The following table defines the errata applicable to available Ram9 18Mb NoBL family devices.
Item
Issues
Description
Device
Fix Status
1. ZZ Pin
When asserted HIGH, the ZZ pin places
deviceina“sleep”conditionwithdataintegrity
preserved.The ZZ pin currently does not have
an internal pull-down resistor and hence
cannot be left floating externally by the user
during normal mode of operation.
18M-Ram9 (90nm)
For the 18M Ram9 (90 nm)
devices, there is no plan to fix
this issue.
2. JTAG
During JTAG test mode, the Boundary scan
18M-Ram9 (90nm)
This issue will be fixed in the
new revision, which use the
65 nm technology. Please
contact your local sales rep for
availability.
Functionality circuitry does not perform as described in the
datasheet.However, it is possible to perform
the JTAG test with these devices in “BYPASS
mode”.
Document Number: 38-05555 Rev. *Q
Page 30 of 34
CY7C1370D
CY7C1372D
1. ZZ Pin Issue
■ PROBLEM DEFINITION
The problem occurs only when the device is operated in the normal mode with ZZ pin left floating. The ZZ pin on the SRAM
device does not have an internal pull-down resistor. Switching noise in the system may cause the SRAM to recognize a HIGH
on the ZZ input, which may cause the SRAM to enter sleep mode. This could result in incorrect or undesirable operation of the
SRAM.
■ TRIGGER CONDITIONS
Device operated with ZZ pin left floating.
■ SCOPE OF IMPACT
When the ZZ pin is left floating, the device delivers incorrect data.
■ WORKAROUND
Tie the ZZ pin externally to ground.
■ FIX STATUS
For the 18M Ram9 (90 nm) devices, there is no plan to fix this issue.
2. JTAG Functionality
■ PROBLEM DEFINITION
The problem occurs only when the device is operated in the JTAG test mode.During this mode, the JTAG circuitry can perform
incorrectly by delivering the incorrect data or the incorrect scan chain length.
■ TRIGGER CONDITIONS
Several conditions can trigger this failure mode.
1. The device can deliver an incorrect length scan chain when operating in JTAG mode.
2. Some Byte Write inputs only recognize a logic HIGH level when in JTAG mode.
3. Incorrect JTAG data can be read from the device when the ZZ input is tied HIGH during JTAG operation.
■ SCOPE OF IMPACT
The device fails for JTAG test. This does not impact the normal functionality of the device.
■ WORKAROUND
1.Perform JTAG testing with these devices in “BYPASS mode”.
2.Do not use JTAG test.
■ FIX STATUS
This issue will be fixed in the new revision, which use the 65 nm technology. Please contact your local sales rep for availability
Document Number: 38-05555 Rev. *Q
Page 31 of 34
CY7C1370D
CY7C1372D
Document History Page
Document Title: CY7C1370D/CY7C1372D, 18-Mbit (512 K × 36/1 M × 18) Pipelined SRAM with NoBL™ Architecture
Document Number: 38-05555
Orig. of
Change
Submission
Date
Rev.
ECN No.
Description of Change
**
254509
276690
RKF
VBL
See ECN New data sheet.
*A
See ECN Updated Ordering Information (Changed TQFP package to Lead-free TQFP
package in Ordering Information section, added comment of Lead-free BG and
BZ packages availability).
*B
*C
288531
326078
SYT
PCI
See ECN Updated IEEE 1149.1 Serial Boundary Scan (JTAG [17]) (Edited description
for non-compliance with 1149.1).
Updated Ordering Information (Added lead-free information for 100-pin TQFP,
119-ball BGA and 165-ball FBGA Packages).
See ECN Changed status from Preliminary to Final.
Updated Selection Guide (Removed shading).
Updated Pin Configurations (Address expansion pins/balls in the pinouts for
all packages are modified as per JEDEC standard).
Updated IEEE 1149.1 Serial Boundary Scan (JTAG [17]) (Updated TAP
Instruction Set (Updated OVERVIEW (Updated description), updated EXTEST
(Updated description), added EXTEST Output Bus Tristate)).
Updated Electrical Characteristics (Removed shading, updated Test
Conditions of VOL, VOH parameters).
Updated Thermal Resistance (Changed values of JA and JC parameters for
100-pin TQFP Package from 31 C/W and 6 C/W to 28.66 C/W and
4.08 C/W respectively, changed values of JA and JC parameters for
119-ball BGA Package from 45 C/W and 7 C/W to 23.8 C/W and 6.2 C/W
respectively, changed values of JA and JC parameters for 165-ball FBGA
Package from 46 C/W and 3 C/W to 20.7 C/W and 4.0 C/W respectively).
Updated Switching Characteristics (Removed shading).
Updated Ordering Information (Updated part numbers, removed comment of
“Lead-free BG packages availability” below the Ordering Information).
*D
*E
370734
416321
PCI
See ECN Updated Electrical Characteristics (Updated Note 25 (Modified test condition
from VDDQ < VDD to VDDQ VDD)).
NXR
See ECN Changed address of Cypress Semiconductor Corporation from “3901 North
First Street” to “198 Champion Court”
Updated Electrical Characteristics (Updated Note 25 (Modified test condition
from VIH < VDD to VIH < VDD, changed “Input Load Current except ZZ and
MODE” to “Input Leakage Current except ZZ and MODE”, changed maximum
value of IX parameter corresponding to Input Current of MODE (Input = VSS
)
from –5 A to –30 A, changed minimum value of IX parameter corresponding
to Input Current of MODE (Input = VDD) from 30 A to 5 A, changed maximum
value of IX parameter corresponding to Input Current of ZZ (Input = VSS) from
–30 A to –5 A, changed minimum value of IX parameter corresponding to
Input Current of ZZ (Input = VDD) from 5 A to 30 A).
Updated Ordering Information (Updated part numbers, replaced Package
Name column with Package Diagram in the Ordering Information table).
Replaced three-state with tri-state in all instances across the document.
*F
475677
VKN
VKN
See ECN Updated TAP AC Switching Characteristics Changed minimum value of tTH
TL parameters from 25 ns to 20 ns, changed maximum value of tTDOV
parameter from 5 ns to 10 ns).
,
t
Updated Maximum Ratings (Added the Maximum Rating for Supply Voltage
on VDDQ Relative to GND).
Updated Ordering Information (Updated part numbers).
*G
2756940
08/27/2009 Added Neutron Soft Error Immunity.
Updated Ordering Information (By including parts that are available, and
modified the disclaimer for the Ordering information).
Document Number: 38-05555 Rev. *Q
Page 32 of 34
CY7C1370D
CY7C1372D
Document History Page (continued)
Document Title: CY7C1370D/CY7C1372D, 18-Mbit (512 K × 36/1 M × 18) Pipelined SRAM with NoBL™ Architecture
Document Number: 38-05555
Orig. of
Change
Submission
Date
Rev.
ECN No.
Description of Change
*H
2896585
NJY
03/21/2010 Updated Ordering Information (Removed obsolete parts from Ordering
Information table).
Updated Package Diagrams.
Updated Sales, Solutions, and Legal Information section.
Updated in new template.
*I
2906603
3055192
NJY
NJY
04/07/2010 Updated Ordering Information (Removed inactive part from Ordering
Information table).
*J
10/11/2010 Updated Ordering Information (Updated part numbers) and added Ordering
Code Definitions.
*K
*L
3067198
3306791
NJY
10/20/2010 Updated Ordering Information (Updated part numbers).
OSN
07/08/2011 Updated Package Diagrams.
Added Acronyms and Units of Measure.
Updated in new template.
*M
3618004
PRIT
05/15/2012 Updated Features (Removed 119-ball BGA package related information).
Updated Pin Configurations (Removed 119-ball BGA package related
information, updated Figure 2 (Removed CY7C1372D related information)).
Updated IEEE 1149.1 Serial Boundary Scan (JTAG [17]) (Removed
CY7C1372D related information).
Updated Identification Register Definitions (Removed CY7C1372D related
information).
Updated Scan Register Sizes (Removed “Bit Size (× 18)” column, removed
119-ball BGA package related information).
Removed Boundary Scan Order (Corresponding to 119-ball BGA package).
Updated Capacitance (Removed 119-ball BGA package related information).
Updated Thermal Resistance (Removed 119-ball BGA package related
information).
Updated Ordering Information (Updated part numbers).
Updated Package Diagrams (Removed 119-ball BGA package related
information (spec 51-85115), spec 51-85180 (changed revision from *C to *E)).
*N
*O
3666992
3981545
PRIT
PRIT
07/05/2012 No technical updates.
Completing Sunset review.
05/02/2013 Updated Package Diagrams:
spec 51-85180 – Changed revision from *E to *F.
Added Errata.
*P
4070421
PRIT
07/20/2013 Added Errata footnotes (Note 1, 2, 3, 4, 5, 17).
Updated Pin Configurations:
Added Note 1 and referred the same note in Figure 1.
Added Note 2, 3 and referred the same note in Figure 2.
Updated Pin Definitions:
Added Note 4 and referred the same note in ZZ pin.
Added Note 5 and referred the same note in TDO, TDI, TMS, TCK pins.
Updated IEEE 1149.1 Serial Boundary Scan (JTAG [17]):
Added Note 17 and referred the same note in JTAG in the heading.
Updated in new template.
Completing Sunset Review.
10/09/2013 Updated Errata.
*Q
4151890
PRIT
Document Number: 38-05555 Rev. *Q
Page 33 of 34
CY7C1370D
CY7C1372D
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
®
Products
PSoC Solutions
Automotive
cypress.com/go/automotive
cypress.com/go/clocks
cypress.com/go/interface
cypress.com/go/powerpsoc
cypress.com/go/plc
psoc.cypress.com/solutions
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP
Clocks & Buffers
Interface
Cypress Developer Community
Lighting & Power Control
Community | Forums | Blogs | Video | Training
Technical Support
Memory
cypress.com/go/memory
cypress.com/go/psoc
cypress.com/go/support
PSoC
Touch Sensing
USB Controllers
Wireless/RF
cypress.com/go/touch
cypress.com/go/USB
cypress.com/go/wireless
© Cypress Semiconductor Corporation, 2004-2013. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 38-05555 Rev. *Q
Revised October 9, 2013
Page 34 of 34
ZBT is a trademark of Integrated Device Technology, Inc. NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation. All products and company names mentioned in this
document may be the trademarks of their respective holders.
相关型号：
CY7C1370D-200BGCT
ZBT SRAM, 512KX36, 3ns, CMOS, PBGA119, (14 X 22 X 2.4) MM, PLASTIC, BGA-119
CYPRESS
CY7C1370D-200BZIT
ZBT SRAM, 512KX36, 3ns, CMOS, PBGA165, 13 X 15 MM, 1.40 MM HEIGHT, MO-216, FBGA-165
CYPRESS
©2020 ICPDF网 联系我们和版权申明