CY7C1361C_2009 [CYPRESS]
9-Mbit (256K x 36/512K x 18) Flow-Through SRAM; 9兆位（ 256K ×36 / 512K ×18 ）流通型SRAM
| 型号： | CY7C1361C_2009 |
| 厂家： | 
CYPRESS |
| 描述： | 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM |
| 文件： | 总32页 (文件大小：1085K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C1361C/CY7C1363C
9-Mbit (256K x 36/512K x 18)
Flow-Through SRAM
Features
Functional Description
■ Supports 100, 133 MHz Bus Operations
■ Supports 100 MHz Bus Operations (Automotive)
■ 256K × 36/512K × 18 Common I/O
The CY7C1361C/CY7C1363C[1] is a 3.3V, 256K x 36/512K x 18
synchronous flow-through SRAMs, respectively designed to
interface with high speed microprocessors with minimum glue
logic. Maximum access delay from clock rise is 6.5 ns (133 MHz
version). A 2-bit on-chip counter captures the first address in a
burst and increments the address automatically for the rest of the
burst access. All synchronous inputs are gated by registers
controlled by a positive-edge-triggered Clock Input (CLK). The
synchronous inputs include all addresses, all data inputs,
address-pipelining Chip Enable (CE1), depth-expansion Chip
Enables (CE2 and CE3[2]), Burst Control inputs (ADSC, ADSP,
and ADV), Write Enables (BWx, and BWE), and Global Write
(GW). Asynchronous inputs include the Output Enable (OE) and
the ZZ pin.
■ 3.3V –5% and +10% Core Power Supply (VDD
)
■ 2.5V or 3.3V I/O Power Supply (VDDQ
)
■ Fast Clock-to-Output Times
❐ 6.5 ns (133-MHz version)
■ Provide High Performance 2-1-1-1 Access Rate
■ User-selectable Burst Counter supporting Intel® Pentium®
Interleaved or Linear Burst Sequences
The CY7C1361C/CY7C1363C enables either interleaved or
linear burst sequences, selected by the MODE input pin. A HIGH
selects an interleaved burst sequence, while a LOW selects a
linear burst sequence. Burst accesses can be initiated with the
Processor Address Strobe (ADSP) or the cache Controller
Address Strobe (ADSC) inputs. Address advancement is
controlled by the Address Advancement (ADV) input.
■ Separate Processor and Controller Address Strobes
■ Synchronous Self-timed Write
■ Asynchronous Output Enable
■ Available in Pb-free 100-Pin TQFP Package, Pb-free and non
Pb-free 119-Ball BGA Package, and 165-Ball FBGA Package
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP) or Address
Strobe Controller (ADSC) are active. Subsequent burst
addresses can be internally generated as controlled by the
Advance pin (ADV).
■ TQFP Available with 3-Chip Enable and 2-Chip Enable
■ IEEE 1149.1 JTAG-Compatible Boundary Scan
■ “ZZ” Sleep Mode option
The CY7C1361C/CY7C1363C operates from a +3.3V core
power supply while all outputs may operate with either a +2.5 or
+3.3V supply. All inputs and outputs are JEDEC-standard
JESD8-5-compatible.
Selection Guide
Description
Maximum Access Time
133 MHz
6.5
100 MHz
8.5
Unit
ns
Maximum Operating Current
250
180
mA
mA
Maximum CMOS Standby Current
Commercial/
Industrial
40
40
Automotive
60
mA
Notes
1. For best-practices recommendations, refer to the Cypress application note System Design Guidelines on www.cypress.com.
2. CE is for A version of TQFP (3 Chip Enable Option) and 165 FBGA package only. 119 BGA is offered only in 2 Chip Enable.
3
Cypress Semiconductor Corporation
Document #: 38-05541 Rev. *G
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised August 26, 2009
[+] Feedback
CY7C1361C/CY7C1363C
Logic Block Diagram – CY7C1361C (256K x 36)
ADDRESS
REGISTER
A0, A1,
A
A
[1:0]
MODE
ADV
CLK
Q1
Q0
BURST
COUNTER
AND LOGIC
CLR
ADSC
ADSP
DQ
BYTE
WRITE REGISTER
D, DQP D
DQ
BYTE
WRITE REGISTER
D, DQP D
BW
D
DQ C, DQP
BYTE
C
DQ C, DQP
BYTE
C
BW
C
WRITE REGISTER
OUTPUT
BUFFERS
DQ s
WRITE REGISTER
MEMORY
ARRAY
SENSE
AMPS
DQP
DQP
DQP
DQP
A
DQ B, DQP
BYTE
B
B
C
D
DQ B, DQP
BYTE
B
BW
B
WRITE REGISTER
WRITE REGISTER
DQ A, DQP
BYTE
A
DQ A, DQP
A
BW
A
WRITE REGISTER
BYTE
BWE
WRITE REGISTER
INPUT
GW
REGISTERS
ENABLE
REGISTER
CE1
CE2
CE3
OE
SLEEP
CONTROL
ZZ
Logic Block Diagram – CY7C1363C (512K x 18)
ADDRESS
REGISTER
A0,A1,A
A[1:0]
MODE
Q1
ADV
CLK
BURST
COUNTER AND
LOGIC
CLR
Q0
ADSC
ADSP
DQ B,DQP B
WRITE DRIVER
DQ B,DQP B
WRITE REGISTER
BW B
MEMORY
ARRAY
OUTPUT
BUFFERS
DQs
DQP
DQP
SENSE
AMPS
A
B
DQ A,DQP A
WRITE DRIVER
DQ A,DQP A
WRITE REGISTER
BW A
BWE
INPUT
REGISTERS
GW
ENABLE
REGISTER
CE
1
CE2
CE3
OE
ZZ
SLEEP
CONTROL
Document #: 38-05541 Rev. *G
Page 2 of 32
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CY7C1361C/CY7C1363C
Pin Configurations
Figure 1. 100-Pin TQFP (3 Chip Enables - A version)
DQPC
1
DQPB
DQB
DQB
VDDQ
VSSQ
DQB
DQB
DQB
DQB
VSSQ
VDDQ
DQB
DQB
VSS
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
NC
NC
VDDQ
VSSQ
NC
A
NC
NC
VDDQ
VSSQ
NC
DQPA
DQA
DQA
VSSQ
VDDQ
DQA
DQA
VSS
NC
1
2
3
4
5
6
7
8
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQC
2
DQC
VDDQ
VSSQ
DQC
3
4
5
6
DQC
7
NC
DQC
8
DQB
DQB
VSSQ
VDDQ
DQB
DQB
VSS/DNU
VDD
DQC
9
10
11
9
VSSQ
VDDQ
DQC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
12
DQC
13
VSS/DNU
14
VDD
15
NC
VDD
ZZ
CY7C1363C
(512K x 18)
CY7C1361C (A)
(256K x 36)
NC
16
NC
VSS
VDD
ZZ
VSS
17
DQD
18
DQA
DQA
VDDQ
VSSQ
DQA
DQA
DQA
DQA
VSSQ
VDDQ
DQA
DQA
DQPA
DQB
DQB
VDDQ
VSSQ
DQB
DQB
DQPB
NC
VSSQ
VDDQ
NC
NC
NC
DQA
DQA
VDDQ
VSSQ
DQA
DQA
NC
DQD
19
20
21
VDDQ
VSSQ
DQD
22
DQD
23
DQD
24
DQD
25
26
27
NC
VSSQ
VDDQ
DQD
DQD
29
VSSQ
VDDQ
NC
NC
NC
28
DQPD
30
Document #: 38-05541 Rev. *G
Page 3 of 32
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CY7C1361C/CY7C1363C
Figure 2. 100-Pin TQFP (2 Chip Enables - AJ Version)
DQPC
DQC
DQC
VDDQ
VSSQ
DQC
DQC
DQC
DQC
VSSQ
VDDQ
DQC
DQC
VSS/DNU
DQPB
DQB
DQB
VDDQ
VSSQ
DQB
DQB
DQB
DQB
VSSQ
VDDQ
DQB
DQB
VSS
1
2
3
4
5
6
7
8
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
NC
NC
VDDQ
VSSQ
NC
A
NC
NC
VDDQ
VSSQ
NC
DQPA
DQA
DQA
VSSQ
VDDQ
DQA
DQA
VSS
NC
1
2
3
4
5
6
7
8
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
DQB
DQB
VSSQ
VDDQ
DQB
DQB
VSS/DNU
VDD
9
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
VDD
NC
VSS
DQD
NC
VDD
ZZ
CY7C1363C
(512K x 18)
CY7C1361C
(256K x 36)
NC
VSS
VDD
ZZ
DQA
DQA
VDDQ
VSSQ
DQA
DQA
DQA
DQA
VSSQ
VDDQ
DQA
DQA
DQPA
DQB
DQB
VDDQ
VSSQ
DQB
DQB
DQPB
NC
VSSQ
VDDQ
NC
NC
NC
DQA
DQA
VDDQ
VSSQ
DQA
DQA
NC
DQD
VDDQ
VSSQ
DQD
DQD
DQD
DQD
NC
VSSQ
VDDQ
DQD
DQD
DQPD
VSSQ
VDDQ
NC
NC
NC
Document #: 38-05541 Rev. *G
Page 4 of 32
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CY7C1361C/CY7C1363C
Figure 3. 100- Ball BGA (2 Chip Enables with JTAG)
CY7C1361C (256K x 36)
1
2
3
4
5
6
7
VDDQ
A
A
A
A
VDDQ
A
ADSP
B
C
NC/288M
NC/144M
CE2
A
A
A
A
A
A
A
NC/512M
NC/1G
ADSC
VDD
DQC
DQC
VDDQ
DQPC
DQC
VSS
VSS
VSS
NC
CE1
OE
VSS
VSS
VSS
DQPB
DQB
DQB
DQB
D
E
F
DQC
DQB
VDDQ
DQC
DQC
VDDQ
DQD
DQC
DQC
VDD
DQB
DQB
VDD
DQA
DQB
DQB
VDDQ
DQA
G
H
J
BWC
VSS
NC
ADV
BWB
VSS
NC
GW
VDD
DQD
VSS
CLK
NC
VSS
K
L
M
N
DQD
VDDQ
DQD
DQD
DQD
DQD
DQA
DQA
DQA
DQA
VDDQ
DQA
BWD
VSS
VSS
BWA
VSS
VSS
BWE
A1
P
R
DQD
NC
DQPD
A
VSS
A0
VSS
NC
DQPA
A
DQA
NC
MODE
VDD
T
NC
NC/72M
TMS
A
A
A
NC/36M
NC
ZZ
U
VDDQ
TDI
TCK
TDO
VDDQ
CY7C1363C (512K x 18)
2
A
1
3
A
4
5
6
7
VDDQ
NC/512M
NC/1G
NC
A
B
C
D
E
F
VDDQ
A
A
ADSP
NC/288M
NC/144M
DQB
CE2
A
A
A
ADSC
VDD
A
A
A
A
NC
DQB
NC
VSS
VSS
VSS
NC
VSS
VSS
VSS
VSS
VSS
DQPA
NC
NC
DQA
CE1
OE
VDDQ
DQA
VDDQ
G
H
J
NC
DQB
NC
VDD
NC
DQA
VDD
DQA
NC
VDDQ
BWB
VSS
NC
ADV
DQB
VDDQ
GW
VDD
NC
NC
DQB
VSS
CLK
NC
VSS
NC
DQA
K
L
DQB
VDDQ
DQB
NC
NC
DQB
NC
VSS
VSS
VSS
VSS
DQA
NC
NC
VDDQ
NC
BWA
VSS
M
N
P
BWE
A1
VSS
VSS
DQA
NC
DQPB
A0
DQA
R
T
NC
A
A
MODE
A
VDD
NC/36M
TCK
NC
A
A
A
NC
ZZ
NC/72M
VDDQ
U
TMS
TDI
TDO
NC
VDDQ
Document #: 38-05541 Rev. *G
Page 5 of 32
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CY7C1361C/CY7C1363C
Figure 4. 165-Ball FBGA (3 Chip Enable)
CY7C1361C (256K x 36)
1
2
A
3
CE1
4
BWC
5
BWB
6
CE3
7
8
9
ADV
10
A
11
NC
NC/288M
NC/144M
DQPC
BWE
GW
VSS
VSS
ADSC
A
B
C
D
A
CE2
VDDQ
VDDQ
BWD
VSS
BWA
VSS
VSS
CLK
VSS
VSS
OE
VSS
VDD
ADSP
VDDQ
VDDQ
A
NC/576M
DQPB
DQB
NC
DQC
NC/1G
DQB
DQC
VDD
DQC
DQC
DQC
DQC
VSS
VDDQ
VDDQ
VDDQ
NC
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
NC
DQB
DQB
DQB
NC
DQB
E
F
DQC
DQC
NC
VSS
VSS
VSS
VSS
VSS
VSS
DQB
DQB
ZZ
G
H
J
DQD
DQD
DQD
DQD
DQD
DQD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
DQA
DQA
DQA
DQA
DQA
DQA
K
L
DQD
DQPD
NC
DQD
NC
VDDQ
VDDQ
A
VDD
VSS
A
VSS
NC
VSS
VSS
NC
VDD
VSS
A
VDDQ
VDDQ
A
DQA
NC
A
DQA
DQPA
A
M
N
P
NC/18M
A1
NC/72M
TDI
TDO
A0
MODE
NC/36M
A
A
TMS
TCK
A
A
A
A
R
CY7C1363C (512K x 18)
1
2
A
3
CE1
4
BWB
5
NC
6
CE
7
8
9
ADV
10
A
11
A
NC/288M
NC/144M
NC
BWE
GW
VSS
VSS
ADSC
A
3
A
CE2
VDDQ
VDDQ
NC
VSS
VDD
BWA
VSS
VSS
CLK
VSS
VSS
OE
VSS
VDD
ADSP
VDDQ
VDDQ
A
NC/576M
DQPA
DQA
B
C
D
NC
NC/1G
NC
NC
DQB
NC
DQB
DQB
DQB
VSS
NC
VDDQ
VDDQ
VDDQ
NC
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
NC
NC
NC
DQA
E
F
NC
NC
VSS
VSS
VSS
VSS
VSS
VSS
DQA
DQA
ZZ
NC
G
H
J
VSS
DQB
DQB
DQB
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
DQA
DQA
DQA
NC
NC
NC
K
L
NC
NC
DQB
DQPB
NC
NC
NC
VDDQ
VDDQ
A
VDD
VSS
A
VSS
NC
VSS
NC/18M
A1
VSS
NC
VDD
VSS
A
VDDQ
VDDQ
A
DQA
NC
A
NC
NC
A
M
N
P
NC/72M
TDI
TDO
MODE
NC/36M
A
A
TMS
A0
TCK
A
A
A
A
R
Document #: 38-05541 Rev. *G
Page 6 of 32
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CY7C1361C/CY7C1363C
Pin Definitions
Name
I/O
Description
A0, A1, A
Input-
Address Inputs used to select one of the address locations. Sampled at the rising
Synchronous edge of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3[2] are sampled
active. A[1:0] feed the 2-bit counter.
BWA,BWB
BWC,BWD
Input-
Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes to the
Synchronous SRAM. Sampled on the rising edge of CLK.
GW
CLK
CE1
Input-
Global Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK, a
Synchronous global write is conducted (ALL bytes are written, regardless of the values on BWX and BWE).
Input-
Clock
Clock Input. Used to capture all synchronous inputs to the device. Also used to increment
the burst counter when ADV is asserted LOW, during a burst operation.
Input-
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in
Synchronous conjunction with CE2 and CE3[2] to select/deselect the device. ADSP is ignored if CE1 is
HIGH. CE1 is sampled only when a new external address is loaded.
CE2
Input-
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in
Synchronous conjunction with CE1 and CE3[2] to select/deselect the device. CE2 is sampled only when
a new external address is loaded.
[2]
CE3
Input-
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in
Synchronous conjunction with CE1 and CE2 to select/deselect the device.CE3 is sampled only when a
new external address is loaded.
OE
Input-
Output Enable, asynchronous input, active LOW. Controls the direction of the I/O pins.
Asynchronous When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are
tristated, and act as input data pins. OE is masked during the first clock of a read cycle when
emerging from a deselected state.
ADV
Input-
Advance Input signal, sampled on the rising edge of CLK. When asserted, it automat-
Synchronous ically increments the address in a burst cycle.
ADSP
Input-
Address Strobe from Processor, sampled on the rising edge of CLK, active LOW.
Synchronous When asserted LOW, addresses presented to the device are captured in the address
registers. A[1:0] are also loaded into the burst counter. When ADSP and ADSC are both
asserted, only ADSP is recognized. ASDP is ignored when
is deasserted HIGH.
CE1
ADSC
Input-
Address Strobe from Controller, sampled on the rising edge of CLK, active LOW.
Synchronous When asserted LOW, addresses presented to the device are captured in the address
registers. A[1:0] are also loaded into the burst counter. When ADSP and ADSC are both
asserted, only ADSP is recognized.
BWE
ZZ
Input-
Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal
Synchronous must be asserted LOW to conduct a byte write.
Input-
ZZ “sleep” Input, active HIGH. When asserted HIGH places the device in a
Asynchronous non-time-critical “sleep” condition with data integrity preserved. For normal operation, this
pin has to be LOW or left floating. ZZ pin has an internal pull down.
I/O-
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is
DQs
Synchronous triggered by the rising edge of CLK. As outputs, they deliver the data contained in the
memory location specified by the addresses presented during the previous clock rise of
the read cycle. The direction of the pins is controlled by OE. When OE is asserted LOW,
the pins behave as outputs. When HIGH, DQs and DQPX are placed in a tristate
condition.The outputs are automatically tristated during the data portion of a write
sequence, during the first clock when emerging from a deselected state, and when the
device is deselected, regardless of the state of OE.
I/O-
Bidirectional Data Parity I/O Lines. Functionally, these signals are identical to DQs.
DQPX
Synchronous During write sequences, DQPX is controlled by BWX correspondingly.
MODE
Input-
Static
Selects Burst Order. When tied to GND selects linear burst sequence. When tied to VDD
or left floating selects interleaved burst sequence. This is a strap pin and should remain
static during device operation. Mode Pin has an internal pull up.
VDD
Power Supply Power supply inputs to the core of the device.
Document #: 38-05541 Rev. *G
Page 7 of 32
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CY7C1361C/CY7C1363C
Pin Definitions (continued)
Name
I/O
Description
VDDQ
VSS
I/O Power Supply Power supply for the I/O circuitry.
Ground
Ground for the core of the device.
Ground for the I/O circuitry.
VSSQ
TDO
I/O Ground
JTAG serial output Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If the
Synchronous JTAG feature is not being used, this pin should be left unconnected. This pin is not
available on TQFP packages.
TDI
JTAG serial input Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG
Synchronous feature is not being used, this pin can be left floating or connected to VDD through a pull
up resistor. This pin is not available on TQFP packages.
TMS
JTAG serial input Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG
Synchronous feature is not being used, this pin can be disconnected or connected to VDD. This pin is
not available on TQFP packages.
TCK
NC
JTAG-
Clock
Clock input to the JTAG circuitry. If the JTAG feature is not being used, this pin must
be connected to VSS. This pin is not available on TQFP packages.
–
No Connects. Not internally connected to the die. 18M, 36M, 72M, 144M, 288M, 576M,
and 1G are address expansion pins and are not internally connected to the die.
VSS/DNU
Ground/DNU
This pin can be connected to Ground or should be left floating.
Document #: 38-05541 Rev. *G
Page 8 of 32
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CY7C1361C/CY7C1363C
Single Write Accesses Initiated by ADSC
Functional Overview
This write access is initiated when the following conditions are
satisfied at clock rise: (1) CE1, CE2, and CE3[2] are all asserted
active, (2) ADSC is asserted LOW, (3) ADSP is deasserted
HIGH, and (4) the write input signals (GW, BWE, and BWX)
indicate a write access. ADSC is ignored if ADSP is active LOW.
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. Maximum access delay from the
clock rise (tCDV) is 6.5 ns (133 MHz device).
The CY7C1361C/CY7C1363C supports secondary cache in
systems using either a linear or interleaved burst sequence. The
interleaved burst order supports Pentium and i486™ processors.
The linear burst sequence is suited for processors that use a
linear burst sequence. The burst order is user-selectable, and is
determined by sampling the MODE input. Accesses can be
initiated with either the Processor Address Strobe (ADSP) or the
Controller Address Strobe (ADSC). Address advancement
through the burst sequence is controlled by the ADV input. A
two-bit on-chip wraparound burst counter captures the first
address in a burst sequence and automatically increments the
address for the rest of the burst access.
The addresses presented are loaded into the address register
and the burst counter/control logic and delivered to the memory
core. The information presented to DQ[A:D] is written into the
specified address location. Byte writes are allowed. All I/Os are
tristated when a write is detected, even a byte write. Since this
is a common I/O device, the asynchronous OE input signal must
be deasserted and the I/Os must be tristated prior to the presen-
tation of data to DQs. As a safety precaution, the data lines are
tristated once a write cycle is detected, regardless of the state of
OE.
Byte write operations are qualified with the Byte Write Enable
(BWE) and Byte Write Select (BWX) inputs. A Global Write
Enable (GW) overrides all byte write inputs and writes data to all
four bytes. All writes are simplified with on-chip synchronous
self-timed write circuitry.
Three synchronous Chip Selects (CE1, CE2, CE3[2]) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output tristate control. ADSP is ignored if CE1 is
HIGH.
Burst Sequences
The CY7C1361C/CY7C1363C provides an on-chip two-bit
wraparound burst counter inside the SRAM. The burst counter is
fed by A[1:0], and can follow either a linear or interleaved burst
order. The burst order is determined by the state of the MODE
input. A LOW on MODE will select a linear burst sequence. A
HIGH on MODE selects an interleaved burst order. Leaving
MODE unconnected causes the device to default to a interleaved
burst sequence.
Single Read Accesses
Table 1. Interleaved Burst Address Table
(MODE = Floating or VDD
)
A single read access is initiated when the following conditions
are satisfied at clock rise: (1) CE1, CE2, and CE3 are all
[2]
First
Address
A1: A0
Second
Address
A1: A0
Third
Address
A1: A0
Fourth
Address
A1: A0
asserted active and (2) ADSP or ADSC is asserted LOW (if the
access is initiated by ADSC, the write inputs must be deasserted
during this first cycle). The address presented to the address
inputs is latched into the address register and the burst
counter/control logic and presented to the memory core. If the
OE input is asserted LOW, the requested data will be available
at the data outputs a maximum to tCDV after clock rise. ADSP is
ignored if CE1 is HIGH.
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Single Write Accesses Initiated by ADSP
Table 2. Linear Burst Address Table (MODE = GND)
This access is initiated when the following conditions are
satisfied at clock rise: (1) CE1, CE2, CE3[2] are all asserted active
and (2) ADSP is asserted LOW. The addresses presented are
loaded into the address register and the burst inputs (GW, BWE,
and BWX) are ignored during this first clock cycle. If the write
inputs are asserted active (see Partial Truth Table for Read/Write
on page 11 for appropriate states that indicate a write) on the
next clock rise, the appropriate data will be latched and written
into the device.Byte writes are allowed. All I/Os are tristated
during a byte write. Since this is a common I/O device, the
asynchronous OE input signal must be deasserted and the I/Os
must be tristated prior to the presentation of data to DQs. As a
safety precaution, the data lines are tristated once a write cycle
is detected, regardless of the state of OE.
First
Second
Address
A1: A0
Third
Address
A1: A0
Fourth
Address
A1: A0
Address
A1: A0
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ places
the SRAM in a power conservation ‘sleep’ mode. Two clock
cycles are required to enter into or exit from this ‘sleep’ mode.
While in this mode, data integrity is guaranteed. Accesses
pending when entering the ‘sleep’ mode are not considered valid
nor is the completion of the operation guaranteed. The device
must be deselected prior to entering the ‘sleep’ mode. CE1, CE2,
CE3[2], ADSP, and ADSC must remain inactive for the duration
of tZZREC after the ZZ input returns LOW.
Document #: 38-05541 Rev. *G
Page 9 of 32
[+] Feedback
CY7C1361C/CY7C1363C
ZZ Mode Electrical Characteristics
Parameter
Description
Test Conditions
ZZ > VDD – 0.2V
Min
Max
50
Unit
mA
mA
ns
IDDZZ
Sleep mode standby current
Comm/ind’l
Automotive
60
tZZS
Device operation to ZZ
ZZ recovery time
ZZ > VDD – 0.2V
2tCYC
tZZREC
tZZI
ZZ < 0.2V
2tCYC
0
ns
ZZ active to sleep current
ZZ Inactive to exit sleep current
This parameter is sampled
This parameter is sampled
2tCYC
ns
tRZZI
ns
Truth Table
The Truth Table for CY7C1361C and CY7C1363C follows. [3, 4, 5, 6, 7]
Address
Used
Cycle Description
CE1 CE2 CE3 ZZ ADSP
ADSC ADV WRITE OE CLK
DQ
Deselected Cycle, Power Down None
Deselected Cycle, Power Down None
Deselected Cycle, Power Down None
Deselected Cycle, Power Down None
Deselected Cycle, Power Down None
H
L
X
L
X
X
H
X
X
X
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
L
L
X
X
L
X
X
X
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
L
L-H
L-H
L-H
L-H
L-H
X
Tristate
Tristate
Tristate
Tristate
Tristate
Tristate
Q
L
X
L
L
L
H
H
X
L
X
X
L
X
X
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
L
Sleep Mode, Power-down
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Write Cycle, Begin Burst
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Write Cycle, Suspend Burst
Write Cycle, Suspend Burst
None
External
External
External
External
External
Next
X
X
X
L
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L
L
L
H
X
L
Tristate
D
L
L
H
H
H
H
H
X
X
H
X
H
H
X
X
H
X
Q
L
L
L
H
H
H
H
H
H
L
L
L
L
H
L
Tristate
Q
X
X
H
H
X
H
X
X
H
H
X
H
X
X
X
X
X
X
X
X
X
X
X
X
H
H
H
H
H
H
H
H
H
H
H
H
Next
L
H
L
Tristate
Next
L
Q
Next
L
H
X
X
L
Tristate
Next
L
D
Next
L
L
D
Current
Current
Current
Current
Current
Current
H
H
H
H
H
H
H
H
H
H
L
Q
Tristate
Q
H
L
H
X
X
Tristate
D
L
D
Notes
3. X=”Don't Care.” H = Logic HIGH, L = Logic LOW.
4. WRITE = L when any one or more Byte Write enable signals and BWE = L or GW = L. WRITE = H when all Byte write enable signals, BWE, GW = H.
5. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
6. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW . Writes may occur only on subsequent clocks
X
after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to tri-state. OE is a
don't care for the remainder of the write cycle.
7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tri-state when OE is
inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW).
Document #: 38-05541 Rev. *G
Page 10 of 32
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CY7C1361C/CY7C1363C
Partial Truth Table for Read/Write
The Partial Truth Table for Read/Write follows.[3, 8]
Function (CY7C1361C)
Read
GW
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
BWE
H
L
BWD
X
H
H
H
H
H
H
H
H
L
BWC
X
H
H
H
H
L
BWB
X
H
H
L
BWA
X
H
L
Read
Write Byte (A, DQPA)
L
Write Byte (B, DQPB)
L
H
L
Write Bytes (B, A, DQPA, DQPB)
Write Byte (C, DQPC)
L
L
L
H
H
L
H
L
Write Bytes (C, A, DQPC, DQPA)
Write Bytes (C, B, DQPC, DQPB)
Write Bytes (C, B, A, DQPC, DQPB, DQPA)
Write Byte (D, DQPD)
L
L
L
L
H
L
L
L
L
L
H
H
H
H
L
H
H
L
H
L
Write Bytes (D, A, DQPD, DQPA)
Write Bytes (D, B, DQPD, DQPA)
Write Bytes (D, B, A, DQPD, DQPB, DQPA)
Write Bytes (D, B, DQPD, DQPB)
Write Bytes (D, B, A, DQPD, DQPC, DQPA)
Write Bytes (D, C, A, DQPD, DQPB, DQPA)
Write All Bytes
L
L
L
L
H
L
L
L
L
L
L
H
H
L
H
L
L
L
L
L
L
L
H
L
L
L
L
L
Write All Bytes
X
X
X
X
X
Truth Table for Read/Write
The Truth Table for Read/Write follows.[3, 8]
GW
H
BWE
BWB
X
BWA
Function (CY7C1363C)
Read
H
L
L
L
L
X
X
H
L
Read
H
H
Write Byte A – (DQA and DQPA)
Write Byte B – (DQB and DQPB)
Write All Bytes
H
H
H
L
H
L
H
L
Write All Bytes
L
X
X
Note
8. Table only lists a partial listing of the byte write combinations. Any Combination of BW is valid Appropriate write will be done based on which byte write is active.
X
Document #: 38-05541 Rev. *G
Page 11 of 32
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CY7C1361C/CY7C1363C
Test Access Port (TAP)
IEEE 1149.1 Serial Boundary Scan (JTAG)
Test Clock (TCK)
The CY7C1361C/CY7C1363C incorporates a serial boundary
scan test access port (TAP) in the BGA package only. The TQFP
package does not offer this functionality. This part operates in
accordance with IEEE Standard 1149.1-1900, but does not have
the set of functions required for full 1149.1 compliance. These
functions from the IEEE specification are excluded because their
inclusion places an added delay in the critical speed path of the
SRAM. Note that the TAP controller functions in a manner that
does not conflict with the operation of other devices using 1149.1
fully compliant TAPs. The TAP operates using JEDEC-standard
3.3V or 2.5V I/O logic levels.
The test clock is used only with the TAP controller. All inputs are
captured on the rising edge of TCK. All outputs are driven from
the falling edge of TCK.
Test MODE SELECT (TMS)
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. It is allowable to leave
this ball unconnected if the TAP is not used. The ball is pulled up
internally, resulting in a logic HIGH level.
Test Data-In (TDI)
The CY7C1361C/CY7C1363C contains a TAP controller,
instruction register, boundary scan register, bypass register, and
ID register.
The TDI ball is used to serially input information into the registers
and can be connected to the input of any of the registers. The
register between TDI and TDO is chosen by the instruction that
is loaded into the TAP instruction register. TDI is internally pulled
up and can be unconnected if the TAP is unused in an appli-
cation. TDI is connected to the most significant bit (MSB) of any
register. (See TAP Controller Block Diagram.)
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(VSS) to prevent clocking of the device. TDI and TMS are inter-
nally pulled up and may be unconnected. They may alternately
be connected to VDD through a pull up resistor. TDO should be
left unconnected. Upon power up, the device comes up in a reset
state which does not interfere with the operation of the device.
Test Data-Out (TDO)
The TDO output ball is used to serially clock data-out from the
registers. The output is active depending upon the current state
of the TAP state machine. The output changes on the falling edge
of TCK. TDO is connected to the least significant bit (LSB) of any
register. (See TAP Controller State Diagram.)
TAP Controller State Diagram
TEST-LOGIC
1
RESET
0
TAP Controller Block Diagram
1
1
1
RUN-TEST/
IDLE
SELECT
DR-SCAN
SELECT
IR-SCAN
0
0
0
0
Bypass Register
1
1
CAPTURE-DR
CAPTURE-IR
2
1
0
0
0
0
0
Selection
Circuitry
Selection
Circuitry
Instruction Register
31 30 29
Identification Register
TDI
TDO
SHIFT-DR
0
SHIFT-IR
0
.
.
. 2 1
1
1
1
1
EXIT1-DR
EXIT1-IR
x
.
.
.
.
. 2 1
0
0
Boundary Scan Register
PAUSE-DR
0
PAUSE-IR
1
0
1
0
0
EXIT2-DR
1
EXIT2-IR
1
TCK
TAP CONTROLLER
TM S
UPDATE-DR
UPDATE-IR
1
0
1
0
The 0/1 next to each state represents the value of TMS at the
rising edge of TCK.
Document #: 38-05541 Rev. *G
Page 12 of 32
[+] Feedback
CY7C1361C/CY7C1363C
Performing a TAP Reset
TAP Instruction Set
A RESET is performed by forcing TMS HIGH (VDD) for five rising
edges of TCK. This RESET does not affect the operation of the
SRAM and may be performed while the SRAM is operating.
Overview
Eight different instructions are possible with the three-bit
instruction register. All combinations are listed in the Instruction
Codes table. Three of these instructions are listed as
RESERVED and should not be used. The other five instructions
are described in detail in this section.
At power up, the TAP is reset internally to ensure that TDO
comes up in a High-Z state.
TAP Registers
The TAP controller used in this SRAM is not fully compliant to the
1149.1 convention because some of the mandatory 1149.1
instructions are not fully implemented.
Registers are connected between the TDI and TDO balls and
allow data to be scanned into and out of the SRAM test circuitry.
Only one register can be selected at a time through the
instruction register. Data is serially loaded into the TDI ball on the
rising edge of TCK. Data is output on the TDO ball on the falling
edge of TCK.
The TAP controller cannot be used to load address data or
control signals into the SRAM and cannot preload the I/O buffers.
The SRAM does not implement the 1149.1 commands EXTEST
or INTEST or the PRELOAD portion of SAMPLE/PRELOAD;
rather, it performs a capture of the I/O ring when these instruc-
tions are executed.
Instruction Register
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the TDI
and TDO balls as shown in the TAP Controller Block Diagram on
page 12. Upon power up, the instruction register is loaded with
the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as described
in the previous section.
Instructions are loaded into the TAP controller during the Shift-IR
state when the instruction register is placed between TDI and
TDO. During this state, instructions are shifted through the
instruction register through the TDI and TDO balls. To execute
the instruction once it is shifted in, the TAP controller needs to be
moved into the Update-IR state.
When the TAP controller is in the Capture-IR state, the two least
significant bits are loaded with a binary ‘01’ pattern to enable fault
isolation of the board-level serial test data path.
EXTEST
EXTEST is a mandatory 1149.1 instruction which is to be
executed whenever the instruction register is loaded with all 0s.
EXTEST is not implemented in this SRAM TAP controller, and
therefore this device is not compliant to 1149.1. The TAP
controller does recognize an all-0 instruction.
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between the
TDI and TDO balls. This enables data to be shifted through the
When an EXTEST instruction is loaded into the instruction
register, the SRAM responds as if a SAMPLE/PRELOAD
instruction has been loaded. There is one difference between the
two instructions. Unlike the SAMPLE/PRELOAD instruction,
EXTEST places the SRAM outputs in a High-Z state.
SRAM with minimal delay. The bypass register is set LOW (VSS
)
when the BYPASS instruction is executed.
Boundary Scan Register
IDCODE
The boundary scan register is connected to all the input and
bidirectional balls on the SRAM.
The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the instruction register. It also places the
instruction register between the TDI and TDO balls and enables
the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state.
The boundary scan register is loaded with the contents of the
RAM I/O ring when the TAP controller is in the Capture-DR state
and is then placed between the TDI and TDO balls when the
controller is moved to the Shift-DR state. The EXTEST,
SAMPLE/PRELOAD, and SAMPLE Z instructions can be used
to capture the contents of the I/O ring.
The IDCODE instruction is loaded into the instruction register
upon power up or whenever the TAP controller is given a test
logic reset state.
The 119-Ball BGA Boundary Scan Order on page 18 and
165-Ball FBGA Boundary Scan Order on page 19 show the order
in which the bits are connected. Each bit corresponds to one of
the bumps on the SRAM package. The MSB of the register is
connected to TDI and the LSB is connected to TDO.
SAMPLE Z
The SAMPLE Z instruction causes the boundary scan register to
be connected between the TDI and TDO balls when the TAP
controller is in a Shift-DR state. It also places all SRAM outputs
into a High-Z state.
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired into
the SRAM and can be shifted out when the TAP controller is in
the Shift-DR state. The ID register has a vendor code and other
information described in Identification Register Definitions on
page 16.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1-mandatory instruction. When
the SAMPLE/PRELOAD instructions are loaded into the instruc-
tion register and the TAP controller is in the Capture-DR state, a
snapshot of data on the inputs and output pins is captured in the
boundary scan register.
Document #: 38-05541 Rev. *G
Page 13 of 32
[+] Feedback
CY7C1361C/CY7C1363C
The user must be aware that the TAP controller clock can only
operate at a frequency up to 20 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because there
is a large difference in the clock frequencies, it is possible that
during the Capture-DR state, an input or output undergoes a
transition. The TAP may then try to capture a signal while in tran-
sition (metastable state). This does not harm the device, but
there is no guarantee as to the value that will be captured. Re-
peatable results may not be possible.
PRELOAD enables an initial data pattern to be placed at the
latched parallel outputs of the boundary scan register cells prior
to the selection of another boundary scan test operation.
The shifting of data for the SAMPLE and PRELOAD phases can
occur concurrently when required - that is, while data captured
is shifted out, the preloaded data can be shifted in.
BYPASS
When the BYPASS instruction is loaded in the instruction register
and the TAP is placed in a Shift-DR state, the bypass register is
placed between the TDI and TDO balls. The advantage of the
BYPASS instruction is that it shortens the boundary scan path
when multiple devices are connected together on a board.
To guarantee that the boundary scan register captures the cor-
rect value of a signal, the SRAM signal must be stabilized long
enough to meet the TAP controller's capture setup plus hold
times (tCS and tCH). The SRAM clock input might not be captured
correctly if there is no way in a design to stop (or slow) the clock
during a SAMPLE/PRELOAD instruction. If this is an issue, it is
still possible to capture all other signals and simply ignore the
value of the CK and CK# captured in the boundary scan register.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
After the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the boundary
scan register between the TDI and TDO pins.
TAP Timing
1
2
3
4
5
6
Test Clock
(TCK)
t
t
t
CYC
TH
TL
t
t
t
t
TM SS
TDIS
TM SH
Test M ode Select
(TM S)
TDIH
Test Data-In
(TDI)
t
TDOV
t
TDOX
Test Data-Out
(TDO)
DON’T CARE
UNDEFINED
Document #: 38-05541 Rev. *G
Page 14 of 32
[+] Feedback
CY7C1361C/CY7C1363C
TAP AC Switching Characteristics Over the Operating Range[9, 10]
Parameter
Clock
tTCYC
tTF
Parameter
Min
Max
Unit
TCK Clock Cycle Time
TCK Clock Frequency
TCK Clock HIGH Time
TCK Clock LOW Time
50
ns
MHz
ns
20
tTH
20
20
tTL
ns
Output Times
tTDOV TCK Clock LOW to TDO Valid
tTDOX TCK Clock LOW to TDO Invalid
Set-up Times
tTMSS TMS Setup to TCK Clock Rise
tTDIS
10
ns
ns
0
5
5
5
ns
ns
ns
TDI Setup to TCK Clock Rise
Capture Setup to TCK Rise
tCS
Hold Times
tTMSH
tTDIH
TMS Hold after TCK Clock Rise
TDI Hold after Clock Rise
5
5
5
ns
ns
ns
tCH
Capture Hold after Clock Rise
Notes
9.
t
and t refer to the setup and hold time requirements of latching data from the boundary scan register.
CS CH
10. Test conditions are specified using the load in TAP AC test conditions. t /t = 1 ns.
R
F
Document #: 38-05541 Rev. *G
Page 15 of 32
[+] Feedback
CY7C1361C/CY7C1363C
3.3V TAP AC Test Conditions
2.5V TAP AC Test Conditions
Input pulse levels.................................................VSS to 3.3V
Input rise and fall times....................................................1 ns
Input timing reference levels........................................... 1.5V
Output reference levels .................................................. 1.5V
Test load termination supply voltage .............................. 1.5V
Input pulse levels.................................................VSS to 2.5V
Input rise and fall time .....................................................1 ns
Input timing reference levels......................................... 1.25V
Output reference levels ................................................ 1.25V
Test load termination supply voltage ............................ 1.25V
3.3V TAP AC Output Load Equivalent
1.5V
2.5V TAP AC Output Load Equivalent
1.25V
50Ω
50Ω
TDO
TDO
ZO= 50Ω
20pF
ZO= 50Ω
20pF
TAP DC Electrical Characteristics And Operating Conditions
(0°C < TA < +70°C; VDD = 3.3V ±0.165V unless otherwise noted)[11]
Parameter
Description
Description
IOH = –4.0 mA
OH = –1.0 mA
Conditions
VDDQ = 3.3V
Min
2.4
2.0
2.9
2.1
Max
Unit
V
VOH1
Output HIGH Voltage
I
VDDQ = 2.5V
VDDQ = 3.3V
V
VOH2
VOL1
VOL2
VIH
Output HIGH Voltage
Output LOW Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Load Current
IOH = –100 µA
V
VDDQ = 2.5V
V
IOL = 8.0 mA
IOL = 8.0 mA
IOL = 100 µA
VDDQ = 3.3V
VDDQ = 2.5V
VDDQ = 3.3V
0.4
0.4
V
V
0.2
V
V
DDQ = 2.5V
VDDQ = 3.3V
DDQ = 2.5V
VDDQ = 3.3V
DDQ = 2.5V
0.2
V
2.0
1.7
VDD + 0.3
VDD + 0.3
0.7
V
V
V
VIL
–0.5
–0.3
–5
V
V
0.7
V
IX
GND < VIN < VDDQ
5
µA
Identification Register Definitions
CY7C1361C
(256K x36)
CY7C1363C
(512K x18)
Instruction Field
Description
Revision Number (31:29)
Device Depth (28:24)[12]
000
000
Describes the version number.
Reserved for Internal Use
01011
01011
Device Width (23:18) 119-BGA
Device Width (23:18) 165-FBGA
Cypress Device ID (17:12)
101001
000001
100110
00000110100
1
101001
000001
010110
Defines memory type and architecture
Defines memory type and architecture
Defines width and density
Cypress JEDEC ID Code (11:1)
ID Register Presence Indicator (0)
00000110100 Allows unique identification of SRAM vendor.
Indicates the presence of an ID register.
1
Notes
11. All voltages referenced to V (GND).
SS
12. Bit #24 is “1” in the Register Definitions for both 2.5V and 3.3V versions of this device.
Document #: 38-05541 Rev. *G
Page 16 of 32
[+] Feedback
CY7C1361C/CY7C1363C
Scan Register Sizes
Register Name
Bit Size (x 36)
Bit Size (x 18)
Instruction
3
3
Bypass
1
1
ID
32
71
71
32
71
71
Boundary Scan Order (119-ball BGA package)
Boundary Scan Order (165-ball FBGA package)
Identification Codes
Instruction
EXTEST
Code
Description
000
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM outputs to High-Z state.
IDCODE
001
010
Loads the ID register with the vendor ID code and places the register between TDI and TDO.
This operation does not affect SRAM operations.
SAMPLE Z
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM output drivers to a High-Z state.
RESERVED
011
100
Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Does not affect SRAM operation.
RESERVED
RESERVED
BYPASS
101
110
111
Do Not Use: This instruction is reserved for future use.
Do Not Use: This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does not affect SRAM
operations.
Document #: 38-05541 Rev. *G
Page 17 of 32
[+] Feedback
CY7C1361C/CY7C1363C
119-Ball BGA Boundary Scan Order
CY7C1361C (256K x 36)
CY7C1363C (512K x 18)
Signal
Name
Signal
Name
Signal
Name
Signal
Name
Bit # ball ID
Bit # ball ID
Bit #
ball ID
Bit #
ball ID
1
CLK
GW
BWE
OE
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
P4
N4
R6
T5
A0
1
CLK
GW
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
P4
N4
A0
A1
K4
H4
M4
F4
B4
A4
G4
C3
B3
D6
H7
G6
E6
D7
E7
F6
G7
H6
T7
K7
L6
K4
H4
2
A1
2
3
A
3
M4
BWE
OE
R6
A
4
A
4
F4
T5
A
5
ADSC
ADSP
ADV
A
T3
A
5
B4
ADSC
ADSP
ADV
A
T3
A
6
R2
R3
P2
A
6
A4
R2
A
7
MODE
DQPD
DQD
DQD
DQD
DQD
DQD
DQD
DQD
DQD
Internal
DQC
DQC
DQC
DQC
DQC
DQC
DQC
DQC
DQPC
A
7
G4
R3
MODE
Internal
Internal
Internal
Internal
DQPB
DQB
8
8
C3
Internal
Internal
Internal
Internal
P2
9
A
P1
9
B3
A
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
DQPB
DQB
DQB
DQB
DQB
DQB
DQB
DQB
DQB
ZZ
L2
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
T2
A
K1
Internal
Internal
Internal
D6
Internal
Internal
Internal
DQPA
DQA
DQA
DQA
DQA
ZZ
N2
N1
M2
L1
N1
M2
DQB
E7
L1
DQB
K2
F6
K2
DQB
Internal
H1
G2
E2
G7
Internal
H1
Internal
DQB
H6
T7
G2
DQB
DQA
DQA
DQA
DQA
DQA
DQA
DQA
DQA
DQPA
A
K7
DQA
DQA
DQA
DQA
Internal
Internal
Internal
Internal
Internal
A
E2
DQB
D1
H2
G1
F2
L6
D1
DQB
N6
P7
N7
M6
L7
N6
Internal
Internal
Internal
Internal
Internal
C2
Internal
Internal
Internal
Internal
Internal
A
P7
Internal
Internal
Internal
Internal
Internal
T6
E1
D2
C2
A2
K6
P6
T4
A3
C5
B5
A5
C6
A6
B6
A
A2
A
E4
CE1
CE2
BWD
BWC
BWB
BWA
Internal
E4
CE1
A
B2
A3
A
B2
CE2
A
L3
C5
A
Internal
Internal
G3
Internal
Internal
BWB
BWA
Internal
A
G3
G5
L5
B5
A
A
A5
A
A
C6
A
L5
A
Internal
A6
A
Internal
A
B6
A
Document #: 38-05541 Rev. *G
Page 18 of 32
[+] Feedback
CY7C1361C/CY7C1363C
165-Ball FBGA Boundary Scan Order
CY7C1361C (256K x 36)
CY7C1363C (512K x 18)
Signal
Name
Signal
Name
Signal
Name
Signal
Name
Bit # ball ID
Bit #
ball ID
Bit # ball ID
Bit #
ball ID
1
B6
B7
CLK
GW
BWE
OE
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
R6
P6
R4
P4
R3
P3
R1
N1
L2
A0
1
B6
B7
CLK
GW
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
R6
P6
A0
A1
2
A1
2
3
A7
A
3
A7
BWE
OE
R4
A
4
B8
A
4
B8
P4
A
5
A8
ADSC
ADSP
ADV
A
A
5
A8
ADSC
ADSP
ADV
A
R3
A
6
B9
A
6
B9
P3
A
7
A9
MODE
DQPD
DQD
DQD
DQD
DQD
DQD
DQD
DQD
DQD
Internal
DQC
DQC
DQC
DQC
DQC
DQC
DQC
DQC
DQPC
A
7
A9
R1
MODE
Internal
Internal
Internal
Internal
DQPB
DQB
8
B10
A10
C11
E10
F10
G10
D10
D11
E11
F11
G11
H11
J10
K10
L10
M10
J11
K11
L11
M11
N11
R11
R10
P10
R9
8
B10
Internal
Internal
Internal
Internal
N1
9
A
9
A10
A
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
DQPB
DQB
DQB
DQB
DQB
DQB
DQB
DQB
DQB
ZZ
K2
J2
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
A11
A
Internal
Internal
Internal
C11
Internal
Internal
Internal
DQPA
DQA
DQA
DQA
DQA
ZZ
M2
M1
L1
M1
L1
DQB
K1
J1
D11
K1
DQB
E11
J1
DQB
Internal
G2
F2
F11
Internal
G2
Internal
DQB
G11
H11
F2
DQB
DQA
DQA
DQA
DQA
DQA
DQA
DQA
DQA
DQPA
A
E2
D2
G1
F1
J10
DQA
DQA
DQA
DQA
Internal
Internal
Internal
Internal
Internal
A
E2
DQB
K10
D2
DQB
L10
Internal
Internal
Internal
Internal
Internal
B2
Internal
Internal
Internal
Internal
Internal
A
M10
Internal
Internal
Internal
Internal
Internal
R11
E1
D1
C1
B2
A2
A3
B3
B4
A4
A5
B5
A6
A
A2
A
CE1
CE2
BWD
BWC
BWB
BWA
CE3
A3
CE1
A
R10
P10
A
B3
CE2
A
A
Internal
Internal
A4
Internal
Internal
BWB
BWA
CE3
A
R9
A
P9
A
P9
A
R8
A
R8
A
B5
P8
A
P8
A
A6
P11
A
P11
A
Document #: 38-05541 Rev. *G
Page 19 of 32
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CY7C1361C/CY7C1363C
Maximum Ratings
Neutron Soft Error Immunity
Test
Conditions
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Parameter Description
Typ Max* Unit
LSBU
LMBU
SEL
Logical
Single-Bit
Upsets
25°C
25°C
85°C
361 394 FIT/
Mb
Storage Temperature ................................ –65°C to + 150°C
Ambient Temperature with
Power Applied ........................................... –55°C to + 125°C
Logical
Multi-Bit
Upsets
0
0
0.01 FIT/
Mb
Supply Voltage on VDD Relative to GND .......–0.5V to + 4.6V
Supply Voltage on VDDQ Relative to GND..... –0.5V to + VDD
Single Event
Latch up
0.1
FIT/
Dev
DC Voltage Applied to Outputs
in tri-state.............................................–0.5V to VDDQ + 0.5V
* No LMBU or SEL events occurred during testing; this column represents a
DC Input Voltage ...................................–0.5V to VDD + 0.5V
Current into Outputs (LOW)......................................... 20 mA
2
statistical χ , 95% confidence limit calculation. For more details refer to Appli-
cation Note AN 54908 “Accelerated Neutron SER Testing and Calculation of
Terrestrial Failure Rates”
Static Discharge Voltage........................................... >2001V
(per MIL-STD-883, Method 3015)
Latch up Current..................................................... >200 mA
Operating Range
Ambient
Temperature
Range
VDD
VDDQ
Commercial 0°C to +70°C 3.3V – 5%/+10% 2.5V – 5%
to VDD
Industrial
–40°C to +85°C
Automotive –40°C to +125°C
[13, 14]
Electrical Characteristics Over the Operating Range
Parameter
VDD
Description
Power Supply Voltage
I/O Supply Voltage
Test Conditions
Min
3.135
3.135
2.375
2.4
Max
3.6
Unit
V
VDDQ
for 3.3V I/O
for 2.5V I/O
VDD
2.625
V
V
VOH
VOL
VIH
VIL
IX
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage[13]
Input LOW Voltage[13]
for 3.3V I/O, IOH = −4.0 mA
for 2.5V I/O, IOH = −1.0 mA
for 3.3V I/O, IOL= 8.0 mA
for 2.5V I/O, IOL= 1.0 mA
for 3.3V I/O
V
2.0
V
0.4
V
0.4
VDD + 0.3V
VDD + 0.3V
0.8
V
2.0
1.7
V
for 2.5V I/O
V
for 3.3V I/O
–0.3
–0.3
–5
V
for 2.5V I/O
0.7
V
Input Leakage Current
except ZZ and MODE
GND ≤ VI ≤ VDDQ
5
μA
Input Current of MODE Input = VSS
Input = VDD
–30
–5
μA
μA
μA
μA
μA
5
Input Current of ZZ
Input = VSS
Input = VDD
30
5
IOZ
Output Leakage Current GND < VI < VDDQ, Output Disabled
–5
Notes
13. Overshoot: V (AC) < V +1.5V (Pulse width less than t
/2), undershoot: V (AC) > –2V (Pulse width less than t
/2).
IH
DD
CYC
IL
CYC
14. T
: Assumes a linear ramp from 0V to V (min.) within 200ms. During this time V < V and V
< V
.
Power-up
DD
IH
DD
DDQ
DD
Document #: 38-05541 Rev. *G
Page 20 of 32
[+] Feedback
CY7C1361C/CY7C1363C
Electrical Characteristics Over the Operating Range (continued)[13, 14]
Parameter
Description
Test Conditions
Min
Max
250
180
110
150
Unit
IDD
VDD Operating Supply
Current
VDD = Max., IOUT = 0 mA,
7.5 ns cycle,133 MHz
10 ns cycle,100 MHz
All speeds (Comm/Ind’l)
mA
f = fMAX = 1/tCYC
ISB1
Automatic CE
Power-down
Current—TTL Inputs
Max. VDD, Device Deselected,
VIN> VIH or VIN < VIL, f = fMAX,
inputs switching
mA
mA
10 ns cycle,100 MHz
(Automotive)
ISB2
Automatic CE
Power-down
Max. VDD, Device Deselected,
All speeds
40
mA
VIN > VDD – 0.3V or VIN < 0.3V,
Current—CMOS Inputs f = 0, inputs static
ISB3
Automatic CE
Power-down
Current—CMOS Inputs f = fMAX, inputs switching
Max. VDD, Device Deselected,
VIN > VDDQ – 0.3V or VIN < 0.3V,
All speeds (Comm/Ind’l)
100
120
mA
mA
10 ns cycle,100 MHz
(Automotive)
ISB4
Automatic CE
Power-down
Current—TTL Inputs
Max. VDD, Device Deselected,
IN > VIH or VIN < VIL
f = 0, inputs static
All speeds (Comm/Ind’l)
40
60
mA
mA
V
10 ns cycle,100 MHz
(Automotive)
Capacitance[15]
100 TQFP 119 BGA 165FBGA
Parameter
Description
Test Conditions
TA = 25°C, f = 1 MHz,
Unit
Max.
Max.
Max.
CIN
Input Capacitance
5
5
5
5
5
7
5
5
7
pF
pF
pF
V
DD = 3.3V
CCLK
CI/O
Clock Input Capacitance
VDDQ = 2.5V
Input/Output Capaci-
tance
Thermal Resistance[15]
100 TQFP 119 BGA 165 FBGA
Parameter
Description
Test Conditions
Unit
Package
Package Package
ΘJA
Thermal Resistance
(Junction to Ambient)
Test conditions follow standard
testmethodsandproceduresfor
measuring thermal impedance,
according to EIA/JESD51
29.41
34.1
14.0
16.8
3.0
°C/W
ΘJC
Thermal Resistance
(Junction to Case)
6.31
°C/W
Figure 5. AC Test Loads and Waveforms
3.3V I/O Test Load
R = 317Ω
3.3V
OUTPUT
ALL INPUT PULSES
90%
VDDQ
OUTPUT
90%
10%
Z = 50Ω
0
R = 50Ω
10%
L
GND
5 pF
R = 351Ω
≤ 1 ns
≤ 1 ns
INCLUDING
JIG AND
SCOPE
V = 1.5V
T
(a)
(b)
(c)
2.5V I/O Test Load
R = 1667Ω
2.5V
OUTPUT
ALL INPUT PULSES
90%
VDDQ
GND
OUTPUT
90%
10%
Z = 50Ω
0
R = 50Ω
10%
L
5 pF
R = 1538Ω
≤ 1 ns
≤ 1 ns
V = 1.25V
T
INCLUDING
JIG AND
SCOPE
(a)
(b)
(c)
Note
15. Tested initially and after any design or process change that may affect these parameters.
Document #: 38-05541 Rev. *G
Page 21 of 32
[+] Feedback
CY7C1361C/CY7C1363C
Switching Characteristics Over the Operating Range[20, 21]
–133
–100
Unit
Description
Parameter
Min
Max
Min
Max
tPOWER
Clock
tCYC
VDD(Typical) to the first Access[16]
1
1
ms
Clock Cycle Time
Clock HIGH
7.5
3.0
3.0
10
4.0
4.0
ns
ns
ns
tCH
tCL
Clock LOW
Output Times
tCDV
Data Output Valid After CLK Rise
Data Output Hold After CLK Rise
Clock to Low-Z[17, 18, 19]
6.5
8.5
ns
ns
ns
ns
ns
ns
ns
tDOH
2.0
0
2.0
0
tCLZ
tCHZ
Clock to High-Z[17, 18, 19]
3.5
3.5
3.5
3.5
tOEV
OE LOW to Output Valid
tOELZ
tOEHZ
Set-up Times
tAS
OE LOW to Output Low-Z[17, 18, 19]
OE HIGH to Output High-Z[17, 18, 19]
0
0
3.5
3.5
Address Setup Before CLK Rise
ADSP, ADSC Setup Before CLK Rise
ADV Setup Before CLK Rise
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
ns
ns
ns
ns
ns
ns
tADS
tADVS
tWES
GW, BWE, BW[A:D] Setup Before CLK Rise
Data Input Setup Before CLK Rise
Chip Enable Setup
tDS
tCES
Hold Times
tAH
Address Hold After CLK Rise
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
ns
ns
tADH
ADSP, ADSC Hold After CLK Rise
GW, BWE, BW[A:D] Hold After CLK Rise
ADV Hold After CLK Rise
tWEH
tADVH
tDH
Data Input Hold After CLK Rise
Chip Enable Hold After CLK Rise
tCEH
Notes
16. This part has a voltage regulator internally; t
is the time that the power needs to be supplied above V (minimum) initially, before a read or write operation
DD
POWER
can be initiated.
17. t
, t
,t
, and t
are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
CHZ CLZ OELZ
OEHZ
18. At any given voltage and temperature, t
is less than t
and t
is less than t
to eliminate bus contention between SRAMs when sharing the same
OEHZ
OELZ
CHZ
CLZ
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions.
19. This parameter is sampled and not 100% tested.
20. Timing reference level is 1.5V when V
= 3.3V and is 1.25V when V
= 2.5V.
DDQ
DDQ
21. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
Document #: 38-05541 Rev. *G
Page 22 of 32
[+] Feedback
CY7C1361C/CY7C1363C
Timing Diagrams
Figure 6. Read Cycle Timing[22]
t
CYC
CLK
t
t
CL
CH
t
t
ADH
ADS
ADSP
ADSC
t
t
ADH
ADS
t
t
AH
AS
A1
A2
ADDRESS
t
t
WES
WEH
GW, BWE,BW
X
Deselect Cycle
t
t
CES
CEH
CE
t
t
ADVH
ADVS
ADV
OE
ADV suspends burst
t
t
t
CDV
OEV
OELZ
t
t
OEHZ
CHZ
t
DOH
t
CLZ
Q(A2)
Q(A2 + 1)
Q(A2 + 2)
Q(A2
+
3)
Q(A2)
Q(A2
+
1)
Q(A2
+
2)
Q(A1)
Data Out (Q)
High-Z
t
CDV
Burst wraps around
to its initial state
Single READ
BURST
READ
DON’T CARE
UNDEFINED
Note
22. On this diagram, when CE is LOW: CE is LOW, CE is HIGH and CE is LOW. When CE is HIGH: CE is HIGH or CE is LOW or CE is HIGH.
1
2
3
1
2
3
Document #: 38-05541 Rev. *G
Page 23 of 32
[+] Feedback
CY7C1361C/CY7C1363C
Timing Diagrams (continued)
Figure 7. Write Cycle Timing[22, 23]
t
CYC
CLK
t
t
CL
CH
t
t
ADH
ADS
ADSP
ADSC extends burst
t
t
ADH
ADS
t
t
ADH
ADS
ADSC
t
t
AH
AS
A1
A2
A3
ADDRESS
Byte write signals are ignored for first cycle when
ADSP initiates burst
t
t
WEH
WES
BWE,
BWX
t
t
WEH
WES
GW
t
t
CEH
CES
CE
t
t
ADVH
ADVS
ADV
ADV suspends burst
OE
t
t
DH
DS
Data in (D)
High-Z
D(A2)
D(A2
+
1)
D(A2
+
1)
D(A2
+
2)
D(A2
+
3)
D(A3)
D(A3
+
1)
D(A3 + 2)
D(A1)
t
OEHZ
Data Out (Q)
BURST READ
BURST WRITE
Extended BURST WRITE
Single WRITE
DON’T CARE
UNDEFINED
Note
23.
Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW LOW.
X
Document #: 38-05541 Rev. *G
Page 24 of 32
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CY7C1361C/CY7C1363C
Timing Diagrams (continued)
Figure 8. Read/Write Cycle Timing[22, 24, 25]
t
CYC
CLK
t
t
CL
CH
t
t
ADH
ADS
ADSP
ADSC
t
t
AH
AS
A1
A2
A3
A4
A5
A6
ADDRESS
t
t
WEH
WES
BWE, BW
X
t
t
CEH
CES
CE
ADV
OE
t
t
DH
DS
t
OELZ
t
High-Z
D(A3)
D(A5)
D(A6)
Data In (D)
t
OEHZ
CDV
Data Out (Q)
Q(A1)
Q(A2)
Q(A4)
Q(A4+1)
Q(A4+2)
Q(A4+3)
Back-to-Back
WRITEs
Back-to-Back READs
Single WRITE
BURST READ
DON’T CARE
UNDEFINED
Notes
24. The data bus (Q) remains in high-Z following a WRITE cycle, unless a new read access is initiated by ADSP or ADSC.
25.
GW is HIGH.
Document #: 38-05541 Rev. *G
Page 25 of 32
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CY7C1361C/CY7C1363C
Timing Diagrams (continued)
Figure 9. ZZ Mode Timing[26, 27]
CLK
ZZ
t
t
ZZ
ZZREC
t
ZZI
I
SUPPLY
I
DDZZ
t
RZZI
ALL INPUTS
(except ZZ)
DESELECT or READ Only
Outputs (Q)
High-Z
DON’T CARE
Notes
26. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device.
27. DQs are in high-Z when exiting ZZ sleep mode.
Document #: 38-05541 Rev. *G
Page 26 of 32
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CY7C1361C/CY7C1363C
Ordering Information
The table below contains only the parts that are currently available. If you don’t see what you are looking for, please contact your local
sales representative. For more information, visit the Cypress website at www.cypress.com and refer to the product summary page at
http://www.cypress.com/products
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives and distributors. To find the office
closest to you, visit us at http://www.cypress.com/go/datasheet/offices
Table 3. Ordering Information
Speed
(MHz)
Package
Diagram
Operating
Range
Part and Package Type
Ordering Code
133 CY7C1361C-133AXC
CY7C1363C-133AXC
CY7C1361C-133AJXC
CY7C1363C-133AJXC
CY7C1361C-133AXI
51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
(3 Chip Enable)
Commercial
51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
(2 Chip Enable)
51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
(3 Chip Enable)
lndustrial
CY7C1363C-133AJXI
51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
(2 Chip Enable)
100 CY7C1361C-100AXC
51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
(3 Chip Enable)
Commercial
Automotive
CY7C1361C-100BGC
51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
100 CY7C1361C-100AXE
51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
Document #: 38-05541 Rev. *G
Page 27 of 32
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CY7C1361C/CY7C1363C
Package Diagrams (continued)
Figure 10. 100-Pin TQFP (14X20X1.4 mm)
16.00 0.20
1.40 0.05
14.00 0.10
100
81
80
1
0.30 0.08
0.65
TYP.
12° 1°
(8X)
SEE DETAIL
A
30
51
31
50
0.20 MAX.
1.60 MAX.
R 0.08 MIN.
0° MIN.
0.20 MAX.
SEATING PLANE
STAND-OFF
0.05 MIN.
0.15 MAX.
NOTE:
0.25
1. JEDEC STD REF MS-026
GAUGE PLANE
2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH
MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE
R 0.08 MIN.
0.20 MAX.
BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH
3. DIMENSIONS IN MILLIMETERS
0°-7°
0.60 0.15
1.00 REF.
0.20 MIN.
51-85050-*B
DETAIL
A
Document #: 38-05541 Rev. *G
Page 28 of 32
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CY7C1361C/CY7C1363C
Figure 11. 119-Ball BGA (14X22X2.4 mm)
Ø0.05 M C
Ø0.25 M C A B
A1 CORNER
Ø0.75 0.15(119X)
Ø1.00(3X) REF.
1
2
3
4
5
6
7
7
6
5
4
3 2 1
A
B
C
D
E
A
B
C
D
E
F
F
G
H
G
H
J
K
L
J
K
L
M
N
P
R
T
M
N
P
R
T
U
U
1.27
0.70 REF.
A
3.81
12.00
7.62
B
14.00 0.20
0.15(4X)
30° TYP.
51-85115-*B
SEATING PLANE
C
Document #: 38-05541 Rev. *G
Page 29 of 32
[+] Feedback
CY7C1361C/CY7C1363C
Figure 12. 165-Ball FBGA (13X15X1.4 mm)
TOP VIEW
BOTTOM VIEW
PIN 1 CORNER
PIN 1 CORNER
Ø0.08 M C
1
2
3
4
5
6
7
8
9
10
11
Ø0.25 M C A B
A
B
-0.06
+0.14
Ø0.50 (165X)
11 10
9
8
7
6
5
4
3
2
1
C
D
A
B
E
C
D
F
G
E
H
J
F
G
K
H
J
L
M
K
N
P
R
L
M
N
P
R
A
A
1.00
5.00
B
13.00 0.10
10.00
13.00 0.10
B
0.15(4X)
NOTES :
SOLDER PAD TYPE : NON-SOLDER MASK DEFINED (NSMD)
PACKAGE WEIGHT : 0.475g
JEDEC REFERENCE : MO-216 / ISSUE E
PACKAGE CODE : BB0AC
SEATING PLANE
C
51-85180-*B
Document #: 38-05541 Rev. *G
Page 30 of 32
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CY7C1361C/CY7C1363C
Document History Page
Document Title: CY7C1361C/CY7C1363C 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM
Document Number: 38-05541
Submission
Date
Orig. of
Change
REV.
ECN NO.
Description of Change
**
241690
278969
332059
See ECN
See ECN
See ECN
RKF
RKF
PCI
New data sheet
*A
*B
Changed Boundary Scan order to match the B rev of these devices.
Removed 117-MHz Speed Bin
Address expansion pins/balls in the pinouts for all packages are modified
as per JEDEC standard
Added Address Expansion pins in the Pin Definitions Table
Changed Device Width (23:18) for 119-BGA from 000001 to 101001
Added separate row for 165 -FBGA Device Width (23:18)
Changed IDDZZ from 35 mA to 50 mA
Changed ISB1 and ISB3 from 40 mA to 110 and 100 mA, respectively
Modified VOL, VOH test conditions
Corrected ISB4 Test Condition from (VIN ≥ VDD – 0.3V or VIN ≤ 0.3V) to
(VIN ≥ VIH or VIN ≤ VIL) in the Electrical Characteristics table
Changed ΘJA and ΘJc for TQFP Package from 25 and 9 °C/W to 29.41
and 6.13 °C/W
respectively
Changed ΘJA and ΘJc for BGA Package from 25 and 6°C/W to 34.1 and
14.0 °C/W
respectively
Changed ΘJA and ΘJc for FBGA Package from 27 and 6 °C/W to 16.8
and 3.0 °C/W respectively
Added lead-free information for 100-pin TQFP, 119 BGA and 165 FBGA
packages
Updated Ordering Information Table
*C
*D
377095
408298
See ECN
See ECN
PCI
Changed ISB2 from 30 to 40 mA
Modified test condition in note# 14 from VIH < VDD to VIH < VDD
RXU
Changed address of Cypress Semiconductor Corporation on Page# 1
from “3901 North First Street” to “198 Champion Court”
Changed tri state to tri-state.
Modified “Input Load” to “Input Leakage Current except ZZ and MODE”
in the Electrical Characteristics Table.
Replaced Package Name column with Package Diagram in the Ordering
Information table.
Updated the ordering information.
*E
*F
433033
501793
See ECN
See ECN
NXR
VKN
Included Automotive range.
Added the Maximum Rating for Supply Voltage on VDDQ Relative to GND
Changed tTH, tTL from 25 ns to 20 ns and tTDOV from 5 ns to 10 ns in TAP
AC Switching Characteristics table.
Updated the Ordering Information table.
*G
2756340
08/26/2009
VKN/AESA Updated template
Included Soft Error Immunity Data
Modified Ordering Information table by including parts that are available
and modified the disclaimer for the Ordering information.
Document #: 38-05541 Rev. *G
Page 31 of 32
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CY7C1361C/CY7C1363C
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at cypress.com/sales.
Products
PSoC
psoc.cypress.com
clocks.cypress.com
wireless.cypress.com
memory.cypress.com
image.cypress.com
Clocks & Buffers
Wireless
Memories
Image Sensors
© Cypress Semiconductor Corporation, 2004-2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 38-05541 Rev. *G
Revised August 26, 2009
Page 32 of 32
All products and company names mentioned in this document may be the trademarks of their respective holders.
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