CY7C136-25NXC [CYPRESS]
2K x 8 Dual-Port Static RAM; 2K ×8双端口静态RAM
| 型号： | CY7C136-25NXC |
| 厂家： | 
CYPRESS |
| 描述： | 2K x 8 Dual-Port Static RAM |
| 文件： | 总18页 (文件大小：564K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C132/CY7C136
CY7C142/CY7C146
2K x 8 Dual-Port Static RAM
Features
Functional Description
• True Dual-Ported memory cells which allow simulta-
neous reads of the same memory location
The CY7C132/CY7C136/CY7C142 and CY7C146 are
high-speed CMOS 2K by 8 dual-port static RAMs. Two ports
are provided to permit independent access to any location in
memory. The CY7C132/ CY7C136 can be utilized as either a
standalone 8-bit dual-port static RAM or as a MASTER
dual-port RAM in conjunction with the CY7C142/CY7C146
SLAVE dual-port device in systems requiring 16-bit or greater
word widths. It is the solution to applications requiring shared
or buffered data such as cache memory for DSP, bit-slice, or
multiprocessor designs.
• 2K x 8 organization
• 0.65-micron CMOS for optimum speed/power
• High-speed access: 15 ns
• Low operating power: ICC = 110 mA (max.)
• Fully asynchronous operation
• Automatic power-down
Each port has independent control pins; chip enable (CE),
write enable (R/W), and output enable (OE). BUSY flags are
provided on each port. In addition, an interrupt flag (INT) is
provided on each port of the 52-pin PLCC version. BUSY
signals that the port is trying to access the same location
currently being accessed by the other port. On the PLCC
version, INT is an interrupt flag indicating that data has been
placed in a unique location (7FF for the left port and 7FE for
the right port).
• Master CY7C132/CY7C136 easily expands data bus
width to 16 or more bits using slave CY7C142/CY7C146
• BUSY output flag on CY7C132/CY7C136; BUSY input
on CY7C142/CY7C146
• INT flag for port-to-port communication (52-pin
PLCC/PQFP versions)
• Availablein48-pinDIP(CY7C132/142),52-pinPLCCand
52-pin TQFP (CY7C136/146)
An automatic power-down feature is controlled independently
on each port by the chip enable (CE) pins.
• Pb-Free packages available
The CY7C132/CY7C142 are available in 48-pin DIP. The
CY7C136/CY7C146 are available in 52-pin PLCC and PQFP.
Logic Block Diagram
Pin Configuration
R/W
L
R/W
R
DIP
CE
L
CE
R
Top View
OE
L
OE
R
V
48
1
CE
L
CC
CE
R/W
R
R/W
BUSY
47
L
R
2
46
3
L
BUSY
45
A
10L
R
4
A
44
5
I/O
I/O
OE
10R
OE
I/O
I/O
7L
L
7R
I/O
CONTROL
I/O
CONTROL
A
0L
43
R
6
42
7
A
0R
0R
A
1L
A
2L
A
3L
0L
[1]
A
1R
A
2R
41
[1]
8
BUSY
BUSY
R
L
40
9
A
A
A
39
10
3R
4L
5L
A
A
A
10L
10R
0R
MEMORY
ARRAY
A
4R
A
5R
ADDRESS
DECODER
ADDRESS
DECODER
38
37
11
12
A
6L
A
7L
A
8L
7C132
A
0L
A
6R
13 7C142
36
35
34
A
7R
A
8R
14
15
16
17
18
A
9L
I/O
0L
I/O
1L
A
9R
33
32
I/O
ARBITRATION
LOGIC
(7C132/7C136 ONLY)
AND
INTERRUPTLOGIC
(7C136/7C146 ONLY)
7R
I/O
2L
I/O
3L
I/O
I/O
I/O
I/O
I/O
31
30
29
28
27
26
25
6R
5R
4R
3R
2R
19
20
21
22
23
24
CE
L
I/O
4L
I/O
5L
CE
R
OE
L
OE
R
I/O
I/O
6L
R/W
L
R/W
R
I/O
I/O
1R
7L
GND
0R
[2]
[2]
INT
INT
R
L
Notes:
1. CY7C132/CY7C136 (Master): BUSY is open drain output and requires pull-up resistor.
CY7C142/CY7C146 (Slave): BUSY is input.
2. Open drain outputs; pull-up resistor required.
Cypress Semiconductor Corporation
Document #: 38-06031 Rev. *C
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised September 1, 2005
CY7C132/CY7C136
CY7C142/CY7C146
Pin Configurations
PLCC
Top View
PQFP
Top View
7
6
5
4
3
2
1
52 51 50 49 48 47
46
A
A
OE
A
1L
2L
3L
4L
5L
6L
7L
8L
9L
0L
1L
8
R
9
45
44
43
42
41
40
39
38
37
36
35
34
0R
A
A
A
A
A
A
52 51 50 49 48 47 46 45 44 43 42 41 40
10
11
12
13
14
15
16
17
18
19
20
1R
A
A
A
A
A
A
A
OE
R
1L
2L
3L
4L
5L
6L
1
39
38
37
36
35
34
33
32
31
30
29
28
27
2R
3R
4R
5R
A
0R
A
2
A
1R
A
3
7C136
7C146
A
2R
A
4
A
3R
A
5
A
6R
A
7R
A
8R
A
9R
A
4R
A
6
7C136
7C146
A
5R
A
7L
A
8L
I/O
I/O
7
A
6R
8
A
I/O
I/O
A
7R
9L
0L
1L
I/O
I/O
9
2L
NC
I/O
A
8R
10
11
12
13
3L
7R
A
9R
2122 23 24 25 26 27 28 29 30 31 32 33
I/O
I/O
NC
I/O
2L
3L
7R
1415 16 17 18 19 20 21 22 23 24 25 26
Selection Guide
7C132-25[3] 7C132-30 7C132-35 7C132-45 7C132-55
7C136-25 7C136-30 7C136-35 7C136-45 7C136-55
7C136-15[3] 7C142-25 7C142-30 7C142-35 7C142-45 7C142-55
7C146-15 7C146-25 7C146-30 7C146-35 7C146-45 7C146-55 Unit
Maximum Access Time
15
25
30
35
120
170
45
45
120
170
45
55
110
120
35
ns
Maximum Operating Current Com’l/Ind
Maximum Operating Current Military
Maximum Standby Current Com’l/Ind
Military
190
170
170
mA
mA
mA
75
65
65
65
65
45
Shaded areas contain preliminary information.
Note:
3. 15 and 25-ns version available in PQFP and PLCC packages only.
Document #: 38-06031 Rev. *C
Page 2 of 18
CY7C132/CY7C136
CY7C142/CY7C146
DC Input Voltage.................................................−3.5V to +7.0V
Maximum Ratings
Output Current into Outputs (LOW)............................. 20 mA
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
Storage Temperature ..................................... −65°C to +150°C
Latch-up Current.................................................... > 200 mA
Ambient Temperature with
Power Applied.................................................. −55°C to +125°C
Operating Range
Supply Voltage to Ground Potential
(Pin 48 to Pin 24).................................................−0.5V to +7.0V
Range
Commercial
Industrial
Ambient Temperature
0°C to +70°C
VCC
5V ± 10%
5V ± 10%
5V ± 10%
DC Voltage Applied to Outputs
in High-Z State.....................................................−0.5V to +7.0V
–40°C to +85–C
–55°C to +125°C
Military[4]
Electrical Characteristics Over the Operating Range[5]
7C132-30[3] 7C132-35,45 7C132-55
7C136-25,30 7C136-35,45 7C136-55
7C136-15[3] 7C142-30 7C142-35,45 7C142-55
7C146-15 7C146-25,30 7C146-35,45 7C146-55
Parameter
VOH
Description
Test Conditions
Min. Max. Min. Max. Min. Max. Min. Max. Unit
Output HIGH voltage VCC = Min., IOH = –4.0 mA
Output LOW voltage IOL = 4.0 mA
2.4
2.4
2.4
2.4
V
V
VOL
0.4
0.5
0.4
0.5
0.4
0.5
0.4
0.5
I
OL = 16.0 mA[6]
VIH
VIL
IIX
Input HIGH voltage
Input LOW voltage
Input load current
2.2
–5
2.2
2.2
2.2
V
V
0.8
+5
+5
0.8
+5
+5
0.8
+5
+5
0.8
GND < VI < VCC
−5
−5
−5
−5
−5
−5
+5 µA
+5 µA
IOZ
Output leakage
current
GND < VO < VCC, Output Disabled –5
IOS
ICC
ISB1
ISB2
Output short circuit VCC = Max., VOUT = GND
current[7]
–350
190
−350
−350
−350 mA
VCC Operating
Supply Current
CE = VIL, Outputs Open, f = Com’l
170
120
170
45
110 mA
120
[8]
fMAX
Mil
Standby current both CEL and CER > VIH,
Com’l
Mil
75
65
35 mA
45
[8]
ports, TTL Inputs
f = fMAX
65
Standby Current
One Port,
TTL Inputs
CEL or CER > VIH,
Com’l
Mil
135
115
90
75 mA
90
Active Port Outputs Open,
115
[8]
f = fMAX
ISB3
Standby Current
Both Ports,
CMOS Inputs
Both Ports CEL and
CER > VCC – 0.2V,
Com’l
Mil
15
15
15
15
15 mA
15
VIN > VCC – 0.2V or
VIN < 0.2V, f = 0
ISB4
Standby Current
One Port,
CMOS Inputs
One Port CEL or CER > VCC – Com’l
125
105
85
70 mA
85
0.2V, VIN > VCC – 0.2V or VIN <
Mil
105
0.2V, Active Port Outputs Open,
[8]
f = fMAX
Capacitance[9]
Parameter
Description
Input Capacitance
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
CC = 5.0V
Max.
Unit
pF
CIN
15
10
V
COUT
pF
Shaded areas contain preliminary information.
Notes:
4. T is the “instant on” case temperature.
A
5. See the last page of this specification for Group A subgroup testing information.
6. BUSY and INT pins only.
7. Duration of the short circuit should not exceed 30 seconds.
8. At f = f
, address and data inputs are cycling at the maximum frequency of read cycle of 1/t and using AC Test Waveforms input levels of GND to 3V.
MAX
rc
9. This parameter is guaranteed but not tested.
Document #: 38-06031 Rev. *C
Page 3 of 18
CY7C132/CY7C136
CY7C142/CY7C146
AC Test Loads and Waveforms
5V
R1 893Ω
R1 893Ω
5V
5V
OUTPUT
OUTPUT
281Ω
BUSY
OR
INT
R2
347Ω
R2
347Ω
30 pF
5 pF
30 pF
INCLUDING
JIG AND
SCOPE
INCLUDING
JIG AND
SCOPE
BUSY Output Load
(CY7C132/CY7C136 Only)
(a)
(b)
Equivalent to:
THÉVENIN EQUIVALENT
ALL INPUT PULSES
3.0V
90%
10%
90%
250Ω
10%
OUTPUT
1.4V
GND
< 5 ns
< 5 ns
Switching Characteristics Over the Operating Range (Speeds -15, -25, -30) [5, 10]
7C132-25[3]
7C132-30
7C136-30
7C142-30
7C146-30
7C136-25
7C142-25
7C146-25
7C136-15[3]
7C146-15
Parameter
Read Cycle
tRC
Description
Min.
Max.
Min.
Max.
Min.
Max.
Unit
Read Cycle Time
15
0
25
0
30
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
Address to Data Valid[11]
Data Hold from Address Change
CE LOW to Data Valid[11]
OE LOW to Data Valid[11]
OE LOW to Low Z[9, 12]
OE HIGH to High Z[9, 12, 13]
CE LOW to Low Z[9, 12]
CE HIGH to High Z[9, 12, 13]
CE LOW to Power-Up[9]
CE HIGH to Power-Down[9]
15
25
30
tOHA
tACE
15
10
25
15
30
20
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
tPU
3
3
0
3
5
0
3
5
0
10
10
15
15
15
25
15
15
25
tPD
Write Cycle[14]
tWC
Write Cycle Time
15
12
12
2
25
20
20
2
30
25
25
2
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSCE
CE LOW to Write End
Address Set-up to Write End
Address Hold from Write End
Address Set-up to Write Start
R/W Pulse Width
tAW
tHA
tSA
0
0
0
tPWE
12
10
0
15
15
0
25
15
0
tSD
Data Set-up to Write End
Data Hold from Write End
R/W LOW to High Z [9]
R/W HIGH to Low Z [9]
tHD
tHZWE
tLZWE
10
15
15
0
0
0
Shaded areas contain preliminary information.
Notes:
10. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading of the specified
I
/I and 30-pF load capacitance.
OL OH,
11. AC test conditions use V = 1.6V and V = 1.4V.
OH
OL
12. At any given temperature and voltage condition for any given device, t
is less than t
and t
is less than t
.
LZOE
HZCE
LZCE
HZOE
13. t
, t
, t
, t
t
and t
are tested with C = 5pF as in (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
LZCE LZWE HZOE LZOE, HZCE,
HZWE L
14. The internal write time of the memory is defined by the overlap of CE LOW and R/W LOW. Both signals must be LOW to initiate a write and either signal can
terminate a write by going HIGH. The data input setup and hold timing should be referenced to the rising edge of the signal that terminates the write.
Document #: 38-06031 Rev. *C
Page 4 of 18
CY7C132/CY7C136
CY7C142/CY7C146
Switching Characteristics Over the Operating Range (Speeds -15, -25, -30) (continued)[5, 10]
7C132-25[3]
7C136-25
7C142-25
7C146-25
7C132-30
7C136-30
7C142-30
7C146-30
7C136-15[3]
7C146-15
Parameter
Description
Min.
Max.
Min.
Max.
Min.
Max.
Unit
Busy/Interrupt Timing
tBLA
tBHA
tBLC
tBHC
tPS
BUSY LOW from Address Match
BUSY HIGH from Address Mismatch[15]
BUSY LOW from CE LOW
15
15
15
15
20
20
20
20
20
20
20
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
BUSY HIGH from CE HIGH[15]
Port Set Up for Priority
5
0
5
0
5
0
tWB
R/W LOW after BUSY LOW[16]
R/W HIGH after BUSY HIGH
BUSY HIGH to Valid Data
tWH
13
20
30
tBDD
tDDD
tWDD
15
25
30
Write Data Valid to Read Data Valid
Write Pulse to Data Delay
Note 17
Note 17
Note 17
Note 17
Note 17
Note 17
Interrupt Timing[18]
tWINS
tEINS
tINS
R/W to INTERRUPT Set Time
15
15
15
15
15
15
25
25
25
25
25
25
25
25
25
25
25
25
ns
ns
ns
ns
ns
ns
CE to INTERRUPT Set Time
Address to INTERRUPT Set Time
OE to INTERRUPT Reset Time[15]
CE to INTERRUPT Reset Time[15]
Address to INTERRUPT Reset Time[15]
tOINR
tEINR
tINR
Switching Characteristics Over the Operating Range (Speeds -35, -45, -55) [5, 10]
7C132-35
7C136-35
7C142-35
7C146-35
7C132-45
7C132-55
7C136-45
7C136-55
7C142-55
7C146-55
7C142-45
7C146-45
Parameter
Description
Min.
Max.
Min.
Max.
Min.
Max.
Unit
Read Cycle
tRC
Read Cycle Time
35
0
45
0
55
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
Address to Data Valid[11]
Data Hold from Address Change
CE LOW to Data Valid[11]
OE LOW to Data Valid[11]
OE LOW to Low Z[9, 12]
OE HIGH to High Z[9, 12, 13]
CE LOW to Low Z[9, 12]
CE HIGH to High Z[9, 12, 13]
CE LOW to Power-Up[9]
CE HIGH to Power-Down[9]
35
45
55
tOHA
tACE
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
tPU
35
20
45
25
55
25
3
5
0
3
5
0
3
5
0
20
20
35
20
20
35
25
25
35
tPD
Notes:
15. These parameters are measured from the input signal changing, until the output pin goes to a high-impedance state.
16. CY7C142/CY7C146 only.
17. A write operation on Port A, where Port A has priority, leaves the data on Port B’s outputs undisturbed until one access time after one of the following:
BUSY on Port B goes HIGH.
Port B’s address toggled.
CE for Port B is toggled.
R/W for Port B is toggled during valid read.
18. 52-pin PLCC and PQFP versions only.
Document #: 38-06031 Rev. *C
Page 5 of 18
CY7C132/CY7C136
CY7C142/CY7C146
Switching Characteristics Over the Operating Range (Speeds -35, -45, -55) (continued)[5, 10]
7C132-35
7C136-35
7C142-35
7C146-35
7C132-45
7C136-45
7C142-45
7C146-45
7C132-55
7C136-55
7C142-55
7C146-55
Parameter
Description
Min.
Max.
Min.
Max.
Min.
Max.
Unit
Write Cycle[14]
tWC
tSCE
tAW
Write Cycle Time
35
30
30
2
45
35
35
2
55
40
40
2
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CE LOW to Write End
Address Set-up to Write End
Address Hold from Write End
Address Set-up to Write Start
R/W Pulse Width
tHA
tSA
0
0
0
tPWE
tSD
25
15
0
30
20
0
30
20
0
Data Set-up to Write End
Data Hold from Write End
R/W LOW to High Z [9]
R/W HIGH to Low Z [9]
tHD
tHZWE
tLZWE
20
20
25
0
0
0
Busy/Interrupt Timing
tBLA
tBHA
tBLC
tBHC
tPS
BUSY LOW from Address Match
BUSY HIGH from Address Mismatch[15]
20
20
20
20
25
25
25
25
30
30
30
30
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
BUSY LOW from CE LOW
BUSY HIGH from CE HIGH[15]
Port Set Up for Priority
R/W LOW after BUSY LOW[16]
R/W HIGH after BUSY HIGH
BUSY HIGH to Valid Data
5
0
5
0
5
0
tWB
tWH
30
35
35
tBDD
tDDD
tWDD
35
45
45
Write Data Valid to Read Data Valid
Note 17
Note 17
Note 17
Note 17
Note 17
Note 17
Write Pulse to Data Delay
Interrupt Timing[18]
tWINS
tEINS
tINS
R/W to INTERRUPT Set Time
25
25
25
25
25
25
35
35
35
35
35
35
45
45
45
45
45
45
ns
ns
ns
ns
ns
ns
CE to INTERRUPT Set Time
Address to INTERRUPT Set Time
OE to INTERRUPT Reset Time[15]
CE to INTERRUPT Reset Time[15]
Address to INTERRUPT Reset Time[15]
tOINR
tEINR
tINR
Document #: 38-06031 Rev. *C
Page 6 of 18
CY7C132/CY7C136
CY7C142/CY7C146
Switching Waveforms
Read Cycle No. 1 (Either Port-Address Access)[19, 20]
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Read Cycle No. 2 (Either Port-CE/OE)[19, 21]
CE
t
HZCE
t
ACE
OE
t
HZOE
t
DOE
t
LZOE
t
LZCE
DATA VALID
DATA OUT
t
PU
t
PD
I
CC
I
SB
Read Cycle No. 3 (Read with BUSY Master: CY7C132 and CY7C136)
t
RC
ADDRESSR
R/WR
ADDRESS MATCH
t
PWE
DINR
VALID
t
PS
ADDRESS MATCH
ADDRESSL
BUSYL
t
BHA
t
t
BDD
BLA
DOUTL
VALID
t
DDD
t
WDD
Notes:
19. R/W is HIGH for read cycle.
20. Device is continuously selected, CE = V and OE = V .
IL
IL
21. Address valid prior to or coincident with CE transition LOW.
Document #: 38-06031 Rev. *C
Page 7 of 18
CY7C132/CY7C136
CY7C142/CY7C146
Switching Waveforms (continued)
Write Cycle No.1 (OE Three-States Data I/Os—Either Port)[14, 22]
t
WC
ADDRESS
CE
t
SCE
t
t
HA
AW
t
SA
t
PWE
R/W
t
t
HD
SD
DATAIN
OE
DATA VALID
t
HZOE
HIGH IMPEDANCE
DOUT
Write Cycle No. 2 (R/W Three-States Data I/Os—Either Port)[14, 23]
t
WC
ADDRESS
CE
t
t
SCE
HA
t
AW
t
SA
t
PWE
R/W
t
t
HD
SD
DATAIN
DATA VALID
t
t
LZWE
HZWE
HIGH IMPEDANCE
DOUT
Notes:
22. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of t
or t
+ t to allow the data I/O pins to enter high impedance
SD
PWE
HZWE
and for data to be placed on the bus for the required t
.
SD
23. If the CE LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in a high-impedance state.
Document #: 38-06031 Rev. *C
Page 8 of 18
CY7C132/CY7C136
CY7C142/CY7C146
Switching Waveforms (continued)
Busy Timing Diagram No. 1 (CE Arbitration)
CEL Valid First:
ADDRESSL,R
ADDRESS MATCH
CEL
t
PS
CER
t
t
BHC
BLC
BUSYR
CER Valid First:
ADDRESSL,R
CER
ADDRESS MATCH
t
PS
CEL
t
t
BHC
BLC
BUSYL
Busy Timing Diagram No. 2 (Address Arbitration)
Left Address Valid First:
t
or t
WC
RC
ADDRESSL
ADDRESSR
ADDRESS MATCH
ADDRESS MISMATCH
t
PS
t
t
BHA
BLA
BUSYR
Right Address Valid First:
t
or t
WC
RC
ADDRESSR
ADDRESS MATCH
ADDRESS MISMATCH
t
PS
ADDRESSL
BUSYL
t
t
BHA
BLA
Document #: 38-06031 Rev. *C
Page 9 of 18
CY7C132/CY7C136
CY7C142/CY7C146
Switching Waveforms (continued)
Busy Timing Diagram No. 3 (Write with BUSY, Slave: CY7C142/CY7C146)
CE
t
PWE
R/W
t
t
WH
WB
BUSY
Interrupt Timing Diagrams[18]
Left Side Sets INTR:
t
WC
ADDRESSL
WRITE 7FF
t
t
HA
INS
CEL
t
EINS
R/WL
t
SA
t
WINS
INTR
Right Side Clears INTR:
t
RC
ADDRESSR
CER
READ 7FF
t
t
HA
INR
t
EINR
R/WR
OER
t
OINR
INTR
Right Side Sets INTL:
t
WC
ADDRESSR
CER
WRITE 7FE
t
t
HA
INS
t
EINS
R/WR
INTL
t
SA
t
WINS
Document #: 38-06031 Rev. *C
Page 10 of 18
CY7C132/CY7C136
CY7C142/CY7C146
Interrupt Timing Diagrams[18] (continued)
Right Side Clears INTL:
t
RC
ADDRESS
READ 7FE
L
t
t
INR
HA
CE
L
t
EINR
R/W
L
OE
L
t
OINR
INT
L
Typical DC and AC Characteristics
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
OUTPUT SOURCE CURRENT
vs. OUTPUT VOLTAGE
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
120
100
80
1.4
1.2
I
CC
1.2
1.0
I
CC
1.0
0.8
0.8
0.6
0.4
60
V
= 5.0V
CC
V
V
= 5.0V
= 5.0V
CC
0.6
0.4
T = 25°C
A
IN
40
0.2
0.6
20
0
I
I
SB3
0.2
0.0
SB3
–55
25
125
0
1.0
2.0
3.0
4.0
4.0
4.5
5.0
5.5
6.0
AMBIENT TEMPERATURE (°C)
OUTPUT VOLTAGE (V)
SUPPLY VOLTAGE (V)
NORMALIZED ACCESS TIME
vs. AMBIENT TEMPERATURE
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
NORMALIZED ACCESS TIME
vs. SUPPLY VOLTAGE
140
120
1.6
1.4
1.4
1.3
1.2
1.1
100
80
1.2
1.0
60
T = 25°C
A
V
= 5.0V
1.0
CC
40
0.8
V
= 5.0V
CC
20
0
0.9
0.8
T = 25°C
A
0.6
0.0
1.0
2.0
3.0
4.0
–55
25
125
4.0
4.5
5.0
5.5
6.0
AMBIENT TEMPERATURE (°C)
OUTPUT VOLTAGE (V)
SUPPLY VOLTAGE (V)
TYPICAL POWER-ON CURRENT
vs. SUPPLY VOLTAGE
TYPICAL ACCESS TIME CHANGE
vs. OUTPUT LOADING
NORMALIZED I vs. CYCLE TIME
CC
1.25
30.0
25.0
3.0
2.5
V
A
V
= 5.0V
CC
T = 25°C
= 0.5V
IN
1.0
0.75
0.50
2.0
20.0
15.0
10.0
1.5
1.0
V
= 4.5V
CC
0.5
0.0
5.0
0
T = 25°C
A
10
20
30
40
0
1.0
2.0
3.0
4.0 5.0
0
200 400 600 800 1000
CAPACITANCE (pF)
CYCLE FREQUENCY (MHz)
SUPPLY VOLTAGE (V)
Document #: 38-06031 Rev. *C
Page 11 of 18
CY7C132/CY7C136
CY7C142/CY7C146
Ordering Information
Speed
Package
Name
Operating
Range
(ns)
Ordering Code
Package Type
48-Lead (600-Mil) Molded DIP
30
CY7C132-30PC
CY7C132-30PI
CY7C132-35PC
CY7C132-35PI
CY7C132-35DMB
CY7C132-45PC
CY7C132-45PI
CY7C132-45DMB
CY7C132-55PC
CY7C132-55PI
CY7C132-55DMB
CY7C136-15JC
CY7C136-15NC
CY7C136-25JC
CY7C136-25JXC
CY7C136-25NC
CY7C136-25NXC
CY7C136-30JC
CY7C136-30NC
CY7C136-30JI
P25
P25
P25
P25
D26
P25
P25
D26
P25
P25
D26
J69
N52
J69
J69
N52
N52
J69
N52
J69
J69
N52
J69
L69
J69
N52
J69
L69
J69
J69
N52
N52
J69
J69
N52
N52
L69
P25
P25
P25
P25
D26
Commercial
Industrial
Commercial
Industrial
Military
48-Lead (600-Mil) Molded DIP
48-Lead (600-Mil) Molded DIP
48-Lead (600-Mil) Molded DIP
48-Lead (600-Mil) Sidebraze DIP
48-Lead (600-Mil) Molded DIP
48-Lead (600-Mil) Molded DIP
48-Lead (600-Mil) Sidebraze DIP
48-Lead (600-Mil) Molded DIP
48-Lead (600-Mil) Molded DIP
48-Lead (600-Mil) Sidebraze DIP
52-Lead Plastic Leaded Chip Carrier
52-Pin Plastic Quad Flatpack
52-Lead Plastic Leaded Chip Carrier
35
45
55
Commercial
Industrial
Military
Commercial
Industrial
Military
15
25
Commercial
Commercial
52-Lead Pb-Free Plastic Leaded Chip Carrier
52-Pin Plastic Quad Flatpack
52-Pin Pb-Free Plastic Quad Flatpack
52-Lead Plastic Leaded Chip Carrier
52-Pin Plastic Quad Flatpack
30
35
Commercial
52-Lead Plastic Leaded Chip Carrier
52-Lead Plastic Leaded Chip Carrier
52-Pin Plastic Quad Flatpack
Industrial
CY7C136-35JC
CY7C136-35NC
CY7C136-35JI
Commercial
52-Lead Plastic Leaded Chip Carrier
52-Square Leadless Chip Carrier
52-Lead Plastic Leaded Chip Carrier
52-Pin Plastic Quad Flatpack
Industrial
Military
CY7C136-35LMB
CY7C136-45JC
CY7C136-45NC
CY7C136-45JI
45
55
Commercial
52-Lead Plastic Leaded Chip Carrier
52-Square Leadless Chip Carrier
52-Lead Plastic Leaded Chip Carrier
52-Lead Pb-Free Plastic Leaded Chip Carrier
52-Pin Plastic Quad Flatpack
Industrial
Military
CY7C136-45LMB
CY7C136-55JC
CY7C136-55JXC
CY7C136-55NC
CY7C136-55NXC
CY7C136-55JI
Commercial
52-Pin Pb-Free Plastic Quad Flatpack
52-Lead Plastic Leaded Chip Carrier
52-Lead Pb-Free Plastic Leaded Chip Carrier
52-Pin Plastic Quad Flatpack
Industrial
CY7C136-55JXI
CY7C136-55NI
CY7C136-55NXI
CY7C136-55LMB
CY7C142-30PC
CY7C142-30PI
CY7C142-35PC
CY7C142-35PI
CY7C142-35DMB
52-Pin Pb-Free Plastic Quad Flatpack
52-Square Leadless Chip Carrier
48-Lead (600-Mil) Molded DIP
Military
30
35
Commercial
Industrial
Commercial
Industrial
Military
48-Lead (600-Mil) Molded DIP
48-Lead (600-Mil) Molded DIP
48-Lead (600-Mil) Molded DIP
48-Lead (600-Mil) Sidebraze DIP
Document #: 38-06031 Rev. *C
Page 12 of 18
CY7C132/CY7C136
CY7C142/CY7C146
Ordering Information (continued)
Speed
Package
Name
Operating
Range
(ns)
Ordering Code
CY7C142-45PC
Package Type
48-Lead (600-Mil) Molded DIP
45
P25
P25
D26
P25
P25
D26
J69
N52
J69
J69
N52
J69
N52
J69
J69
N52
J69
L69
J69
N52
J69
L69
J69
J69
N52
J69
L69
Commercial
Industrial
Military
CY7C142-45PI
CY7C142-45DMB
CY7C142-55PC
CY7C142-55PI
CY7C142-55DMB
CY7C146-15JC
CY7C146-15NC
CY7C146-25JC
CY7C146-25JXC
CY7C146-25NC
CY7C146-30JC
CY7C146-30NC
CY7C146-30JI
CY7C146-35JC
CY7C146-35NC
CY7C146-35JI
CY7C146-35LMB
CY7C146-45JC
CY7C146-45NC
CY7C146-45JI
CY7C146-45LMB
CY7C146-55JC
CY7C146-55JXC
CY7C146-55NC
CY7C146-55JI
CY7C146-55LMB
48-Lead (600-Mil) Molded DIP
48-Lead (600-Mil) Sidebraze DIP
48-Lead (600-Mil) Molded DIP
48-Lead (600-Mil) Molded DIP
48-Lead (600-Mil) Sidebraze DIP
52-Lead Plastic Leaded Chip Carrier
52-Pin Plastic Quad Flatpack
55
Commercial
Industrial
Military
15
25
Commercial
52-Lead Plastic Leaded Chip Carrier
Commercial
52-Lead Pb-Free Plastic Leaded Chip Carrier
52-Pin Plastic Quad Flatpack
30
35
52-Lead Plastic Leaded Chip Carrier
52-Pin Plastic Quad Flatpack
Commercial
52-Lead Plastic Leaded Chip Carrier
52-Lead Plastic Leaded Chip Carrier
52-Pin Plastic Quad Flatpack
Industrial
Commercial
52-Lead Plastic Leaded Chip Carrier
52-Square Leadless Chip Carrier
52-Lead Plastic Leaded Chip Carrier
52-Pin Plastic Quad Flatpack
Industrial
Military
45
55
Commercial
52-Lead Plastic Leaded Chip Carrier
52-Square Leadless Chip Carrier
52-Lead Plastic Leaded Chip Carrier
52-Lead Pb-Free Plastic Leaded Chip Carrier
52-Pin Plastic Quad Flatpack
Industrial
Military
Commercial
52-Lead Plastic Leaded Chip Carrier
52-Square Leadless Chip Carrier
Industrial
Military
Document #: 38-06031 Rev. *C
Page 13 of 18
CY7C132/CY7C136
CY7C142/CY7C146
MILITARY SPECIFICATIONS
Switching Characteristics
Group A Subgroup Testing—DC Characteristics
Parameter
Subgroups
Parameter
VOH
VOL
Subgroups
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
Read Cycle
tRC
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
tAA
VIH
tACE
VIL Max.
IIX
tDOE
Write Cycle
IOZ
tWC
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
ICC
tSCE
ISB1
tAW
ISB2
tHA
ISB3
tSA
ISB4
tPWE
tSD
tHD
Busy/Interrupt Timing
tBLA
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
tBHA
tBLC
tBHC
tPS
tWINS
tEINS
tINS
tOINR
tEINR
tINR
BUSY TIMING
[24]
tWB
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
tWH
tBDD
Note:
24. CY7C142/CY7C146 only.
Document #: 38-06031 Rev. *C
Page 14 of 18
CY7C132/CY7C136
CY7C142/CY7C146
Package Diagrams
48-Lead (600-Mil) Sidebraze DIP D26
MIL-STD-1835 D-14 Config. C
51-80044-**
52-Lead Plastic Leaded Chip Carrier J69
52-Lead Pb-Free Plastic Leaded Chip Carrier J69
51-85004-*A
Document #: 38-06031 Rev. *C
Page 15 of 18
CY7C132/CY7C136
CY7C142/CY7C146
Package Diagrams (continued)
52-Square Leadless Chip Carrier L69
51-80054-**
52-Lead Plastic Quad Flatpack N52
52-Lead Pb-Free Plastic Quad Flatpack N52
51-85042-**
Document #: 38-06031 Rev. *C
Page 16 of 18
CY7C132/CY7C136
CY7C142/CY7C146
Package Diagrams (continued)
48-Lead (600-Mil) Molded DIP P25
51-85020-*A
All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-06031 Rev. *C
Page 17 of 18
© Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY7C132/CY7C136
CY7C142/CY7C146
Document History Page
Document Title: CY7C132/CY7C136/CY7C142/CY7C146 2K x 8 Dual Port Static RAM
Document Number: 38-06031
Orig. of
REV.
**
ECN NO. Issue Date Change
Description of Change
110171
128959
236748
393184
10/21/01
09/03/03
SZV
JFU
Change from Spec number: 38-06031
Added CY7C136-55NI to Order Information
*A
*B
See ECN YDT
See ECN YIM
Removed cross information from features section
*C
Added Pb-Free Logo
Added Pb-Free parts to ordering information:
CY7C136-25JXC, CY7C136-25NXC, CY7C136-55JXC, CY7C136-55NXC,
CY7C136-55JXI, CY7C136-55NXI, CY7C146-25JXC, CY7C146-55JXC
Document #: 38-06031 Rev. *C
Page 18 of 18
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