概述
数据手册CY7C1345G-100BGC 概述
4-Mbit (128K x 36) Flow-Through Sync SRAM 4兆位（ 128K ×36 ）流通型同步SRAM
CY7C1345G-100BGC 数据手册
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PDF下载CY7C1345G
PRELIMINARY
4-Mbit (128K x 36) Flow-Through Sync SRAM
Features
Functional Description[1]
The CY7C1345G is a 131,072 x 36 synchronous cache RAM
designed to interface with high-speed microprocessors with
• 128K X 36 common I/O
• 3.3V –5% and +10% core power supply (VDD
)
minimum glue logic. Maximum access delay from clock rise is
6.5 ns (133-MHz version). A 2-bit on-chip counter captures the
first address in a burst and increments the address automati-
cally for the rest of the burst access. All synchronous inputs
are gated by registers controlled by a positive-edge-triggered
Clock Input (CLK). The synchronous inputs include all
addresses, all data inputs, address-pipelining Chip Enable
• 2.5V or 3.3V I/O supply (VDDQ
• Fast clock-to-output times
— 6.5 ns (133-MHz version)
— 7.5 ns (117-MHz version)
— 8.0 ns (100-MHz version)
)
(
), depth-expansion Chip Enables (CE and
), Burst
CE3
CE1
Control inputs (
2
• Provide high-performance 2-1-1-1 access rate
,
,
), Write Enables
). Asynchronous
)
and the ZZ pin
and
(
,
BWx
ADV
ADSC ADSP
), and Global Write (
• User-selectable burst counter supporting Intel®
GW
and
nputs
BWE
include the Output Enable
i
Pentium® interleaved or linear burst sequences
(
.
OE
The CY7C1345G allows either interleaved or linear burst
sequences, selected by the MODE input pin. A HIGH selects
an interleaved burst sequence, while a LOW selects a linear
burst sequence. Burst accesses can be initiated with the
Processor Address Strobe (ADSP) or the cache Controller
Address Strobe (ADSC) inputs.
• Separate processor and controller address strobes
• Synchronous self-timed write
• Asynchronous output enable
• Lead-Free 100-pin TQFP and 119-ball BGA packages
• “ZZ” Sleep Mode option
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (
) or
ADSP
Address Strobe Controller (
burst addresses can be internally generated as controlled by
the Advance pin ( ).
) are active. Subsequent
ADSC
ADV
The CY7C1345G operates from a +3.3V core power supply
while all outputs may operate with either a +2.5 or +3.3V
supply. All inputs and outputs are JEDEC-standard
JESD8-5-compatible.
Logic Block Diagram
ADDRESS
REGISTER
A0, A1, A
A[1:0]
MODE
ADV
CLK
Q1
BURST
COUNTER
AND LOGIC
Q0
CLR
ADSC
ADSP
DQ
BYTE
WRITE REGISTER
D, DQPD
DQ
BYTE
WRITE REGISTER
D, DQPD
BW
D
DQ
BYTE
WRITE REGISTER
C, DQPC
DQ
BYTE
WRITE REGISTER
C, DQPC
BW
C
OUTPUT
BUFFERS
DQs
MEMORY
ARRAY
SENSE
AMPS
DQP
DQP
DQP
A
DQ
BYTE
WRITE REGISTER
B, DQPB
B
C
DQ
BYTE
WRITE REGISTER
B, DQPB
BW
B
DQPD
DQ
BYTE
WRITE REGISTER
A, DQPA
DQ
A, DQPA
BW
A
BYTE
BWE
WRITE REGISTER
INPUT
REGISTERS
GW
ENABLE
REGISTER
CE1
CE2
CE3
OE
SLEEP
CONTROL
ZZ
Note:
1. For best–practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
Cypress Semiconductor Corporation
Document #: 38-05517 Rev. *A
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Revised October 21, 2004
CY7C1345G
PRELIMINARY
Selection Guide
133 MHz
6.5
117 MHz
100 MHz
8.0
Unit
ns
mA
mA
Maximum Access Time
Maximum Operating Current
Maximum Standby Current
7.5
220
40
225
40
205
40
Shaded areas contain advance information. Please contact your local Cypress sales representative for availability of these parts.
Pin Configurations
100-Pin TQFP
DQPC
DQC
DQC
VDDQ
VSSQ
DQC
DQC
DQC
DQC
VSSQ
VDDQ
DQC
DQC
NC
1
DQPB
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
2
DQB
DQB
3
4
VDDQ
VSSQ
DQB
DQB
DQB
DQB
VSSQ
VDDQ
DQB
DQB
VSS
5
6
7
8
BYTE C
BYTE B
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
CY7C1345G
VDD
NC
NC
VDD
ZZ
VSS
DQD
DQD
VDDQ
VSSQ
DQD
DQD
DQD
DQD
VSSQ
VDDQ
DQD
DQD
DQPD
DQA
DQA
VDDQ
VSSQ
DQA
DQA
DQA
DQA
VSSQ
VDDQ
DQA
DQA
DQPA
BYTE D
BYTE A
Document #: 38-05517 Rev. *A
Page 2 of 17
CY7C1345G
PRELIMINARY
Pin Configurations (continued)
119-Ball BGA
2
1
3
A
4
5
A
6
7
VDDQ
NC
A
A
VDDQ
NC
A
B
C
D
E
F
ADSP
CE2
A
A
A
ADSC
VDD
CE3
A
NC
A
A
NC
DQC
DQC
VDDQ
DQC
DQC
VDDQ
DQD
DQPC
DQC
DQC
DQC
DQC
VDD
DQD
VSS
VSS
VSS
NC
VSS
VSS
VSS
DQPB
DQB
DQB
DQB
DQB
VDD
DQB
DQB
VDDQ
DQB
DQB
VDDQ
DQA
CE1
OE
G
H
J
BWC
VSS
NC
BWB
VSS
NC
ADV
GW
VDD
K
VSS
CLK
NC
VSS
DQA
L
M
N
DQD
VDDQ
DQD
DQD
DQD
DQD
BWD
VSS
VSS
BWA
VSS
VSS
DQA
DQA
DQA
DQA
VDDQ
DQA
BWE
A1
P
R
T
DQD
NC
DQPD
A
VSS
MODE
A
A0
VDD
A
VSS
NC
A
DQPA
A
DQA
NC
NC
NC
NC
NC
NC
ZZ
VDDQ
NC
NC
NC
VDDQ
U
Pin Definitions
Name
I/O
Input-
Description
Address Inputs used to select one of the 128K address locations. Sampled at the rising edge
A0, A1, A
Synchronous of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 are sampled active. A[1:0] feed
the 2-bit counter.
BWA,BWB
BWC,BWD
GW
Input-
Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes to the SRAM.
Synchronous Sampled on the rising edge of CLK.
Input-
Global Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK, a global
Synchronous write is conducted (ALL bytes are written, regardless of the values on BW[A:D] and BWE).
Input-
Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal must be
BWE
CLK
Synchronous asserted LOW to conduct a byte write.
Input-Clock Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the burst
counter when ADV is asserted LOW, during a burst operation.
Input-
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
if CE1 is HIGH. CE1 is sampled only
when a new external address is loaded.
CE1
CE2
Synchronous CE and CE to select/deselect the device. ADSP is ignored
2
3
Input-
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with
Synchronous CE1 and CE3 to select/deselect the device.CE
2 is sampled only when a new external address is
loaded.
Input-
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1
CE3
OE
Synchronous and CE2 to select/deselect the device. CE
3 is sampled only when a new external address is loaded.
Input-
Output Enable, asynchronous input, active LOW. Controls the direction of the I/O pins. When
Asynchronous LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tri-stated, and act as
input data pins. OE is masked during the first clock of a read cycle when emerging from a deselected
state.
Input-
Advance Input signal, sampled on the rising edge of CLK. When asserted, it automatically
ADV
Synchronous increments the address in a burst cycle.
Document #: 38-05517 Rev. *A
Page 3 of 17
CY7C1345G
PRELIMINARY
Pin Definitions (continued)
Name
ADSP
I/O
Description
Address Strobe from Processor, sampled on the rising edge of CLK, active LOW. When
Input-
Synchronous asserted LOW, addresses presented to the device are captured in the address registers. A[1:0] are
also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recog-
nized. ASDP is ignored when
CE1 is deasserted HIGH
Input-
Address Strobe from Controller, sampled on the rising edge of CLK, active LOW. When
ADSC
ZZ
Synchronous asserted LOW, addresses presented to the device are captured in the address registers. A[1:0] are
also loaded into the burst counter. When ADSP
and ADSC are both asserted, only ADSP is recog-
.
nized
ZZ “sleep” Input, active HIGH. When asserted HIGH places the device ina non-time-critical “sleep”
Input-
Asynchronous condition with data integrity preserved. For normal operation, this pin has to be LOW or left floating.
ZZ pin has an internal pull-down.
DQs
I/O-
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered by
DQPA,
DQPB
DQPC,
DQPD
Synchronous the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified
by the addresses presented during the previous clock rise of the read cycle. The direction of the
pins is controlled by
. When
OE
is asserted LOW, the pins behave as outputs. When HIGH, DQs
OE
and DQP[A:D] are placed in a tri-state condition.
VDD
VSS
Power Supply Power supply inputs to the core of the device.
Ground
Ground for the core of the device.
VDDQ
I/O Power Power supply for the I/O circuitry.
Supply
VSSQ
I/O Ground Ground for the I/O circuitry.
MODE
Input-
Static
Selects Burst Order. When tied to GND selects linear burst sequence. When tied to VDD or left
floating selects interleaved burst sequence. This is a strap pin and should remain static during device
operation. Mode Pin has an internal pull-up.
NC
No Connects. Not Internally connected to the die.
Functional Overview
Single Read Accesses
A single read access is initiated when the following conditions
are satisfied at clock rise: (1) CE1, CE2, and CE3 are all
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. Maximum access delay from
the clock rise (tC0) is 6.5 ns (133-MHz device).
asserted active, and (2) ADSP or ADSC is asserted LOW (if
the access is initiated by ADSC, the write inputs must be
deasserted during this first cycle). The address presented to
the address inputs is latched into the address register and the
burst counter/control logic and presented to the memory core.
If the OE input is asserted LOW, the requested data will be
available at the data outputs a maximum to tCDV after clock
The CY7C1345G supports secondary cache in systems
utilizing either a linear or interleaved burst sequence. The
interleaved burst order supports Pentium® and i486
processors. The linear burst sequence is suited for processors
that utilize a linear burst sequence. The burst order is
user-selectable, and is determined by sampling the MODE
input. Accesses can be initiated with either the Processor
Address Strobe (ADSP) or the Controller Address Strobe
(ADSC). Address advancement through the burst sequence is
controlled by the ADV input. A two-bit on-chip wraparound
burst counter captures the first address in a burst sequence
and automatically increments the address for the rest of the
burst access.
rise. ADSP is ignored if CE1 is HIGH.
Single Write Accesses Initiated by ADSP
This access is initiated when the following conditions are
satisfied at clock rise: (1)
CE1, CE2, CE3 are all asserted
ADSP is asserted LOW. The addresses
active, and (2)
presented are loaded into the address register and the burst
inputs (
GW, BWE, and BWx )are ignored during this first clock
cycle. If the write inputs are asserted active ( see Write Cycle
Descriptions table for appropriate states that indicate a write)
on the next clock rise,the appropriate data will be latched and
written into the device.Byte writes are allowed. During byte
Byte write operations are qualified with the Byte Write Enable
[A:D]
(BWE) and Byte Write Select (BW
) inputs. A Global Write
Enable (GW) overrides all byte write inputs and writes data to
all four bytes. All writes are simplified with on-chip
synchronous self-timed write circuitry.
BWC
BWA controls DQA and BWB controls DQB,
writes,
controls DQC, and BWD controls DQ .
D All I/Os are tri-stated
during a byte write.Since this is a common I/O device, the
Three synchronous Chip Selects (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide for easy bank
asynchronous
OE input signal must be deasserted and the
I/Os must be tri-stated prior to the presentation of data to DQs.
As a safety precaution, the data lines are tri-stated once a write
cycle is detected, regardless of the state of OE.
selection and output tri-state control. ADSP is ignored if
is HIGH.
CE1
Document #: 38-05517 Rev. *A
Page 4 of 17
CY7C1345G
PRELIMINARY
Single Write Accesses Initiated by ADSC
Interleaved Burst Address Table (MODE =
Floating or VDD
This write access is initiated when the following conditions are
satisfied at clock rise: (1) CE1, CE2, and CE3 are all asserted
active, (2) ADSC is asserted LOW, (3) ADSP is deasserted
HIGH, and (4) the write input signals (GW, BWE, and BWx)
indicate a write access. ADSC is ignored if ADSP is active LOW.
)
First
Second
Address
A1, A0
Third
Address
A1, A0
Fourth
Address
A1, A0
Address
A1, A0
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
The addresses presented are loaded into the address register
and the burst counter/control logic and delivered to the
memory core. The information presented to DQ[D:A] will be
written into the specified address location. Byte writes are
allowed. During byte writes, BWA controls DQA, BWB controls
DQB, BWC controls DQC, and BWD controls DQD. All I/Os are
tri-stated when a write is detected, even a byte write. Since this
is a common I/O device, the asynchronous OE input signal
must be deasserted and the I/Os must be tri-stated prior to the
presentation of data to DQs. As a safety precaution, the data
lines are tri-stated once a write cycle is detected, regardless
Linear Burst Address Table (MODE = GND)
First
Address
A1,A0
Second
Address
A1,A0
Third
Address
A1,A0
Fourth
Address
A1,A0
of the state of OE.
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
Burst Sequences
The CY7C1345G provides an on-chip two-bit wraparound
burst counter inside the SRAM. The burst counter is fed by
A[1:0], and can follow either a linear or interleaved burst order.
The burst order is determined by the state of the MODE input.
A LOW on MODE will select a linear burst sequence. A HIGH
on MODE will select an interleaved burst order. Leaving
MODE unconnected will cause the device to default to a inter-
leaved burst sequence.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CEs, ADSP, and ADSC must remain
inactive for the duration of tZZREC after the ZZ input returns
LOW.
ZZ Mode Electrical Characteristics
Parameter
IDDZZ
Description
Snooze mode standby current
Device operation to ZZ
Test Conditions
ZZ > VDD – 0.2V
Min.
Max.
40
Unit
mA
ns
tZZS
ZZ > VDD – 0.2V
2tCYC
tZZREC
tZZI
ZZ recovery time
ZZ < 0.2V
2tCYC
0
ns
ZZ Active to snooze current
ZZ Inactive to exit snooze current
This parameter is sampled
This parameter is sampled
2tCYC
ns
tRZZI
ns
Document #: 38-05517 Rev. *A
Page 5 of 17
CY7C1345G
PRELIMINARY
Truth Table[2, 3, 4, 5, 6]
Address
Used
Cycle Description
CE1 CE2 CE3 ZZ ADSP ADSC ADV WRITE OE CLK
DQ
Deselected Cycle,
Power-down
None
None
None
None
None
H
L
L
L
X
X
X
X
H
X
X
L
L
L
L
L
X
L
X
X
L
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L-H tri-state
L-H tri-state
L-H tri-state
L-H tri-state
L-H tri-state
Deselected Cycle,
Power-down
L
L
Deselected Cycle,
Power-down
X
L
L
Deselected Cycle,
Power-down
H
H
Deselected Cycle,
Power-down
X
Snooze Mode, Power-down
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Write Cycle, Begin Burst
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Write Cycle, Suspend Burst
None
External
External
External
External
External
Next
X
L
X
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
X
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
L
X
X
X
L
X
X
X
X
X
X
L
X
X
X
L
X
L
X
tri-state
Q
L-H
L
L
L
H
X
L
L-H tri-state
L
L
H
H
H
H
H
X
X
H
X
H
H
X
X
H
X
L-H
L-H
D
Q
L
L
L
H
H
H
H
H
H
L
L
L
L
H
L
L-H tri-state
L-H
L-H tri-state
L-H
L-H tri-state
X
X
H
H
X
H
X
X
H
H
X
H
X
X
X
X
X
X
X
X
X
X
X
X
H
H
H
H
H
H
H
H
H
H
H
H
Q
Next
L
H
L
Next
L
Q
Next
L
H
X
X
L
Next
L
L-H
L-H
L-H
D
D
Q
Next
L
L
Current
Current
Current
Current
Current
Current
H
H
H
H
H
H
H
H
H
H
L
H
L
L-H tri-state
L-H
L-H tri-state
Q
H
X
X
L-H
L-H
D
D
Write Cycle, Suspend Burst
L
Notes:
2. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.
3. WRITE = L when any one or more Byte Write enable signals (BW , BW , BW , BW ) and BWE = L or GW= L. WRITE = H when all Byte write enable signals
A
B
C
D
(BW , BW , BW , BW ), BWE, GW = H.
A
B
C
D
4. The DQ pins are controlled by the current cycle and the
signal.
is asynchronous and is not sampled with the clock.
OE
OE
5. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW
. Writes may occur only on subsequent clocks
[A: D]
after the
or with the assertion of
. As a result,
ADSC
must be driven HIGH prior to the start of the write cycle to allow the outputs to tri-state.
is a
OE
OE
ADSP
don't care for the remainder of the write cycle.
is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tri-state when
6.
is
OE
OE
inactive or when the device is deselected, and all data bits behave as output when
is active (LOW).
OE
Document #: 38-05517 Rev. *A
Page 6 of 17
CY7C1345G
PRELIMINARY
Partial Truth Table for Read/Write[2, 7]
Function
Read
BWD
X
H
H
H
H
H
H
H
H
L
BWC
X
H
H
H
H
L
BWB
X
H
H
L
BWA
X
H
L
GW
BWE
H
H
Read
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
Write Byte (A, DQPA)
Write Byte (B, DQPB)
H
L
Write Bytes (B, A, DQPA, DQPB)
Write Byte (C, DQPC)
L
H
H
L
H
L
Write Bytes (C, A, DQPC, DQPA)
Write Bytes (C, B, DQPC, DQPB)
Write Bytes (C, B, A, DQPC, DQPB, DQPA)
Write Byte (D, DQPD)
L
L
H
L
L
L
H
H
H
H
L
H
H
L
H
L
Write Bytes (D, A, DQPD, DQPA)
Write Bytes (D, B, DQPD, DQPA)
Write Bytes (D, B, A, DQPD, DQPB, DQPA)
Write Bytes (D, B, DQPD, DQPB)
Write Bytes (D, B, A, DQPD, DQPC, DQPA)
Write Bytes (D, C, A, DQPD, DQPB, DQPA)
Write All Bytes
L
L
H
L
L
L
L
H
H
L
H
L
L
L
L
L
H
L
L
L
L
Write All Bytes
X
X
X
X
Note:
7. Table only lists a partial listing of the byte write combinations. Any combination of BW is valid. Appropriate write will be done based on which byte write is active.
x
Document #: 38-05517 Rev. *A
Page 7 of 17
CY7C1345G
PRELIMINARY
Current into Outputs (LOW)......................................... 20 mA
Maximum Ratings
Static Discharge Voltage........................................... >2001V
(per MIL-STD-883, Method 3015)
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Latch-up Current..................................................... >200 mA
Storage Temperature .................................–65°C to +150°C
Operating Range
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Ambient
Supply Voltage on VDD Relative to GND........ –0.5V to +4.6V
Range
Temperature]
VDD
VDDQ
DC Voltage Applied to Outputs
in tri-state ............................................ –0.5V to VDDQ + 0.5V
Commercial 0°C to +70°C 3.3V −5%/+10% 2.5V –5%
to VDD
Industrial
–40°C to +85°C
DC Input Voltage....................................–0.5V to VDD + 0.5V
[8, 9]
Electrical Characteristics Over the Operating Range
CY7C1345F
Parameter
VDD
Description
Power Supply Voltage
I/O Supply Voltage
Test Conditions
Min.
Max.
3.6
Unit
V
3.135
2.375
2.4
VDDQ
VDD
V
VOH
Output HIGH Voltage
VDDQ = 3.3V, VDD = Min., IOH = –4.0 mA
DDQ = 2.5V, VDD = Min., IOH = –1.0 mA
V
V
2.0
V
VOL
VIH
VIL
IX
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage[8]
VDDQ = 3.3V, VDD = Min., IOL = 8.0 mA
VDDQ = 2.5V, VDD = Min., IOL = 1.0 mA
VDDQ = 3.3V
0.4
0.4
V
V
2.0 VDD + 0.3V
1.7 VDD + 0.3V
V
V
DDQ = 2.5V
VDDQ = 3.3V
DDQ = 2.5V
V
–0.3
–0.3
−5
0.8
0.7
5
V
V
V
Input Load Current
(except ZZ and MODE)
GND ≤ VI ≤ VDDQ
µA
Input Current of MODE
Input = VSS
–30
–5
µA
µA
Input = VDD
5
Input Current of ZZ
Input = VSS
µA
Input = VDD
30
5
µA
IOZ
IDD
Output Leakage Current
GND ≤ VI ≤ VDD, Output Disabled
–5
µA
VDD Operating Supply Current
VDD = Max., IOUT = 0 mA,
f = fMAX= 1/tCYC
7.5-ns cycle, 133 MHz
8.0-ns cycle, 117 MHz
10-ns cycle, 100 MHz
7.5-ns cycle, 133 MHz
8.0-ns cycle, 117 MHz
10-ns cycle, 100 MHz
All speeds
225
220
205
90
mA
mA
mA
mA
mA
mA
mA
ISB1
Automatic CE Power-down
Current—TTL Inputs
Max. VDD, Device Deselected,
VIN ≥ VIH or VIN ≤ VIL, f = fMAX
inputs switching
,
85
80
ISB2
Automatic CE Power-down
Current—CMOS Inputs
Max. VDD, Device Deselected,
VIN ≥ VDD – 0.3V or VIN ≤ 0.3V,
f = 0, inputs static
40
ISB3
Automatic CE Power-down
Current—CMOS Inputs
Max. VDD, Device Deselected,
VIN ≥VDDQ – 0.3V or VIN ≤ 0.3V,
f = fMAX, inputs switching
7.5-ns cycle, 133 MHz
8.0-ns cycle, 117 MHz
10-ns cycle, 100 MHz
75
70
65
45
mA
mA
mA
mA
ISB4
Automatic CE Power-down
Current—TTL Inputs
Max. VDD, Device Deselected, All speeds
VIN ≥ VDD – 0.3V or VIN ≤ 0.3V,
f = 0, inputs static
Shaded areas contain advance information.
Notes:
8. Overshoot: V (AC) < V +1.5V (Pulse width less than t
/2), undershoot: V (AC) > -2V (Pulse width less than t
/2).
IH
DD
CYC
IL
CYC
9. T
: Assumes a linear ramp from 0v to V (min.) within 200ms. During this time V < V and V
< V
Power-up
DD
IH
DD
DDQ DD.
Document #: 38-05517 Rev. *A
Page 8 of 17
CY7C1345G
PRELIMINARY
Thermal Resistance[10]
Parameter
ΘJA
Description
Test Conditions
TQFP Package
BGA Package Unit
Thermal Resistance
(Junction to Ambient)
Test conditions follow standard
test methods and procedures for
measuring thermal impedance,
per EIA / JESD51.
TBD
TBD
°C/W
ΘJC
Thermal Resistance
(Junction to Case)
TBD
TBD
°C/W
Capacitance[10]
Parameter
Description
Input Capacitance
Test Conditions
TQFP Package BGA Package
Unit
CIN
TA = 25°C, f = 1 MHz,
DD = 3.3V.
VDDQ = 3.3V
5
5
5
5
5
7
pF
pF
pF
V
CCLK
CI/O
Clock Input Capacitance
Input/Output Capacitance
AC Test Loads and Waveforms
3.3V I/O Test Load
R = 317Ω
3.3V
OUTPUT
ALL INPUT PULSES
90%
VDDQ
OUTPUT
90%
10%
Z = 50Ω
0
10%
R = 50Ω
L
GND
5 pF
R = 351Ω
≤ 1ns
≤ 1ns
V = 1.5V
T
INCLUDING
JIG AND
SCOPE
(a)
2.5V I/O Test Load
OUTPUT
(b)
(c)
R = 1667Ω
2.5V
OUTPUT
ALL INPUT PULSES
90%
VDDQ
GND
90%
10%
Z = 50Ω
0
R = 50Ω
10%
L
5 pF
INCLUDING
R =1538Ω
≤ 1ns
≤ 1ns
V = 1.25V
T
JIG AND
SCOPE
(a)
(b)
(c)
Switching Characteristics Over the Operating Range [15, 16]
133 MHz
117 MHz
100 MHz
Parameter
tPOWER
Description
VDD(Typical) to the first Access[11]
Min. Max. Min. Max. Min. Max. Unit
1
1
1
ms
Clock
tCYC
Clock Cycle Time
Clock HIGH
7.5
2.5
2.5
8.5
3.0
3.0
10
4.0
4.0
ns
ns
ns
tCH
tCL
Clock LOW
Output Times
tCDV
Data Output Valid After CLK Rise
Data Output Hold After CLK Rise
Clock to Low-Z[12, 13, 14]
6.5
7.5
8.0
ns
ns
ns
tDOH
2.0
0
2.0
0
2.0
0
tCLZ
Notes:
10. Tested initially and after any design or process change that may affect these parameters.
11. This part has a voltage regulator internally; t
is the time that the power needs to be supplied above V (minimum) initially before a read or write operation
POWER
DD
can be initiated.
12. t
, t
,t
, and t
are specified with AC test conditions shown in (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
CHZ CLZ OELZ
OEHZ
13. At any given voltage and temperature, t
is less than t
and t
is less than t
to eliminate bus contention between SRAMs when sharing the same
OEHZ
OELZ
CHZ
CLZ
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions.
14. This parameter is sampled and not 100% tested.
15. Timing reference level is 1.5V when V
= 3.3V and is 1.25V when V
= 2.5V.
DDQ
DDQ
16. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
Document #: 38-05517 Rev. *A
Page 9 of 17
CY7C1345G
PRELIMINARY
Switching Characteristics Over the Operating Range (continued)[15, 16]
133 MHz
117 MHz
100 MHz
Parameter
tCHZ
Description
Clock to High-Z[12, 13, 14]
Min. Max. Min. Max. Min. Max. Unit
3.5
3.5
3.5
3.5
3.5
3.5
ns
ns
ns
ns
tOEV
OE LOW to Output Valid
tOELZ
tOEHZ
Set-up Times
tAS
OE LOW to Output Low-Z[12, 13, 14]
OE HIGH to Output High-Z[12, 13, 14]
0
0
0
3.5
3.5
3.5
Address Set-up Before CLK Rise
ADSP, ADSC Set-up Before CLK Rise
ADV Set-up Before CLK Rise
1.5
1.5
1.5
1.5
1.5
1.5
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
ns
ns
ns
ns
ns
ns
tADS
tADVS
tWES
Set-up Before CLK Rise
GW, BWE, BWx
tDS
Data Input Set-up Before CLK Rise
Chip Enable Set-up
tCES
Hold Times
tAH
Address Hold After CLK Rise
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
ns
ns
tADH
ADSP, ADSC Hold After CLK Rise
,
,
tWEH
GW BWE BWx Hold After CLK Rise
ADV Hold After CLK Rise
tADVH
tDH
Data Input Hold After CLK Rise
Chip Enable Hold After CLK Rise
tCEH
Document #: 38-05517 Rev. *A
Page 10 of 17
CY7C1345G
PRELIMINARY
Timing Diagrams
Read Cycle Timing[17]
t
CYC
t
CLK
t
CL
CH
t
t
ADH
ADS
ADSP
ADSC
t
t
ADH
ADS
t
t
AH
AS
A1
A2
ADDRESS
t
t
WES
WEH
GW, BWE,BW
[A:D]
CE
Deselect Cycle
t
t
CES
CEH
t
t
ADVH
ADVS
ADV
OE
ADV suspends burst.
t
t
t
CDV
OEV
OELZ
t
t
OEHZ
CHZ
t
DOH
t
CLZ
Q(A2)
Q(A2 + 1)
Q(A2 + 2)
Q(A2 + 3)
Q(A2)
Q(A2 + 1)
Q(A2 + 2)
Q(A1)
Data Out (Q)
High-Z
t
CDV
Burst wraps around
to its initial state
Single READ
BURST
READ
DON’T CARE
UNDEFINED
Notes:
17. On this diagram, when CE is LOW: CE is LOW, CE is HIGH and CE is LOW. When CE is HIGH: CE is HIGH or CE is LOW or CE is HIGH.
1
2
3
1
2
3
18.
Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW LOW.
x
Document #: 38-05517 Rev. *A
Page 11 of 17
CY7C1345G
PRELIMINARY
Timing Diagrams (continued)
Write Cycle Timing[17, 18]
t
CYC
CLK
t
t
CL
CH
t
t
ADH
ADS
ADSP
ADSC
t
t
ADH
ADS
t
t
AH
AS
A1
A2
ADDRESS
t
t
WES
WEH
GW, BWE,BW
[A:D]
CE
Deselect Cycle
t
t
CES
CEH
t
t
ADVH
ADVS
ADV
OE
ADV suspends burst.
t
t
t
CDV
OEV
OELZ
t
t
OEHZ
CHZ
t
DOH
t
CLZ
Q(A2)
Q(A2 + 1)
Q(A2 + 2)
Q(A2 + 3)
Q(A2)
Q(A2 + 1)
Q(A2 + 2)
Q(A1)
Data Out (Q)
High-Z
t
CDV
Burst wraps around
to its initial state
Single READ
BURST
READ
DON’T CARE
UNDEFINED
Document #: 38-05517 Rev. *A
Page 12 of 17
CY7C1345G
PRELIMINARY
Timing Diagrams (continued)
Read/Write Timing[17, 19, 20]
t
CYC
CLK
t
t
CL
CH
t
t
ADH
ADS
ADSP
ADSC extends burst
t
t
ADH
ADS
t
t
ADH
ADS
ADSC
t
t
AH
AS
A1
A2
A3
ADDRESS
Byte write signals are ignored for first cycle when
ADSP initiates burst
t
t
WEH
WES
BWE,
BW[A:D]
t
t
WEH
WES
GW
CE
t
t
CEH
CES
t
t
ADVH
ADVS
ADV
ADV suspends burst
OE
t
t
DH
DS
Data in (D)
High-Z
D(A2)
D(A2 + 1)
D(A2 + 1)
D(A2 + 2)
D(A2 + 3)
D(A3)
D(A3 + 1)
D(A3 + 2)
D(A1)
t
OEHZ
Data Out (Q)
BURST READ
BURST WRITE
Extended BURST WRITE
Single WRITE
DON’T CARE
UNDEFINED
Notes:
19.
20.
.
The data bus (Q) remains in high-Z following a WRITE cycle, unless a new read access is initiated by
GW is HIGH.
ADSP or ADSC
Document #: 38-05517 Rev. *A
Page 13 of 17
CY7C1345G
PRELIMINARY
Timing Diagrams (continued)
ZZ Mode Timing [21, 22]
CLK
t
t
ZZ
ZZREC
ZZ
t
ZZI
I
SUPPLY
I
DDZZ
t
RZZI
ALL INPUTS
(except ZZ)
DESELECT or READ Only
Outputs (Q)
High-Z
DON’T CARE
Ordering Information
Speed
Package
Name
Operating
Range
(MHz)
Ordering Code
CY7C1345G-133AXC
CY7C1345G-133BGC
CY7C1345G-133BGXC
CY7C1345G-133AXI
CY7C1345G-133BGI
CY7C1345G-133BGXI
CY7C1345G-117AXC
CY7C1345G-117BGC
CY7C1345G-117BGXC
CY7C1345G-117AXI
CY7C1345G-117BGI
CY7C1345G-117BGXI
CY7C1345G-100AXC
CY7C1345G-100BGC
CY7C1345G-100BGXC
CY7C1345G-100AXI
CY7C1345G-100BGI
CY7C1345G-100BGXI
Package Type
133
A101
BG119
BG119
A101
Lead-free 100-Lead Thin Quad Flat Pack (14 x 20 x 1.4mm) Commercial
119-Ball PBGA (14 x 22 x 2.4mm)
Lead-free 119-Ball PBGA (14 x 22 x 2.4mm)
Lead-free 100-Lead Thin Quad Flat Pack (14 x 20 x 1.4mm)
119-Ball PBGA (14 x 22 x 2.4mm)
Industrial
BG119
BG119
A101
Lead-free 119-Ball PBGA (14 x 22 x 2.4mm)
117
100
Lead-free 100-Lead Thin Quad Flat Pack (14 x 20 x 1.4mm) Commercial
119-Ball PBGA (14 x 22 x 2.4mm)
BG119
BG119
A101
Lead-free 119-Ball PBGA (14 x 22 x 2.4mm)
Lead-free 100-Lead Thin Quad Flat Pack (14 x 20 x 1.4mm)
119-Ball PBGA (14 x 22 x 2.4mm)
Industrial
BG119
BG119
A101
Lead-free 119-Ball PBGA (14 x 22 x 2.4mm)
Lead-free 100-Lead Thin Quad Flat Pack (14 x 20 x 1.4mm) Commercial
119-Ball PBGA (14 x 22 x 2.4mm)
BG119
BG119
A101
Lead-free 119-Ball PBGA (14 x 22 x 2.4mm)
Lead-free 100-Lead Thin Quad Flat Pack (14 x 20 x 1.4mm)
119-Ball PBGA (14 x 22 x 2.4mm)
Industrial
BG119
BG119
Lead-free 119-Ball PBGA (14 x 22 x 2.4mm)
Shaded areas contain advance information. Please contact your local Cypress sales representative for availability of these parts. Lead-Free BG pkg will be available
in 2005.
Notes:
21. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device.
22. DQs are in high-Z when exiting ZZ sleep mode.
Document #: 38-05517 Rev. *A
Page 14 of 17
CY7C1345G
PRELIMINARY
Package Diagrams
100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101
51-85050-*A
Document #: 38-05517 Rev. *A
Page 15 of 17
PRELIMINARY
CY7C1345G
Package Diagrams (continued)
119-Lead BGA (14 x 22 x 2.4 mm) BG119
51-85115-*B
Intel and Pentium are registered trademarks of Intel Corporation. All product and company names mentioned in this document
may be the trademarks of their respective holders.
Document #: 38-05517 Rev. *A
Page 16 of 17
© Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY7C1345G
PRELIMINARY
Document History Page
Document Title: CY7C1345G 4-Mbit (128K x 36) Flow-Through Sync SRAM
Document Number: 38-05517
Orig. of
REV.
**
ECN NO. Issue Date Change
Description of Change
See ECN
See ECN
224365
278513
RKF
VBL
New data sheet
Deleted 66 MHz
*A
Changed TQFP package to lead-free TQFP in Ordering Information section
Added BG lead-free package
Document #: 38-05517 Rev. *A
Page 17 of 17
CY7C1345G-100BGC 相关器件
| 型号 | 制造商 | 描述 | 价格 | 文档 |
| CY7C1345G-100BGCT | CYPRESS | Cache SRAM, 128KX36, 8ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, BGA-119 | 获取价格 |
|
| CY7C1345G-100BGI | CYPRESS | 4-Mbit (128K x 36) Flow-Through Sync SRAM | 获取价格 |
|
| CY7C1345G-100BGXC | CYPRESS | 4-Mbit (128K x 36) Flow-Through Sync SRAM | 获取价格 |
|
| CY7C1345G-100BGXI | CYPRESS | 4-Mbit (128K x 36) Flow-Through Sync SRAM | 获取价格 |
|
| CY7C1345G-117AXC | CYPRESS | 4-Mbit (128K x 36) Flow-Through Sync SRAM | 获取价格 |
|
| CY7C1345G-117AXI | CYPRESS | 4-Mbit (128K x 36) Flow-Through Sync SRAM | 获取价格 |
|
| CY7C1345G-117BGC | CYPRESS | 4-Mbit (128K x 36) Flow-Through Sync SRAM | 获取价格 |
|
| CY7C1345G-117BGI | CYPRESS | 4-Mbit (128K x 36) Flow-Through Sync SRAM | 获取价格 |
|
| CY7C1345G-117BGXC | CYPRESS | 4-Mbit (128K x 36) Flow-Through Sync SRAM | 获取价格 |
|
| CY7C1345G-117BGXI | CYPRESS | 4-Mbit (128K x 36) Flow-Through Sync SRAM | 获取价格 |
|
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