CY7C1338F-117AI_技术文档

CY7C1338F

4-Mb (128K x 32) Flow-Through Sync SRAM

6.5 ns (133-MHz version). A 2-bit on-chip counter captures the

first address in a burst and increments the address automati-

cally for the rest of the burst access. All synchronous inputs

Features

• 128K X 32 common I/O

• 3.3V –5% and +10% core power supply (V_DD

are gated by registers controlled by a positive-edge-triggered

Clock Input (CLK). The synchronous inputs include all

addresses, all data inputs, address-pipelining Chip Enable

)

• 2.5V or 3.3V I/O supply (V_DDQ

• Fast clock-to-output times

— 6.5 ns (133-MHz version)

— 7.5 ns (117-MHz version)

— 8.0 ns (100-MHz version)

— 11.0 ns (66-MHz version)

)

(

), depth-expansion Chip Enables (CE and

), Burst

CE₃

CE₁

2

Control inputs (

,

), Write Enables

). Asynchronous

and

ADV

ADSC ADSP

(

,

and

), and Global Write (

BW_[A:D]

BWE

GW

(

)

and the ZZ pin

.

nputs include the Output Enable

OE

i

The CY7C1338F allows either interleaved or linear burst

sequences, selected by the MODE input pin. A HIGH selects

an interleaved burst sequence, while a LOW selects a linear

burst sequence. Burst accesses can be initiated with the

Processor Address Strobe (ADSP) or the cache Controller

Address Strobe (ADSC) inputs. Address advancement is

controlled by the Address Advancement (ADV) input.

• Provide high-performance 2-1-1-1 access rate

• User-selectable burst counter supporting Intel^

Pentium^interleaved or linear burst sequences

• Separate processor and controller address strobes

• Synchronous self-timed write

Addresses and chip enables are registered at rising edge of

• Asynchronous output enable

clock when either Address Strobe Processor (

) or

ADSP

• Offered in JEDEC-standard 100-pin TQFP and 119-ball

Address Strobe Controller (

) are active. Subsequent

ADSC

BGA packages

burst addresses can be internally generated as controlled by

the Advance pin ( ).

• “ZZ” Sleep Mode option

ADV

Functional Description^[1]

The CY7C1338F is a 131,072 x 32 synchronous cache RAM

designed to interface with high-speed microprocessors with

minimum glue logic. Maximum access delay from clock rise is

The CY7C1338F operates from a +3.3V core power supply

while all outputs may operate with either a +2.5 or +3.3V

supply. All inputs and outputs are JEDEC-standard

JESD8-5-compatible.

Logic Block Diagram

ADDRESS

REGISTER

A0, A1, A

A[1:0]

MODE

ADV

CLK

Q1

BURST

COUNTER

AND LOGIC

Q0

CLR

ADSC

ADSP

DQ

D BYTE

DQ

D BYTE

WRITE REGISTER

BW

D

WRITE REGISTER

DQ

C BYTE

DQ

C BYTE

WRITE REGISTER

BW

C

WRITE REGISTER

OUTPUT

BUFFERS

MEMORY

ARRAY

SENSE

AMPS

DQs

DQ

B BYTE

DQ

B BYTE

WRITE REGISTER

BW

B

WRITE REGISTER

DQ

A BYTE

WRITE REGISTER

DQA BYTE

BW

A

WRITE REGISTER

BWE

INPUT

REGISTERS

GW

ENABLE

REGISTER

CE1

CE2

CE3

OE

SLEEP

CONTROL

ZZ

Note:

1. For best–practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Document #: 38-05218 Rev. *A

Revised February 2, 2004

CY7C1338F

Selection Guide

133 MHz

6.5

117 MHz

7.5

100 MHz

8.0

66 MHz

Unit

ns

mA

Maximum Access Time

Maximum Operating Current

Maximum Standby Current

Shaded areas contain advance information.

11.0

195

40

225

40

220

40

205

40

Please contact your local Cypress sales representative for availablity of these parts.

Pin Configurations

100-Pin TQFP

NC

DQ_C

V_DDQ

V_SSQ

DQ_C

V_SSQ

V_DDQ

DQ_C

NC

1

2

3

4

5

6

7

8

NC

DQ_B

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

V_DDQ

V_SSQ

DQ_B

V_SSQ

V_DDQ

DQ_B

V_SS

BYTE C

BYTE B

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

CY7C1338F

V_DD

NC

V_SS

NC

V_DD

ZZ

DQ_D

V_DDQ

V_SSQ

DQ_D

V_SSQ

V_DDQ

DQ_D

NC

DQ_A

V_DDQ

V_SSQ

DQ_A

V_SSQ

V_DDQ

DQ_A

NC

BYTE D

BYTE A

Document #: 38-05218 Rev. *A

Page 2 of 17

CY7C1338F

Pin Configurations (continued)

119-Ball BGA

2

A

1

3

A

4

5

A

6

A

7

V_DDQ

A

B

C

D

E

F

G

H

J

ADSP

NC

CE₂

A

NC

A

NC

ADSC

V_DD

NC

CE₁

OE

ADV

GW

V_DD

CLK

NC

BWE

A1

NC

A

NC

DQ_C

V_DDQ

DQ_C

V_DDQ

DQ_D

V_DDQ

DQ_D

V_SS

BW_C

V_SS

NC

V_SS

BW_B

V_SS

NC

DQ_B

V_DDQ

DQ_B

V_DDQ

DQ_A

V_DDQ

DQ_A

DQ_C

V_DD

DQ_D

DQ_B

V_DD

DQ_A

K

V_SS

L

M

N

BW_D

V_SS

BW_A

V_SS

P

R

T

DQ_D

NC

A

NC

V_SS

MODE

A

A0

V_DD

A

V_SS

NC

A

NC

A

NC

DQ_A

NC

ZZ

V_DDQ

NC

V_DDQ

U

Pin Descriptions

Name

A0, A1, A

TQFP

37,36,32, P4,N4,A2,

BGA

I/O

Input-

Description

Address Inputs used to select one of the 128K address locations.

33,34,35, A3,A5,A6, Synchronous Sampled at the rising edge of the CLK if ADSP or ADSC is active LOW,

44,45,46, B3,B5,C2,

47,48,49, C3,C5,C6,

50,81,82, R2,R6,T3,

and CE₁, CE₂, and CE₃are sampled active. A_[1:0]feed the 2-bit counter.

99,100

T4,T5

BW_A,BW_B

93,94,95, L5,G5,G3,

Input-

Byte Write Select Inputs, active LOW. Qualified with BWE to conduct

96

88

L3

Synchronous byte writes to the SRAM. Sampled on the rising edge of CLK.

BW_C,BW_D

GW

H4

Input-

Global Write Enable Input, active LOW. When asserted LOW on the

Synchronous rising edge of CLK, a global write is conducted (ALL bytes are written,

regardless of the values on BW_[A:D]and BWE).

87

89

M4

K4

Input-

Byte Write Enable Input, active LOW. Sampled on the rising edge of

BWE

CLK

Synchronous CLK. This signal must be asserted LOW to conduct a byte write.

Input-Clock Clock Input. Used to capture all synchronous inputs to the device. Also

used to increment the burst counter when ADV is asserted LOW, during a

burst operation.

CE₁

98

E4

Input-

Synchronous Used in conjunction with CE₂and CE₃to select/deselect the device. ADSP

is ignored

Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK.

if CE₁is HIGH.

CE₂

CE₃

OE

97

92

86

B2

-

Input-

Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK.

Synchronous Used in conjunction with CE₁and CE₃to select/deselect the device.

Input- Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK.

Synchronous Used in conjunction with CE₁and CE₂to select/deselect the device.

F4

Input-

Output Enable, asynchronous input, active LOW. Controls the direction

Asynchronous of the I/O pins. When LOW, the I/O pins behave as outputs. When

deasserted HIGH, I/O pins are three-stated, and act as input data pins. OE

is masked during the first clock of a read cycle when emerging from a

deselected state.

Document #: 38-05218 Rev. *A

Page 3 of 17

CY7C1338F

Pin Descriptions (continued)

Name

ADV

TQFP

83

BGA

G4

I/O

Input-

Description

Advance Input signal, sampled on the rising edge of CLK. When

Synchronous asserted, it automatically increments the address in a burst cycle.

ADSP

84

A4

Input-

Address Strobe from Processor, sampled on the rising edge of CLK,

Synchronous active LOW. When asserted LOW, addresses presented to the device are

captured in the address registers. A_[1:0]are also loaded into the burst

counter. When ADSP and ADSC are both asserted, only ADSP is recog-

nized. ASDP is ignored when

CE₁is deasserted HIGH

85

64

B4

T7

Input-

Address Strobe from Controller, sampled on the rising edge of CLK,

ADSC

ZZ

Synchronous active LOW. When asserted LOW, addresses presented to the device are

captured in the address registers. A_[1:0]are also loaded into the burst counter.

When ADSP and ADSC are both asserted, only ADSP is recognized.

Input-

ZZ “sleep” Input, active HIGH. When asserted HIGH places the device

Asynchronous in a non-time-critical “sleep” condition with data integrity preserved. For

normal operation, this pin has to be LOW or left floating. ZZ pin has an

internal pull-down.

DQs

52,53,56, K6,K7,L6,

I/O-

Bidirectional Data I/O lines. As inputs, they feed into an on-chip data

57,58,59, L7,M6,N6, Synchronous register that is triggered by the rising edge of CLK. As outputs, they deliver

62,63,68, N7,P7,D7,

69,72,73, E6,E7,F6,

74,75,78, G6,G7,H6,

79,2,3,6, H7,D1,E1,

7,8,9,12, E2,F2,G1,

13,18,19, G2,H1,H2,

22,23,24, K1,K2,L1,

25,28,29 L2,M2,N1

N2,P1

the data contained in the memory location specified by the addresses

presented during the previous clock rise of the read cycle. The direction of

the pins is controlled by

. When

is asserted LOW, the pins behave

OE

as outputs. When HIGH, DQs are placed in a three-state condition.

V_DD

V_SS

15,41,65, C4,J2,J4,

Power

Supply

Ground

Power supply inputs to the core of the device.

Ground for the core of the device.

91

R4,J6

17,40,67, D3,D5,E3,

90

E5,F3,F5,

H3,H5,K3,

K5,M3,M5,

N3,N5,P3,

P5

V_DDQ

4,11,20, A1,A7,F1, I/O Power Power supply for the I/O circuitry.

27,54,61, F7,J1,J7,

Supply

70,77

M1,M7,U1,

U7

V_SSQ

5,10,21,55

,60,71,76

–

I/O Ground Ground for the I/O circuitry.

MODE

31

R3

Input-

Static

Selects Burst Order. When tied to GND selects linear burst sequence.

When tied to V_DDor left floating selects interleaved burst sequence. This

is a strap pin and should remain static during device operation. Mode Pin

has an internal pull-up.

NC

14,16,38, B1,B6,B7,

39,42,43, C1,C7,D4,

66,51,80, J3,J5,L4,

No Connects. Not Internally connected to the die.

1,30

R1,R5,R7,

T1,T2,T6,

U2,U3,U4,

U5,U6,P6,

D6,D2,P2

Document #: 38-05218 Rev. *A

Page 4 of 17

CY7C1338F

Single Write Accesses Initiated by ADSC

Functional Overview

All synchronous inputs pass through input registers controlled

by the rising edge of the clock. Maximum access delay from

the clock rise (t_C0) is 6.5 ns (133-MHz device).

This write access is initiated when the following conditions are

satisfied at clock rise: (1) CE₁, CE₂, and CE₃are all asserted

active, (2) ADSC is asserted LOW, (3) ADSP is deasserted

HIGH, and (4) the write input signals (GW, BWE, and BW_[A:D]

)

The CY7C1338F supports secondary cache in systems

utilizing either a linear or interleaved burst sequence. The

interleaved burst order supports Pentium^®and i486

processors. The linear burst sequence is suited for processors

that utilize a linear burst sequence. The burst order is

user-selectable, and is determined by sampling the MODE

input. Accesses can be initiated with either the Processor

Address Strobe (ADSP) or the Controller Address Strobe

(ADSC). Address advancement through the burst sequence is

controlled by the ADV input. A two-bit on-chip wraparound

burst counter captures the first address in a burst sequence

and automatically increments the address for the rest of the

burst access.

Byte write operations are qualified with the Byte Write Enable

(BWE) and Byte Write Select (BW_[A:D]) inputs. A Global Write

Enable (GW) overrides all byte write inputs and writes data to

all four bytes. All writes are simplified with on-chip

synchronous self-timed write circuitry.

Three synchronous Chip Selects (CE₁, CE₂, CE₃) and an

asynchronous Output Enable (OE) provide for easy bank

selection and output three-state control. ADSP is ignored if

CE₁is HIGH.

indicate a write access. ADSC is ignored if ADSP is active

LOW.

The addresses presented are loaded into the address register

and the burst counter/control logic and delivered to the

memory core. The information presented to DQ_[A:D]will be

written into the specified address location. Byte writes are

allowed. During byte writes, BW_Acontrols DQ_A, BW_Bcontrols

DQ_B, BW_Ccontrols DQ_C, and BW_Dcontrols DQ_D. All I/Os are

three-stated when a write is detected, even a byte write. Since

this is a common I/O device, the asynchronous OE input signal

must be deasserted and the I/Os must be three-stated prior to

the presentation of data to DQs. As a safety precaution, the

data lines are three-stated once a write cycle is detected,

regardless of the state of OE.

Burst Sequences

The CY7C1338F provides an on-chip two-bit wraparound

burst counter inside the SRAM. The burst counter is fed by

A[1:0], and can follow either a linear or interleaved burst order.

The burst order is determined by the state of the MODE input.

A LOW on MODE will select a linear burst sequence. A HIGH

on MODE will select an interleaved burst order. Leaving

MODE unconnected will cause the device to default to a inter-

leaved burst sequence.

Single Read Accesses

A single read access is initiated when the following conditions

are satisfied at clock rise: (1) CE₁, CE₂, and CE₃are all

asserted active, and (2) ADSP or ADSC is asserted LOW (if

the access is initiated by ADSC, the write inputs must be

deasserted during this first cycle). The address presented to

the address inputs is latched into the address register and the

burst counter/control logic and presented to the memory core.

If the OE input is asserted LOW, the requested data will be

available at the data outputs a maximum to t_CDVafter clock

rise. ADSP is ignored if CE₁is HIGH.

Sleep Mode

The ZZ input pin is an asynchronous input. Asserting ZZ

places the SRAM in a power conservation “sleep” mode. Two

clock cycles are required to enter into or exit from this “sleep”

mode. While in this mode, data integrity is guaranteed.

Accesses pending when entering the “sleep” mode are not

considered valid nor is the completion of the operation

guaranteed. The device must be deselected prior to entering

the “sleep” mode. CEs, ADSP, and ADSC must remain

inactive for the duration of t_ZZRECafter the ZZ input returns

LOW.

Single Write Accesses Initiated by ADSP

This access is initiated when the following conditions are

satisfied at clock rise: (1) CE₁, CE₂, CE₃are all asserted

active, and (2) ADSP is asserted LOW. The addresses

presented are loaded into the address register and the burst

inputs (GW, BWE, and BW[_A:D] )are ignored during this first

clock cycle. If the write inputs are asserted active (see Write

Cycle Descriptions table for appropriate states that indicate a

write) on the next clock rise,the appropriate data will be latched

and written into the device. Byte writes are allowed. During

byte writes, BW_Acontrols DQ_Aand BWB controls DQ_B. BWC

controls DQ_C, and BW_Dcontrols DQ_D. All I/Os are three-stated

during a byte write.Since this is a common I/O device, the

asynchronous OE input signal must be deasserted and the

I/Os must be three-stated prior to the presentation of data to

DQs. As a safety precaution, the data lines are three-stated

once a write cycle is detected, regardless of the state of OE.

Interleaved Burst Address Table

(MODE = Floating or V_DD

)

First

Second

Address

A1, A0

Third

Address

A1, A0

Fourth

Address

A1, A0

Address

A1, A0

00

01

10

11

01

00

11

10

11

00

01

11

10

01

00

Linear Burst Address Table (MODE = GND)

First

Address

A₁,A₀

Second

Address

A₁,A₀

Third

Address

A₁,A₀

Fourth

Address

A₁,A₀

00

01

10

11

01

10

11

00

10

11

00

01

11

00

01

10

Document #: 38-05218 Rev. *A

Page 5 of 17

CY7C1338F

ZZ Mode Electrical Characteristics

Parameter

I_DDZZ

t_ZZS

Description

Snooze mode standby current

Device operation to ZZ

Test Conditions

ZZ > V_DD– 0.2V

Min.

Max.

40

2t_CYC

Unit

mA

ns

t_ZZREC

t_ZZI

t_RZZI

ZZ recovery time

ZZ active to snooze current

ZZ Inactive to exit snooze current

ZZ < 0.2V

This parameter is sampled

2t_CYC

0

ns

2t_CYC

Truth Table^{[2, 3, 4, 5, 6]}

Address

Used

Cycle Description

CE₁CE₂CE₃ZZ ADSP ADSC ADV WRITE OE CLK

DQ

Deselected Cycle,

None

H

L

X

H

X

L

X

L

X

L

X

L-H three-state

Power-down

Deselected Cycle,

Power-down

L

Deselected Cycle,

X

L

Power-down

Deselected Cycle,

Power-down

H

Deselected Cycle,

X

Power-down

Snooze Mode, Power-down

Read Cycle, Begin Burst

Write Cycle, Begin Burst

Read Cycle, Begin Burst

Read Cycle, Continue Burst

Write Cycle, Continue Burst

Read Cycle, Suspend Burst

Write Cycle, Suspend Burst

None

External

L

X

H

X

L

H

L

X

L

X

L

H

X

L

X

L

H

L

X

L

H

X

L

H

L

H

L

H

X

L

H

L

H

X

L-H

three-state

Q

L-H three-state

L-H

H

X

H

X

H

X

H

X

D

Q

L

L-H three-state

L-H

L-H three-state

L-H

L-H three-state

L-H

L-H three-state

L-H

L-H three-state

L-H

X

H

X

H

X

H

X

H

X

Q

D

Q

L

Current

H

L

Q

D

Write Cycle, Suspend Burst

L

Notes:

2. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.

3. WRITE = L when any one or more Byte Write enable signals (BW , BW , BW , BW ) and BWE = L or GW= L. WRITE = H when all Byte write enable signals

A

B

C

D

( BW , BW , BW , BW ), BWE, GW = H.

A

B

C

D

4. The DQ pins are controlled by the current cycle and the

signal.

is asynchronous and is not sampled with the clock.

OE

5. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW

. Writes may occur only on subsequent clocks

[A:D]

after the

or with the assertion of

. As a result,

must be driven HIGH prior to the start of the write cycle to allow the outputs to three-state.

OE

is

ADSC

a don't care for the remainder of the write cycle.

is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are three-state when

OE

ADSP

6.

OE

is

OE

inactive or when the device is deselected, and all data bits behave as output when

is active (LOW).

OE

7. Table only lists a partial listing of the byte write combinations. Any combination of BW[A:D] is valid. Appropriate write will be done based on which byte write is

active.

Document #: 38-05218 Rev. *A

Page 6 of 17

CY7C1338F

Partial Truth Table for Read/Write^{[2, 7]}

Function

Read

Write Byte A

Write Byte B

GW

H

L

BWE

H

L

BW_D

X

H

L

X

BW_C

X

H

L

H

L

X

BW_B

BW_A

X

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

X

H

L

Write Bytes B, A

Write Byte C

Write Bytes C, A

Write Bytes C, B

Write Bytes C, B, A

Write Byte D

Write Bytes D, A

Write Bytes D, B

Write Bytes D, B, A

Write Bytes D, B

Write Bytes D, B, A

Write Bytes D, C, A

Write All Bytes

L

H

L

H

L

H

L

X

L

X

Document #: 38-05218 Rev. *A

Page 7 of 17

CY7C1338F

Current into Outputs (LOW)......................................... 20 mA

Maximum Ratings

Static Discharge Voltage........................................... >2001V

(Above which the useful life may be impaired. For user guide-

(per MIL-STD-883, Method 3015)

lines, not tested.)

Latch-up Current..................................................... >200 mA

Storage Temperature .................................–65°C to +150°C

Operating Range

Ambient Temperature with

Power Applied.............................................–55°C to +125°C

Ambient

Supply Voltage on V_DDRelative to GND........ –0.5V to +4.6V

Range

Temperature^]

V_DD

V_DDQ

DC Voltage Applied to Outputs

Commercial 0°C to +70°C 3.3V −5%/+10% 2.5V –5%

in three-state....................................... –0.5V to V_DDQ+ 0.5V

to V_DD

Industrial

–40°C to +85°C

DC Input Voltage....................................–0.5V to V_DD+ 0.5V

Electrical Characteristics Over the Operating Range ^{[8, 9]}

CY7C1345F

Parameter

V_DD

V_DDQ

Description

Power Supply Voltage

I/O Supply Voltage

Test Conditions

Min.

Max.

3.6

V_DD

Unit

V

3.135

2.375

2.4

V_OH

Output HIGH Voltage

V_DDQ= 3.3V, V_DD= Min., I_OH= –4.0 mA

V

V_DDQ= 2.5V, V_DD= Min., I_OH= –1.0 mA

2.0

V

V_OL

V_IH

V_IL

I_X

Output LOW Voltage

Input HIGH Voltage

Input LOW Voltage^[8]

V_DDQ= 3.3V, V_DD= Min., I_OL= 8.0 mA

V_DDQ= 2.5V, V_DD= Min., I_OL= 1.0 mA

V_DDQ= 3.3V

0.4

V

µA

2.0 V_DD+ 0.3V

1.7 V_DD+ 0.3V

V

_DDQ= 2.5V

V_DDQ= 3.3V

_DDQ= 2.5V

–0.3

−5

0.8

0.7

5

V

Input Load Current

GND ≤ V_I≤ V_DDQ

(except ZZ and MODE)

Input Current of MODE

Input = V_SS

Input = V_DD

Input = V_SS

Input = V_DD

GND ≤ V_I≤ V_DD, Output Disabled

V_DD= Max., V_OUT= GND

–30

–5

µA

mA

5

Input Current of ZZ

30

5

–300

225

I_OZ

I_OS

I_DD

Output Leakage Current

Output Short Circuit Current

V_DDOperating Supply Current

–5

V_DD= Max., I_OUT= 0 mA,

7.5-ns cycle, 133

f = f_MAX= 1/t_CYC

MHz

8.0-ns cycle, 117 MHz

10-ns cycle, 100 MHz

15-ns cycle, 66 MHz

220

205

195

90

mA

I_SB1

Automatic CE Power-Down

Current—TTL Inputs

Max.V_DD,DeviceDeselected, 7.5-ns cycle, 133

V

_IN≥ V_IHor V_IN≤ V_IL, f = f_MAX

,

MHz

inputs switching

8.0-ns cycle, 117

85

mA

MHz

10-ns cycle, 100 MHz

15-ns cycle, 66 MHz

Max.V_DD,DeviceDeselected, All speeds

_IN≥V_DD– 0.3V or V_IN≤ 0.3V,

f = 0, inputs static

80

60

40

mA

I_SB2

Automatic CE Power-Down

Current—CMOS Inputs

V

Shaded areas contain advance information.

Notes:

8. Overshoot: V (AC) < V +1.5V (Pulse width less than t

/2), undershoot: V (AC) > -2V (Pulse width less than t

/2).

IH

DD

CYC

IL

CYC

9.

: Assumes a linear ramp from 0v to V (min.) within 200ms. During this time V < V and V

< V

DDQ DD.

TPower-up

DD

IH

DD

Document #: 38-05218 Rev. *A

Page 8 of 17

CY7C1338F

Electrical Characteristics Over the Operating Range (continued)^{[8, 9]}

CY7C1345F

Parameter

Description

Test Conditions

Min.

Max.

Unit

I_SB3

Automatic CE Power-Down

Max. V_DD, Device Deselected, 7.5-ns cycle, 133

75

mA

Current—CMOS Inputs

V

_IN≥ V_DDQ– 0.3V or V_IN

≤

MHz

0.3V,

8.0-ns cycle, 117

70

mA

f = f_MAX, inputs switching

MHz

10-ns cycle, 100 MHz

15-ns cycle, 66 MHz

Max. V_DD, Device Deselected, All speeds

_IN≥ V_DD– 0.3V or V_IN≤ 0.3V,

f = 0, inputs static

65

45

mA

I_SB4

Automatic CE Power-Down

Current—TTL Inputs

V

Thermal Resistance^[10]

TQFP

BGA

Parameter

ΘJA

Description

Test Conditions

Package

Unit

°C/W

Thermal Resistance

Test conditions follow standard

test methods and procedures for

measuring thermal impedence,

per EIA / JESD51.

41.83

47.63

(Junction to Ambient)

ΘJC

Thermal Resistance

(Junction to Case)

9.99

11.71

°C/W

Capacitance^[10]

TQFP

BGA

Parameter

Description

Input Capacitance

Clock Input Capacitance

Input/Output Capacitance

Test Conditions

Package

Unit

C_IN

C_CLK

C_I/O

T_A= 25°C, f = 1 MHz,

5

7

pF

V_DD= 3.3V.

V

_DDQ= 3.3V

AC Test Loads and Waveforms

3.3V I/O Test Load

OUTPUT

R = 317Ω

3.3V

ALL INPUT PULSES

90%

V_DD

OUTPUT

90%

Z = 50Ω

0

R = 50Ω

10%

L

GND

5 pF

R = 351Ω

≤ 1ns

V = 1.5V

L

INCLUDING

JIG AND

SCOPE

(c)

(a)

(b)

2.5V I/O Test Load

R = 1667Ω

2.5V

OUTPUT

R = 50Ω

OUTPUT

ALL INPUT PULSES

90%

V_DD

Z = 50Ω

0

10%

L

GND

≤ 1ns

5 pF

R =1538Ω

≤ 1ns

V = 1.25V

L

INCLUDING

JIG AND

SCOPE

(c)

(a)

(b)

Note:

10. Tested initially and after any design or process change that may affect these parameters.

Document #: 38-05218 Rev. *A

Page 9 of 17

CY7C1338F

Switching Characteristics Over the Operating Range ^{[15, 16]}

133 MHz

117 MHz

100 MHz

66 MHz

Parameter

t_POWER

Clock

t_CYC

t_CH

t_CL

Description

Min. Max. Min. Max. Min. Max. Min. Max. Unit

V_DD(Typical) to the first Access^[11]

1

ms

Clock Cycle Time

Clock HIGH

7.5

2.5

8.5

3.0

10

4.0

15

5.0

ns

Clock LOW

Output Times

t_CDV

t_DOH

t_CLZ

t_CHZ

Data Output Valid After CLK Rise

Data Output Hold After CLK Rise

Clock to Low-Z^{[12, 13, 14]}

6.5

7.5

8.0

11.0

ns

2.0

0

2.0

0

2.0

0

2.0

0

Clock to High-Z^{[12, 13, 14]}

3.5

5.0

6.0

t_OEV

OE LOW to Output Valid

t_OELZ

t_OEHZ

Setup Times

t_AS

t_ADS

t_ADVS

t_WES

OE LOW to Output Low-Z^{[12, 13, 14]}

OE HIGH to Output High-Z^{[12, 13, 14]}

0

3.5

6.0

Address Set-up Before CLK Rise

ADSP, ADSC Set-up Before CLK Rise

ADV Set-up Before CLK Rise

1.5

2.0

1.5

2.0

1.5

2.0

1.5

2.0

ns

Set-up Before CLK Rise

GW, BWE, BW_[A:D]

t_DS

t_CES

Data Input Set-up Before CLK Rise

Chip Enable Set-up

Hold Times

t_AH

t_ADH

t_WEH

t_ADVH

t_DH

Address Hold After CLK Rise

ADSP, ADSC Hold After CLK Rise

0.5

ns

,

GW BWE BW_[A:D]Hold After CLK Rise

ADV Hold After CLK Rise

Data Input Hold After CLK Rise

Chip Enable Hold After CLK Rise

t_CEH

Shaded areas contain advance information.

Notes:

is the time that the power needs to be supplied above V (minimum) initially before a read or write operation

DD

POWER

12. t

, t

,t

, and t

are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.

CHZ CLZ OELZ

13. At any given voltage and temperature, t

is less than t

and t

is less than t

to eliminate bus contention between SRAMs when sharing the same

CLZ

OELZ

CHZ

data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed

to achieve High-Z prior to Low-Z under the same system conditions.

14. This parameter is sampled and not 100% tested.

15. Timing reference level is 1.5V when V

= 2.5V.

DDQ

16. Test conditions shown in (a) of AC Test Loads unless otherwise noted.

Document #: 38-05218 Rev. *A

Page 10 of 17

CY7C1338F

Timing Diagrams

Read Cycle Timing^[17]

t

CYC

t

CLK

t

CL

CH

t

ADH

ADS

ADSP

t

ADH

ADS

ADSC

t

AH

AS

A1

A2

ADDRESS

t

WES

WEH

GW, BWE,BW

[A:D]

Deselect Cycle

t

CEH

CES

CE

t

ADVH

ADVS

ADV

OE

ADV suspends burst.

t

CDV

OEV

OELZ

t

OEHZ

CHZ

t

DOH

t

CLZ

Q(A2)

Q(A2 + 1)

Q(A2 + 2)

Q(A2 + 3)

Q(A2)

Q(A2 + 1)

Q(A2 + 2)

Q(A1)

Data Out (Q)

High-Z

t

CDV

Burst wraps around

to its initial state

Single READ

BURST

READ

DON’T CARE

UNDEFINED

Notes:

17. On this diagram, when CE is LOW: CE is LOW, CE is HIGH and CE is LOW. When CE is HIGH: CE is HIGH or CE is LOW or CE is HIGH.

1

2

3

1

2

3

Document #: 38-05218 Rev. *A

Page 11 of 17

CY7C1338F

Timing Diagrams (continued)

Write Cycle Timing^{[17, 18]}

t

CYC

CLK

t

CL

CH

t

ADH

ADS

ADSP

ADSC extends burst

t

ADH

ADS

t

ADH

ADS

ADSC

t

AH

AS

A1

A2

A3

ADDRESS

Byte write signals are ignored for first cycle when

ADSP initiates burst

t

WEH

WES

BWE,

BW^[A:D]

t

WEH

WES

GW

t

CEH

CES

CE

t

ADVH

ADVS

ADV

ADV suspends burst

OE

t

DH

DS

Data in (D)

High-Z

D(A2)

D(A2 + 1)

D(A2 + 2)

D(A2 + 3)

D(A3)

D(A3 + 1)

D(A3 + 2)

D(A1)

t

OEHZ

Data Out (Q)

BURST READ

BURST WRITE

Extended BURST WRITE

Single WRITE

DON’T CARE

UNDEFINED

Note:

18.

Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW

LOW.

[A:D]

Document #: 38-05218 Rev. *A

Page 12 of 17

CY7C1338F

Timing Diagrams (continued)

Read/Write Timing^{[17, 19, 20]}

t

CYC

CLK

t

CL

CH

t

ADH

ADS

ADSP

ADSC

t

AH

AS

A1

A2

A3

A4

A5

A6

ADDRESS

BWE, BW[A:D]

CE

t

WEH

WES

t

CEH

CES

ADV

OE

t

DH

DS

t

OELZ

t

High-Z

D(A3)

D(A5)

D(A6)

Data In (D)

t

OEHZ

CDV

Data Out (Q)

Q(A1)

Q(A2)

Q(A4)

Q(A4+1)

Q(A4+2)

Q(A4+3)

Back-to-Back

Back-to-Back READs

Single WRITE

BURST READ

WRITEs

DON’T CARE

UNDEFINED

Notes:

19.

20.

.

The data bus (Q) remains in high-Z following a WRITE cycle, unless a new read access is initiated by

GW is HIGH.

ADSP or ADSC

Document #: 38-05218 Rev. *A

Page 13 of 17

CY7C1338F

Timing Diagrams (continued)

ZZ Mode Timing ^{[21, 22]}

CLK

t

ZZ

ZZREC

ZZ

t

ZZI

I

SUPPLY

I

DDZZ

t

RZZI

ALL INPUTS

(except ZZ)

DESELECT or READ Only

Outputs (Q)

High-Z

DON’T CARE

Ordering Information

Speed

Package

Name

A101

BG119

A101

BG119

A101

BG119

A101

BG119

A101

BG119

A101

BG119

A101

BG119

A101

Operating

Range

Commercial

(MHz)

Ordering Code

CY7C1338F-133AC

CY7C1338F-133BGC

CY7C1338F-133AI

CY7C1338F-133BGI

CY7C1338F-117AC

CY7C1338F-117BGC

CY7C1338F-117AI

CY7C1338F-117BGI

CY7C1338F-100AC

CY7C1338F-100BGC

CY7C1338F-100AI

CY7C1338F-100BGI

CY7C1338F-66AC

CY7C1338F-66BGC

CY7C1338F-66AI

Package Type

100-Lead Thin Quad Flat Pack ( 14 x 20 x 1.4mm )

119-Ball PBGA ( 14 x 22 x 2.4mm )

100-Lead Thin Quad Flat Pack ( 14 x 20 x 1.4mm )

119-Ball PBGA ( 14 x 22 x 2.4mm )

100-Lead Thin Quad Flat Pack ( 14 x 20 x 1.4mm )

119-Ball PBGA ( 14 x 22 x 2.4mm )

100-Lead Thin Quad Flat Pack ( 14 x 20 x 1.4mm )

119-Ball PBGA ( 14 x 22 x 2.4mm )

100-Lead Thin Quad Flat Pack ( 14 x 20 x 1.4mm )

119-Ball PBGA ( 14 x 22 x 2.4mm )

100-Lead Thin Quad Flat Pack ( 14 x 20 x 1.4mm )

119-Ball PBGA ( 14 x 22 x 2.4mm )

100-Lead Thin Quad Flat Pack ( 14 x 20 x 1.4mm )

119-Ball PBGA ( 14 x 22 x 2.4mm )

133

Industrial

117

100

66

Commercial

Industrial

Commercial

Industrial

Commercial

Industrial

100-Lead Thin Quad Flat Pack ( 14 x 20 x 1.4mm )

CY7C1338F-66BGI

BG119

119-Ball PBGA ( 14 x 22 x 2.4mm )

Shaded areas contain advance information. Please contact your local Cypress sales representative for availability of these parts.

Notes:

21. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device.

22. DQs are in high-Z when exiting ZZ sleep mode.

Document #: 38-05218 Rev. *A

Page 14 of 17

CY7C1338F

Package Diagrams

100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101

DIMENSIONS ARE IN MILLIMETERS.

ꢁ6.00 0.20

ꢁ4.00 0.ꢁ0

ꢁ.40 0.05

ꢁ00

ꢀꢁ

ꢀ0

ꢁ

0.30 0.0ꢀ

0.65

TYP.

ꢁ2° ꢁ°

(ꢀX)

SEE DETAIL

A

30

5ꢁ

3ꢁ

50

0.20 MAX.

ꢁ.60 MAX.

R 0.0ꢀ MIN.

0.20 MAX.

0° MIN.

STAND-OFF

0.05 MIN.

0.ꢁ5 MAX.

SEATING PLANE

0.25

GAUGE PLANE

R 0.0ꢀ MIN.

0.20 MAX.

0°-7°

0.60 0.ꢁ5

0.20 MIN.

ꢁ.00 REF.

51-85050-*A

DETAIL

A

Document #: 38-05218 Rev. *A

Page 15 of 17

CY7C1338F

Package Diagrams (continued)

119-Lead PBGA (14 x 22 x 2.4 mm) BG119

51-85115-*B

Intel and Pentium are registered trademarks of Intel Corporation. All product and company names mentioned in this document

may be the trademarks of their respective holders.

Document #: 38-05218 Rev. *A

Page 16 of 17

CY7C1338F

Document History Page

Document Title: CY7C1338B 4-Mb (128K x 32) Flow-Through Sync SRAM

Document Number: 38-05218

Orig. of

REV.

**

*A

ECN NO. Issue Date Change

Description of Change

119832

12/11/02

HGK

SWI

New Data Sheet

Final Data Sheet

200663

12/19/03

Document #: 38-05218 Rev. *A

Page 17 of 17


型号：	CY7C1338F-117AI
厂家：	CYPRESS
描述：	4-Mb (128K x 32) Flow-Through Sync SRAM 4 -MB （ 128K ×32 ）流通型同步SRAM 静态存储器
文件：	总17页 (文件大小：405K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CY7C1338F-117AI [CYPRESS]

相关型号：

CY7C1338F-117AXC

CY7C1338F-117AXI

CY7C1338F-117BGC

CY7C1338F-117BGI

CY7C1338F-133AC

CY7C1338F-133AI

CY7C1338F-133AXI

CY7C1338F-133BGC

CY7C1338F-133BGI

CY7C1338F-66AC

CY7C1338F-66AI

CY7C1338F-66AXC