CY7C1329H_11 [CYPRESS]
2-Mbit (64 K x 32) Pipelined Sync SRAM 2.5 V/3.3 V I/O operation; 2兆位（ 64千×32 ）流水线同步SRAM 2.5 V / 3.3 V的I / O操作
| 型号： | CY7C1329H_11 |
| 厂家： | 
CYPRESS |
| 描述： | 2-Mbit (64 K x 32) Pipelined Sync SRAM 2.5 V/3.3 V I/O operation |
| 文件： | 总20页 (文件大小：587K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C1329H
2-Mbit (64 K × 32) Pipelined Sync SRAM
2-Mbit (64
K × 32) Pipelined Sync SRAM
Features
Functional Description
■ Registered inputs and outputs for pipelined operation
■ 64 K × 32 common I/O architecture
■ 3.3 V core power supply
The CY7C1329H[1] SRAM integrates 64 K × 32 SRAM cells with
advanced synchronous peripheral circuitry and a two-bit counter
for internal burst operation. All synchronous inputs are gated by
registers controlled by a positive-edge-triggered Clock Input
(CLK). The synchronous inputs include all addresses, all data
inputs, address-pipelining Chip Enable (CE1), depth-expansion
Chip Enables (CE2 and CE3), Burst Control inputs (ADSC,
■ 2.5 V/3.3 V I/O operation
■ Fast clock-to-output times
❐ 3.5 ns (for 166-MHz device)
❐ 4.0 ns (for 133-MHz device)
ADSP,
ADV), Write Enables (BW[A:D] and BWE), and Global
and
Write (GW). Asynchronous inputs include the Output Enable
(OE) and the ZZ pin.
■ Provide high-performance 3-1-1-1 access rate
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP) or Address
Strobe Controller (ADSC) are active. Subsequent burst
addresses can be internally generated as controlled by the
Advance pin (ADV).
■ User-selectable burst counter supporting Intel Pentium®
interleaved or linear burst sequences
■ Separate processor and controller address strobes
■ Synchronous self-timed write
Address, data inputs, and write controls are registered on-chip
to initiate a self-timed Write cycle. This part supports Byte Write
operations (see Pin Descriptions and Truth Table for further
details). Write cycles can be one to four bytes wide as controlled
■ Asynchronous output enable
■ Offered in JEDEC-standard lead-free 100-pin TQFP package
■ “ZZ” Sleep Mode Option
by the Byte Write control inputs. GW when active
all bytes to be written.
causes
LOW
The CY7C1329H operates from a +3.3 V core power supply
while all outputs operate with either a +2.5 V or +3.3 V supply.
All
inputs
and
outputs
are
JEDEC-standard
JESD8-5-compatible.
Logic Block Diagram
A0, A1, A
ADDRESS
REGISTER
2
A[1:0]
MODE
Q1
ADV
CLK
BURST
COUNTER
AND
CLR
Q0
LOGIC
ADSC
ADSP
DQ
BYTE
WRITE REGISTER
D
DQ
BYTE
WRITE DRIVER
D
BW
D
DQ
BYTE
C
DQ
BYTE
C
BW
C
OUTPUT
BUFFERS
WRITE DRIVER
OUTPUT
REGISTERS
WRITE REGISTER
MEMORY
ARRAY
SENSE
AMPS
DQ s
DQ
B
E
DQ
B
BYTE
WRITE DRIVER
BYTE
WRITE REGISTER
BW
BW
B
A
DQ
A
DQ
A
BYTE
WRITE DRIVER
BYTE
WRITE REGISTER
BWE
INPUT
REGISTERS
GW
ENABLE
REGISTER
PIPELINED
ENABLE
CE
CE
CE
1
2
3
OE
SLEEP
CONTROL
ZZ
Note
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
Cypress Semiconductor Corporation
Document #: 38-05673 Rev. *E
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised June 27, 2011
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CY7C1329H
Contents
Selection Guide ................................................................3
Pin Configuration .............................................................3
Pin Definitions ..................................................................4
Functional Overview ........................................................5
Single Read Accesses ................................................5
Single Write Accesses Initiated by ADSP ...................5
Single Write Accesses Initiated by ADSC ...................5
Burst Sequences .........................................................5
Sleep Mode .................................................................5
Interleaved Burst Address Table
(MODE = Floating or VDD) ...............................................6
Linear Burst Address Table (MODE = GND) ..................6
ZZ Mode Electrical Characteristics .................................6
Truth Table ........................................................................7
Truth Table for Read/Write ..............................................8
Maximum Ratings .............................................................9
Operating Range ...............................................................9
Electrical Characteristics .................................................9
Capacitance ....................................................................10
Thermal Resistance ........................................................10
AC Test Loads and Waveforms .....................................10
Switching Characteristics ..............................................11
Switching Waveforms ....................................................12
Ordering Information ......................................................16
Ordering Code Definitions .........................................16
Package Diagram ............................................................17
Acronyms ........................................................................18
Document Conventions .................................................18
Units of Measure .......................................................18
Document History Page .................................................19
Sales, Solutions, and Legal Information ......................20
Worldwide Sales and Design Support .......................20
Products ....................................................................20
PSoC Solutions .........................................................20
Document #: 38-05673 Rev. *E
Page 2 of 20
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CY7C1329H
Selection Guide
166 MHz
3.5
133 MHz Unit
Maximum Access Time
4.0
225
40
ns
Maximum Operating Current
Maximum CMOS Standby Current
240
mA
mA
40
Pin Configuration
Figure 1. 100-pin TQFP Pinout
NC
DQC
DQC
VDDQ
VSSQ
DQC
DQC
DQC
DQC
VSSQ
VDDQ
DQC
DQC
NC
NC
1
2
3
4
5
6
7
8
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQB
DQB
VDDQ
VSSQ
DQB
DQB
DQB
DQB
VSSQ
VDDQ
DQB
DQB
VSS
BYTE C
BYTE B
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
CY7C1329H
VDD
NC
VSS
NC
VDD
ZZ
DQD
DQD
VDDQ
VSSQ
DQD
DQD
DQD
DQD
VSSQ
VDDQ
DQD
DQD
NC
DQA
DQA
VDDQ
VSSQ
DQA
DQA
DQA
DQA
VSSQ
VDDQ
DQA
DQA
NC
BYTE D
BYTE A
Document #: 38-05673 Rev. *E
Page 3 of 20
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CY7C1329H
Pin Definitions
Name
I/O
Description
Address Inputs used to select one of the 64K address locations. Sampled at the rising edge of the
A0, A1, A
Input-
Synchronous CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 are sampled active. A1, A0 feed the 2-bit
counter.
BWA,BWB,
BWC, BWD
Input-
Byte Write Select Inputs, active LOW. Qualified with BWE to conduct Byte Writes to the SRAM. Sampled
Synchronous on the rising edge of CLK.
GW
Input-
Global Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK, a global Write
Synchronous is conducted (All bytes are written, regardless of the values on BW[A:D] and BWE).
BWE
CLK
CE1
Input-
Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal must be asserted
Synchronous LOW to conduct a Byte Write.
Input-
Clock
Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the burst
counter when ADV is asserted LOW, during a burst operation.
CE
Input-
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
2
Synchronous and CE3 to select/deselect the device. ADSP is ignored if CE1 is HIGH. CE1 is sampled only when a new
external address is loaded.
CE2
CE3
Input-
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1
2 is sampled only when a new external address is loaded.
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1
Synchronous and CE3 to select/deselect the device. CE
Input-
Synchronous and CE2 to select/deselect the device. Not connected for BGA. Where referenced, CE3 is assumed active
throughout this document for BGA. CE3 is sampled only when a new external address is loaded.
OE
Input-
Output Enable, asynchronous input, active LOW. Controls the direction of the I/O pins. When LOW,
Asynchronous the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tri-stated, and act as input data pins.
OE is masked during the first clock of a Read cycle when emerging from a deselected state.
ADV
Input-
Advance Input signal, sampled on the rising edge of CLK, active LOW. When asserted, it automat-
Synchronous ically increments the address in a burst cycle.
ADSP
Input- Address Strobe from Processor, sampled on the rising edge of CLK, active LOW. When asserted
Synchronous LOW, A is captured in the address registers. A , A are also loaded into the burst counter. When
ADSP
1
0
and ADSC are both asserted, only ADSP is recognized. ASDP is ignored when CE1 is deasserted HIGH.
ADSC
ZZ
Input-
Address Strobe from Controller, sampled on the rising edge of CLK, active LOW. When asserted
Synchronous LOW, A is captured in the address registers. A1, A0 are also loaded into the burst counter. When ADSP
and ADSC are both asserted, only ADSP is recognized.
Input-
ZZ “sleep” Input, active HIGH. This input, when HIGH places the device in a non-time-critical “sleep”
Asynchronous condition with data integrity preserved. For normal operation, this pin has to be LOW or left floating. ZZ
pin has an internal pull-down.
DQA, DQB
I/O-
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the
DQC, DQD Synchronous rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by “A”
during the previous clock rise of the Read cycle. The direction of the pins is controlled by OE. When OE
is asserted LOW, the pins behave as outputs. When HIGH, DQ are placed in a tri-state condition.
VDD
VSS
Power Supply Power supply inputs to the core of the device.
Ground Ground for the core of the device.
VDDQ
I/O Power Power supply for the I/O circuitry.
Supply
VSSQ
I/O Ground Ground for the I/O circuitry.
MODE
Input-
Static
Selects Burst Order. When tied to GND selects linear burst sequence. When tied to VDD or left floating
selects interleaved burst sequence. This is a strap pin and should remain static during device operation.
Mode Pin has an internal pull-up.
NC
No Connects. Not internally connected to the die. 4M, 9M, 18M, 72M, 144M, 288M, 576M and 1G are
address expansion pins and are not internally connected to the die.
Document #: 38-05673 Rev. *E
Page 4 of 20
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CY7C1329H
Write operation is controlled by BWE and BW[A:D] signals. The
CY7C1329H provides Byte Write capability that is described in
the Write Cycle Descriptions table. Asserting the Byte Write
Enable input (BWE) with the selected Byte Write (BW[A:D]) input,
will selectively write to only the desired bytes. Bytes not selected
during a Byte Write operation will remain unaltered. A
synchronous self-timed Write mechanism has been provided to
simplify the Write operations.
Functional Overview
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. All data outputs pass through output
registers controlled by the rising edge of the clock.
The CY7C1329H supports secondary cache in systems utilizing
either a linear or interleaved burst sequence. The interleaved
burst order supports Pentium and i486 processors. The linear
burst sequence is suited for processors that utilize a linear burst
sequence. The burst order is user selectable, and is determined
by sampling the MODE input. Accesses can be initiated with
either the Processor Address Strobe (ADSP) or the Controller
Address Strobe (ADSC). Address advancement through the
burst sequence is controlled by the ADV input. A two-bit on-chip
wraparound burst counter captures the first address in a burst
sequence and automatically increments the address for the rest
of the burst access.
Because the CY7C1329H is a common I/O device, the Output
Enable (OE) must be deasserted HIGH before presenting data
to the DQ inputs. Doing so will tri-state the output drivers. As a
safety precaution, DQs are automatically tri-stated whenever a
Write cycle is detected, regardless of the state of OE.
Single Write Accesses Initiated by ADSC
ADSC Write accesses are initiated when the following conditions
are satisfied: (1) ADSC is asserted LOW, (2) ADSP is deasserted
HIGH, (3) CE1, CE2, CE3 are all asserted active, and (4) the
appropriate combination of the Write inputs (GW, BWE, and
BW[A:D]) are asserted active to conduct a Write to the desired
byte(s). ADSC-triggered Write accesses require a single clock
cycle to complete. The address presented to A is loaded into the
address register and the address advancement logic while being
delivered to the memory array. The ADV input is ignored during
this cycle. If a global Write is conducted, the data presented to
DQ is written into the corresponding address location in the
memory core. If a Byte Write is conducted, only the selected
bytes are written. Bytes not selected during a Byte Write
operation will remain unaltered. A synchronous self-timed Write
mechanism has been provided to simplify the Write operations.
Byte Write operations are qualified with the Byte Write Enable
(BWE) and Byte Write Select (BW[A:D]) inputs. A Global Write
Enable (GW) overrides all Byte Write inputs and writes data to
all four bytes. All Writes are simplified with on-chip synchronous
self-timed Write circuitry.
Three synchronous Chip Selects (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output tri-state control. ADSP is ignored if CE1 is
HIGH.
Single Read Accesses
This access is initiated when the following conditions are
satisfied at clock rise: (1) ADSP or ADSC is asserted LOW,
(2) CE1, CE2, CE3 are all asserted active, and (3) the Write
signals (GW, BWE) are all deasserted HIGH. ADSP is ignored if
CE1 is HIGH. The address presented to the address inputs (A)
is stored into the address advancement logic and the address
register while being presented to the memory array. The
corresponding data is allowed to propagate to the input of the
output registers. At the rising edge of the next clock the data is
allowed to propagate through the output register and onto the
data bus within tCO if OE is active LOW. The only exception
occurs when the SRAM is emerging from a deselected state to
a selected state, its outputs are always tri-stated during the first
cycle of the access. After the first cycle of the access, the outputs
are controlled by the OE signal. Consecutive single Read cycles
are supported. Once the SRAM is deselected at clock rise by the
chip select and either ADSP or ADSC signals, its output will
tri-state immediately.
Because the CY7C1329H is a common I/O device, the Output
Enable (OE) must be deasserted HIGH before presenting data
to the DQ inputs. Doing so will tri-state the output drivers. As a
safety precaution, DQs are automatically tri-stated whenever a
Write cycle is detected, regardless of the state of OE.
Burst Sequences
The CY7C1329H provides a two-bit wraparound counter, fed by
A1, A0, that implements either an interleaved or linear burst
sequence. The interleaved burst sequence is designed
specifically to support Intel Pentium applications. The linear
burst sequence is designed to support processors that follow a
linear burst sequence. The burst sequence is user selectable
through the MODE input.Asserting ADV LOW at clock rise will
automatically increment the burst counter to the next address in
the burst sequence. Both Read and Write burst operations are
supported.
Single Write Accesses Initiated by ADSP
Sleep Mode
This access is initiated when both of the following conditions are
satisfied at clock rise: (1) ADSP is asserted LOW, and (2) CE1,
CE2, CE3 are all asserted active. The address presented to A is
loaded into the address register and the address advancement
logic while being delivered to the RAM array. The Write signals
(GW, BWE, and BW[A:D]) and ADV inputs are ignored during this
first cycle.
The ZZ input pin is an asynchronous input. Asserting ZZ places
the SRAM in a power conservation “sleep” mode. Two clock
cycles are required to enter into or exit from this “sleep” mode.
While in this mode, data integrity is guaranteed. Accesses
pending when entering the “sleep” mode are not considered valid
nor is the completion of the operation guaranteed. The device
must be deselected prior to entering the “sleep” mode. CE1, CE2,
CE3, ADSP, and ADSC must remain inactive for the duration of
ADSP-triggered Write accesses require two clock cycles to
complete. If GW is asserted LOW on the second clock rise, the
data presented to the DQ inputs is written into the corresponding
address location in the memory array. If GW is HIGH, then the
tZZREC after the ZZ input returns LOW.
Document #: 38-05673 Rev. *E
Page 5 of 20
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CY7C1329H
Interleaved Burst Address Table
(MODE = Floating or V )
Linear Burst Address Table (MODE = GND)
DD
First
Address
A1, A0
Second
Address
A1, A0
Third
Address
A1, A0
Fourth
Address
A1, A0
First
Address
A1, A0
Second
Address
A1, A0
Third
Address
A1, A0
Fourth
Address
A1, A0
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
ZZ Mode Electrical Characteristics
Parameter
IDDZZ
Description
Sleep mode standby current
Device operation to ZZ
Test Conditions
Min
Max
40
Unit
ZZ > VDD– 0.2 V
ZZ > VDD – 0.2 V
ZZ < 0.2 V
–
mA
ns
ns
ns
ns
tZZS
–
2tCYC
–
2tCYC
–
tZZREC
tZZI
ZZ recovery time
ZZ Active to sleep current
ZZ Inactive to exit sleep current
This parameter is sampled
This parameter is sampled
2tCYC
–
tRZZI
0
Document #: 38-05673 Rev. *E
Page 6 of 20
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CY7C1329H
Truth Table [2, 3, 4, 5, 6, 7]
Next Cycle
Unselected
Address Used
Address Used
CE1
CE2
CE3
ZZ
ADSP ADSC ADV WRITE OE
None
None
None
H
X
X
L
X
L
L
X
X
L
X
X
X
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
L
Unselected
None
None
L
L
L
L
X
L
L
L
L
L
X
L
X
L
X
H
X
H
X
L
L
L
L
L
H
L
L
L
L
L
L
Unselected
None
L
Unselected
None
None
H
H
X
L
Unselected
None
None
X
X
H
H
H
H
H
X
L
Begin Read
External
External
Next
None
X
X
X
L
Begin Read
External
External
External
External
External
Next
Continue Read
Continue Read
Continue Read
Continue Read
Suspend Read
Suspend Read
Suspend Read
Suspend Read
Begin Write
L
L
H
X
L
Next
L
H
H
H
H
Next
L
L
H
H
H
Next
L
L
H
L
Current
Current
Current
Current
Current
Current
External
Next
X
H
Next
Next
X
H
H
X
H
X
X
H
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
L
L
L
L
L
H
X
X
H
X
H
H
X
X
H
H
H
H
H
H
H
H
H
H
H
L
L
H
H
H
L
H
L
Next
L
H
X
X
L
Begin Write
Next
L
Begin Write
Next
L
L
Continue Write
Continue Write
Suspend Write
Suspend Write
ZZ “Sleep”
Current
Current
Current
Current
Current
H
H
H
H
H
H
H
H
H
L
Next
H
L
Current
Current
None
H
X
Notes
2. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.
3. WRITE = L when any one or more Byte Write Enable signals (BW , BW , BW , BW and BWE = L or GW = L. WRITE = H when all Byte Write Enable signals (BW ,
)
A
B
C
D
A
BW , BW , BW BWE, GW = H.
),
B
C
D
4. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
5. CE , CE , and CE are available only in the TQFP package.
1
2
3
6. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW
. Writes may occur only on subsequent clocks after
[A:D]
the ADSP or with the assertion of ADSC. As a result,
for the remainder of the Write cycle.
must be driven HIGH prior to the start of the Write cycle to allow the outputs to Tri-State. OE is a don't care
OE
7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during Write cycles. During a Read cycle all data bits are Tri-State when OE is
inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW).
Document #: 38-05673 Rev. *E
Page 7 of 20
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CY7C1329H
Truth Table for Read/Write [8, 9]
Function
GW
BWE
BWD
BWC
BWB
BWA
Read
H
H
X
X
X
H
H
L
X
Read
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
H
H
H
H
H
H
H
H
L
H
H
H
H
L
H
L
Write Byte A – DQA
Write Byte B – DQB
Write Bytes B, A
Write Byte C – DQC
Write Bytes C, A
Write Bytes C, B
Write Bytes C, B, A
Write Byte D – DQD
Write Bytes D, A
Write Bytes D, B
Write Bytes D, B, A
Write Bytes D, C
Write Bytes D, C, A
Write Bytes D, C, B
Write All Bytes
H
L
L
H
H
L
H
L
L
L
H
L
L
L
H
H
H
H
L
H
H
L
H
L
L
L
H
L
L
L
L
H
H
L
H
L
L
L
L
L
H
L
L
L
L
Write All Bytes
X
X
X
X
Notes
8. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.
9. WRITE = L when any one or more Byte Write Enable signals (BW , BW , BW , BW and BWE = L or GW = L. WRITE = H when all Byte Write Enable signals (BW ,
)
A
B
C
D
A
BW , BW , BW BWE, GW = H.
),
B
C
D
Document #: 38-05673 Rev. *E
Page 8 of 20
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CY7C1329H
DC Input Voltage ................................ –0.5 V to VDD + 0.5 V
Current into Outputs (LOW) ........................................ 20 mA
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Static Discharge Voltage
(per MIL-STD-883, Method 3015) ......................... > 2001 V
Storage Temperature ............................... –65 C to +150C
Latch-up Current ................................................... > 200 mA
Ambient Temperature with
Power Applied ......................................... –55 C to +125 C
Operating Range
Supply Voltage on VDD Relative to GND .....–0.5 V to +4.6 V
Supply Voltage on VDDQ Relative to GND .... –0.5 V to +VDD
Ambient
Range
VDD
VDDQ
Temperature
Commercial
Industrial
0 °C to +70 °C 3.3 V– 5% / 2.5V–5%to
–40 °C to +85 °C
DC Voltage Applied to Outputs
in Tri-State ........................................–0.5 V to VDDQ + 0.5 V
+ 10%
VDD
Electrical Characteristics
Over the Operating Range
Parameter [10, 11]
Description
Power Supply Voltage
I/O Supply Voltage
Test Conditions
Min
3.135
3.135
2.375
2.4
Max
Unit
V
VDD
3.6
VDDQ
for 3.3 V I/O
for 2.5 V I/O
VDD
V
2.625
V
VOH
VOL
VIH
VIL
IX
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage [10]
Input LOW Voltage [10]
for 3.3 V I/O, IOH = –4.0 mA
for 2.5 V I/O, IOH = –1.0 mA
for 3.3 V I/O, IOL = 8.0 mA
for 2.5 V I/O, IOL = 1.0 mA
for 3.3 V I/O
–
V
2.0
–
V
–
0.4
V
–
0.4
VDD + 0.3 V
VDD + 0.3 V
0.8
V
2.0
V
for 2.5 V I/O
1.7
V
for 3.3 V I/O
–0.3
–0.3
–5
V
for 2.5 V I/O
0.7
V
InputLeakageCurrentexcept GND VI VDDQ
ZZ and MODE
5
A
Input Current of MODE
Input = VSS
Input = VDD
Input = VSS
Input = VDD
–30
–
–
5
A
A
Input Current of ZZ
–5
–
–
A
30
5
A
IOZ
IDD
Output Leakage Current
GND VI VDDQ, Output Disabled
–5
–
A
VDD Operating Supply
Current
VDD = Max, IOUT = 0 mA, 6-ns cycle,166 MHz
f = fMAX = 1/tCYC
240
225
100
90
mA
mA
mA
mA
7.5-ns cycle,133 MHz
–
ISB1
Automatic CS Power-down VDD = Max,
Current—TTL Inputs Device Deselected,
6-ns cycle, 166 MHz
7.5-ns cycle,133 MHz
–
–
VIN VIH or VIN VIL,
f = fMAX = 1/tCYC
ISB2
Automatic CS Power-down VDD = Max,
Current—CMOS Inputs Device Deselected,
All speeds
–
40
mA
VIN 0.3 V or
VIN > VDDQ – 0.3 V, f = 0
Notes
10. Overshoot: V (AC) < V + 1.5 V (Pulse width less than t
/2), undershoot: V (AC) > –2 V (Pulse width less than t
/2).
IH
DD
CYC
IL
CYC
11. T
: Assumes a linear ramp from 0 V to V (min.) within 200 ms. During this time V < V and V
< V
.
Power-up
DD
IH
DD
DDQ
DD
Document #: 38-05673 Rev. *E
Page 9 of 20
[+] Feedback
CY7C1329H
Electrical Characteristics
Over the Operating Range
Parameter [10, 11]
Description
Automatic CS Power-down VDD = Max,
Current—CMOS Inputs Device Deselected, or
Test Conditions
Min
–
Max
85
Unit
mA
ISB3
6-ns cycle, 166 MHz
7.5-ns cycle,133 MHz
All speeds
–
75
mA
VIN 0.3 V or
VIN > VDDQ – 0.3 V,
f = fMAX = 1/tCYC
ISB4
Automatic CS Power-down VDD = Max,
–
45
mA
Current—TTL Inputs
Device Deselected,
VIN VIH or VIN VIL,
f = 0
Capacitance
100-pin TQFP
Max
Parameter [12]
Description
Test Conditions
Unit
CIN
CCLK
CI/O
Input Capacitance
TA = 25 C, f = 1 MHz, VDD = 3.3 V, VDDQ = 2.5 V
5
5
5
pF
pF
pF
Clock Input Capacitance
Input/Output Capacitance
Thermal Resistance
100-pin TQFP
Package
Parameter [12]
Description
Test Conditions
Unit
JA
Thermal Resistance
(Junction to Ambient)
Test conditions follow standard test methods and
procedures for measuring thermal impedance, per
EIA/JESD51
30.32
C/W
JC
Thermal Resistance
(Junction to Case)
6.85
C/W
AC Test Loads and Waveforms
Figure 2. AC Test Loads and Waveforms
3.3 V I/O Test Load
OUTPUT
R = 317
3.3 V
ALL INPUT PULSES
90%
VDDQ
OUTPUT
90%
10%
Z = 50
0
10%
R = 50
L
GND
5 pF
INCLUDING
R = 351
1 ns
1 ns
V = 1.5 V
T
(a)
JIG AND
SCOPE
(b)
(c)
2.5 V I/O Test Load
R = 1667
2.5 V
OUTPUT
R = 50
OUTPUT
ALL INPUT PULSES
90%
VDDQ
GND
90%
10%
Z = 50
0
10%
L
5 pF
R =1538
1 ns
1 ns
INCLUDING
V = 1.25 V
T
JIG AND
SCOPE
(a)
(b)
(c)
Note
12. Tested initially and after any design or process change that may affect these parameters.
Document #: 38-05673 Rev. *E
Page 10 of 20
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CY7C1329H
Switching Characteristics
Over the Operating Range
166 MHz
Max
133 MHz
Parameter [13, 14]
Description
Unit
Min
Min
Max
tPOWER
Clock
tCYC
VDD(Typical) to the First Access[15]
1
–
1
–
ms
Clock Cycle Time
Clock HIGH
6.0
2.5
2.5
–
–
–
7.5
3.0
3.0
–
–
–
ns
ns
ns
tCH
tCL
Clock LOW
Output Times
tCO
Data Output Valid after CLK Rise
Data Output Hold after CLK Rise
Clock to Low Z [16, 17, 18]
–
1.5
0
3.5
–
–
1.5
0
4.0
–
ns
ns
ns
ns
ns
ns
ns
tDOH
tCLZ
–
–
tCHZ
Clock to High Z [16, 17, 18]
–
3.5
3.5
–
–
4.0
4.5
–
tOEV
OE LOW to Output Valid
–
–
tOELZ
tOEHZ
Set-up Times
tAS
OE LOW to Output Low Z [16, 17, 18]
OE HIGH to Output High Z [16, 17, 18]
0
0
–
3.5
–
4.0
Address Set-up before CLK Rise
ADSC, ADSP Set-up before CLK Rise
ADV Set-up before CLK Rise
1.5
1.5
1.5
1.5
1.5
1.5
–
–
–
–
–
–
1.5
1.5
1.5
1.5
1.5
1.5
–
–
–
–
–
–
ns
ns
ns
ns
ns
ns
tADS
tADVS
tWES
GW, BWE, BW[A:D] Set-up before CLK Rise
Data Input Set-up before CLK Rise
Chip Enable Set-Up before CLK Rise
tDS
tCES
Hold Times
tAH
Address Hold after CLK Rise
0.5
0.5
0.5
0.5
0.5
0.5
–
–
–
–
–
–
0.5
0.5
0.5
0.5
0.5
0.5
–
–
–
–
–
–
ns
ns
ns
ns
ns
ns
tADH
ADSP, ADSC Hold after CLK Rise
ADV Hold after CLK Rise
tADVH
tWEH
GW, BWE, BW[A:D] Hold after CLK Rise
Data Input Hold after CLK Rise
Chip Enable Hold after CLK Rise
tDH
tCEH
Notes
13. Timing reference level is 1.5 V when V
= 3.3 V and is 1.25 V when V
= 2.5 V.
DDQ
DDQ
14. Test conditions shown in (a) ofFigure 2 on page 10 unless otherwise noted.
15. This part has a voltage regulator internally; t
is the time that the power needs to be supplied above V (minimum) initially before a Read or Write operation
POWER
DD
can be initiated.
16. t
, t
,t
, and t
are specified with AC test conditions shown in part (b) of Figure 2 on page 10. Transition is measured ± 200 mV from steady-state voltage.
CHZ CLZ OELZ
OEHZ
17. At any given voltage and temperature, t
is less than t
and t
is less than t
to eliminate bus contention between SRAMs when sharing the same data
CLZ
OEHZ
OELZ
CHZ
bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve
High Z prior to Low Z under the same system conditions.
18. This parameter is sampled and not 100% tested.
Document #: 38-05673 Rev. *E
Page 11 of 20
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CY7C1329H
Switching Waveforms
Figure 3. Read Cycle Timing [19]
t
CYC
CLK
t
t
CL
CH
t
t
ADH
ADS
ADSP
ADSC
t
t
ADH
ADS
t
t
AH
AS
A1
A2
A3
ADDRESS
Burst continued with
new base address
t
t
WEH
WES
GW, BWE,
BW[A:D]
Deselect
cycle
t
t
CEH
CES
CE
t
t
ADVH
ADVS
ADV
OE
ADV
suspends
burst.
t
t
OEV
CO
t
t
OEHZ
t
t
CHZ
OELZ
DOH
t
CLZ
t
Q(A2)
Q(A2 + 1)
Q(A2 + 2)
Q(A2 + 3)
Q(A2)
Q(A2 + 1)
Q(A1)
Data Out (Q)
High-Z
CO
Burst wraps around
to its initial state
Single READ
BURST READ
DON’T CARE
UNDEFINED
Note
19. On this diagram, when CE is LOW, CE is LOW, CE is HIGH and CE is LOW. When CE is HIGH, CE is HIGH or CE is LOW or CE is HIGH.
1
2
3
1
2
3
Document #: 38-05673 Rev. *E
Page 12 of 20
[+] Feedback
CY7C1329H
Switching Waveforms (continued)
Figure 4. Write Cycle Timing [20, 21]
t
CYC
CLK
t
t
CL
CH
t
t
ADH
ADS
ADSP
ADSC extends burst
t
t
ADH
ADS
t
t
ADH
ADS
ADSC
t
t
AH
AS
A1
A2
A3
ADDRESS
Byte write signals are
ignored for first cycle when
ADSP initiates burst
t
t
WEH
WES
BWE,
BW[A :D]
t
t
WEH
WES
GW
CE
t
t
CEH
CES
t
t
ADVH
ADVS
ADV
OE
ADV suspends burst
t
t
DH
DS
Data In (D)
D(A2)
D(A2 + 1)
D(A2 + 1)
D(A2 + 2)
D(A2 + 3)
D(A3)
D(A3 + 1)
D(A3 + 2)
D(A1)
High-Z
t
OEHZ
Data Out (Q)
BURST READ
Single WRITE
BURST WRITE
Extended BURST WRITE
DON’T CARE
UNDEFINED
Notes
20. On this diagram, when CE is LOW, CE is LOW, CE is HIGH and CE is LOW. When CE is HIGH, CE is HIGH or CE is LOW or CE is HIGH.
1
2
3
1
2
3
21.
Full width Write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW
LOW.
[A : D]
Document #: 38-05673 Rev. *E
Page 13 of 20
[+] Feedback
CY7C1329H
Switching Waveforms (continued)
Figure 5. Read/Write Cycle Timing [22, 23, 24]
t
CYC
CLK
t
t
CL
CH
t
t
ADH
ADS
ADSP
ADSC
t
t
AH
AS
A1
A2
A3
A4
A5
A6
ADDRESS
t
t
WEH
WES
BWE,
BW[A:D]
t
t
CEH
CES
CE
ADV
OE
t
t
DH
t
CO
DS
t
OELZ
Data In (D)
High-Z
High-Z
D(A3)
D(A5)
D(A6)
t
t
OEHZ
CLZ
Data Out (Q)
Q(A1)
Q(A2)
Q(A4)
Q(A4+1)
Q(A4+2)
Q(A4+3)
Back-to-Back READs
Single WRITE
BURST READ
Back-to-Back
WRITEs
DON’T CARE
UNDEFINED
Notes
22. On this diagram, when CE is LOW, CE is LOW, CE is HIGH and CE is LOW. When CE is HIGH, CE is HIGH or CE is LOW or CE is HIGH.
1
2
3
1
2
3
23. The data bus (Q) remains in High Z following a Write cycle unless an ADSP, ADSC, or ADV cycle is performed.
24. GW is HIGH.
Document #: 38-05673 Rev. *E
Page 14 of 20
[+] Feedback
CY7C1329H
Switching Waveforms (continued)
Figure 6. ZZ Mode Timing [25, 26]
CLK
t
t
ZZ
ZZREC
ZZ
t
ZZI
I
SUPPLY
I
DDZZ
t
RZZI
ALL INPUTS
(except ZZ)
DESELECT or READ Only
Outputs (Q)
High-Z
DON’T CARE
Notes
25. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device.
26. DQs are in High Z when exiting ZZ sleep mode.
Document #: 38-05673 Rev. *E
Page 15 of 20
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CY7C1329H
Ordering Information
Cypress offers other versions of this type of product in many different configurations and features. The following table contains only
the list of parts that are currently available.
For a complete listing of all options, visit the Cypress website at www.cypress.com and refer to the product summary page at
http://www.cypress.com/products or contact your local sales representative.
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives and distributors. To find the
office closest to you, visit us at http://www.cypress.com/go/datasheet/offices.
Speed
(MHz)
Package
Diagram
Operating
Range
Ordering Code
Package Type
133
CY7C1329H-133AXC
51-85050 100-pin Thin Quad Flat Pack (14 × 20 × 1.4 mm) Pb-free Commercial
Ordering Code Definitions
CY 7 C 1329
H
- 133
A
X
C
Temperature Range:
C = Commercial
Pb-free
Package Type:
AX = 100-pin TQFP
Speed: 133 MHz
Process Technology: greater than or equal to 90 nm
1329 = SCD, 064 K × 32 (2 Mb)
Technology Code: C = CMOS
Marketing Code: 7 = SRAM
Company ID: CY = Cypress
Document #: 38-05673 Rev. *E
Page 16 of 20
[+] Feedback
CY7C1329H
Package Diagram
Figure 7. 100-pin TQFP (14 × 20 × 1.4 mm) A100RA, 51-85050
51-85050 *D
Document #: 38-05673 Rev. *E
Page 17 of 20
[+] Feedback
CY7C1329H
Acronyms
Document Conventions
Units of Measure
Acronym
Description
CE
chip enable
Symbol
°C
Unit of Measure
CMOS
I/O
complementary metal oxide semiconductor
input/output
degree Celsius
micro Amperes
micro seconds
milli Amperes
milli meter
milli seconds
milli Volts
µA
µs
OE
output enable
SRAM
TQFP
TTL
static random access memory
thin quad flat pack
mA
mm
ms
mV
mW
MHz
ns
transistor-transistor logic
milli Watts
Mega Hertz
nano seconds
percent
%
pF
pico Farad
Volts
V
W
Watts
Document #: 38-05673 Rev. *E
Page 18 of 20
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CY7C1329H
Document History Page
Document Title: CY7C1329H, 2-Mbit (64 K × 32) Pipelined Sync SRAM
Document Number: 38-05673
Orig. of
Change
REV.
ECN NO. Issue Date
Description of Change
**
347357
424820
See ECN
See ECN
PCI
New Data Sheet
Converted from Preliminary to Final.
*A
RXU
Changed address of Cypress Semiconductor Corporation on Page# 1 from “3901
North First Street” to “198 Champion Court”
Changed Three-State to Tri-State.
Modified “Input Load” to “Input Leakage Current except ZZ and MODE” in the
Electrical Characteristics Table.
Modified test condition from VIH < VDD to VIH VDD
Replaced Package Name column with Package Diagram in the Ordering Infor-
mation table.
Updated the Ordering Information Table.
Replaced Package Diagram of 51-85050 from *A to *B
*B
*C
*D
*E
433014
See ECN
NXR
NJY
NJY
NJY
Included 3.3V I/O option
Updated the Ordering Information table.
2896585 03/20/2010
3052882 10/08/2010
3293640 06/27/2011
Removed obsolete part numbers from Ordering Information table and updated
package diagrams.
Removed obsolete part numbers from Ordering Information table and added
Ordering definitions.
Updated Package Diagram.
Added Acronyms and Units of Measure.
Updated in new template.
Document #: 38-05673 Rev. *E
Page 19 of 20
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CY7C1329H
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
Products
Automotive
cypress.com/go/automotive
cypress.com/go/clocks
cypress.com/go/interface
cypress.com/go/powerpsoc
cypress.com/go/plc
PSoC Solutions
Clocks & Buffers
Interface
psoc.cypress.com/solutions
PSoC 1 | PSoC 3 | PSoC 5
Lighting & Power Control
Memory
cypress.com/go/memory
cypress.com/go/image
cypress.com/go/psoc
Optical & Image Sensing
PSoC
Touch Sensing
USB Controllers
Wireless/RF
cypress.com/go/touch
cypress.com/go/USB
cypress.com/go/wireless
© Cypress Semiconductor Corporation, 2005-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 38-05673 Rev. *E
Revised June 27, 2011
Page 20 of 20
i486 is a trademark, and Intel and Pentium are registered trademarks, of Intel Corporation. PowerPC is a registered trademark of IBM Corporation. All products and company names mentioned in this
document may be the trademarks of their respective holders.
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