CY7C1265V18-400BZXI [CYPRESS]
36-Mbit QDR⑩-II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency); 36兆位QDR⑩ -II + SRAM 4字突发架构（ 2.5周期读延迟）
| 型号： | CY7C1265V18-400BZXI |
| 厂家： | 
CYPRESS |
| 描述： | 36-Mbit QDR⑩-II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency) |
| 文件： | 总28页 (文件大小：1259K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C1261V18
CY7C1276V18
CY7C1263V18
CY7C1265V18
36-Mbit QDR™-II+ SRAM 4-Word
Burst Architecture (2.5 Cycle Read Latency)
Functional Description
Features
• Separate independent read and write data ports
— Supports concurrent transactions
The CY7C1261V18, CY7C1276V18, CY7C1263V18, and
CY7C1265V18 are 1.8V Synchronous Pipelined SRAMs,
equipped with Quad Data Rate-II+ (QDR-II+) architecture.
QDR-II+ architecture consists of two separate ports to access
the memory array. The read port has dedicated data outputs
to support read operations and the write port has dedicated
data inputs to support write operations. QDR-II+ architecture
has separate data inputs and data outputs to completely
eliminate the need to “turn around” the data bus required with
common IO devices. Each port is accessed through a common
address bus. Addresses for read and write addresses are
latched on alternate rising edges of the input (K) clock.
Accesses to the QDR-II+ read and write ports are completely
independent of one another. To maximize data throughput,
both read and write ports are equipped with Double Data Rate
(DDR) interfaces. Each address location is associated with
• 300 MHz to 400 MHz clock for high bandwidth
• 4-Word Burst for reducing address bus frequency
• Double Data Rate (DDR) interfaces on both read and write
ports (data transferred at 800 MHz) at 400 MHz
• Read latency of 2.5 clock cycles
• Two input clocks (K and K) for precise DDR timing
— SRAM uses rising edges only
• Echo clocks (CQ and CQ) simplify data capture in
high-speed systems
• Singlemultiplexedaddressinputbuslatchesaddressinputs
for both read and write ports
four
8-bit
words
(CY7C1261V18),
9-bit
words
• Separate Port Selects for depth expansion
• Data valid pin (QVLD) to indicate valid data on the output
• Synchronous internally self-timed writes
(CY7C1276V18), 18-bit words (CY7C1263V18), or 36-bit
words (CY7C1265V18) that burst sequentially into or out of the
device. Because data can be transferred into and out of the
device on every rising edge of both input clocks (K and K),
memory bandwidth is maximized while simplifying system
design by eliminating bus “turn-arounds”.
• Available in x8, x9, x18, and x36 configurations
• Full data coherency providing most current data
[1]
• Core VDD = 1.8V ± 0.1V; IO VDDQ = 1.4V to VDD
Depth expansion is accomplished with Port Selects for each
port. Port selects enable each port to operate independently.
• HSTL inputs and Variable drive HSTL output buffers
• Available in 165-ball FBGA package (15 x 17 x 1.4 mm)
• Offered in both Pb-free and non Pb-free packages
• JTAG 1149.1 compatible test access port
All synchronous inputs pass through input registers controlled
by the K or K input clocks. All data outputs pass through output
registers controlled by the K or K input clocks. Writes are
conducted with on-chip synchronous self-timed write circuitry.
• Delay Lock Loop (DLL) for accurate data placement
Configurations
With Read Cycle Latency of 2.0 cycles:
CY7C1261V18 – 4M x 8
CY7C1276V18 – 4M x 9
CY7C1263V18 – 2M x 18
CY7C1265V18 – 1M x 36
Selection Guide
400 MHz
400
375 MHz
333 MHz
333
300 MHz
300
Unit
MHz
mA
Maximum Operating Frequency
Maximum Operating Current
375
1330
1240
1120
1040
Note
1. The QDR consortium specification for V
is 1.5V + 0.1V. The Cypress QDR devices exceed the QDR consortium specification and are capable of supporting
DDQ
V
= 1.4V to V
.
DDQ
DD
Cypress Semiconductor Corporation
Document Number: 001-06366 Rev. *C
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised May 14, 2007
[+] Feedback
CY7C1261V18
CY7C1276V18
CY7C1263V18
CY7C1265V18
Logic Block Diagram (CY7C1261V18)
D
[7:0]
8
Write Write Write Write
Address
Register
A
(19:0)
Reg
Reg Reg
Reg
20
Address
Register
A
(19:0)
20
RPS
K
K
Control
Logic
CLK
Gen.
DOFF
Read Data Reg.
32
CQ
CQ
16
V
REF
Reg.
Reg.
Reg.
WPS
Control
Logic
Q
[7:0]
16
NWS
8
[1:0]
8
QVLD
Logic Block Diagram (CY7C1276V18)
D
[8:0]
9
Write Write Write Write
Address
Register
A
(19:0)
Reg
Reg Reg
Reg
20
Address
Register
A
(19:0)
20
RPS
K
K
Control
Logic
CLK
Gen.
DOFF
Read Data Reg.
36
CQ
CQ
18
V
REF
Reg.
Reg.
Reg.
WPS
BWS
Control
Logic
Q
[8:0]
18
[0]
9
9
QVLD
Document Number: 001-06366 Rev. *C
Page 2 of 28
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CY7C1261V18
CY7C1276V18
CY7C1263V18
CY7C1265V18
Logic Block Diagram (CY7C1263V18)
D
[17:0]
18
Write Write Write Write
Address
Register
A
(18:0)
Reg
Reg Reg
Reg
19
Address
Register
A
(18:0)
19
RPS
K
K
Control
Logic
CLK
Gen.
DOFF
Read Data Reg.
72
CQ
CQ
36
V
REF
Reg.
Reg.
Reg.
WPS
BWS
Control
Logic
Q
[17:0]
36
[1:0]
18
18
QVLD
Logic Block Diagram (CY7C1265V18)
D
[35:0]
36
Write Write Write Write
Address
Register
A
(17:0)
Reg
Reg Reg
Reg
18
Address
Register
A
(17:0)
18
RPS
K
K
Control
Logic
CLK
Gen.
DOFF
Read Data Reg.
144
CQ
CQ
72
V
REF
Reg.
Reg.
Reg.
WPS
BWS
Control
Logic
Q
72
[35:0]
[3:0]
36
36
QVLD
Document Number: 001-06366 Rev. *C
Page 3 of 28
[+] Feedback
CY7C1261V18
CY7C1276V18
CY7C1263V18
CY7C1265V18
Pin Configurations
165-Ball FBGA (15 x 17 x 1.4 mm) Pinout
CY7C1261V18 (4M x 8)
1
2
3
6
9
10
11
5
7
8
4
NC/72M
A
NC/144M
A
A
CQ
A
CQ
WPS
NWS1
K
RPS
NC
NC
NC
NC
NC
D4
NC
NC
NC
A
NC/288M
K
NWS0
A
A
NC
NC
NC
NC
NC
NC
Q3
D3
NC
B
C
D
VSS
VSS
A
NC
VSS
VSS
VSS
VSS
VSS
NC
NC
NC
NC
NC
D5
Q4
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
NC
D2
NC
Q2
NC
NC
ZQ
D1
NC
Q0
E
F
Q5
NC
NC
G
VREF
NC
NC
Q6
VDDQ
NC
VDDQ
NC
VREF
Q1
H
J
DOFF
NC
NC
NC
NC
NC
NC
NC
NC
NC
K
L
D6
NC
NC
NC
D7
NC
NC
NC
Q7
VSS
VSS
VSS
A
VSS
A
VSS
A
VSS
VSS
NC
NC
NC
NC
NC
NC
D0
NC
NC
M
N
P
A
QVLD
A
A
A
A
A
A
A
TDO
TCK
A
A
TMS
TDI
R
NC
CY7C1276V18 (4M x 9)
1
2
NC/72M
NC
3
6
K
9
10
A
11
CQ
Q4
D4
NC
5
NC
7
8
4
WPS
A
CQ
NC
NC
NC
A
NC/144M RPS
A
A
B
C
D
NC
NC
NC
NC/288M
A
K
BWS0
A
A
NC
NC
NC
NC
NC
NC
NC
VSS
VSS
NC
VSS
VSS
VSS
D5
VSS
VSS
NC
NC
NC
NC
D6
Q5
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
NC
D3
NC
Q3
NC
NC
ZQ
D2
NC
Q1
E
F
NC
Q6
NC
NC
G
H
J
VDDQ
NC
VREF
Q2
DOFF
NC
VREF
NC
NC
Q7
VDDQ
NC
NC
NC
D7
NC
NC
Q8
NC
NC
K
L
NC
NC
NC
NC
NC
NC
NC
D8
NC
VSS
VSS
VSS
A
VSS
A
VSS
A
VSS
VSS
NC
NC
NC
NC
NC
D0
D1
NC
Q0
M
N
P
A
QVLD
A
A
A
A
A
A
A
TDO
TCK
A
A
TMS
TDI
R
NC
Document Number: 001-06366 Rev. *C
Page 4 of 28
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CY7C1261V18
CY7C1276V18
CY7C1263V18
CY7C1265V18
Pin Configurations (continued)
165-Ball FBGA (15 x 17 x 1.4 mm) Pinout
CY7C1263V18 (2M x 18)
2
NC/144M
Q9
3
5
6
7
NC/288M
BWS0
A
9
10
NC/72M
NC
11
CQ
Q8
D8
D7
Q6
Q5
D5
1
4
WPS
A
8
RPS
A
A
A
A
B
C
D
E
F
CQ
NC
NC
NC
BWS1
NC
K
K
D9
NC
NC
NC
NC
D10
Q10
Q11
D12
Q13
VSS
VSS
A
NC
VSS
VSS
VSS
Q7
D11
VSS
VSS
NC
NC
NC
NC
NC
VDDQ
VDDQ
VDDQ
VSS
VDD
VDD
VSS
VSS
VSS
VSS
VDD
VDD
VDDQ
VDDQ
VDDQ
NC
NC
D6
Q12
D13
NC
NC
NC
G
VDDQ
NC
VREF
NC
VDDQ
D14
VDDQ
VDDQ
VDD
VDD
VSS
VSS
VDD
VDD
VDDQ
VDDQ
VREF
Q4
ZQ
D4
H
J
DOFF
NC
NC
NC
NC
NC
NC
NC
Q15
NC
Q14
D15
D16
Q16
Q17
VDDQ
VDDQ
VSS
VDD
VSS
VSS
A
VSS
VSS
VSS
A
VDD
VSS
VSS
A
VDDQ
VDDQ
VSS
NC
D3
NC
Q1
NC
D0
Q3
Q2
D2
D1
Q0
K
L
NC
NC
NC
NC
M
N
P
D17
NC
VSS
VSS
A
QVLD
A
A
A
A
A
A
A
R
TDO
A
A
TMS
TDI
TCK
NC
CY7C1265V18 (1M x 36)
7
1
2
3
8
9
A
10
NC/144M
11
CQ
Q8
D8
D7
4
WPS
A
5
6
K
NC/288M NC/72M
A
B
C
D
CQ
Q27
D27
D28
BWS2
BWS3
A
BWS1
BWS0
A
RPS
A
Q18
Q28
D20
D18
D19
Q19
K
D17
D16
Q16
Q17
Q7
VSS
VSS
NC
VSS
VSS
VSS
VSS
VSS
D15
Q29
Q30
D30
D29
Q21
D22
VREF
Q31
D32
Q24
Q20
D21
Q22
VDDQ
D23
Q23
D24
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
Q15
D14
Q13
VDDQ
D12
Q12
D11
D6
Q14
D13
VREF
Q4
Q6
Q5
D5
ZQ
D4
Q3
Q2
E
F
G
H
J
DOFF
D31
Q32
Q33
D33
D34
Q35
D3
K
L
Q11
Q34
D26
D35
D25
Q25
Q26
VSS
VSS
VSS
A
VSS
A
VSS
A
VSS
VSS
D10
Q10
Q9
Q1
D9
D0
D2
D1
Q0
M
N
P
A
QVLD
A
A
A
A
A
A
A
TDO
TCK
A
A
TMS
TDI
R
NC
Document Number: 001-06366 Rev. *C
Page 5 of 28
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CY7C1261V18
CY7C1276V18
CY7C1263V18
CY7C1265V18
Pin Definitions
Pin Name
IO
Pin Description
Data input signals. Sampled on the rising edge of K and K clocks during valid write operations.
D[x:0]
Input-
–
Synchronous CY7C1261V18 D[7:0]
–
CY7C1276V18 D[8:0]
–
CY7C1263V18 D[17:0]
–
CY7C1265V18 D[35:0]
WPS
Input-
Write Port Select, Active LOW. Sampled on the rising edge of the K clock. When asserted
Synchronous active, a write operation is initiated. Deasserting deselects the write port. Deselecting the write
port causes D[x:0] to be ignored.
NWS ,
Input-
Nibble Write Select 0, 1, Active LOW (CY7C1261V18 Only). Sampled on the rising edge of
NWS1,
0
Synchronous the K and K clocks
. Used to select which nibble is written into
when write operations are active
the device
NWS controls D[3:0] and NWS1
during the current portion of the write operations.
0
controls D[7:4]
.
All the Nibble Write Selects are sampled on the same edge as the data.
The corresponding
nibble of data is ignored by deselecting a nibble write select and is not written into the device.
BWS0, BWS1,
BWS2, BWS3
Byte Write Select 0, 1, 2, and 3, Active LOW. Sampled on the rising edge of the K and K clocks
during write operations. Used to select which byte is written into the device during the current
portion of the Write operations. Bytes not written remain unaltered.
CY7C1276V18 – BWS0 controls D[8:0]
Input-
Synchronous
CY7C1263V18 – BWS0 controls D[8:0] and BWS1 controls D[17:9]
CY7C1265V18 – BWS0 controls D[8:0], BWS1 controls D[17:9], BWS2 controls D[26:18], and BWS3
controls D[35:27]
.
.
All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write
Select causes the corresponding byte of data to be ignored and not written into the device.
A
Input-
Address Inputs. Sampled on the rising edge of the K clock during active read and write opera-
Synchronous tions. These address inputs are multiplexed for both read and write operations. Internally, the
device is organized as 4M x 8 (4 arrays each of 1M x 8) for CY7C1261V18, 4M x 9 (4 arrays
each of 1M x 9) for CY7C1276V18, 2M x 18 (4 arrays each of 512K x 18) for CY7C1263V18
and 1M x 36 (4 arrays each of 256K x 36) for CY7C1265V18. Therefore, only 20 address inputs
are needed to access the entire memoryarrayofCY7C1261V18 and CY7C1276V18, 19 address
inputs for CY7C1263V18 and 18 address inputs for CY7C1265V18. These inputs are ignored
when the appropriate port is deselected.
Q[x:0]
Outputs-
Data Output Signals. These pins drive out the requested data during a read operation. Valid
Synchronous data is driven out on the rising edge of both the K and K clocks during read operations. When
the read port is deselected, Q[x:0] are automatically tri-stated.
CY7C1261V18 – Q[7:0]
CY7C1276V18 – Q[8:0]
CY7C1263V18 – Q[17:0]
CY7C1265V18 – Q[35:0]
RPS
Input-
Read Port Select, Active LOW. Sampled on the rising edge of Positive Input Clock (K). When
Synchronous active, a read operation is initiated. Deasserting causes the read port to be deselected. When
deselected, the pending access is allowed to complete and the output drivers are automatically
tri-stated following the next rising edge of the K clock. Each read access consists of a burst of
four sequential transfers.
QVLD
K
Valid Output Valid Output Indicator. The Q Valid indicates valid output data. QVLD is edge aligned with CQ
Indicator
and CQ.
Input-
Clock
Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the
device and to drive out data through Q[x:0] when in single clock mode. All accesses are initiated
on the rising edge of K.
K
Input-
Clock
Negative Input Clock Input. K is used to capture synchronous inputs being presented to the
device and to drive out data through Q[x:0] when in single clock mode.
Document Number: 001-06366 Rev. *C
Page 6 of 28
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CY7C1261V18
CY7C1276V18
CY7C1263V18
CY7C1265V18
Pin Definitions (continued)
Pin Name
CQ
IO
Pin Description
Echo Clock Synchronous Echo Clock Outputs. This is a free running clock and is synchronized to the
input clock (K) of the QDR-II+. The timing for the echo clocks is shown in “Switching Character-
istics” on page 23.
CQ
ZQ
Echo Clock Synchronous Echo Clock Outputs. This is a free running clock and is synchronized to the
input clock (K) of the QDR-II+. The timing for the echo clocks is shown in “Switching Character-
istics” on page 23.
Input
Input
Output Impedance Matching Input. This input is used to tune the device outputs to the system
data bus impedance. CQ, CQ, and Q[x:0] output impedance are set to 0.2 x RQ, where RQ is a
resistor connected between ZQ and ground. Alternatively, this pin can be connected directly to
VDDQ, which enables the minimum impedance mode. This pin cannot be connected directly to
GND or left unconnected.
DOFF
DLL Turn Off, Active LOW. Connecting this pin to ground turns off the DLL inside the device.
The timing in the DLL turned off operation is different from that listed in this data sheet. For
normal operation, this pin can be connected to a pull up through a 10 Kohm or less pull up
resistor. The device behaves in QDR-I mode when the DLL is turned off. In this mode, the device
can be operated at a frequency of up to 167 MHz with QDR-I timing.
TDO
Output
Input
Input
Input
N/A
TDO for JTAG.
TCK
TCK pin for JTAG.
TDI
TDI pin for JTAG.
TMS
TMS pin for JTAG.
NC
Not connected to the die. Can be tied to any voltage level.
Not connected to the die. Can be tied to any voltage level.
Not connected to the die. Can be tied to any voltage level.
Not connected to the die. Can be tied to any voltage level.
Reference Voltage Input. Static input used to set the reference level for HSTL inputs, outputs,
NC/72M
NC/144M
NC/288M
VREF
N/A
N/A
N/A
Input-
Reference and AC measurement points.
VDD
VSS
Power Supply Power supply inputs to the core of the device.
Ground
Ground for the device.
VDDQ
Power Supply Power supply inputs for the outputs of the device.
Document Number: 001-06366 Rev. *C
Page 7 of 28
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CY7C1261V18
CY7C1276V18
CY7C1263V18
CY7C1265V18
Write Operations
Functional Overview
Write operations are initiated by asserting WPS active at the
rising edge of the Positive Input Clock (K). On the following K
clock rise, the data presented to D[17:0] is latched and stored
into the lower 18-bit Write Data register, provided BWS[1:0] are
both asserted active. On the subsequent rising edge of the
Negative Input Clock (K), the information presented to D[17:0]
is also stored into the Write Data register, provided BWS[1:0]
are both asserted active. This process continues for one more
cycle until four 18-bit words (a total of 72 bits) of data are
stored in the SRAM. The 72 bits of data are then written into
the memory array at the specified location. Therefore, write
accesses to the device cannot be initiated on two consecutive
K clock rises. The internal logic of the device ignores the
second write request. Write accesses can be initiated on every
other rising edge of the Positive Input Clock (K). Doing so
pipelines the data flow such that 18 bits of data can be trans-
ferred into the device on every rising edge of the input clocks
(K and K). When deselected, the write port ignores all inputs
after the pending write operations have been completed.
The CY7C1261V18, CY7C1276V18, CY7C1263V18, and
CY7C1265V18 are synchronous pipelined Burst SRAMs
equipped with a read port and a write port. The read port is
dedicated to read operations and the write port is dedicated to
write operations. Data flows into the SRAM through the write
port and out through the read port. These devices multiplex the
address inputs to minimize the number of address pins
required. By having separate read and write ports, the QDR-II+
completely eliminates the need to “turn around” the data bus
and avoids any possible data contention, thereby simplifying
system design. Each access consists of four 8-bit data
transfers in the case of CY7C1261V18, four 9-bit data
transfers in the case of CY7C1276V18, four 18-bit data
transfers in the case of CY7C1263V18, and four 36-bit data
transfers in the case of CY7C1265V18, in two clock cycles.
Accesses for both ports are initiated on the Positive Input
Clock (K). All synchronous input and output timing refer to the
rising edge of the Input clocks (K/K).
All synchronous data inputs (D[x:0]) inputs pass through input
registers controlled by the input clocks (K and K). All
synchronous data outputs (Q[x:0]) outputs pass through output
registers controlled by the rising edge of the Input clocks (K
and K).
Byte Write Operations
Byte write operations are supported by the CY7C1263V18. A
write operation is initiated as described in the Write Operations
section. The bytes that are written are determined by BWS0
and BWS1, which are sampled with each set of 18-bit data
words. Asserting the appropriate Byte Write Select input
during the data portion of a write enables the data being
presented to be latched and written into the device.
Deasserting the Byte Write Select input during the data portion
of a write enables the data stored in the device for that byte to
remain unaltered. This feature can be used to simplify
read/modify/write operations to a byte write operation.
All synchronous control (RPS, WPS, BWS[x:0]) inputs pass
through input registers controlled by the rising edge of the
input clocks (K/K).
CY7C1263V18 is described in the following sections. The
same basic descriptions apply to CY7C1261V18,
CY7C1276V18, and CY7C1265V18.
Read Operations
Concurrent Transactions
The CY7C1263V18 is organized internally as 4 arrays of 512K
x 18. Accesses are completed in a burst of four sequential
18-bit data words. Read operations are initiated by asserting
RPS active at the rising edge of the Positive Input Clock (K).
The addresses presented to address inputs are stored in the
Read address register. Following the next two K clock rising
edges, the corresponding lowest order 18-bit word of data is
driven onto the Q[17:0] using K as the output timing reference.
On the subsequent rising edge of K the next 18-bit data word
is driven onto the Q[17:0]. This process continues until all four
18-bit data words have been driven out onto Q[17:0]. The
requested data is valid 0.45 ns from the rising edge of the Input
clock (K or K). To maintain the internal logic, each read access
must be allowed to complete. Each read access consists of
four 18-bit data words and takes two clock cycles to complete.
Therefore, read accesses to the device cannot be initiated on
two consecutive K clock rises. The internal logic of the device
ignores the second read request. Read accesses can be
initiated on every other K clock rise. Doing so pipelines the
data flow such that data is transferred out of the device on
every rising edge of the input clocks (K and K).
The read and write ports on the CY7C1263V18 operate
completely independently of one another. Because each port
latches the address inputs on different clock edges, the user
can read or write to any location, regardless of the transaction
on the other port. If the ports access the same location when
a read follows a write in successive clock cycles, the SRAM
delivers the most recent information associated with the
specified address location. This includes forwarding data from
a write cycle that was initiated on the previous K clock rise.
Read accesses and write access must be scheduled such that
one transaction is initiated on any clock cycle. If both ports are
selected on the same K clock rise, the arbitration depends on
the previous state of the SRAM. If both ports are deselected,
the read port takes priority. If a read was initiated on the
previous cycle, the Write port assumes priority (because read
operations cannot be initiated on consecutive cycles). If a write
was initiated on the previous cycle, the read port assumes
priority (because write operations cannot be initiated on
consecutive cycles). Therefore, asserting both port selects
active from a deselected state results in alternating read/write
operations being initiated, with the first access being a read.
When the read port is deselected, the CY7C1263V18=
completes the pending read transactions. Synchronous
internal circuitry automatically tri-states the outputs following
the next rising edge of the negative Input Clock (K). This
enables a seamless transition between devices without the
insertion of wait states in a depth expanded memory.
Depth Expansion
The CY7C1263V18 has a Port Select input for each port. This
enables easy depth expansion. Both Port Selects are sampled
on the rising edge of the Positive Input Clock only (K). Each
Document Number: 001-06366 Rev. *C
Page 8 of 28
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CY7C1261V18
CY7C1276V18
CY7C1263V18
CY7C1265V18
port select input can deselect the specified port. Deselecting
a port does not affect the other port. All pending transactions
(read and write) are completed before the device is
deselected.
The timing for the echo clocks is shown in “Switching Charac-
teristics” on page 23.
Valid Data Indicator (QVLD)
QVLD is provided on the QDR-II+ to simplify data capture on
high speed systems. The QVLD is generated by the QDR-II+
device along with data output. This signal is also edge aligned
with the echo clock and follows the timing of any data pin. This
signal is asserted half a cycle before valid data arrives.
Programmable Impedance
An external resistor, RQ, must be connected between the ZQ
pin on the SRAM and VSS to enable the SRAM to adjust its
output driver impedance. The value of RQ must be 5X the
value of the intended line impedance driven by the SRAM. The
allowable range of RQ to guarantee impedance matching with
a tolerance of ±15% is between 175Ω and 350Ω, with
VDDQ = 1.5V. The output impedance is adjusted every 1024
cycles upon power up to account for drifts in supply voltage
and temperature.
Delay Lock Loop (DLL)
These chips use a DLL that is designed to function between
120 MHz and the specified maximum clock frequency. To
disable the DLL, apply ground to the DOFF pin. When the DLL
is turned off, the device behaves in QDR-I mode (with 1.0 cycle
latency and a longer access time). For more information, refer
to the application note, DLL Considerations in
QDRII/DDRII/QDRII+/DDRII+. The DLL can also be reset by
slowing or stopping the input clocks K and K for a minimum of
30 ns. However, it is not necessary for the DLL to be reset to
lock to the frequency you want. During power up, when the
DOFF is tied HIGH, the DLL is locked after 2048 cycles of
stable clock.
Echo Clocks
Echo clocks are provided on the QDR-II+ to simplify data
capture on high speed systems. Two echo clocks are
generated by the QDR-II+. CQ is referenced with respect to K
and CQ is referenced with respect to K. These are free running
clocks and are synchronized to the input clock of the QDR-II+.
Document Number: 001-06366 Rev. *C
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CY7C1276V18
CY7C1263V18
CY7C1265V18
Application Example
Figure 1 shows the use of four QDR-II+ SRAMs in an application.
Figure 1. Application Example
RQ = 250ohms
RQ = 250ohms
ZQ
CQ/CQ
Q
ZQ
CQ/CQ
Q
Vt
SRAM #1
BWS
SRAM #4
D
A
D
A
R
K
K
RPS WPS
K
K
BWS
RPS WPS
DATA IN
DATA OUT
Address
R
R
Vt
Vt
RPS
BUS MASTER
WPS
BWS
(CPU or ASIC)
CLKIN/CLKIN
Source K
Source K
R = 50ohms, Vt = V
/2
DDQ
Truth Table
The truth table for the CY7C1261V18, CY7C1276V18, CY7C1263V18, and CY7C1265V18 follows.[2, 3, 4, 5, 6, 7]
Operation RPS WPS DQ DQ DQ
Write Cycle:
H[8] L[9] D(A) at K(t + 1) ↑ D(A + 1) at K(t +1) ↑ D(A + 2) at K(t + 2) ↑ D(A + 3) at K(t + 2) ↑
K
DQ
L-H
Load address on the
rising edge of K; input
write data on two
consecutive K and K
rising edges.
Read Cycle:
L-H
L[9]
X
Q(A) at K(t + 2) ↑ Q(A + 1) at K(t + 3) ↑ Q(A + 2) at K(t + 3) ↑ Q(A + 3) at K(t + 4) ↑
(2.5 cycle Latency)
Load address on the
rising edge of K; wait
two and half cycle;
read data on two
consecutive K and K
rising edges.
NOP: No Operation L-H
H
H
X
D = X
Q = High-Z
D = X
Q = High-Z
D = X
Q = High-Z
D = X
Q = High-Z
Standby: Clock
Stopped
Stopped X
Previous State
Previous State
Previous State
Previous State
Notes
2. X = “Don't Care,” H = Logic HIGH, L = Logic LOW, ↑ represents rising edge.
3. Device powers up deselected with the outputs in a tri-state condition.
4. “A” represents address location latched by the devices when transaction was initiated. A + 1, A + 2, and A + 3 represent the address sequence in the burst.
5. “t” represents the cycle at which a read/write operation is started. t + 1, t + 2, t + 3 and t + 4 are the first, second, third, and fourth clock cycles, respectively,
succeeding the “t” clock cycle.
6. Data inputs are registered at K and K rising edges. Data outputs are delivered on K and K rising edges.
7. Cypress recommends that K = K = HIGH when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line charging
symmetrically.
8. If this signal was LOW to initiate the previous cycle, this signal becomes a “Don’t Care” for this operation.
9. This signal was HIGH on previous K clock rise. Initiating consecutive read or write operations on consecutive K clock rises is not permitted. The device will ignore
the second read or write request.
Document Number: 001-06366 Rev. *C
Page 10 of 28
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CY7C1261V18
CY7C1276V18
CY7C1263V18
CY7C1265V18
Write Cycle Descriptions
The write cycle descriptions table for CY7C1261V18 and CY7C1263V18 follows.[2, 10]
BWS0/ BWS1/
K
Comments
During the data portion of a write sequence :
CY7C1261V18 − both nibbles (D[7:0]) are written into the device,
CY7C1263V18 − both bytes (D[17:0]) are written into the device.
K
NWS0 NWS1
L
L
L
L
L–H
–
–
L–H
–
L-H During the data portion of a write sequence :
CY7C1261V18 − both nibbles (D[7:0]) are written into the device,
CY7C1263V18 − both bytes (D[17:0]) are written into the device.
L
H
H
L
–
During the data portion of a write sequence :
CY7C1261V18 − only the lower nibble (D[3:0]) is written into the device, D[7:4] remains unaltered.
CY7C1263V18 − only the lower byte (D[8:0]) is written into the device, D[17:9] remains unaltered.
L
L–H During the data portion of a write sequence :
CY7C1261V18 − only the lower nibble (D[3:0]) is written into the device, D[7:4] remains unaltered.
CY7C1263V18 − only the lower byte (D[8:0]) is written into the device, D[17:9] remains unaltered.
H
H
L–H
–
–
During the data portion of a write sequence :
CY7C1261V18 − only the upper nibble (D[7:4]) is written into the device, D[3:0] remains unaltered.
CY7C1263V18 − only the upper byte (D[17:9]) is written into the device, D[8:0] remains unaltered.
L
L–H During the data portion of a write sequence :
CY7C1261V18 − only the upper nibble (D[7:4]) is written into the device, D[3:0] remains unaltered.
CY7C1263V18 − only the upper byte (D[17:9]) is written into the device, D[8:0] remains unaltered.
H
H
H
H
L–H
–
–
No data is written into the devices during this portion of a write operation.
L–H No data is written into the devices during this portion of a write operation.
Write Cycle Descriptions
The write cycle descriptions table for CY7C1276V18 follows.[2, 10]
BWS0
K
L–H
–
K
Comments
L
L
–
During the data portion of a write sequence, the single byte (D[8:0]) is written into the device.
L–H During the data portion of a write sequence, the single byte (D[8:0]) is written into the device.
No data is written into the device during this portion of a write operation.
L–H No data is written into the device during this portion of a write operation.
H
H
L–H
–
–
Note
10. Assumes a write cycle was initiated per the Write Cycle Descriptions table. NWS , NWS BWS , BWS , BWS , and BWS can be altered on different portions
0
1,
0
1
2
3
of a write cycle, as long as the setup and hold requirements are met.
Document Number: 001-06366 Rev. *C
Page 11 of 28
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CY7C1261V18
CY7C1276V18
CY7C1263V18
CY7C1265V18
Write Cycle Descriptions
The write cycle descriptions table for CY7C1265V18 follows.[2, 10]
BWS0 BWS1 BWS2 BWS3
K
K
Comments
L
L
L
L
L–H
–
During the data portion of a write sequence, all four bytes (D[35:0]) are written
into the device.
L
L
L
L
–
L–H
–
L–H During the data portion of a write sequence, all four bytes (D[35:0]) are written
into the device.
L
H
H
L
H
H
H
H
L
H
H
H
H
H
H
L
–
During the data portion of a write sequence, only the lower byte (D[8:0]) is
written into the device. D[35:9] remains unaltered.
L
L–H During the data portion of a write sequence, only the lower byte (D[8:0]) is
written into the device. D[35:9] remains unaltered.
H
H
H
H
H
H
L–H
–
–
During the data portion of a write sequence, only the byte (D[17:9]) is written
into the device. D[8:0] and D[35:18] remain unaltered.
L
L–H During the data portion of a write sequence, only the byte (D[17:9]) is written
into the device. D[8:0] and D[35:18] remain unaltered.
H
H
H
H
L–H
–
–
During the data portion of a write sequence, only the byte (D[26:18]) is written
into the device. D[17:0] and D[35:27] remain unaltered.
L
L–H During the data portion of a write sequence, only the byte (D[26:18]) is written
into the device. D[17:0] and D[35:27] remain unaltered.
H
H
L–H
–
–
During the data portion of a write sequence, only the byte (D[35:27]) is written
into the device. D[26:0] remains unaltered.
L
L–H During the data portion of a write sequence, only the byte (D[35:27]) is written
into the device. D[26:0] remains unaltered.
H
H
H
H
H
H
H
H
L–H
–
–
No data is written into the device during this portion of a write operation.
L–H No data is written into the device during this portion of a write operation.
Document Number: 001-06366 Rev. *C
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CY7C1261V18
CY7C1276V18
CY7C1263V18
CY7C1265V18
Instruction Register
IEEE 1149.1 Serial Boundary Scan (JTAG)
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the
TDI and TDO pins as shown in “TAP Controller Block Diagram”
on page 16. Upon power up, the instruction register is loaded
with the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as
described in the previous section.
These SRAMs incorporate a serial boundary scan test access
port (TAP) in the FBGA package. This part is fully compliant
with IEEE Standard #1149.1-2001. The TAP operates using
JEDEC standard 1.8V IO logic levels.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, tie TCK LOW (VSS) to
prevent device clocking. TDI and TMS are internally pulled up
and may be unconnected. They may alternatively be
connected to VDD through a pull up resistor. TDO must be left
unconnected. Upon power up, the device comes up in a reset
state, which does not interfere with the operation of the device.
When the TAP controller is in the Capture IR state, the two
least significant bits are loaded with a binary ‘01’ pattern to
enable fault isolation of the board level serial test path.
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between TDI
and TDO pins. This enables data to be shifted through the
SRAM with minimal delay. The bypass register is set LOW
(VSS) when the BYPASS instruction is executed.
Test Access Port – Test Clock
The test clock is used only with the TAP controller. All inputs
are captured on the rising edge of TCK. All outputs are driven
from the falling edge of TCK.
Boundary Scan Register
Test Mode Select
The boundary scan register is connected to all of the input and
output pins on the SRAM. Several no connect (NC) pins are
also included in the scan register to reserve pins for higher
density devices.
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. You can leave this
pin unconnected if the TAP is not used. The pin is pulled up
internally, resulting in a logic HIGH level.
The boundary scan register is loaded with the contents of the
RAM input and output ring when the TAP controller is in the
Capture-DR state and is then placed between the TDI and
TDO pins when the controller is moved to the Shift-DR state.
The EXTEST, SAMPLE/PRELOAD, and SAMPLE Z instruc-
tions can be used to capture the contents of the input and
output ring.
Test Data-In (TDI)
The TDI pin is used to serially input information into the
registers and can be connected to the input of any of the
registers. The register between TDI and TDO is chosen by the
instruction that is loaded into the TAP instruction register. For
information on loading the instruction register, see the “TAP
Controller State Diagram” on page 15. TDI is internally pulled
up and can be unconnected if the TAP is unused in an appli-
cation. TDI is connected to the most significant bit (MSB) on
any register.
“Boundary Scan Order” on page 19 shows the order in which
the bits are connected. Each bit corresponds to one of the
bumps on the SRAM package. The MSB of the register is
connected to TDI, and the LSB is connected to TDO.
Test Data-Out (TDO)
Identification (ID) Register
The TDO output pin is used to serially clock data-out from the
registers. Whether the output is active depends on the current
state of the TAP state machine (see “Instruction Codes” on
page 18). The output changes on the falling edge of TCK. TDO
is connected to the least significant bit (LSB) of any register.
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired
into the SRAM and can be shifted out when the TAP controller
is in the Shift-DR state. The ID register has a vendor code and
other information described in “Identification Register Defini-
tions” on page 18.
Performing a TAP Reset
A Reset is performed by forcing TMS HIGH (VDD) for five rising
edges of TCK. This RESET does not affect the operation of
the SRAM and may be performed while the SRAM is
operating. At power up, the TAP is reset internally to ensure
that TDO comes up in a high-Z state.
TAP Instruction Set
Eight different instructions are possible with the three-bit
instruction register. All combinations are listed in “Instruction
Codes” on page 18. Three of these instructions are listed as
RESERVED and must not be used. The other five instructions
are described in this section in detail.
TAP Registers
Registers are connected between the TDI and TDO pins and
enable data to be scanned into and out of the SRAM test
circuitry. Only one register can be selected at a time through
the instruction registers. Data is serially loaded into the TDI pin
on the rising edge of TCK. Data is output on the TDO pin on
the falling edge of TCK.
Instructions are loaded into the TAP controller during the
Shift-IR state when the instruction register is placed between
TDI and TDO. During this state, instructions are shifted
through the instruction register through the TDI and TDO pins.
To execute the instruction after it is shifted in, the TAP
controller must be moved into the Update-IR state.
Document Number: 001-06366 Rev. *C
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CY7C1265V18
IDCODE
PRELOAD enables an initial data pattern to be placed at the
latched parallel outputs of the boundary scan register cells be-
fore the selection of another boundary scan test operation.
The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the instruction register. It also places the
instruction register between the TDI and TDO pins and
enables the IDCODE to be shifted out of the device when the
TAP controller enters the Shift-DR state. The IDCODE
instruction is loaded into the instruction register upon
The shifting of data for the SAMPLE and PRELOAD phases
can occur concurrently when required — that is, while data
captured is shifted out, the preloaded data can be shifted in.
BYPASS
power-up or whenever the TAP controller is in
Test-Logic-Reset state.
a
When the BYPASS instruction is loaded in the instruction
register and the TAP is placed in a Shift-DR state, the bypass
register is placed between the TDI and TDO pins. The
advantage of the BYPASS instruction is that it shortens the
boundary scan path when multiple devices are connected
together on a board.
SAMPLE Z
The SAMPLE Z instruction causes the boundary scan register
to be connected between the TDI and TDO pins when the TAP
controller is in a Shift-DR state. The SAMPLE Z command puts
the output bus into a High-Z state until the next command is
issued during the Update-IR state.
EXTEST
The EXTEST instruction enables the preloaded data to be
driven out through the system output pins. This instruction also
selects the boundary scan register to be connected for serial
access between the TDI and TDO in the Shift-DR controller
state.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When
the SAMPLE/PRELOAD instructions are loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and output pins is cap-
tured in the boundary scan register.
EXTEST OUTPUT BUS TRI-STATE
IEEE Standard 1149.1 mandates that the TAP controller be
able to put the output bus into a tri-state mode.
Be aware that the TAP controller clock can only operate at a
frequency up to 20 MHz, although the SRAM clock operates
more than an order of magnitude faster. Because there is a
large difference in the clock frequencies, it is possible that dur-
ing the Capture-DR state, an input or output may undergo a
transition. The TAP may then try to capture a signal while in
transition (metastable state). This does not harm the device,
but there is no guarantee as to the value that is captured. Re-
peatable results may not be possible.
The boundary scan register has a special bit located at bit
#108. When this scan cell, called the “extest output bus
tri-state,” is latched into the preload register during the
Update-DR state in the TAP controller, it directly controls the
state of the output (Q-bus) pins, when the EXTEST is entered
as the current instruction. When HIGH, it enables the output
buffers to drive the output bus. When LOW, this bit places the
output bus into a High-Z condition.
To guarantee that the boundary scan register captures the cor-
rect value of a signal, the SRAM signal must be stabilized long
enough to meet the TAP controller's capture setup plus hold
times (tCS and tCH). The SRAM clock input might not be cap-
tured correctly if there is no way in a design to stop (or slow)
the clock during a SAMPLE/PRELOAD instruction. If this is an
issue, it is still possible to capture all other signals and simply
ignore the value of the CK and CK captured in the boundary
scan register.
This bit can be set by entering the SAMPLE/PRELOAD or
EXTEST command, and then shifting the desired bit into that
cell, during the Shift-DR state. During Update-DR” the value
loaded into that shift register cell latches into the preload
register. When the EXTEST instruction is entered, this bit
directly controls the output Q-bus pins. Note that this bit is
preset HIGH to enable the output when the device is powered
up, and also when the TAP controller is in the Test-Logic-Reset
state.
After the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the bound-
ary scan register between the TDI and TDO pins.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
Document Number: 001-06366 Rev. *C
Page 14 of 28
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CY7C1276V18
CY7C1263V18
CY7C1265V18
TAP Controller State Diagram
The state diagram for the TAP Controller follows.[11]
TEST-LOGIC
1
RESET
0
1
1
1
TEST-LOGIC/
IDLE
SELECT
DR-SCAN
SELECT
IR-SCAN
0
0
0
1
1
CAPTURE-DR
CAPTURE-IR
0
0
SHIFT-DR
0
SHIFT-IR
0
1
1
EXIT1-DR
0
1
EXIT1-IR
0
1
0
0
PAUSE-DR
1
PAUSE-IR
1
0
0
EXIT2-DR
1
EXIT2-IR
1
UPDATE-DR
UPDATE-IR
1
1
0
0
Note
11. The 0/1 next to each state represents the value at TMS at the rising edge of TCK
Document Number: 001-06366 Rev. *C
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CY7C1265V18
TAP Controller Block Diagram
0
Bypass Register
Selection
TDI
Selection
Circuitry
2
1
0
0
0
TDO
Circuitry
Instruction Register
29
31 30
.
.
2
1
Identification Register
.
108 .
.
.
2
1
Boundary Scan Register
TCK
TMS
TAP Controller
TAP Electrical Characteristics
Over the Operating Range[12, 13, 14]
Parameter
VOH1
Description
Test Conditions
IOH = −2.0 mA
Min
1.4
1.6
Max
Unit
V
Output HIGH Voltage
Output HIGH Voltage
Output LOW Voltage
Output LOW Voltage
Input HIGH Voltage
VOH2
VOL1
VOL2
VIH
IOH = −100 µA
IOL = 2.0 mA
IOL = 100 µA
V
0.4
0.2
V
V
0.65VDD VDD + 0.3
V
VIL
Input LOW Voltage
–0.3
–5
0.35VDD
5
V
IX
Input and Output Load Current
GND ≤ VI ≤ VDD
µA
Notes
12. These characteristics apply to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in “Electrical Characteristics” on page 21.
13. Overshoot: V (AC) < V + 0.3V (pulse width less than t /2).
/2). Undershoot: V (AC) > −0.3V (pulse width less than t
IH
DDQ
CYC
IL
CYC
14. All voltage refer to Ground.
Document Number: 001-06366 Rev. *C
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CY7C1261V18
CY7C1276V18
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CY7C1265V18
TAP AC Switching Characteristics
Over the Operating Range[15, 16]
Parameter
Description
Min
Max
Unit
ns
tTCYC
TCK Clock Cycle Time
TCK Clock Frequency
TCK Clock HIGH
50
tTF
20
MHz
ns
tTH
20
20
tTL
TCK Clock LOW
ns
Setup Times
tTMSS
tTDIS
TMS Setup to TCK Clock Rise
TDI Setup to TCK Clock Rise
Capture Setup to TCK Rise
5
5
5
ns
ns
ns
tCS
Hold Times
tTMSH
tTDIH
TMS Hold after TCK Clock Rise
TDI Hold after Clock Rise
5
5
5
ns
ns
ns
tCH
Capture Hold after Clock Rise
Output Times
tTDOV
tTDOX
TCK Clock LOW to TDO Valid
TCK Clock LOW to TDO Invalid
10
ns
ns
0
TAP Timing and Test Conditions[16]
0.9V
ALL INPUT PULSES
0.9V
50Ω
1.8V
TDO
0V
Z = 50Ω
0
C = 20 pF
L
t
t
TL
TH
GND
(a)
Test Clock
TCK
t
TCYC
t
TMSH
t
TMSS
Test Mode Select
TMS
t
TDIS
t
TDIH
Test Data In
TDI
Test Data Out
TDO
t
TDOV
t
TDOX
Notes
15. t and t refer to the setup and hold time requirements of latching data from the boundary scan register.
CS
CH
16. Test conditions are specified using the load in TAP AC test conditions. t /t = 1 ns.
R
F
Document Number: 001-06366 Rev. *C
Page 17 of 28
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Identification Register Definitions
Value
Instruction
Description
Field
CY7C1261V18
CY7C1276V18
CY7C1263V18
CY7C1265V18
000
Revision
000
000
000
Version number.
Number (31:29)
Cypress Device 11010010001000111 11010010001001111 11010010001010111 11010010001100111 Defines the type
ID (28:12)
of SRAM.
Cypress JEDEC
ID (11:1)
00000110100
1
00000110100
1
00000110100
1
00000110100
1
Enables unique
identification of
SRAM vendor.
ID Register
Presence (0)
Indicates the
presence of an
ID register.
Scan Register Sizes
Register Name
Bit Size
Instruction
Bypass
3
1
ID
32
109
Boundary Scan
Instruction Codes
Instruction
EXTEST
Code
000
Description
Captures the input/output ring contents.
IDCODE
001
Loads the ID register with the vendor ID code and places the register between
TDI and TDO. This operation does not affect SRAM operation.
SAMPLE Z
010
Captures the input/output contents. Places the boundary scan register between
TDI and TDO. Forces all SRAM output drivers to a High-Z state.
RESERVED
011
100
Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD
Captures the input/output ring contents. Places the boundary scan register
between TDI and TDO. Does not affect the SRAM operation.
RESERVED
RESERVED
BYPASS
101
110
111
Do Not Use: This instruction is reserved for future use.
Do Not Use: This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does not affect
SRAM operation.
Document Number: 001-06366 Rev. *C
Page 18 of 28
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Boundary Scan Order
Bit #
0
Bump ID
6R
Bit #
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
Bump ID
10G
9G
Bit #
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
Bump ID
6A
5B
5A
4A
5C
4B
3A
2A
1A
2B
3B
1C
1B
3D
3C
1D
2C
3E
2D
2E
1E
2F
Bit #
84
Bump ID
1J
1
6P
85
2J
2
6N
11F
11G
9F
86
3K
3
7P
87
3J
4
7N
88
2K
5
7R
10F
11E
10E
10D
9E
89
1K
6
8R
90
2L
7
8P
91
3L
8
9R
92
1M
1L
9
11P
10P
10N
9P
93
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
10C
11D
9C
94
3N
95
3M
1N
96
10M
11N
9M
9D
97
2M
3P
11B
11C
9B
98
99
2N
9N
100
101
102
103
104
105
106
107
108
2P
11L
11M
9L
10B
11A
10A
9A
1P
3R
4R
10L
11K
10K
9J
4P
8B
5P
7C
3F
5N
6C
1G
1F
5R
9K
8A
Internal
10J
11J
11H
7A
3G
2G
1H
7B
6B
Document Number: 001-06366 Rev. *C
Page 19 of 28
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DLL Constraints
• DLL uses K clock as its synchronizing input. The input must
have low phase jitter, which is specified as tKC Var
Power Up Sequence in QDR-II+ SRAM
QDR-II+ SRAMs must be powered up and initialized in a
predefined manner to prevent undefined operations. During
power up, when the DOFF is tied HIGH, the DLL is locked after
2048 cycles of stable clock.
.
• The DLL functions at frequencies down to 120 MHz.
• If the input clock is unstable and the DLL is enabled, then
the DLL may lock onto an incorrect frequency, causing
unstable SRAM behavior. To avoid this, provide 2048 cycles
stable clock to relock to the clock frequency you want.
Power Up Sequence
• Apply power with DOFF tied HIGH (All other inputs can be
HIGH or LOW)
— Apply VDD before VDDQ
— Apply VDDQ before VREF or at the same time as VREF
• Provide stable power and clock (K, K) for 2048 cycles to
lock the DLL
Power Up Waveforms
Figure 2. Power Up Waveforms
K
K
Start Normal
Operation
Unstable Clock
> 2048 Stable Clock
Clock Start (Clock Starts after V /V
DD DDQ
is Stable)
V
/V
+
/V Stable (< 0.1V DC per 50 ns)
DD DDQ
V
DD DDQ
Fix HIGH (tie to V
DDQ
)
DOFF
Document Number: 001-06366 Rev. *C
Page 20 of 28
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Maximum Ratings
Exceeding maximum ratings may shorten the battery life of the
device. User guidelines are not tested.
Current into Outputs (LOW)......................................... 20 mA
Static Discharge Voltage (MIL-STD-883, M. 3015)... >2001V
Latch up Current..................................................... >200 mA
Storage Temperature ................................–65°C to + 150°C
Ambient Temperature with Power Applied.–55°C to + 125°C
Supply Voltage on VDD Relative to GND....... –0.5V to + 2.9V
Supply Voltage on VDDQ Relative to GND .....–0.5V to + VDD
DC Applied to Outputs in High-Z .........–0.5V to VDDQ + 0.3V
DC Input Voltage[13] ...............................–0.5V to VDD + 0.3V
Operating Range
Ambient
[17]
[17]
Range Temperature (TA)
VDD
VDDQ
1.4V to VDD
Com’l
Ind’l
0°C to +70°C
1.8 ± 0.1V
–40°C to +85°C
Electrical Characteristics
Over the Operating Range[14]
DC Electrical Characteristics
Parameter
VDD
Description
Power Supply Voltage
I/O Supply Voltage
Test Conditions
Min
1.7
Typ
1.8
1.5
Max
Unit
V
1.9
VDDQ
VOH
1.4
VDD
V
Output HIGH Voltage
Output LOW Voltage
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Note 18
Note 19
VDDQ/2 – 0.12
VDDQ/2 – 0.12
VDDQ – 0.2
VSS
VDDQ/2 + 0.12
V
VOL
VDDQ/2 + 0.12
V
VOH(LOW)
VOL(LOW)
VIH
IOH = −0.1 mA, Nominal Impedance
VDDQ
0.2
V
IOL = 0.1 mA, Nominal Impedance
V
VREF + 0.1
–0.15
VDDQ + 0.15
VREF – 0.1
2
V
VIL
V
IX
Input Leakage Current
GND ≤ VI ≤ VDDQ
−2
µA
µA
V
IOZ
Output Leakage Current
Input Reference Voltage[20] Typical Value = 0.75V
GND ≤ VI ≤ VDDQ, Output Disabled
−2
2
VREF
IDD
0.68
0.75
0.95
VDD Operating Supply
VDD = Max., IOUT = 0mA, 300 MHz
1040
1120
1240
1330
280
mA
mA
mA
mA
mA
mA
mA
mA
f = fMAX = 1/tCYC
333 MHz
375 MHz
400 MHz
300 MHz
333 MHz
375 MHz
400 MHz
ISB1
Automatic
Power-down
Current
Max. VDD, Both Ports
Deselected, VIN ≥ VIH or
VIN ≤ VIL
300
f = fMAX = 1/tCYC
Inputs Static
,
310
320
AC Electrical Characteristics
Over the Operating Range [13]
Parameter
Description
Test Conditions
Min.
VREF + 0.2
–0.24
Typ.
Max.
Unit
V
VIH
VIL
Input HIGH Voltage
Input LOW Voltage
–
–
VDDQ + 0.24
VREF – 0.2
V
Notes
17. Power up: assumes a linear ramp from 0V to V (min) within 200 ms. During this time V < V and V
< V
DD.
DD
IH
DD
DDQ
18. Outputs are impedance controlled. I = −(V
/2)/(RQ/5) for values of 175Ω <= RQ <= 350Ωs.
OH
DDQ
19. Outputs are impedance controlled. I = (V
/2)/(RQ/5) for values of 175Ω <= RQ <= 350Ωs.
DDQ
OL
20. V
(min) = 0.68V or 0.46V
, whichever is larger, V
(max) = 0.95V or 0.54V
, whichever is smaller.
REF
DDQ
REF
DDQ
Document Number: 001-06366 Rev. *C
Page 21 of 28
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Capacitance
Tested initially and after any design or process change that may affect these parameters.
Parameter
CIN
Description
Input Capacitance
Test Conditions
Max.
Unit
pF
TA = 25°C, f = 1 MHz,
5
4
5
V
DD = 1.8V
CCLK
Clock Input Capacitance
Output Capacitance
pF
VDDQ = 1.5V
CO
pF
Thermal Resistance
Tested initially and after any design or process change that may affect these parameters.
165 FBGA
Package
Parameter
Description
Test Conditions
Unit
ΘJA
Thermal Resistance
(Junction to Ambient)
Test conditions follow standard test methods and
procedures for measuring thermal impedance, per
EIA/JESD51.
16.25
°C/W
ΘJC
Thermal Resistance
(Junction to Case)
2.91
°C/W
AC Test Loads and Waveforms
Figure 3. AC Test Loads and Waveforms
VREF = 0.75V
0.75V
VREF
VREF
0.75V
R = 50Ω
OUTPUT
[21]
ALL INPUT PULSES
Z = 50Ω
0
OUTPUT
1.25V
Device
Under
Test
R = 50Ω
L
0.75V
Device
Under
0.25V
5 pF
VREF = 0.75V
Slew Rate = 2 V/ns
ZQ
Test
ZQ
RQ =
RQ =
250
250Ω
Ω
INCLUDING
JIG AND
SCOPE
(a)
(b)
Note
21. Unless otherwise noted, test conditions assume signal transition time of 2V/ns, timing reference levels of 0.75V, V
= 0.75V, RQ = 250Ω, V
= 1.5V, input
DDQ
REF
pulse levels of 0.25V to 1.25V, and output loading of the specified I /I and load capacitance shown in (a) of AC Test Loads and Waveforms.
OL OH
Document Number: 001-06366 Rev. *C
Page 22 of 28
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Switching Characteristics
Over the Operating Range[21, 22]
400 MHz
375 MHz
333 MHz
300 MHz
Cypress Consortium
Parameter Parameter
Description
Unit
Min Max Min Max Min Max Min. Max.
tPOWER
tCYC
tKH
VDD(Typical) to the First Access[23]
K Clock Cycle Time
1
–
1
–
1
–
1
–
ms
ns
tKHKH
tKHKL
tKLKH
tKHKH
2.50 8.4 2.66 8.4 3.0 8.4 3.3 8.4
Input Clock (K/K) HIGH
Input Clock (K/K) LOW
0.4
0.4
–
–
–
0.4
0.4
–
–
–
0.4
0.4
–
–
–
0.4
0.4
–
–
–
tCYC
tCYC
ns
tKL
tKHKH
K Clock Rise to K Clock Rise
(rising edge to rising edge)
1.06
1.13
1.28
1.40
Set-up Times
tSA
tAVKH
tIVKH
tIVKH
Address Set-up to K Clock Rise
0.4
–
–
–
0.4
0.4
–
–
–
0.4
0.4
–
–
–
0.4
0.4
–
–
–
ns
ns
ns
tSC
Control Set-up to K Clock Rise (RPS, WPS) 0.4
tSCDDR
Double Data Rate Control Set-up to Clock 0.28
(K, K) Rise (BWS0, BWS1, BWS2, BWS3)
0.28
0.28
0.28
tSD
tDVKH
D[X:0] Set-up to Clock (K/K) Rise
0.28
–
0.28
–
0.28
–
0.28
–
ns
Hold Times
tHA
tKHAX
tKHIX
tKHIX
Address Hold after K Clock Rise
0.4
–
–
–
0.4
0.4
–
–
–
0.4
0.4
–
–
–
0.4
0.4
–
–
–
ns
ns
ns
tHC
Control Hold after K Clock Rise (RPS, WPS) 0.4
tHCDDR
Double Data Rate Control Hold after Clock 0.28
(K/K) Rise (BWS0, BWS1, BWS2, BWS3)
0.28
0.28
0.28
tHD
tKHDX
D[X:0] Hold after Clock (K/K) Rise
0.28
–
0.28
–
0.28
–
0.28
–
ns
Output Times
tCO
tCHQV
K/K Clock Rise to Data Valid
–
0.45
–
–
0.45
–
–
0.45
–
–
0.45
–
ns
ns
tDOH
tCHQX
Data Output Hold after Output K/K Clock
Rise (Active to Active)
–0.45
–0.45
–0.45
–0.45
tCCQO
tCQOH
tCQD
tCHCQV
tCHCQX
tCQHQV
tCQHQX
tCQHCQL
K/K Clock Rise to Echo Clock Valid
Echo Clock Hold after K/K Clock Rise
Echo Clock High to Data Valid
–
0.45
–
–
0.45
–
–
0.45
–
–
0.45
–
ns
ns
ns
ns
ns
ns
–0.45
–
–0.45
–0.45
–0.45
0.2
–
0.2
–
0.2
–
0.2
–
tCQDOH
tCQH
Echo Clock High to Data Invalid
Output Clock (CQ/CQ) HIGH[24]
CQ Clock Rise to CQ Clock Rise[24]
–0.2
0.81
0.81
–0.2
0.88
0.88
–0.2
1.03
1.03
–0.2
1.15
1.15
–
–
–
–
tCQHCQH tCQHCQH
–
–
–
–
(rising edge to rising edge)
tCHZ
tCHQZ
Clock (K/K) Rise to High-Z
(Active to High-Z)[25, 26]
–
0.45
–
0.45
–
0.45
–
0.45
ns
tCLZ
tCHQX1
Clock (K/K) Rise to Low-Z[25, 26]
Echo Clock High to QVLD Valid[27]
–0.45
–
–0.45
–
–0.45
–
–0.45
–
ns
ns
tQVLD
tCQHQVLD
–0.20 0.20 –0.20 0.20 –0.20 0.20 –0.20 0.20
DLL Timing
tKC Var tKC Var
tKC lock tKC lock
Clock Phase Jitter
–
0.20
–
–
0.20
–
–
0.20
–
–
0.20
–
ns
Cycles
ns
DLL Lock Time (K)
K Static to DLL Reset[28]
2048
30
2048
30
2048
30
2048
30
tKC Reset tKC Reset
–
–
–
–
Notes
22. When a part with a maximum frequency above 300 MHz is operating at a lower clock frequency, it requires the input timings of the frequency range in which it is
being operated and will output data with the output timings of that frequency range.
23. This part has an internal voltage regulator; t
can be initiated.
is the time that the power needs to be supplied above V minimum initially before a read or write operation
DD
POWER
24. These parameters are extrapolated from the input timing parameters (t
– 250 ps, where 250 ps is the internal jitter. An input jitter of 200 ps (t
) is already
KHKH
KC Var
included in the t
). These parameters are only guaranteed by design and are not tested in production.
KHKH
25. t
, t
, are specified with a load capacitance of 5 pF as in part (b) of “AC Test Loads and Waveforms” on page 22. Transition is measured ±100 mV from
CHZ CLZ
steady-state voltage.
26. At any voltage and temperature t
is less than t
and t
less than t
.
CHZ
CLZ
CHZ
CO
27. t
spec is applicable for both rising and falling edges of QVLD signal.
QVLD
28. Hold to >V or <V .
IH
IL
Document Number: 001-06366 Rev. *C
Page 23 of 28
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Switching Waveforms
Figure 4. Read/Write/Deselect Sequence waveform for 2.5 Cycle Read Latency[29, 30, 31]
WRITE
3
READ
4
NOP
1
READ
2
WRITE
5
NOP
6
7
8
K
t
t
KL
t
t
KH
CYC
KHKH
K
RPS
t
t
SC HC
t
t
SC
HC
WPS
A
A0
A1
A2
A3
t
t
HD
t
t
HD
SA
HA
t
SD
t
SD
D11
D12
D30
D32
D33
D10
QVLD
D13
D31
D
t
QVLD
t
QVLD
t
DOH
t
t
CQDOH
t
CO
t
CHZ
t
CLZ
t
CQD
Q
Q00 Q01 Q02
CCQO
Q20 Q21 Q22
Q23
Q03
(Read Latency = 2.5 Cycles)
CQOH
CQ
CQ
CCQO
t
t
t
CQHCQH
CQH
CQOH
DON’T CARE
UNDEFINED
Notes
29. Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, that is, A0+1.
30. Outputs are disabled (High-Z) one clock cycle after a NOP.
31. In this example, if address A2 = A1, then data Q20 = D10 and Q21 = D11. Write data is forwarded immediately as read results. This note applies to the whole
diagram.
Document Number: 001-06366 Rev. *C
Page 24 of 28
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Ordering Information
Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit
www.cypress.com for actual products offered.
Speed
(MHz)
Package
Diagram
Operating
Range
Ordering Code
Package Type
400 CY7C1261V18-400BZC
CY7C1276V18-400BZC
CY7C1263V18-400BZC
CY7C1265V18-400BZC
CY7C1261V18-400BZXC
CY7C1276V18-400BZXC
CY7C1263V18-400BZXC
CY7C1265V18-400BZXC
CY7C1261V18-400BZI
CY7C1276V18-400BZI
CY7C1263V18-400BZI
CY7C1265V18-400BZI
CY7C1261V18-400BZXI
CY7C1276V18-400BZXI
CY7C1263V18-400BZXI
CY7C1265V18-400BZXI
375 CY7C1261V18-375BZC
CY7C1276V18-375BZC
CY7C1263V18-375BZC
CY7C1265V18-375BZC
CY7C1261V18-375BZXC
CY7C1276V18-375BZXC
CY7C1263V18-375BZXC
CY7C1265V18-375BZXC
CY7C1261V18-375BZI
CY7C1276V18-375BZI
CY7C1263V18-375BZI
CY7C1265V18-375BZI
CY7C1261V18-375BZXI
CY7C1276V18-375BZXI
CY7C1263V18-375BZXI
CY7C1265V18-375BZXI
51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm)
51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free
51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm)
51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free
51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm)
51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free
51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm)
51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free
Commercial
Industrial
Commercial
Industrial
Document Number: 001-06366 Rev. *C
Page 25 of 28
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Ordering Information (continued)
Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit
www.cypress.com for actual products offered.
Speed
(MHz)
Package
Diagram
Operating
Range
Ordering Code
Package Type
333 CY7C1261V18-333BZC
CY7C1276V18-333BZC
CY7C1263V18-333BZC
CY7C1265V18-333BZC
CY7C1261V18-333BZXC
CY7C1276V18-333BZXC
CY7C1263V18-333BZXC
CY7C1265V18-333BZXC
CY7C1261V18-333BZI
CY7C1276V18-333BZI
CY7C1263V18-333BZI
CY7C1265V18-333BZI
CY7C1261V18-333BZXI
CY7C1276V18-333BZXI
CY7C1263V18-333BZXI
CY7C1265V18-333BZXI
300 CY7C1261V18-300BZC
CY7C1276V18-300BZC
CY7C1263V18-300BZC
CY7C1265V18-300BZC
CY7C1261V18-300BZXC
CY7C1276V18-300BZXC
CY7C1263V18-300BZXC
CY7C1265V18-300BZXC
CY7C1261V18-300BZI
CY7C1276V18-300BZI
CY7C1263V18-300BZI
CY7C1265V18-300BZI
CY7C1261V18-300BZXI
CY7C1276V18-300BZXI
CY7C1263V18-300BZXI
CY7C1265V18-300BZXI
51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm)
51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free
51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm)
51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free
51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm)
51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free
51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm)
51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free
Commercial
Industrial
Commercial
Industrial
Document Number: 001-06366 Rev. *C
Page 26 of 28
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CY7C1261V18
CY7C1276V18
CY7C1263V18
CY7C1265V18
Package Diagram
Figure 5. 165-ball FBGA (15 x 17 x 1.40 mm), 51-85195
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Document Number: 001-06366 Rev. *C
Page 27 of 28
© Cypress Semiconductor Corporation, 2006-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the
use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to
be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress, IDT, NEC, Renesas, andSamsung. All other trademarks or registered trademarks referenced
herein are property of the respective corporations.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and
foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create
derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only
in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except
as specified above is prohibited without the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WAR-
RANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein.
Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in
life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress' product in a life-support systems application
implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
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CY7C1261V18
CY7C1276V18
CY7C1263V18
CY7C1265V18
Document History Page
Document Title: CY7C1261V18/CY7C1276V18/CY7C1263V18/CY7C1265V18, 36-Mbit QDR™-II+ SRAM 4-Word Burst
Architecture (2.5 Cycle Read Latency)
Document Number: 001-06366
ISSUE
DATE
ORIG. OF
CHANGE
REV.
ECN NO.
DESCRIPTION OF CHANGE
**
425689
461639
See ECN
See ECN
NXR
NXR
New Data Sheet
*A
Revised the MPNs from
CY7C1256AV18 to CY7C1276V18
CY7C1263AV18 to CY7C1263V18
CY7C1265AV18 to CY7C1265V18
Changed tTH and tTL from 40 ns to 20 ns, changed tTMSS, tTDIS, tCS
,
tTMSH, tTDIH, tCH from 10 ns to 5 ns and changed tTDOV from 20 ns to 10
ns in TAP AC Switching Characteristics table
Modified Power-Up waveform
*B
497628
See ECN
NXR
Changed the VDDQ operating voltage to 1.4V to VDD in the Features
section, in Operating Range table and in the DC Electrical Characteristics
table
Added foot note in page# 1
Changed the Maximum rating of Ambient Temperature with Power
Applied from –10°C to +85°C to –55°C to +125°C
Changed VREF (Max.) spec from 0.85V to 0.95V in the DC Electrical
Characteristics table and in the note below the table
Updated note# 20 to specify Overshoot and Undershoot Spec
Updated ΘJA and ΘJC values
Removed x9 part and its related information
Updated footnote #25
*C
1072841
See ECN VKN/KKVTMP Converted from preliminary to final
Added x8 and x9 parts
Changed IDD values from 1050 mA to 1330 mA for 400 MHz, 950 mA to
1240 mA for 375 MHz, 850 mA to 1120 mA for 333 MHz, 800 mA to 1040
mA for 300 MHz
Changed ISB values from 325 mA to 320 mA for 400 MHz, 300 mA to 310
mA for 375 MHz, 275 mA to 300 mA for 333 MHz, 250 mA to 280 mA for
300 MHz
Changed tCYC max spec to 8.4 ns for all speed bins
Changed ΘJA value from 12.43 °C/W to 16.25 °C/W
Updated Ordering Information table
Document Number: 001-06366 Rev. *C
Page 28 of 28
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