CY7C1049BNV33-12VXI [CYPRESS]
512K x 8 Static RAM; 512K ×8静态RAM
| 型号： | CY7C1049BNV33-12VXI |
| 厂家： | 
CYPRESS |
| 描述： | 512K x 8 Static RAM |
| 文件： | 总8页 (文件大小：420K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C1049BNV33
512K x 8 Static RAM
Features
Functional Description[1]
• High speed
The CY7C1049BNV33 is a high-performance CMOS Static
RAM organized as 524,288 words by 8 bits. Easy memory
expansion is provided by an active LOW Chip Enable (CE), an
active LOW Output Enable (OE), and three-state drivers.
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. Data on the eight I/O
pins (I/O0 through I/O7) is then written into the location
specified on the address pins (A0 through A18).
— tAA = 12 ns
• Low active power
— 504 mW (max.)
• Low CMOS standby power (Commercial L version)
— 1.8 mW (max.)
• 2.0V Data Retention (660 µW at 2.0V retention)
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE and OE features
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing Write
Enable (WE) HIGH. Under these conditions, the contents of
the memory location specified by the address pins will appear
on the I/O pins.
The eight input/output pins (I/O0 through I/O7) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a write
operation (CE LOW, and WE LOW).
The CY7C1049BNV33 is available in a standard 400-mil-wide
36-pin SOJ and 44-pin TSOPII packages with center power
and ground (revolutionary) pinout.
Logic Block Diagram
Pin Configuration
TSOP
SOJ
Top View
Top View
A
A
36
35
34
33
1
2
3
4
5
6
7
8
9
44
NC
NC
NC
1
0
1
NC
NC
43
42
41
40
39
38
2
3
4
5
6
A
A
A
A
18
17
16
15
NC
A
0
A
2
A
A
1
18
A
A
3
4
A
A
2
17
32
I/O0
A
A
16
3
INPUTBUFFER
CE
31
30
29
28
OE
I/O
A
A
4
CE
7
15
A0
A1
A2
A3
A4
37
36
35
34
33
I/O1
I/O2
I/O
8
OE
I/O
0
1
7
I/O
9
0
I/O
I/O
V
7
6
10
11
12
13
I/O
V
SS
I/O
1
CC
6
GND
CC
V
SS
27
26
25
GND
I/O
I/O3
10
11
12
13
A5
A6
A7
A8
A9
V
I/O3
I/O4
I/O5
CC
V
V
512K x 8
ARRAY
CC
I/O
32
I/O
I/O
5
2
2
5
4
I/O
31
30
29
28
I/O
A
I/O
14
15
16
17
18
19
20
4
3
WE
WE
14
24
23
22
21
20
19
A
14
A10
A
A
13
5
A
A
A
A
A
14
15
16
17
18
13
5
A
12
A
6
A
A
12
A
6
I/O6
I/O7
27
26
25
11
7
POWER
DOWN
COLUMN
A
A
CE
A
10
NC
7
11
8
9
DECODER
A
A
8
10
WE
NC
NC
NC 21
24
23
A
NC
9
22
NC
OE
Cypress Semiconductor Corporation
Document #: 001-06432 Rev. **
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised February 1, 2006
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CY7C1049BNV33
Selection Guide
-12
12
-15
15
-20
20
Maximum Access Time (ns)
Maximum Operating Current (mA)
Com’l
200
220
8
180
200
8
160
170
8
Ind’l
Maximum CMOS Standby Current (mA)
Com’l/Ind’l
Com’l
L
0.5
0.5
0.5
DC Input Voltage[2] ................................ –0.5V to VCC + 0.5V
Current into Outputs (LOW)......................................... 20 mA
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Operating Range
Storage Temperature .................................–65°C to +150°C
Ambient
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Supply Voltage on VCC to Relative GND[2].....–0.5V to +4.6V
DC Voltage Applied to Outputs[2]
Range
Commercial
Industrial
Temperature
0°C to +70°C
–40°C to +85°C
VCC
3.3V ± 0.3V
in High Z State .......................................–0.5V to VCC + 0.5V
DC Electrical Characteristics Over the Operating Range
-12
-15
-20
Parameter
Description
Output HIGH
Voltage
Test Conditions
VCC = Min.,
OH = –4.0 mA
Min.
Max.
Min.
2.4
Max.
Min.
2.4
Max.
Unit
VOH
2.4
V
I
VOL
Output LOW Voltage VCC = Min.,
IOL = 8.0 mA
0.4
0.4
0.4
V
VIH
VIL
IIX
Input HIGH Voltage
Input LOW Voltage[2]
2.2 VCC + 0.5 2.2 VCC + 0.5 2.2 VCC + 0.5
V
V
–0.5
–1
0.8
+1
–0.5
–1
0.8
+1
–0.5
–1
0.8
+1
Input Leakage
Current
GND < VI < VCC
µA
IOZ
ICC
Output Leakage
Current
GND < VOUT < VCC
Output Disabled
,
–1
+1
–1
+1
–1
+1
µA
VCC Operating
Supply Current
VCC = Max.,
f = fMAX = 1/tRC
Com’l
Ind’l
200
220
30
180
200
30
160
170
30
mA
mA
mA
ISB1
Automatic CE
Power-Down
Current
Max. VCC, CE > VIH
VIN > VIH or
VIN < VIL, f = fMAX
—TTL Inputs
ISB2
Automatic CE
Power-Down
Current
Max. VCC
CE > VCC – 0.3V,
IN > VCC – 0.3V,
,
Com’l/Ind’l
8
8
8
mA
mA
Com’l
L
0.5
0.5
0.5
V
—CMOS Inputs
or VIN < 0.3V, f = 0
Capacitance[3]
Parameter
Description
Test Conditions
TA = 25°C, f = 1 MHz,
CC = 3.3V
Max.
Unit
CIN
Input Capacitance
8
pF
V
COUT
I/O Capacitance
8
pF
Notes:
1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.
2. V (min.) = –2.0V for pulse durations of less than 20 ns.
IL
3. Tested initially and after any design or process changes that may affect these parameters.
Document #: 001-06432 Rev. **
Page 2 of 8
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CY7C1049BNV33
AC Test Loads and Waveforms
R1 317Ω
THÉ
VENIN EQUIVALENT
3.3V
167Ω
ALL INPUT PULSES
90%
10%
1.73V
OUTPUT
OUTPUT
3.3V
90%
10%
R2
351Ω
30 pF
(b)
GND
INCLUDING
JIG AND
SCOPE
RiseTime:1 V/ns
Fall time:
1 V/ns
(a)
AC Switching Characteristics[4] Over the Operating Range
-12
-15
-20
Parameter
Read Cycle
tpower
tRC
Description
Min.
Max.
Min.
Max.
Min.
Max.
Unit
VCC (typical) to the First Access[5]
Read Cycle Time
1
1
1
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
12
15
20
tAA
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
OE HIGH to High Z[6, 7]
CE LOW to Low Z[7]
CE HIGH to High Z[6, 7]
CE LOW to Power-Up
CE HIGH to Power-Down
12
15
20
tOHA
3
3
3
tACE
12
6
15
7
20
8
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
tPU
0
3
0
0
3
0
0
3
0
6
6
7
7
8
8
tPD
12
15
20
Write Cycle[8, 9]
tWC
tSCE
tAW
tHA
Write Cycle Time
12
10
10
0
15
12
12
0
20
13
13
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
tSA
0
0
0
tPWE
tSD
10
7
12
8
13
9
Data Set-Up to Write End
Data Hold from Write End
WE HIGH to Low Z[7]
tHD
0
0
0
tLZWE
3
3
3
tHZWE
WE LOW to High Z[6, 7]
6
7
8
Notes:
4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
/I and 30-pF load capacitance.
OL OH
5. This part has a voltage regulator which steps down the voltage from 5V to 3.3V internally. T.
started.
time has to be provided initially before a read/write operation is
power
6. t
, t
, and t
are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ± 500 mV from steady-state voltage.
HZOE HZCE
HZWE
7. At any given temperature and voltage condition, t
is less than t
, t
is less than t
, and t
is less than t
for any given device.
HZCE
LZCE HZOE
LZOE
HZWE
LZWE
8. The internal write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a write, and the transition of either
of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
9. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of t
and t
.
SD
HZWE
10. No input may exceed V + 0.5V
CC
11. .t < 3 ns for the -12 and -15 speeds. t < 5 ns for the -20 ns and slower speeds.
r
r
Document #: 001-06432 Rev. **
Page 3 of 8
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CY7C1049BNV33
Data Retention Characteristics Over the Operating Range (For L version only)
Parameter
Description
VCC for Data Retention
Data Retention Current
Conditions[10]
Min.
Max
Unit
V
VDR
2.0
ICCDR
VCC = VDR = 2.0V,
CE > VCC – 0.3V
IN > VCC – 0.3V or VIN < 0.3V
330
µA
ns
[3]
tCDR
Chip Deselect to Data Retention
Time
0
V
[11]
tR
Operation Recovery Time
tRC
ns
Data Retention Waveform
DATA RETENTION MODE
> 2V
3.0V
3.0V
V
VCC
CE
DR
t
t
R
CDR
Switching Waveforms
Read Cycle No. 1[12, 13]
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Read Cycle No. 2 (OE Controlled)[13, 14]
ADDRESS
CE
t
RC
t
ACE
OE
t
HZOE
t
DOE
t
HZCE
t
LZOE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA OUT
DATA VALID
t
LZCE
t
PD
ICC
t
V
PU
CC
50%
50%
SUPPLY
ISB
CURRENT
Notes:
12. Device is continuously selected. OE, CE = V .
IL
13. WE is HIGH for read cycle.
14. Address valid prior to or coincident with CE transition LOW.
Document #: 001-06432 Rev. **
Page 4 of 8
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CY7C1049BNV33
Switching Waveforms (continued)
Write Cycle No. 1 (WE Controlled, OE HIGH During Write)[15, 16]
t
WC
ADDRESS
CE
t
SCE
t
t
HA
AW
t
t
PWE
SA
WE
OE
t
t
SD
HD
DATA VALID
DATA I/O
IN
NOTE 17
t
HZOE
Write Cycle No. 2 (WE Controlled, OE LOW)[16]
t
WC
ADDRESS
CE
t
SCE
t
t
HA
AW
t
SA
t
PWE
WE
t
t
HD
SD
NOTE 17
DATA I/O
DATA VALID
t
t
LZWE
HZWE
Truth Table
CE
H
OE
WE
X
I/O0 – I/O7
Mode
Power
Standby (ISB
X
L
High Z
Power-Down
Read
)
L
H
Data Out
Data In
High Z
Active (ICC
)
)
)
L
X
H
L
Write
Active (ICC
Active (ICC
L
H
Selected, Outputs Disabled
Notes:
15. Data I/O is high-impedance if OE = V
.
IH
16. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
17. During this period the I/Os are in the output state and input signals should not be applied.
Document #: 001-06432 Rev. **
Page 5 of 8
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CY7C1049BNV33
Ordering Information
Speed
Package
Name
Operating
Range
(ns)
Ordering Code
Package Type
44-Pin TSOP II Z44
12
CY7C1049BNV33-12ZC
CY7C1049BNV33-12VXC
CY7C1049BNV33-12VI
CY7C1049BNV33-12VXI
CY7C1049BNV33-15VC
CY7C1049BNV33-15VXC
CY7C1049BNV33L-15VXC
CY7C1049BNV33-15ZC
CY7C1049BNV33-15VI
CY7C1049BNV33-15VXI
CY7C1049BNV33-15ZI
CY7C1049BNV33-20VC
CY7C1049BNV33-20VXC
CY7C1049BNV33-20VXI
51-85087
51-85090
51-85090
51-85090
51-85090
51-85090
51-85090
51-85087
51-85090
51-85090
51-85087
51-85090
51-85090
51-85090
Commercial
36-Lead (400-Mil) Molded SOJ (Pb-free)
36-Lead (400-Mil) Molded SOJ
Industrial
36-Lead (400-Mil) Molded SOJ (Pb-free)
36-Lead (400-Mil) Molded SOJ
15
Commercial
36-Lead (400-Mil) Molded SOJ (Pb-free)
36-Lead (400-Mil) Molded SOJ (Pb-free)
44-Pin TSOP II Z44
36-Lead (400-Mil) Molded SOJ
Industrial
36-Lead (400-Mil) Molded SOJ (Pb-free)
44-Pin TSOP II Z44
20
36-Lead (400-Mil) Molded SOJ
Commercial
Industrial
36-Lead (400-Mil) Molded SOJ (Pb-free)
36-Lead (400-Mil) Molded SOJ (Pb-free)
Please contact local sales representative regarding availability of these parts
\\
Package Diagrams
36-pin (400-Mil) Molded SOJ (51-85090)
51-85090-*B
Document #: 001-06432 Rev. **
Page 6 of 8
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CY7C1049BNV33
Package Diagrams (continued)
44-Pin TSOP II Z44 (51-85087)
51-85087-*A
All product and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 001-06432 Rev. **
Page 7 of 8
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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CY7C1049BNV33
Document History Page
Document Title: CY7C1049BNV33 512K x 8 Static RAM
Document Number: 001-06432
Issue
Date
Orig. of
Change
REV.
ECN NO.
Description of Change
**
423847
See ECN
NXR
New Data Sheet
Document #: 001-06432 Rev. **
Page 8 of 8
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