CY7C1049B-20VIT [CYPRESS]
Standard SRAM, 512KX8, 20ns, CMOS, PDSO36, 0.400 INCH, SOJ-36;
| 型号： | CY7C1049B-20VIT |
| 厂家： | 
CYPRESS |
| 描述： | Standard SRAM, 512KX8, 20ns, CMOS, PDSO36, 0.400 INCH, SOJ-36 静态存储器 光电二极管 内存集成电路 |
| 文件： | 总10页 (文件大小：132K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
049B
CY7C1049B
512K x 8 Static RAM
is provided by an active LOW Chip Enable (CE), an active
LOW Output Enable (OE), and three-state drivers. Writing to
the device is accomplished by taking Chip Enable (CE) and
Write Enable (WE) inputs LOW. Data on the eight I/O pins (I/O0
through I/O7) is then written into the location specified on the
address pins (A0 through A18).
Features
• High speed
— tAA = 12 ns
• Low active power
— 1320 mW (max.)
Reading from the device is accomplished by taking Chip En-
able (CE) and Output Enable (OE) LOW while forcing Write
Enable (WE) HIGH. Under these conditions, the contents of
the memory location specified by the address pins will appear
on the I/O pins.
• Low CMOS standby power (Commercial L version)
— 2.75 mW (max.)
• 2.0V Data Retention (400 µW at 2.0V retention)
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE and OE features
The eight input/output pins (I/O0 through I/O7) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a write
operation (CE LOW, and WE LOW).
Functional Description[1]
The CY7C1049B is available in a standard 400-mil-wide
36-pin SOJ package with center power and ground (revolu-
tionary) pinout.
The CY7C1049B is a high-performance CMOS static RAM or-
ganized as 524,288 words by 8 bits. Easy memory expansion
Logic Block Diagram
Pin Configuration
SOJ
Top View
A
A
36
35
34
33
32
1
2
3
4
5
6
7
8
9
NC
0
1
A
A
A
A
18
17
16
15
A
2
A
A
3
4
CE
I/O
31
30
29
28
OE
I/O
0
1
7
I/O
I/O
V
I/O
6
0
GND
INPUT BUFFER
CC
27
26
25
GND 10
V
CC
A
1
0
I/O
I/O
I/O
I/O3
WE
I/O
I/O
A
11
12
13
1
5
4
2
A
A
2
24
23
22
21
20
19
14
2
A
A
A
A
A
A
5
3
4
14
15
16
17
18
13
A
A
12
6
A
7
A
11
10
5
6
I/O
I/O
I/O
3
4
5
512K x 8
ARRAY
A
A
8
A
9
NC
A
7
A
8
A
9
A
10
I/O
6
7
POWER
DOWN
COLUMN
DECODER
CE
I/O
WE
OE
Selection Guide
7C1049B-12 7C1049B-15 7C1049B-17 7C1049B-20 7C1049B-25
Maximum Access Time (ns)
12
15
17
195
8
20
185
8
25
180
8
Maximum Operating Current (mA)
240
220
Maximum CMOS Standby
Current (mA)
Com’l
8
-
8
-
Com’l/Ind’l L
Ind’l
0.5
-
0.5
9
0.5
9
-
-
Note:
1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Document #: 38-05169 Rev. *A
Revised September 13, 2002
CY7C1049B
Current into Outputs (LOW) ........................................ 20 mA
Maximum Ratings
Static Discharge Voltage............................................ >2001V
(per MIL-STD-883, Method 3015)
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Latch-Up Current..................................................... >200 mA
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Operating Range
Ambient
Supply Voltage on VCC to Relative GND[2] .... –0.5V to +7.0V
Range
Commercial
Industrial
Temperature
0°C to +70°C
–40°C to +85°C
VCC
DC Voltage Applied to Outputs
4.5V–5.5V
in High Z State[2] ....................................–0.5V to VCC + 0.5V
DC Input Voltage[2].................................–0.5V to VCC + 0.5V
Electrical Characteristics Over the Operating Range
Parameter
Description
Test Conditions
7C1049B-12
7C1049B-15
7C1049B-17
Min.
Max.
Min.
Max.
Min.
Max. Unit
VOH
VOL
VIH
Output HIGH Voltage VCC = Min., IOH = –4.0 mA
Output LOW Voltage VCC = Min., IOL = 8.0 mA
Input HIGH Voltage
2.4
2.4
2.4
V
0.4
0.4
0.4
V
V
2.2
VCC
+ 0.3
2.2
VCC
+ 0.3
2.2
VCC
+ 0.3
VIL
IIX
Input LOW Voltage[2]
–0.3
–1
0.8
+1
+1
–0.3
–1
0.8
+1
+1
–0.3
–1
0.3
+1
+1
V
Input Load Current
GND < VI < VCC
µA
µA
IOZ
Output Leakage
Current
GND < VOUT < VCC
Output Disabled
,
–1
–1
–1
ICC
VCC Operating
Supply Current
VCC = Max.,
f = fMAX = 1/tRC
240
40
220
40
195
40
mA
mA
ISB1
Automatic CE
Max. VCC, CE > VIH
Power-Down Current VIN > VIH or
—TTL Inputs
VIN < VIL, f = fMAX
ISB2
Automatic CE
Power-Down Current CE > VCC – 0.3V,
—CMOS Inputs VIN > VCC – 0.3V,
Max. VCC
,
Com’l
Com’l
8
-
8
-
8
mA
mA
mA
mA
L
L
0.5
8
or VIN < 0.3V, f = 0 Ind’l
Ind’l
-
-
-
-
0.5
Note:
2. Minimum voltage is–2.0V for pulse durations of less than 20 ns.
Document #: 38-05169 Rev. *A
Page 2 of 10
CY7C1049B
Electrical Characteristics Over the Operating Range (continued)
Test Conditions
7C1049B-20
7C1049B-25
Min. Max.
2.4
Parameter
VOH
Description
Min.
Max.
Unit
V
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage[2]
Input Load Current
VCC = Min., IOH = –4.0 mA
2.4
VOL
VIH
VIL
IIX
VCC = Min., IOL = 8.0 mA
0.4
VCC + 0.3
0.8
0.4
2.2 VCC + 0.3
V
2.2
–0.3
–1
V
–0.3
–1
0.8
+1
+1
V
GND < VI < VCC
+1
µA
µA
IOZ
Output Leakage
Current
GND < VOUT < VCC
,
–1
+1
–1
Output Disabled
ICC
VCC Operating
Supply Current
VCC = Max.,
f = fMAX = 1/tRC
185
40
180
40
mA
mA
ISB1
Automatic CE
Power-Down Current
Max. VCC, CE > VIH
VIN > VIH or
—TTL Inputs
VIN < VIL, f = fMAX
ISB2
Automatic CE
Power-Down Current
—CMOS Inputs
Max. VCC
,
Com’l
Com’l
Ind’l
8
8
mA
mA
mA
mA
CE > VCC – 0.3V,
VIN > VCC – 0.3V,
or VIN < 0.3V, f = 0
L
L
0.5
8
0.5
8
Ind’l
0.5
0.5
Capacitance[3]
Parameter
Description
Input Capacitance
I/O Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
VCC = 5.0V
Max.
Unit
pF
CIN
8
8
COUT
pF
Note:
3. Tested initially and after any design or process changes that may affect these parameters.
AC Test Loads and Waveforms
ALL INPUT PULSES
90%
Ω
R1 481
R1 481Ω
5V
5V
3.0V
GND
90%
10%
OUTPUT
OUTPUT
10%
R2
255Ω
R2
255Ω
30 pF
5 pF
≤ 3 ns
≤ 3 ns
INCLUDING
JIG AND
SCOPE
INCLUDING
JIG AND
SCOPE
(b)
(a)
THÉ
Equivalent to:
VENIN EQUIVALENT
167Ω
1.73V
OUTPUT
Document #: 38-05169 Rev. *A
Page 3 of 10
CY7C1049B
Switching Characteristics[4] Over the Operating Range
7C1049B-12
7C1049B-15
7C1049B-17
Parameter
Read Cycle
tpower
tRC
Description
Min.
Max.
Min.
Max.
Min.
Max.
Unit
VCC(typical) to the First Access[5]
Read Cycle Time
1
1
1
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
12
15
17
tAA
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z[7]
OE HIGH to High Z[6, 7]
CE LOW to Low Z[7]
CE HIGH to High Z[6, 7]
CE LOW to Power-Up
CE HIGH to Power-Down
12
15
17
tOHA
3
3
3
tACE
12
6
15
7
17
8
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
tPU
0
3
0
0
3
0
0
3
0
6
6
7
7
7
7
tPD
12
15
17
Write Cycle[8, 9]
tWC
tSCE
tAW
tHA
Write Cycle Time
12
10
10
0
15
12
12
0
17
12
12
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
tSA
0
0
0
tPWE
tSD
10
7
12
8
12
8
Data Set-Up to Write End
Data Hold from Write End
WE HIGH to Low Z[7]
tHD
0
0
0
tLZWE
3
3
3
tHZWE
WE LOW to High Z[6, 7]
6
7
8
Notes:
4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and 30-pF load capacitance.
5. This part has a voltage regulator which steps down the voltage from 5V to 3.3V internally. tpower time has to be provided initially before a read/write operation
is started.
6. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
7. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
8. The internal write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a write, and the transition of either of
these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
9. The minimum write cycle time for Write Cycle no. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD
.
Document #: 38-05169 Rev. *A
Page 4 of 10
CY7C1049B
Switching Characteristics[4] Over the Operating Range (continued)
7C1049B-20
Min. Max.
7C1049B-25
Min. Max.
Parameter
Read Cycle
tpower
tRC
Description
Unit
VCC(typical) to the First Access[5]
Read Cycle Time
1
1
1
20
25
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z[7]
OE HIGH to High Z[6, 7]
CE LOW to Low Z[7]
CE HIGH to High Z[6, 7]
CE LOW to Power-Up
CE HIGH to Power-Down
20
25
tOHA
3
5
tACE
20
8
25
10
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
tPU
0
3
0
0
5
0
8
8
10
10
25
tPD
20
Write Cycle[8]
tWC
Write Cycle Time
20
13
13
0
25
15
15
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSCE
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
tAW
tHA
tSA
0
0
tPWE
13
9
15
10
0
tSD
Data Set-Up to Write End
Data Hold from Write End
WE HIGH to Low Z[7]
tHD
0
tLZWE
tHZWE
3
5
WE LOW to High Z[6, 7]
8
10
Data Retention Characteristics Over the Operating Range
Parameter
VDR
Description
VCC for Data Retention
Conditions[11]
Min.
Max Unit
2.0
V
ICCDR
Data Retention Current
Com’l
Ind’l
L
VCC = VDR = 3.0V,
CE > VCC – 0.3V
VIN > VCC – 0.3V or VIN < 0.3V
200
1
µA
mA
ns
[3]
tCDR
Chip Deselect to Data Retention Time
Operation Recovery Time
0
[10]
tR
tRC
ns
Notes:
10. tr < 3 ns for the -12 and -15 speeds. tr < 5 ns for the -20 ns and slower speeds.
11. No input may exceed VCC + 0.5V.
Document #: 38-05169 Rev. *A
Page 5 of 10
CY7C1049B
Data Retention Waveform
DATA RETENTION MODE
> 2V
3.0V
3.0V
V
V
CC
DR
t
t
R
CDR
CE
Switching Waveforms
Read Cycle No. 1[12, 13]
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Read Cycle No. 2 (OE Controlled)[13, 14]
ADDRESS
CE
t
RC
t
ACE
OE
t
HZOE
t
DOE
t
HZCE
t
LZOE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA OUT
DATA VALID
t
LZCE
t
PD
I
t
PU
CC
V
CC
50%
50%
SUPPLY
CURRENT
I
SB
Notes:
12. Device is continuously selected. OE, CE = VIL.
13. WE is HIGH for read cycle.
14. Address valid prior to or coincident with CE transition LOW.
Document #: 38-05169 Rev. *A
Page 6 of 10
CY7C1049B
Switching Waveforms (continued)
Write Cycle No. 1 (CE Controlled)[15, 16]
t
WC
ADDRESS
CE
t
SCE
t
SA
t
SCE
t
t
HA
AW
t
PWE
WE
t
t
HD
SD
DATA I/O
DATA VALID
Write Cycle No. 2 (WE Controlled, OE HIGH During Write)[15, 16]
t
WC
ADDRESS
CE
t
SCE
t
t
HA
AW
t
SA
t
PWE
WE
OE
t
t
SD
HD
DATA VALID
DATA I/O
IN
NOTE 17
t
HZOE
Notes:
15. Data I/O is high impedance if OE = VIH
.
16. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
17. During this period the I/Os are in the output state and input signals should not be applied.
Document #: 38-05169 Rev. *A
Page 7 of 10
CY7C1049B
Switching Waveforms (continued)
Write Cycle No. 3 (WE Controlled, OE LOW)[16]
t
WC
ADDRESS
CE
t
SCE
t
t
HA
AW
t
SA
t
PWE
WE
t
t
HD
SD
NOTE 17
DATA I/O
DATA VALID
t
t
LZWE
HZWE
Ordering Information
Speed
Package
Name
Operating
Range
(ns)
Ordering Code
CY7C1049B-12VC
CY7C1049B-15VC
CY7C1049B-15VI
CY7C1049B-17VC
CY7C1049BL-17VC
CY7C1049B-17VI
CY7C1049B-20VC
CY7C1049BL-20VC
CY7C1049B-20VI
CY7C1049BL-20VI
CY7C1049B-25VC
CY7C1049BL-25VC
CY7C1049B-25VI
CY7C1049BL-25VI
Package Type
12
V36
V36
V36
V36
V36
V36
V36
V36
V36
V36
V36
V36
V36
V36
36-Lead (400-Mil) Molded SOJ
36-Lead (400-Mil) Molded SOJ
36-Lead (400-Mil) Molded SOJ
36-Lead (400-Mil) Molded SOJ
36-Lead (400-Mil) Molded SOJ
36-Lead (400-Mil) Molded SOJ
36-Lead (400-Mil) Molded SOJ
36-Lead (400-Mil) Molded SOJ
36-Lead (400-Mil) Molded SOJ
36-Lead (400-Mil) Molded SOJ
36-Lead (400-Mil) Molded SOJ
36-Lead (400-Mil) Molded SOJ
36-Lead (400-Mil) Molded SOJ
36-Lead (400-Mil) Molded SOJ
Commercial
15
Industrial
17
20
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
25
Document #: 38-05169 Rev. *A
Page 8 of 10
CY7C1049B
Package Diagram
36-Lead (400-Mil) Molded SOJ V36
51-85090-*B
All product and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-05169 Rev. *A
Page 9 of 10
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C1049B
Document History Page
Document Title: CY7C1049B 512K x 8 Static RAM
Document Number: 38-05169
Issue
Date
Orig. of
Change
REV.
**
ECN NO.
110209
116465
Description of Change
Change from Spec number: 38-00937 to 38-05169
Add applications foot note to data sheet, page 1.
12/02/01
09/16/02
SZV
CEA
*A
Document #: 38-05169 Rev. *A
Page 10 of 10
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