CY7C1021DV33-10ZSXAT [CYPRESS]
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| 型号： | CY7C1021DV33-10ZSXAT |
| 厂家： | 
CYPRESS |
| 描述： | 暂无描述 |
| 文件： | 总13页 (文件大小：564K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C1021DV33
1-Mbit (64K x 16) Static RAM
Features
Functional Description[1]
• Temperature Ranges
The CY7C1021DV33 is a high-performance CMOS static
RAM organized as 65,536 words by 16 bits. This device has
an automatic power-down feature that significantly reduces
power consumption when deselected.
— Industrial: –40°C to 85°C
— Automotive-A: –40°C to 85°C
— Automotive-E: –40°C to 125°C
• Pin-and function-compatible with CY7C1021CV33
• High speed
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is
written into the location specified on the address pins (A0
through A15). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O8 through I/O15) is written into the location
specified on the address pins (A0 through A15).
— tAA = 10 ns
• Low active power
— ICC = 60 mA @ 10 ns
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is
LOW, then data from memory will appear on I/O8 to I/O15. See
the truth table at the end of this data sheet for a complete
description of Read and Write modes.
• Low CMOS standby power
— ISB2 = 3 mA
• 2.0V data retention
• Automatic power-down when deselected
• CMOS for optimum speed/power
• Independent control of upper and lower bits
• Available in Pb-free 44-pin 400-Mil wide Molded SOJ,
44-pin TSOP II and 48-ball VFBGA packages
The input/output pins (I/O0 through I/O15) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE
are disabled (BHE, BLE HIGH), or during a Write operation
(CE LOW, and WE LOW).
The CY7C1021DV33 is available in Pb-free 44-pin 400-Mil
wide Molded SOJ, 44-pin TSOP II and 48-ball VFBGA
packages.
Logic Block Diagram
DATA IN DRIVERS
A7
A6
A5
64K x 16
A4
I/O0–I/O7
RAM Array
A3
A2
A1
A0
I/O8–I/O15
COLUMN DECODER
BHE
WE
CE
OE
BLE
Note
1. For guidelines on SRAM system design, please refer to the “System Design Guidelines” Cypress application note, available on the internet at www.cypress.com
Cypress Semiconductor Corporation
Document #: 38-05460 Rev. *F
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised December 14, 2010
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CY7C1021DV33
Selection Guide
–10 (Industrial/Automotive-A)
–12 (Automotive-E)[2]
Unit
ns
10
60
3
Maximum Access Time
12
100
15
mA
mA
Maximum Operating Current
Maximum CMOS Standby Current
Pin Configuration[3]
SOJ/TSOP II
Top View
48-ball VFBGA
Top View
A
A
A
A
A
7
OE
BHE
BLE
I/O
15
I/O
I/O
13
I/O
1
2
3
4
5
6
7
8
44
4
3
5
1
4
3
2
5
6
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
6
A
A
A
2
1
A
A
A
NC
I/O
OE
BLE
0
1
2
A
B
C
0
I/O
A
A
4
BHE
CE
CE
8
3
0
I/O
0
1
2
3
I/O
I/O
I/O
V
14
I/O
10
A
A
6
I/O
I/O
I/O
1
5
9
2
9
10
11
12
13
14
15
16
12
I/O
A
I/O
V
CC
V
NC
NC
3
D
E
F
SS
7
11
V
SS
CC
V
SS
V
CC
I/O
I/O
I/O
I/O
I/O
NC
4
5
6
7
V
V
SS
I/O
I/O
11
10
CC
12
4
I/O
I/O
I/O
9
I/O
A
A
I/O
I/O
I/O
6
14
15
5
13
14
8
WE 17
A
NC
A
A
A
I/O
7
18
G
H
15
I/O
NC
WE
8
13
12
15
A
A
A
A
19
20
21
22
14
13
12
9
A
A
10
11
A
A
A
A
NC
NC
10
9
11
8
NC
NC
Notes
2. Automotive product information is Preliminary.
3. NC pins are not connected on the die.
Document #: 38-05460 Rev. *F
Page 2 of 13
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CY7C1021DV33
Current into Outputs (LOW)......................................... 20 mA
Maximum Ratings
Static Discharge Voltage...........................................> 2001V
(per MIL-STD-883, Method 3015)
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Latch-up Current......................................................>200 mA
Storage Temperature .................................–65C to +150C
Ambient Temperature with
Power Applied.............................................–55C to +125C
Operating Range
Ambient
Temperature
Supply Voltage on VCC to Relative GND[4] .... –0.3V to +4.6V
Range
VCC
Speed
DC Voltage Applied to Outputs
Industrial
–40 C to +85 C 3.3V 0.3V
10 ns
10 ns
12 ns
in High-Z State[4] ......................................–0.3V to VCC+0.3V
Automotive-A –40 C to +85 C
Automotive-E –40 C to +125 C
DC Input Voltage[4]...................................–0.3V to VCC+0.3V
DC Electrical Characteristics Over the Operating Range
–10 (Ind’l/Auto-A)
–12 (Auto-E)
Min. Max.
Parameter
Description
Test Conditions
Unit
Min.
Max.
VOH
VOL
VIH
VIL
IIX
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage[4]
Input Leakage Current
Output Leakage Current
VCC = Min., IOH = –4.0 mA
VCC = Min., IOL = 8.0 mA
2.4
2.4
V
V
0.4
VCC + 0.3
0.8
0.4
2.0
0.3
1
2.0
0.3
5
VCC + 0.3
V
0.8
+5
+5
-
V
GND < VI < VCC
+1
A
A
mA
mA
mA
mA
mA
IOZ
ICC
GND < VI < VCC, Output Disabled
1
+1
5
VCC Operating
Supply Current
VCC = Max.,
IOUT = 0 mA,
f = fMAX = 1/tRC
100 MHz
83 MHz
66 MHz
40 MHz
60
55
100
90
60
50
45
30
ISB1
ISB2
AutomaticCEPower-Down Max. VCC, CE > VIH
Current —TTL Inputs VIN > VIH or VIN < VIL, f = fMAX
10
AutomaticCEPower-Down Max. VCC, CE > VCC – 0.3V,
3
15
mA
Current —CMOS Inputs
VIN > VCC – 0.3V or VIN < 0.3V, f = 0
Capacitance[5]
Parameter
CIN
Description
Input Capacitance
Output Capacitance
Test Conditions
Max.
Unit
pF
TA = 25C, f = 1 MHz, VCC = 3.3V
8
8
COUT
pF
Thermal Resistance[5]
Parameter
JA
Description
Test Conditions
SOJ TSOP II VFBGA Unit
Thermal Resistance
(Junction to Ambient)
Still Air, soldered on a 3 × 4.5 inch,
four-layer printed circuit board
59.52
53.91
36
C/W
JC
Thermal Resistance
(Junction to Case)
36.75
21.24
9
C/W
Notes
4. V (min.) = –2.0V and V (max) = V + 1V for pulse durations of less than 5 ns.
IL
IH
CC
5. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05460 Rev. *F
Page 3 of 13
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CY7C1021DV33
AC Test Loads and Waveforms[6]
ALL INPUT PULSES
3.0V
Z = 50
90%
10%
90%
10%
OUTPUT
50
30 pF*
GND
* CAPACITIVE LOAD CONSISTS
OF ALL COMPONENTS OF THE
TEST ENVIRONMENT
1.5V
Fall Time: 1 V/ns
Rise Time: 1 V/ns
(b)
(a)
High-Z characteristics:
R 317
3.3V
OUTPUT
5 pF
R2
351
(c)
Note
6. AC characteristics (except High-Z) are tested using the load conditions shown in Figure (a). High-Z characteristics are tested for all speeds using the test load
shown in Figure (c).
Document #: 38-05460 Rev. *F
Page 4 of 13
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CY7C1021DV33
Switching Characteristics Over the Operating Range[7]
-10 (Ind’l/Auto-A)
-12 (Auto-E)
Parameter
Description
Min.
Max.
Min.
Max.
Unit
Read Cycle
[8]
tpower
VCC(typical) to the first access
Read Cycle Time
100
10
100
12
s
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tRC
tAA
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low-Z[10]
OE HIGH to High-Z[9, 10]
CE LOW to Low-Z[10]
CE HIGH to High-Z[9, 10]
CE LOW to Power-Up
CE HIGH to Power-Down
Byte Enable to Data Valid
Byte Enable to Low-Z
Byte Disable to High-Z
10
12
tOHA
tACE
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
3
3
10
5
12
6
0
3
0
0
3
0
5
5
6
6
[11]
tPU
[11]
tPD
10
5
12
6
tDBE
tLZBE
tHZBE
Write Cycle[12]
tWC
0
0
6
6
Write Cycle Time
10
8
12
9
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSCE
CE LOW to Write End
tAW
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
8
9
tHA
0
0
tSA
0
0
tPWE
tSD
7
8
Data Set-Up to Write End
Data Hold from Write End
WE HIGH to Low-Z[10]
WE LOW to High-Z[9, 10]
Byte Enable to End of Write
5
6
tHD
0
0
tLZWE
tHZWE
tBW
3
3
5
6
7
8
Notes
7. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V.
8. t
9. t
gives the minimum amount of time that the power supply should be at typical V values until the first memory access can be performed.
POWER
CC
, t
, t
, andt
are specified with a load capacitance of 5 pF as in (c) of AC Test Loads. Transitionismeasuredwhentheoutputsenterahighimpedancestate
HZOE HZBE HZCE
HZWE
10. At any given temperature and voltage condition, t
is less than t
, t
is less than t
, and t
is less than t
for any given device.
HZCE
LZCE HZOE
LZOE
HZWE
LZWE
11. This parameter is guaranteed by design and is not tested.
12. The internal Write time of the memory is defined by the overlap of CE LOW, WE LOW and BHE/BLE LOW. CE, WE and BHE/BLE must be LOW to initiate a Write
and the transition of these signals can terminate the Write. The input data set-up and hold timing should be referenced to the leading edge of the signal that
terminates the Write.
Document #: 38-05460 Rev. *F
Page 5 of 13
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CY7C1021DV33
Data Retention Characteristics Over the Operating Range
Parameter
VDR
Description
VCC for Data Retention
Conditions
Min. Max.
Unit
V
2
ICCDR
Data Retention Current
VCC = VDR = 2.0V, CE > VCC – 0.3V, Industrial
3
15
mA
mA
ns
VIN > VCC – 0.3V or VIN < 0.3V
Automotive
[5]
tCDR
Chip Deselect to Data Retention Time
Operation Recovery Time
0
[13]
tR
tRC
ns
Data Retention Waveform
DATA RETENTION MODE
3.0V
3.0V
VDR > 2V
V
CC
t
t
R
CDR
CE
Switching Waveforms
Read Cycle No. 1 (Address Transition Controlled)[14, 15]
tRC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Read Cycle No. 2 (OE Controlled)[15, 16]
ADDRESS
t
RC
CE
t
ACE
OE
t
HZOE
t
DOE
t
LZOE
BHE, BLE
t
HZCE
t
DBE
t
LZBE
t
HZBE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA OUT
DATA VALID
t
LZCE
t
PD
ICC
ISB
t
PU
VCC
SUPPLY
CURRENT
50%
50%
Notes
13. Full device operation requires linear V ramp from V to V
> 50 s or stable at V > 50 s.
CC(min.)
CC
DR
CC(min.)
14. Device is continuously selected. OE, CE, BHE and/or BLE = V .
IL
15. WE is HIGH for Read cycle.
16. Address valid prior to or coincident with CE transition LOW.
Document #: 38-05460 Rev. *F
Page 6 of 13
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CY7C1021DV33
Switching Waveforms (continued)
Write Cycle No. 1 (CE Controlled)[17, 18]
t
WC
ADDRESS
t
SA
t
SCE
CE
t
AW
t
HA
t
PWE
WE
t
BW
BHE, BLE
t
t
SD
HD
DATA I/O
Write Cycle No. 2 (BLE or BHE Controlled)
t
WC
ADDRESS
t
SA
t
BW
BHE, BLE
t
AW
t
HA
t
PWE
WE
CE
t
SCE
t
t
SD
HD
DATA I/O
Notes
17. Data I/O is high impedance if OE or BHE and/or BLE = V
.
IH
18. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
Document #: 38-05460 Rev. *F
Page 7 of 13
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CY7C1021DV33
Switching Waveforms (continued)
Write Cycle No. 3 (WE Controlled, OE LOW)
t
WC
ADDRESS
CE
t
SCE
t
AW
t
HA
t
SA
t
PWE
WE
t
BW
BHE, BLE
t
HZWE
t
t
SD
HD
DATA I/O
t
LZWE
Truth Table
CE OE WE BLE BHE
I/O0–I/O7
High-Z
I/O8–I/O15
Mode
Power
H
L
X
L
X
H
X
L
X
L
High-Z
Data Out
High-Z
Data Out
Data In
High-Z
Data In
High-Z
High-Z
Power-down
Read – All bits
Standby (ISB
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
)
Data Out
Data Out
High-Z
Data In
Data In
High-Z
High-Z
High-Z
)
L
H
L
Read – Lower bits only
Read – Upper bits only
Write – All bits
)
H
L
)
L
X
L
L
)
L
H
L
Write – Lower bits only
Write – Upper bits only
)
H
X
H
)
L
L
H
X
H
X
X
H
Selected, Outputs Disabled
Selected, Outputs Disabled
)
)
Document #: 38-05460 Rev. *F
Page 8 of 13
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CY7C1021DV33
Ordering Information
Speed
(ns)
Package
Name
Operating
Range
Package Type
Ordering Code
10
CY7C1021DV33-10VXI
CY7C1021DV33-10ZSXI
CY7C1021DV33-10BVXI
CY7C1021DV33-10ZSXA
CY7C1021DV33-12ZSXE
51-85082
51-85087
51-85150
51-85087
51-85087
44-pin (400-Mil) Molded SOJ (Pb-free)
44-pin TSOP Type II (Pb-free)
48-ball VFBGA (Pb-free)
Industrial
10
12
44-pin TSOP Type II (Pb-free)
44-pin TSOP Type II (Pb-free)
Automotive-A
Automotive-E
Ordering Code Definitions
CY 7 1 02 D V33 - XX XXX X
C
1
Temperature Range: X = I or A or E
I = Industrial; A = Automotive-A; E = Automotive-E
Package Type: XXX = VX or ZSX or BVX
VX = 44-pin Molded SOJ (Pb-free)
ZSX = 44-pin TSOP Type II (Pb-free)
BVX = 48-ball VFBGA (Pb-free)
Speed: XX = 10 ns or 12 ns
V33 = Voltage range (3 V to 3.6 V)
D = C9, 90 nm Technology
1 = Data width × 16-bits
02 = 1-Mbit density
1 = Fast Asynchronous SRAM family
Technology Code: C = CMOS
7 = SRAM
CY = Cypress
Please contact your local Cypress sales representative for availability of these parts.
Document #: 38-05460 Rev. *F
Page 9 of 13
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CY7C1021DV33
Package Diagrams
Figure 1. 44-pin (400-Mil) Molded SOJ (51-85082)
51-85082 *C
Figure 2. 44-pin Thin Small Outline Package Type II (51-85087)
51-85087 *C
Document #: 38-05460 Rev. *F
Page 10 of 13
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CY7C1021DV33
Package Diagrams (continued)
Figure 3. 48-ball VFBGA (6 x 8 x 1 mm) (51-85150)
51-85150 *F
All products and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-05460 Rev. *F
Page 11 of 13
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CY7C1021DV33
Document History Page
Document Title: CY7C1021DV33, 1-Mbit (64K x 16) Static RAM
Document Number: 38-05460
Orig. of
REV.
ECN NO. Issue Date
Description of Change
Advance Information data sheet for C9 IPP
Change
**
201560
233693
See ECN
See ECN
SWI
*A
RKF
DC parameters are modified as per Eros (Spec # 01-02165).
Pb-free Offering In Ordering Information
*B
263769
See ECN
RKF
Changed I/O1 – I/O16 to I/O0 – I/O15
Added Data Retention Characteristics table
Added Tpower Spec in Switching Characteristics table
Shaded Ordering Information
*C
*D
307601
520652
See ECN
See ECN
RKF
VKN
Reduced Speed bins to –8 and –10 ns
Converted from Preliminary to Final
Removed Commercial Operating range
Removed 8 ns speed bin
Added ICC values for the frequencies 83MHz, 66MHz and 40MHz
Added Automotive Information
Updated Thermal Resistance table
Updated Ordering Information Table
Changed Overshoot spec from VCC+2V to VCC+1V in footnote #4
*E
*F
2898399 03/24/2010
3109897 12/14/2010
AJU
AJU
Updated Package Diagrams
Added Ordering Code Definitions.
Updated Package Diagrams.
Document #: 38-05460 Rev. *F
Page 12 of 13
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CY7C1021DV33
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the
office closest to you, visit us at cypress.com/sales.
Products
Automotive
cypress.com/go/automotive
cypress.com/go/clocks
cypress.com/go/interface
cypress.com/go/powerpsoc
cypress.com/go/plc
PSoC Solutions
Clocks & Buffers
Interface
psoc.cypress.com/solutions
PSoC 1 | PSoC 3 | PSoC 5
Lighting & Power Control
Memory
cypress.com/go/memory
cypress.com/go/image
cypress.com/go/psoc
Optical & Image Sensing
PSoC
Touch Sensing
USB Controllers
Wireless/RF
cypress.com/go/touch
cypress.com/go/USB
cypress.com/go/wireless
Document #: 38-05460 Rev. *F
Page 13 of 13
© Cypress Semiconductor Corporation, 2004-2010. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the
use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to
be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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相关型号：
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