CY7C1021CV33 [CYPRESS]
64K x 16 Static RAM; 64K ×16静态RAM
| 型号： | CY7C1021CV33 |
| 厂家： | 
CYPRESS |
| 描述： | 64K x 16 Static RAM |
| 文件： | 总12页 (文件大小：233K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C1021CV33
64K x 16 Static RAM
(BLE) is LOW, then data from I/O pins (I/O1 through I/O8), is
written into the location specified on the address pins (A0
through A15). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O9 through I/O16) is written into the location
specified on the address pins (A0 through A15).
Features
• Pin- and function-compatible with CY7C1021BV33
• High speed
— tAA = 8, 10, 12, and 15 ns
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O1 to I/O8. If Byte High Enable (BHE) is
LOW, then data from memory will appear on I/O9 to I/O16. See
the truth table at the end of this data sheet for a complete
description of Read and Write modes.
• CMOS for optimum speed/power
• Low active power
— 360 mW (max.)
• Data retention at 2.0V
• Automatic power-down when deselected
• Independent control of upper and lower bits
• Available in 44-pin TSOP II, 400-mil SOJ, 48-ball FBGA
The input/output pins (I/O1 through I/O16) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE
are disabled (BHE, BLE HIGH), or during a Write operation
(CE LOW, and WE LOW).
Functional Description
The CY7C1021CV33 is a high-performance CMOS static
RAM organized as 65,536 words by 16 bits. This device has
an automatic power-down feature that significantly reduces
power consumption when deselected.
The CY7C1021CV33 is available in standard 44-pin TSOP
Type II 400-mil-wide SOJ packages, as well as a 48-ball
FBGA.
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
Logic Block Diagram
Pin Configuration
SOJ / TSOP II
DATA IN DRIVERS
Top View
44
1
A
4
A
5
43
42
41
40
39
38
A
A
2
3
4
5
6
3
6
A
A
2
7
A
A
A
7
6
5
4
OE
A
1
BHE
BLE
I/O
I/O
I/O
A
0
64K x 16
CE
A
A
A
A
I/O –I/O
RAM Array
512 X 2048
I/O
1
8
7
1
16
37
36
35
34
33
3
2
I/O
I/O
8
2
3
15
14
13
I/O –I/O
9
9
16
10
11
12
13
I/O
V
SS
I/O
1
0
4
CC
V
SS
A
V
V
CC
32
I/O
I/O
I/O
5
6
7
8
12
11
31
30
29
28
I/O
I/O
I/O
14
15
16
I/O
I/O
10
9
COLUMN DECODER
WE 17
NC
18
27
26
25
A
A
8
15
BHE
19
A
A
14
13
9
10
11
WE
CE
OE
A
20
21
22
A
A
A
12
24
23
NC
NC
BLE
Selection Guide
CY7C1021CV33-8 CY7C1021CV33-10 CY7C1021CV33-12 CY7C1021CV33-15 Unit
8
95
5
10
90
5
12
85
5
15
80
5
ns
Maximum Access Time
mA
mA
Maximum Operating Current
Maximum CMOS Standby Current
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Document #: 38-05132 Rev. *C
Revised October 30, 2002
CY7C1021CV33
Pin Configuration
48-ball FBGA
(Top View)
1
2
4
3
5
6
A
A
A
2
NC
I/O
OE
BLE
0
1
A
B
C
I/O
8
A
A
4
BHE
CE
I/O
3
0
I/O
10
A
A
6
I/O
9
I/O
1
5
2
I/O
A
I/O
11
V
CC
V
NC
NC
3
D
E
F
SS
7
NC
V
CC
V
SS
I/O
12
I/O
4
I/O
A
A
I/O
5
I/O
13
I/O
14
6
14
15
A
I/O
7
A
G
H
I/O
15
NC
WE
13
12
A
A
9
A
A
8
NC
NC
10
11
Document #: 38-05132 Rev. *C
Page 2 of 12
CY7C1021CV33
Current into Outputs (LOW)......................................... 20 mA
Maximum Ratings
Static Discharge Voltage............................................ >2001V
(per MIL-STD-883, Method 3015)
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Latch-up Current......................................................>200 mA
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Operating Range
Range
Commercial
Industrial
Ambient Temperature
0°C to +70°C
VCC
Supply Voltage on VCC to Relative GND[1] .... –0.5V to +4.6V
3.3V ± 10%
3.3V ± 10%
DC Voltage Applied to Outputs
in High-Z State[1] ......................................–0.5V to VCC+0.5V
–40°C to +85°C
DC Input Voltage[1]...................................–0.5V to VCC+0.5V
Electrical Characteristics Over the Operating Range
1021CV33-8 1021CV33-10 1021CV33-12 1021CV33-15
Min. Max. Min. Max. Min. Max. Min. Max. Unit
Test
Parameter
Description
Output HIGH
Voltage
Conditions
VOH
VCC = Min.,
OH = –4.0 mA
2.4
2.4
2.4
2.4
V
V
V
V
I
VOL
VIH
VIL
Output LOW
Voltage
VCC = Min.,
IOL = 8.0 mA
0.4
0.4
0.4
0.4
Input HIGH Voltage
2.0
VCC
+ 0.3
2.0
VCC
+ 0.3
2.0
VCC
+ 0.3
2.0
VCC
+ 0.3
Input LOW
Voltage[1]
–0.3
0.8
−0.3
0.8
–0.3
0.8
–0.3
0.8
IIX
Input Load Current GND < VI < VCC
−1
−1
+1
+1
−1
−1
+1
+1
–1
–1
+1
+1
–1
–1
+1
+1
µA
µA
IOZ
Output Leakage
Current
GND < VI < VCC
Output Disabled
,
IOS
ICC
Output Short Circuit VCC = Max.,
-300
95
−300
–300
–300 mA
Current[2]
VOUT = GND
VCC Operating
Supply Current
VCC = Max.,
IOUT = 0 mA,
f = fMAX = 1/tRC
90
85
80
15
mA
mA
ISB1
Automatic CE
Power-Down
Current —TTL
Inputs
Max. VCC, CE > VIH
VIN > VIH or
VIN < VIL,
15
5
15
5
15
5
f = fMAX
ISB2
Automatic CE
Power-Down
Current —CMOS
Inputs
Max. VCC
CE > VCC – 0.3V, VIN
VCC – 0.3V,
or VIN < 0.3V, f = 0
,
5
mA
>
Capacitance[3]
Parameter
Description
Test Conditions
Max.
Unit
pF
CIN
Input Capacitance
Output Capacitance
TA = 25°C, f = 1 MHz,
VCC = 3.3V
8
8
COUT
pF
Notes:
1.
VIL (min.) = –2.0V for pulse durations of less than 20 ns.
2. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
3. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05132 Rev. *C
Page 3 of 12
CY7C1021CV33
AC Test Loads and Waveforms[4]
10-, 12-, 15-ns devices:
8-ns devices:
R 317Ω
Z = 50
Ω
3.3V
OUTPUT
OUTPUT
30 pF
50Ω
30 pF*
R2
351Ω
* CAPACITIVE LOAD CONSISTS
OF ALL COMPONENTS OF THE
TEST ENVIRONMENT
1.5V
(b)
(a)
High-Z characteristics:
R 317Ω
3.3V
OUTPUT
5 pF
ALL INPUT PULSES
3.0V
90%
10%
90%
10%
R2
GND
351Ω
(c)
Fall Time: 1 V/ns
Rise Time: 1 V/ns
(d)
Note:
4. AC characteristics (except High-Z) for all 8-ns parts are tested using the load conditions shown in Figure (a). All other speeds are tested using the Thevenin
load shown in Figure (b). High-Z characteristics are tested for all speeds using the test load shown in Figure (d).
Document #: 38-05132 Rev. *C
Page 4 of 12
CY7C1021CV33
Switching Characteristics Over the Operating Range[5]
1021CV33-8
1021CV33-10 1021CV33-12 1021CV33-15
Parameter
Read Cycle
tRC
Description
Min.
Max.
Min.
Max.
Min.
12
3
Max.
Min.
15
3
Max. Unit
Read Cycle Time
8
3
10
ns
tAA
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low-Z[6]
OE HIGH to High-Z[6, 7]
CE LOW to Low-Z[6]
CE HIGH to High-Z[6, 7]
CE LOW to Power-Up
CE HIGH to Power-Down
Byte Enable to Data Valid
Byte Enable to Low-Z
Byte Disable to High-Z
8
10
12
15
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tOHA
3
tACE
8
5
10
5
12
6
15
7
tDOE
tLZOE
0
3
0
0
3
0
0
3
0
0
3
0
tHZOE
tLZCE
4
4
5
5
6
6
7
7
tHZCE
[8]
tPU
[8]
tPD
8
5
10
5
12
6
15
7
tDBE
tLZBE
tHZBE
Write Cycle[9]
tWC
0
0
0
0
4
5
6
7
Write Cycle Time
8
7
7
0
0
6
5
0
3
10
8
12
9
15
10
10
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSCE
CE LOW to Write End
tAW
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
8
9
tHA
0
0
tSA
0
0
0
tPWE
tSD
7
8
10
8
Data Set-Up to Write End
Data Hold from Write End
WE HIGH to Low-Z[6]
5
6
tHD
0
0
0
tLZWE
tHZWE
3
3
3
WE LOW to High-Z[6, 7]
4
5
6
7
tBW
Byte Enable to End of Write
6
7
8
9
Notes:
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V.
6. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
7. tHZOE, tHZBE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (d) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
8. This parameter is guaranteed by design and is not tested.
9. The internal Write time of the memory is defined by the overlap of CE LOW, WE LOW and BHE/BLE LOW. CE, WE and BHE/BLE must be LOW to initiate a Write,
and the transition of these signals can terminate the Write. The input data set-up and hold timing should be referenced to theleading edge of the signal that terminates the Write.
Document #: 38-05132 Rev. *C
Page 5 of 12
CY7C1021CV33
Switching Waveforms
Read Cycle No. 1[10, 11]
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
[11, 12]
(OEControlled)
Read Cycle No. 2
ADDRESS
t
RC
CE
t
ACE
OE
t
HZOE
t
DOE
BHE, BLE
t
LZOE
t
HZCE
t
DBE
t
LZBE
t
HZBE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA OUT
DATA VALID
t
LZCE
t
PD
I
t
CC
PU
V
CC
50%
50%
SUPPLY
CURRENT
I
SB
Notes:
10. Device is continuously selected. OE, CE, BHE and/or BHE = VIL.
11. WE is HIGH for Read cycle.
12. Address valid prior to or coincident with CE transition LOW.
Document #: 38-05132 Rev. *C
Page 6 of 12
CY7C1021CV33
Switching Waveforms (continued)
Write Cycle No. 1 (CE Controlled) [13, 14]
t
WC
ADDRESS
t
SA
t
SCE
CE
t
AW
t
HA
t
PWE
WE
t
BW
BHE, BLE
t
t
SD
HD
DATA I/O
Write Cycle No. 2 (BLEor BHE Controlled)
t
WC
ADDRESS
t
t
BW
SA
BHE, BLE
t
AW
t
HA
t
PWE
WE
CE
t
SCE
t
t
SD
HD
DATA I/O
Notes:
13. Data I/O is high impedance if OE or BHE and/or BLE= VIH
.
14. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
Document #: 38-05132 Rev. *C
Page 7 of 12
CY7C1021CV33
Switching Waveforms (continued)
Write Cycle No. 3
Controlled, LOW)
(WE
t
WC
ADDRESS
t
SCE
CE
t
AW
t
HA
t
SA
t
PWE
WE
t
BW
BHE, BLE
t
HZWE
t
t
SD
HD
DATA I/O
t
LZWE
Truth Table
CE OE WE BLE BHE
I/O1–I/O8
High-Z
I/O9–I/O16
High-Z
Mode
Power
H
L
X
L
X
H
X
L
X
L
Power-down
Read – All bits
Standby (ISB
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
)
Data Out
Data Out
High-Z
Data Out
High-Z
)
L
H
L
Read – Lower bits only
Read – Upper bits only
Write – All bits
)
H
L
Data Out
Data In
High-Z
)
L
X
L
L
Data In
Data In
High-Z
)
L
H
L
Write – Lower bits only
Write – Upper bits only
)
H
X
H
Data In
High-Z
)
L
L
H
X
H
X
X
H
High-Z
Selected, Outputs Disabled
Selected, Outputs Disabled
)
High-Z
High-Z
)
Document #: 38-05132 Rev. *C
Page 8 of 12
CY7C1021CV33
Ordering Information
Speed
Package
Name
Operating
Range
(ns)
Ordering Code
Package Type
44-lead (400-Mil) Molded SOJ
44-lead TSOP Type II
8
CY7C1021CV33-8VC
CY7C1021CV33-8ZC
CY7C1021CV33-8BAC
CY7C1021CV33-10VC
CY7C1021CV33-10VI
CY7C1021CV33-10ZC
CY7C1021CV33-10ZI
CY7C1021CV33-10BAC
CY7C1021CV33-10BAI
CY7C1021CV33-12VC
CY7C1021CV33-12VI
CY7C1021CV33-12ZC
CY7C1021CV33-12ZI
CY7C1021CV33-12BAC
CY7C1021CV33-12BAI
CY7C1021CV33-15VC
CY7C1021CV33-15VI
CY7C1021CV33-15ZC
CY7C1021CV33-15ZI
CY7C1021CV33-15BAC
CY7C1021CV33-15BAI
V34
Z44
Commercial
BA48A
V34
48-ball FBGA
10
12
15
44-lead (400-Mil) Molded SOJ
Commercial
Industrial
Z44
BA48A
V34
44-lead TSOP Type II
48-ball FBGA
Commercial
Industrial
Commercial
Industrial
44-lead (400-Mil) Molded SOJ
44-lead TSOP Type II
48-ball FBGA
Commercial
Industrial
Z44
Commercial
Industrial
BA48A
V34
Commercial
Industrial
44-lead (400-Mil) Molded SOJ
44-lead TSOP Type II
48-ball FBGA
Commercial
Industrial
Z44
Commercial
Industrial
BA48A
Commercial
Industrial
Document #: 38-05132 Rev. *C
Page 9 of 12
CY7C1021CV33
Package Diagrams
48-Ball (7.00 mm x 7.00 mm x 1.2 mm) FBGA BA48A
51-85096-*E
Document #: 38-05132 Rev. *C
Page 10 of 12
CY7C1021CV33
Package Diagrams (continued)
44-Lead (400-Mil) Molded SOJ V34
51-85082-*B
44-pin TSOP II Z44
51-85087-*A
All products and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-05132 Rev. *C
Page 11 of 12
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C1021CV33
Document History Page
Document Title: CY7C1021CV33 64K x 16 Static RAM
Document Number: 38-05132
Issue
Date
Orig. of
Change
REV.
**
ECN NO.
109472
115044
Description of Change
12/06/01
05/08/02
HGK
HGK
New Data Sheet
*A
Ram7 version C4K x 16 Async.
Remove “Preliminary”
*B
*C
115808
120413
06/25/02
10/31/02
HGK
DFP
ISB1 and ICC values changed
Updated BGA pin E4 to NC.
Document #: 38-05132 Rev. *C
Page 12 of 12
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CYPRESS
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