CY7C0832AV [CYPRESS]
FLEx18⑩ 3.3V 64K/128K x 36 and 128K/256K x 18 Synchronous Dual-Port RAM; FLEx18⑩ 3.3V 64K / 128K ×36和128K / 256K ×18同步双端口RAM
| 型号： | CY7C0832AV |
| 厂家： | 
CYPRESS |
| 描述： | FLEx18⑩ 3.3V 64K/128K x 36 and 128K/256K x 18 Synchronous Dual-Port RAM |
| 文件： | 总28页 (文件大小：821K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C093794V CY7C093894V CY7C09289V CY7C09369V CY7C09379V CY7C09389VFLEx18™ 3.3V 64K/128K
x 36 and 128K/256K x 18
Synchronous Dual-Port RAM
CY7C0837AV
CY7C0830AV/CY7C0831AV
CY7C0832AV/CY7C0833AV
FLEx18™3.3V64K/128Kx36and128K/256Kx18
Synchronous Dual-Port RAM
Functional Description
Features
• True dual-ported memory cells that allow simultaneous
The FLEx18™ family includes 512-Kbit, 1-Mbit, 2-Mbit, 4-Mbit
and 9-Mbit pipelined, synchronous, true dual-port static RAMs
that are high-speed, low-power 3.3V CMOS. Two ports are
provided, permitting independent, simultaneous access to any
location in memory. The result of writing to the same location
by more than one port at the same time is undefined. Registers
on control, address, and data lines allow for minimal set-up
and hold time.
During a Read operation, data is registered for decreased
cycle time. Each port contains a burst counter on the input
address register. After externally loading the counter with the
initial address, the counter will increment the address inter-
nally (more details to follow). The internal Write pulse width is
independent of the duration of the R/W input signal. The
internal Write pulse is self-timed to allow the shortest possible
cycle times.
A HIGH on CE0 or LOW on CE1 for one clock cycle will power
down the internal circuitry to reduce the static power
consumption. One cycle with chip enables asserted is required
to reactivate the outputs.
Additional features include: readback of burst-counter internal
address value on address lines, counter-mask registers to
control the counter wrap-around, counter interrupt (CNTINT)
flags, readback of mask register value on address lines,
retransmit functionality, interrupt flags for message passing,
JTAG for boundary scan, and asynchronous Master Reset
(MRST).
access of the same memory location
• Synchronous pipelined operation
• Family of 512-Kbit, 1-Mbit, 2-Mbit, 4-Mbit and 9-Mbit
devices
• Pipelined output mode allows fast operation
• 0.18-micron CMOS for optimum speed and power
• High-speed clock to data access
• 3.3V low power
— Active as low as 225 mA (typ)
— Standby as low as 55 mA (typ)
• Mailbox function for message passing
• Global master reset
• Separate byte enables on both ports
• Commercial and industrial temperature ranges
• IEEE 1149.1-compatible JTAG boundary scan
• 144-ball FBGA (13 mm × 13 mm) (1.0 mm pitch)
• 120TQFP (14 mm x 14 mm x 1.4 mm)
• Lead(Pb)-free packages available
• Counter wrap around control
— Internal mask register controls counter wrap-around
— Counter-interrupt flags to indicate wrap-around
— Memory block retransmit operation
• Counter readback on address lines
• Mask register readback on address lines
The CY7C0833AV device in this family has limited features.
Please see Address Counter and Mask Register
Operations[15] on page 6 for details.
• Dual Chip Enables on both ports for easy depth
expansion
Table 1. Product Selection Guide
Density
512-Kbit
1-Mbit
2-Mbit
4-Mbit
9-Mbit
(32K x 18)
(64K x 18)
(128K x 18)
(256K x 18)
(512K x 18)
Part Number
CY7C0837AV CY7C0830AV CY7C0831AV CY7C0832AV CY7C0833AV
Max. Speed (MHz)
167
4.0
225
167
4.0
225
167
4.0
225
167
4.0
225
133
4.7
270
Max. Access Time - clock to Data (ns)
Typical operating current (mA)
Package
144 FBGA
120 TQFP
120 TQFP
120 TQFP
144 FBGA
144 FBGA
144 FBGA
144 FBGA
Cypress Semiconductor Corporation
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Document #: 38-06059 Rev. *Q
Revised May 10, 2006
[+] Feedback
CY7C0837AV
CY7C0830AV/CY7C0831AV
CY7C0832AV/CY7C0833AV
Logic Block Diagram[1]
OE
OE
R/W
L
R
R
R/W
L
B0
B1
B0
B1
L
L
R
R
CE
CE
CE
CE
0L
1L
0R
1R
I/O
I/O
9
9
9
9
DQ –DQ
Control
Control
DQ –DQ
9L
17L
8L
9R
17R
DQ –DQ
DQ –DQ
0L
0R
8R
Addr.
Read
Back
Addr.
Read
Back
True
Dual-Ported
RAM Array
19
19
A0L–A18L
A0R–A18R
CNT/MSKR
Mask Register
Mask Register
CNT/MSKL
ADS
CNTEN
ADSL
Counter/
Address
Register
Counter/
Address
Register
Address
Decode
Address
Decode
CNTENL
CNTRSTR
CLKR
CNTINTR
CNTRSTL
CLKL
CNTINTL
Mirror Reg
Mirror Reg
TMS
TDI
TCK
Reset
Logic
Interrupt
Logic
Interrupt
Logic
JTAG
TDO
MRST
INTL
INTR
Note:
1. CY7C0837AV has 15 address CY7C0830AV has 16 address bits, CY7C0831AV has 17 address bits, CY7C0832AV has 18 address bits and CY7C0833AV has
19 address bits.
Document #: 38-06059 Rev. *Q
Page 2 of 28
[+] Feedback
CY7C0837AV
CY7C0830AV/CY7C0831AV
CY7C0832AV/CY7C0833AV
Pin Configurations
144-ball BGA
Top View
CY7C0837AV / CY7C0830AV / CY7C0831AV
CY7C0832AV / CY7C0833AV
1
2
3
4
5
6
7
8
9
10
11
12
A
B
C
D
E
F
DQ17
DQ16
DQ14
DQ12
DQ10
DQ9
DQ9
DQ10
DQ12
DQ14
DQ16
DQ17
R
L
L
L
L
L
L
L
R
R
R
R
R
A0
L
A1
L
DQ15
CE1
DQ13
DQ11
MRST
NC
DQ11
DQ13
INT
DQ15
CE1
A1
R
A0
R
L
L
R
R
R
ADS
L
ADS
[7]
CNTINTL
[8]
CNTINTR
[8]
L
R
R
A2
L
A3
L
INT
L
A3
R
A2
R
R
[6]
[7]
[6]
CE0
[7]
CE0
[7]
L
R
A4
L
A5
L
NC
NC
VDD
VDD
VSS
VSS
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VDD
TMS
VDD
VDD
VSS
VSS
VDD
VDD
NC
A5
R
A4
R
A6
L
A7
L
B1
VSS
VSS
VSS
VSS
VDD
TCK
NC
NC
B1
A7
R
A6
R
L
L
R
A8
L
A9
L
C
NC
C
A9
R
A8
R
L
R
A10
A11
L
B0
NC
NC
B0
A11
A10
R
G
H
J
L
L
R
R
A12
A14
A13
OE
NC
NC
OE
A13
A12
A14
L
L
L
R
R
R
R
A15
[2]
A15
[2]
RW
NC
NC
RW
R
L
L
L
R
R
A16
[3]
A17
[4]
A17
[4]
A16
[3]
CNT/MSKL
[6]
CNTRSTL
[6]
CNTRSTR
[6]
CNT/MSKR
[6]
L
R
TDO
DQ4
TDI
DQ4
K
L
A18
[5]
A18
[5]
CNTENL
[7]
CNTENR
[7]
L
R
NC
DQ6
L
DQ2
L
DQ2
R
DQ6
R
NC
L
R
M
DQ8
DQ7
DQ5
L
DQ3
DQ1
L
DQ0
L
DQ0
R
DQ1
R
DQ3
DQ5
R
DQ7
DQ8
R
L
L
L
R
R
Notes:
2. Leave this ball unconnected for CY7C0837AV.
3. Leave this ball unconnected for CY7C0837AV and CY7C0830AV.
4. Leave this ball unconnected for CY7C0837AV, CY7C0830AV and CY7C0831AV.
5. Leave this ball unconnected for CY7C0837AV, CY7C0830AV, CY7C0831AV and CY7C0832AV.
6. These balls are not applicable for CY7C0833AV device. They need to be tied to VDD.
7. These balls are not applicable for CY7C0833AV device. They need to be tied to VSS.
8. These balls are not applicable for CY7C0833AV device. They need to be no connected.
Document #: 38-06059 Rev. *Q
Page 3 of 28
[+] Feedback
CY7C0837AV
CY7C0830AV/CY7C0831AV
CY7C0832AV/CY7C0833AV
Pin Configurations (continued)
120-pin Thin Quad Flat Pack (TQFP)
Top View
CY7C0830AV / CY7C0831AV / CY7C0832AV
A
A
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
2L
1
A
A
V
V
A
A
A
A
2R
3R
3L
2
V
V
SS
3
SS
DD
4R
5R
6R
7R
DD
4
A
A
A
A
CE
B
4L
5L
6L
5
6
7
8
9
10
11
12
13
7L
1L
0L
1L
CE
1R
B
B
0R
1R
B
OE
L
OE
CE
R
CE
V
0L
0R
DD
14
15
V
V
DD
SS
R/W
V
SS
R/W
CLK
16
17
18
19
20
21
22
23
24
L
L
R
CLK
MRST
ADS
CNTEN
CNTRST
CNT/MSK
R
V
SS
ADS
CNTEN
CNTRST
L
L
L
L
8L
9L
R
R
R
R
CNT/MSK
A
A
A
A
8R
9R
A
A
A
10L
11L
12L
25
26
27
28
29
30
A
A
A
V
V
A
10R
11R
12R
SS
V
SS
DD
13L
V
A
DD
13R
Notes:
9. Leave this pin unconnected for CY7C0830AV.
10. Leave this pin unconnected for CY7C0830AV and CY7C0831AV.
Document #: 38-06059 Rev. *Q
Page 4 of 28
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CY7C0837AV
CY7C0830AV/CY7C0831AV
CY7C0832AV/CY7C0833AV
Pin Definitions
Left Port
Right Port
Description
[1]
[1]
A0L–A18L
A0R–A18R
Address Inputs.
[7]
[7]
ADSL
ADSR
Address Strobe Input. Used as an address qualifier. This signal should be asserted LOW
for the part using the externally supplied address on the address pins and for loading this
address into the burst address counter.
[7]
[7]
CE0L
CE1L
CE0R
CE1R
Active LOW Chip Enable Input.
Active HIGH Chip Enable Input.
[6]
[6]
CLKL
CNTENL
CLKR
CNTENR
Clock Signal. Maximum clock input rate is fMAX.
Counter Enable Input. Asserting this signal LOW increments the burst address counter of
its respective port on each rising edge of CLK. The increment is disabled if ADS or CNTRST
are asserted LOW.
Counter Reset Input. Asserting this signal LOW resets to zero the unmasked portion of
the burst address counter of its respective port. CNTRST is not disabled by asserting ADS
or CNTEN.
Address Counter Mask Register Enable Input. Asserting this signal LOW enables access
to the mask register. When tied HIGH, the mask register is not accessible and the address
counter operations are enabled based on the status of the counter control signals.
[7]
[7]
[6]
[6]
CNTRSTL
CNTRSTR
[6]
[6]
CNT/MSKL
CNT/MSKR
[1]
[1]
DQ0L–DQ17L
OEL
DQ0R–DQ17R
OER
Data Bus Input/Output.
Output Enable Input. This asynchronous signal must be asserted LOW to enable the DQ
data pins during Read operations.
INTL
INTR
Mailbox Interrupt Flag Output. The mailbox permits communications between ports. The
upper two memory locations can be used for message passing. INTL is asserted LOW when
the right port writes to the mailbox location of the left port, and vice versa. An interrupt to a
port is deasserted HIGH when it reads the contents of its mailbox.
[8]
[8]
CNTINTL
CNTINTR
Counter Interrupt Output. This pin is asserted LOW when the unmasked portion of the
counter is incremented to all “1s.”
R/WL
R/WR
Read/Write Enable Input. Assert this pin LOW to write to, or HIGH to Read from the dual
port memory array.
B0L–B1L
B0R–B1R
Byte Select Inputs. Asserting these signals enables Read and Write operations to the
corresponding bytes of the memory array.
MRST
TMS
Master Reset Input. MRST is an asynchronous input signal and affects both ports.
Asserting MRST LOW performs all of the reset functions as described in the text. A MRST
operation is required at power-up.
JTAG Test Mode Select Input. It controls the advance of JTAG TAP state machine. State
machine transitions occur on the rising edge of TCK.
TDI
TCK
TDO
JTAG Test Data Input. Data on the TDI input will be shifted serially into selected registers.
JTAG Test Clock Input.
JTAG Test Data Output. TDO transitions occur on the falling edge of TCK. TDO is normally
three-stated except when captured data is shifted out of the JTAG TAP.
VSS
VDD
Ground Inputs.
Power Inputs.
Byte Select Operation
Control Pin
Effect
B0
B1
DQ0–8 Byte Control
DQ9–17 Byte Control
Document #: 38-06059 Rev. *Q
Page 5 of 28
[+] Feedback
CY7C0837AV
CY7C0830AV/CY7C0831AV
CY7C0832AV/CY7C0833AV
The counter register contains the address used to access the
RAM array. It is changed only by the Counter Load, Increment,
Counter Reset, and by master reset (MRST) operations.
Master Reset
The FLEx18 family devices undergo a complete reset by
taking its MRST input LOW. The MRST input can switch
asynchronously to the clocks. An MRST initializes the internal
burst counters to zero, and the counter mask registers to all
ones (completely unmasked). MRST also forces the Mailbox
Interrupt (INT) flags and the Counter Interrupt (CNTINT) flags
HIGH. MRST must be performed on the FLEx18 family
devices after power-up.
The mask register value affects the Increment and Counter
Reset operations by preventing the corresponding bits of the
counter register from changing. It also affects the counter
interrupt output (CNTINT). The mask register is changed only
by the Mask Load and Mask Reset operations, and by the
MRST. The mask register defines the counting range of the
counter register. It divides the counter register into two
regions: zero or more “0s” in the most significant bits define
the masked region, one or more “1s” in the least significant bits
define the unmasked region. Bit 0 may also be “0,” masking
the least significant counter bit and causing the counter to
increment by two instead of one.
The mirror register is used to reload the counter register on
increment operations (see “retransmit,” below). It always
contains the value last loaded into the counter register, and is
changed only by the Counter Load, and by the MRST instruc-
tions. Table 3 summarizes the operation of these registers and
the required input control signals. The MRST control signal is
asynchronous. All the other control signals in Table 3
(CNT/MSK, CNTRST, ADS, CNTEN) are synchronized to the
port’s CLK. All these counter and mask operations are
independent of the port’s chip enable inputs (CE0 and CE1).
Counter enable (CNTEN) inputs are provided to stall the
operation of the address input and utilize the internal address
generated by the internal counter for fast, interleaved memory
applications. A port’s burst counter is loaded when the port’s
address strobe (ADS) and CNTEN signals are LOW. When the
port’s CNTEN is asserted and the ADS is deasserted, the
address counter will increment on each LOW to HIGH
transition of that port’s clock signal. This will Read/Write one
word from/into each successive address location until CNTEN
s deasserted. The counter can address the entire memory
array, and will loop back to the start. Counter reset (CNTRST)
is used to reset the unmasked portion of the burst counter to
i0s. A counter-mask register is used to control the counter
wrap.
Mailbox Interrupts
The upper two memory locations may be used for message
passing and permit communications between ports. Table 2
shows the interrupt operation for both ports of CY7C0833AV.
The highest memory location, 7FFFF is the mailbox for the
right port and 7FFFE is the mailbox for the left port. Table 2
shows that in order to set the INTR flag, a Write operation by
the left port to address 7FFFF will assert INTR LOW. At least
one byte has to be active for a Write to generate an interrupt.
A valid Read of the 7FFFF location by the right port will reset
INTR HIGH. At least one byte has to be active in order for a
Read to reset the interrupt. When one port Writes to the other
port’s mailbox, the INT of the port that the mailbox belongs to
is asserted LOW. The INT is reset when the owner (port) of the
mailbox Reads the contents of the mailbox. The interrupt flag
is set in a flow-thru mode (i.e., it follows the clock edge of the
writing port). Also, the flag is reset in a flow-thru mode (i.e., it
follows the clock edge of the reading port).
Each port can read the other port’s mailbox without resetting
the interrupt. And each port can write to its own mailbox
without setting the interrupt. If an application does not require
message passing, INT pins should be left open.
Address Counter and Mask Register Operations[15]
This section describes the features only apply to
512Kbit,1Mbit, 2Mbit, and 4Mbit devices. It does not apply to
9Mbit device. Each port of these devices has a programmable
burst address counter. The burst counter contains three
registers: a counter register, a mask register, and a mirror
register.
Table 2. Interrupt Operation Example [1, 11, 12, 13, 14, 16]
FUNCTION
LEFT PORT
RIGHT PORT
R/WL
CEL
L
X
X
L
A0L–A18L
3FFFF
X
INTL
X
X
L
H
R/WR
CER
X
L
L
X
A0R–A18R
INTR
Set Right INTR Flag
Reset Right INTR Flag
Set Left INTL Flag
Reset Left INTL Flag
Set Right INTR Flag
L
X
X
H
L
X
H
L
X
X
X
3FFFF
3FFFE
X
L
H
X
X
L
X
3FFFE
3FFFF
L
X
X
X
Notes:
11. CE is internal signal. CE = LOW if CE = LOW and CE = HIGH. For a single Read operation, CE only needs to be asserted once at the rising edge of the CLK
0
1
and can be deasserted after that. Data will be out after the following CLK edge and will be three-stated after the next CLK edge.
12. OE is “Don’t Care” for mailbox operation.
13. At least one of BE0, BE1 must be LOW.
14. A18x is a NC for CY7C0832AV, therefore the Interrupt Addresses are 3FFFF and 3FFFE. A18x and A17x are NC for CY7C0831AV, therefore the Interrupt
addresses are 1FFFF and 1FFFE; A18x, A17x and A16x are NC for CY7C0830AV, therefore the Interrupt Addresses are FFFF and FFFE;A18x, A17x, A16x
and A15x are NC for CY7C0837AV, therefore the Interrupt Addresses are 7FFF and 7FFE.
15. This section describes the CY7C0832AV, CY7C0831AV, CY7C0830AV and CY7C0837AV having 18, 17, 16 and 15 address bits.
16. “X” = “Don’t Care,” “H” = HIGH, “L” = LOW.
Document #: 38-06059 Rev. *Q
Page 6 of 28
[+] Feedback
CY7C0837AV
CY7C0830AV/CY7C0831AV
CY7C0832AV/CY7C0833AV
Counter Reset Operation
memory space. The address counter is then loaded with an
initial value of 8h. The base address bits (in this case, the 6th
address through the 16th address) are loaded with an address
value but do not increment once the counter is configured for
increment operation. The counter address will start at address
8h. The counter will increment its internal address value till it
reaches the mask register value of 3Fh. The counter wraps
around the memory block to location 8h at the next count.
CNTINT is issued when the counter reaches its maximum
value
All unmasked bits of the counter are reset to “0.” All masked
bits remain unchanged. The mirror register is loaded with the
value of the burst counter. A Mask Reset followed by a Counter
Reset will reset the counter and mirror registers to 00000, as
will master reset (MRST).
Counter Load Operation
The address counter and mirror registers are both loaded with
the address value presented at the address lines.
Counter Hold Operation
Counter Increment Operation
The value of all three registers can be constantly maintained
unchanged for an unlimited number of clock cycles. Such
operation is useful in applications where wait states are
needed, or when address is available a few cycles ahead of
data in a shared bus interface.
Once the address counter register is initially loaded with an
external address, the counter can internally increment the
address value, potentially addressing the entire memory array.
Only the unmasked bits of the counter register are incre-
mented. The corresponding bit in the mask register must be
a “1” for a counter bit to change. The counter register is incre-
mented by 1 if the least significant bit is unmasked, and by 2
if it is masked. If all unmasked bits are “1,” the next increment
will wrap the counter back to the initially loaded value. If an
Increment results in all the unmasked bits of the counter being
“1s,” a counter interrupt flag (CNTINT) is asserted. The next
Increment will return the counter register to its initial value,
which was stored in the mirror register. The counter address
can instead be forced to loop to 00000 by externally
connecting CNTINT to CNTRST.[18] An increment that results
in one or more of the unmasked bits of the counter being “0”
will deassert the counter interrupt flag. The example in
Figure 2 shows the counter mask register loaded with a mask
value of 0003Fh unmasking the first 6 bits with bit “0” as the
LSB and bit “16” as the MSB. The maximum value the mask
register can be loaded with is 3FFFFh. Setting the mask
register to this value allows the counter to access the entire
Counter Interrupt
The counter interrupt (CNTINT) is asserted LOW when an
increment operation results in the unmasked portion of the
counter register being all “1s.” It is deasserted HIGH when an
Increment operation results in any other value. It is also
de-asserted by Counter Reset, Counter Load, Mask Reset
and Mask Load operations, and by MRST.
Counter Readback Operation
The internal value of the counter register can be read out on
the address lines. Readback is pipelined; the address will be
valid tCA2 after the next rising edge of the port’s clock. If
address readback occurs while the port is enabled (CE0 LOW
and CE1 HIGH), the data lines (DQs) will be three-stated.
Figure 1 shows a block diagram of the operation.
Table 3. Address Counter and Counter-Mask Register Control Operation (Any Port)[16, 17]
CLK MRST CNT/MSK CNTRST
ADS CNTEN
Operation
Description
X
L
X
X
X
X
Master Reset
Reset address counter to all 0s and mask
register to all 1s.
H
H
H
H
L
X
L
X
L
Counter Reset
Counter Load
Reset counter unmasked portion to all 0s.
H
Load counter with external address value
presented on address lines.
H
H
H
L
H
Counter
Read out counter internal value on address
lines.
Readback
H
H
H
H
H
H
H
H
L
Counter Increment Internally increment address counter value.
H
Counter Hold
Constantly hold the address value for
multiple clock cycles.
H
H
L
L
L
X
L
X
L
Mask Reset
Mask Load
Reset mask register to all 1s.
H
Load mask register with value presented on
the address lines.
H
H
L
L
H
H
L
H
X
Mask Readback
Reserved
Read out mask register value on address
lines.
Operation undefined
H
Notes:
17. Counter operation and mask register operation is independent of chip enables.
18. CNTINT and CNTRST specs are guaranteed by design to operate properly at speed grade operating frequency when tied together.
Document #: 38-06059 Rev. *Q
Page 7 of 28
[+] Feedback
CY7C0837AV
CY7C0830AV/CY7C0831AV
CY7C0832AV/CY7C0833AV
Retransmit
operations. Permitted values are of the form 2n – 1 or 2n – 2.
From the most significant bit to the least significant bit,
permitted values have zero or more “0s,” one or more “1s,” or
one “0.” Thus 3FFFF, 003FE, and 00001 are permitted values,
but 3F0FF, 003FC, and 00000 are not.
Retransmit is a feature that allows the Read of a block of
memory more than once without the need to reload the initial
address. This eliminates the need for external logic to store
and route data. It also reduces the complexity of the system
design and saves board space. An internal “mirror register” is
used to store the initially loaded address counter value. When
the counter unmasked portion reaches its maximum value set
by the mask register, it wraps back to the initial value stored in
this “mirror register.” If the counter is continuously configured
in increment mode, it increments again to its maximum value
and wraps back to the value initially stored into the “mirror
register.” Thus, the repeated access of the same data is
allowed without the need for any external logic.
Mask Readback Operation
The internal value of the mask register can be read out on the
address lines. Readback is pipelined; the address will be valid
tCM2 after the next rising edge of the port’s clock. If mask
readback occurs while the port is enabled (CE0 LOW and CE1
HIGH), the data lines (DQs) will be three-stated. Figure 1
shows a block diagram of the operation.
Counting by Two
Mask Reset Operation
The mask register is reset to all “1s,” which unmasks every bit
of the counter. Master reset (MRST) also resets the mask
register to all “1s.”
When the least significant bit of the mask register is “0,” the
counter increments by two. This may be used to connect the
x18 devices as a 36-bit single port SRAM in which the counter
of one port counts even addresses and the counter of the other
port counts odd addresses. This even-odd address scheme
stores one half of the 36-bit data in even memory locations,
and the other half in odd memory locations.
Mask Load Operation
The mask register is loaded with the address value presented
at the address lines. Not all values permit correct increment
Document #: 38-06059 Rev. *Q
Page 8 of 28
[+] Feedback
CY7C0837AV
CY7C0830AV/CY7C0831AV
CY7C0832AV/CY7C0833AV
CNT/MSK
CNTEN
ADS
Decode
Logic
CNTRST
MRST
Bidirectional
Address
Lines
Mask
Register
Counter/
Address
Register
Address
Decode
RAM
Array
CLK
Load/Increment
17
17
From
Address
Lines
Mirror
Counter
To Readback
and Address
Decode
1
0
1
0
From
Increment
Logic
Mask
17
Wrap
Register
17
17
17
Bit 0
From
Mask
From
Counter
+1
+2
Wrap
Wrap
To
1
0
Detect
17
1
0
Counter
Figure 1. Counter, Mask, and Mirror Logic Block Diagram[1]
Document #: 38-06059 Rev. *Q
Page 9 of 28
[+] Feedback
CY7C0837AV
CY7C0830AV/CY7C0831AV
CY7C0832AV/CY7C0833AV
CNTINT
H
Example:
Load
Counter-Mask
Register = 3F
0
0
0s
0
1
1
1
1
1
1
216 215
26 25 24 23 22 21 20
Unmasked Address
Mask
Register
bit-0
Masked Address
Load
Address
Counter = 8
H
L
X
X
Xs
Xs
Xs
X
0
0
1
0
0
0
216 215
26 25 24 23 22 21 20
Address
Counter
bit-0
Max
Address
Register
X
X
X
1
1
1
1 1
1
216 215
26 25 24 23 22 21 20
Max + 1
Address
Register
H
X
X
X
0
0
1
0
0
0
216 215
26 25 24 23 22 21 20
Figure 2. Programmable Counter-Mask Register Operation[1, 19]
IEEE 1149.1 Serial Boundary Scan (JTAG)[20]
Boundary Scan Hierarchy for 9-Mbit Device
Internally, the CY7C0833AV have two DIEs. Each DIE contain
all the circuitry required to support boundary scan testing. The
circuitry includes the TAP, TAP controller, instruction register,
and data registers. The circuity and operation of the DIE
boundary scan are described in detail below. The scan chain
of each DIE are connected serially to form the scan chain of
the CY7C0833AV as shown in Figure 3. TMS and TCK are
connected in parallel to each DIE to drive all TAP controllers
in unison. In many cases, each DIE will be supplied with the
same instruction. In other cases, it might be useful to supply
different instructions to each DIE. One example would be
testing the device ID of one DIE while bypassing the others.
Each pin of FLEx18 family is typically connected to multiple
DIEs. For connectivity testing with the EXTEST instruction, it
is desirable to check the internal connections between DIEs
as well as the external connections to the package. This can
be accomplished by merging the netlist of the devices with the
netlist of the user’s circuit board. To facilitate boundary scan
testing of the devices, Cypress provides the BSDL file for each
DIE, the internal netlist of the device, and a description of the
device scan chain. The user can use these materials to easily
integrate the devices into the board’s boundary scan
environment. Further information can be found in the Cypress
application note Using JTAG Boundary Scan For System in a
Package (SIP) Dual-Port SRAMs.
The FLEx18 family devices incorporate an IEEE 1149.1 serial
boundary scan test access port (TAP). The TAP controller
functions in a manner that does not conflict with the operation
of other devices using 1149.1-compliant TAPs. The TAP
operates using JEDEC-standard 3.3V I/O logic levels. It is
composed of three input connections and one output
connection required by the test logic defined by the standard.
Performing a TAP Reset
A reset is performed by forcing TMS HIGH (VDD) for five rising
edges of TCK. This reset does not affect the operation of the
devices, and may be performed while the device is operating.
An MRST must be performed on the devices after power-up.
Performing a Pause/Restart
When a SHIFT-DR PAUSE-DR SHIFT-DR is performed the
scan chain will output the next bit in the chain twice. For
example, if the value expected from the chain is 1010101, the
device will output a 11010101. This extra bit will cause some
testers to report an erroneous failure for the devices in a scan
test. Therefore the tester should be configured to never enter
the PAUSE-DR state.
Notes:
19. The “X” in this diagram represents the counter upper bits
20. Boundary scan is IEEE 1149.1-compatible. See “Performing a Pause/Restart” for deviation from strict 1149.1 compliance
Document #: 38-06059 Rev. *Q
Page 10 of 28
[+] Feedback
CY7C0837AV
CY7C0830AV/CY7C0831AV
CY7C0832AV/CY7C0833AV
TDO
TDO
D2
TDI
TDO
D1
TDI
TDI
Figure 3. Scan Chain for 9Mb Device
Table 4. Identification Register Definitions
Instruction Field
Revision Number (31:28)
Cypress Device ID (27:12)
Value
Description
0h
Reserved for version number.
C090h
C091h
C093h
C094h
034h
1
Defines Cypress part number for CY7C0832AV
Defines Cypress part number for CY7C0831AV
Defines Cypress part number for CY7C0830AV
Defines Cypress part number for CY7C0837AV.
Allows unique identification of the DP family device vendor.
Indicates the presence of an ID register.
Cypress JEDEC ID (11:1)
ID Register Presence (0)
Table 5. Scan Registers Sizes
Register Name
Instruction
Bit Size
4
Bypass
1
Identification
Boundary Scan
32
n[21]
Table 6. Instruction Identification Codes
Instruction
EXTEST
BYPASS
IDCODE
HIGHZ
Code
Description
0000
1111
1011
0111
0100
Captures the Input/Output ring contents. Places the BSR between the TDI and TDO.
Places the BYR between TDI and TDO.
Loads the IDR with the vendor ID code and places the register between TDI and TDO.
Places BYR between TDI and TDO. Forces all device output drivers to a High-Z state.
Controls boundary to 1/0. Places BYR between TDI and TDO.
CLAMP
SAMPLE/PRELOAD 1000
Captures the input/output ring contents. Places BSR between TDI and TDO.
Resets the non-boundary scan logic. Places BYR between TDI and TDO.
NBSRST
1100
RESERVED
All other codes Other combinations are reserved. Do not use other than the above.
Notes:
21. See details in the device BSDL file.
Document #: 38-06059 Rev. *Q
Page 11 of 28
[+] Feedback
CY7C0837AV
CY7C0830AV/CY7C0831AV
CY7C0832AV/CY7C0833AV
Maximum Ratings[22]
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage...........................................> 2000V
(JEDEC JESD22-A114-2000B)
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Latch-up Current.....................................................> 200 mA
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Supply Voltage to Ground Potential............... –0.5V to +4.6V
Operating Range
Ambient
Range
Commercial
Industrial
Temperature
0°C to +70°C
–40°C to +85°C
VDD
3.3V±165 mV
3.3V±165 mV
DC Voltage Applied to
Outputs in High-Z State..........................–0.5V to VDD + 0.5V
DC Input Voltage...............................–0.5V to VDD + 0.5V[23]
Electrical Characteristics Over the Operating Range
-167
-133
-100
Parameter
Description
Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit
VOH
Output HIGH Voltage
2.4
2.4
2.4
V
(VDD = Min., IOH= –4.0 mA)
VOL
Output LOW Voltage
0.4
0.4
0.4
V
(VDD = Min., IOL= +4.0 mA)
VIH
VIL
IOZ
IIX1
IIX2
ICC
Input HIGH Voltage
Input LOW Voltage
Output Leakage Current
Input Leakage Current Except TDI, TMS, MRST
Input Leakage Current TDI, TMS, MRST
2.0
2.0
2.0
V
V
µA
µA
0.8
0.8
0.8
10
10
–10
–10
–0.1
10 –10
10 –10
1.0 –0.1
10 –10
10 –10
1.0 –0.1
1.0 mA
mA
Operating Current for
CY7C0837AV
225 300
225 300
(VDD = Max., IOUT = 0 mA), Outputs CY7C0830AV
Disabled
CY7C0831AV
CY7C0832AV
CY7C0833AV
270 400
90 115
200 310 mA
90 115 mA
[24]
ISB1
Standby Current
90 115
160 210
(Both Ports TTL Level)
CEL and CER ≥ VIH, f = fMAX
[24]
ISB2
Standby Current
160 210
160 210 mA
(One Port TTL Level)
CEL | CER ≥ VIH, f = fMAX
[24]
ISB3
Standby Current
55
75
55
75
55
75
mA
(Both Ports CMOS Level)
CEL and CER ≥ VDD – 0.2V, f = 0
[24]
ISB4
Standby Current
160 210
160 210
70 100
160 210 mA
70 100 mA
(One Port CMOS Level)
CEL | CER ≥ VIH, f = fMAX
ISB5
Operating Current
CY7C0833AV
(VDD = Max, IOUT = 0 mA, f = 0)
Outputs Disabled
Notes:
22. The voltage on any input or I/O pin can not exceed the power pin during power-up.
23. Pulse width < 20 ns.
24. I
, I
, I
and I
are not applicable for CY7C0833AV because it can not be powered down by using chip enable pins.
SB4
SB1 SB2 SB3
Document #: 38-06059 Rev. *Q
Page 12 of 28
[+] Feedback
CY7C0837AV
CY7C0830AV/CY7C0831AV
CY7C0832AV/CY7C0833AV
Capacitance [25]
Part Number
Parameter
CIN
COUT
Description
Input Capacitance
Output Capacitance
Test Conditions
Max.
13
10
Unit
pF
pF
CY7C0837AV
CY7C0830AV
CY7C0831AV
CY7C0832AV
TA = 25°C, f = 1 MHz,
V
DD = 3.3V
CY7C0833AV
CIN
COUT
Input Capacitance
Output Capacitance
22
20
pF
pF
AC Test Load and Waveforms
3.3V
Z0 = 50Ω
R = 50Ω
OUTPUT
R1 = 590 Ω
OUTPUT
C = 10 pF
C = 5 pF
R2 = 435 Ω
VTH = 1.5V
(a) Normal Load (Load 1)
(b) Three-state Delay (Load 2)
3.0V
90%
10%
90%
10%
ALL INPUT PULSES
Vss
< 2 ns
< 2 ns
Switching Characteristics Over the Operating Range
-167
-133
-100
CY7C0837AV CY7C0837AV
CY7C0830AV CY7C0830AV
CY7C0831AV CY7C0831AV
CY7C0832AV CY7C0832AV CY7C0833AV CY7C0833AV
Parameter
fMAX2
tCYC2
Description
Maximum Operating Frequency
Clock Cycle Time
Clock HIGH Time
Clock LOW Time
Min.
Max.
167
Min.
Max.
133
Min.
Max.
133
Min.
Max.
100
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
6.0
2.7
2.7
7.5
3.0
3.0
7.5
3.0
3.0
10
4.0
4.0
tCH2
tCL2
[26]
tR
tF
Clock Rise Time
Clock Fall Time
2.0
2.0
2.0
2.0
2.0
2.0
3.0
3.0
[26]
tSA
tHA
tSB
tHB
tSC
tHC
tSW
Address Set-up Time
Address Hold Time
Byte Select Set-up Time
Byte Select Hold Time
Chip Enable Set-up Time
Chip Enable Hold Time
R/W Set-up Time
2.3
0.6
2.3
0.6
2.3
0.6
2.3
0.6
2.5
0.6
2.5
0.6
2.5
0.6
2.5
0.6
2.5
0.6
2.5
0.6
NA
NA
2.5
0.6
3.0
0.6
3.0
0.6
NA
NA
3.0
0.6
tHW
R/W Hold Time
Notes:
25. C
also references C
.
OUT
I/O
26. Except JTAG signals (t and t < 10 ns [max.]).
r
f
Document #: 38-06059 Rev. *Q
Page 13 of 28
[+] Feedback
CY7C0837AV
CY7C0830AV/CY7C0831AV
CY7C0832AV/CY7C0833AV
Switching Characteristics Over the Operating Range (continued)
-167
-133
-100
CY7C0837AV CY7C0837AV
CY7C0830AV CY7C0830AV
CY7C0831AV CY7C0831AV
CY7C0832AV CY7C0832AV CY7C0833AV CY7C0833AV
Parameter
tSD
tHD
tSAD
tHAD
Description
Input Data Set-up Time
Input Data Hold Time
ADS Set-up Time
ADS Hold Time
CNTEN Set-up Time
CNTEN Hold Time
CNTRST Set-up Time
CNTRST Hold Time
CNT/MSK Set-up Time
CNT/MSK Hold Time
Output Enable to Data Valid
OE to Low Z
OE to High Z
Clock to Data Valid
Clock to Counter Address Valid
Min.
2.3
0.6
2.3
0.6
2.3
0.6
2.3
0.6
2.3
0.6
Max.
Min.
2.5
0.6
2.5
0.6
2.5
0.6
2.5
0.6
2.5
0.6
Max.
Min.
2.5
0.6
NA
NA
NA
NA
NA
NA
NA
NA
Max.
Min.
3.0
0.6
NA
NA
NA
NA
NA
NA
NA
NA
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSCN
tHCN
tSRST
tHRST
tSCM
tHCM
tOE
4.0
4.4
4.7
5.0
[27,28]
tOLZ
0
0
0
0
[27,28]
tOHZ
4.0
4.0
4.0
4.0
4.4
4.4
4.4
4.4
4.7
4.7
NA
NA
5.0
5.0
NA
NA
tCD2
tCA2
tCM2
Clock to Mask Register Readback
Valid
tDC
tCKHZ
tCKLZ
tSINT
tRINT
tSCINT
tRCINT
Data Output Hold After Clock HIGH
Clock HIGH to Output High Z
Clock HIGH to Output Low Z
Clock to INT Set Time
Clock to INT Reset Time
Clock to CNTINT Set Time
Clock to CNTINT Reset time
1.0
0
1.0
0
1.0
1.0
ns
ns
ns
ns
ns
ns
ns
[27,28]
4.0
4.0
6.7
6.7
5.0
5.0
4.4
4.4
7.5
7.5
5.7
5.7
4.7
4.7
7.5
7.5
NA
NA
5.0
5.0
10
10
NA
NA
[27, 28]
1.0
0.5
0.5
0.5
0.5
1.0
0.5
0.5
0.5
0.5
1.0
0.5
0.5
NA
NA
1.0
0.5
0.5
NA
NA
Port to Port Delays
tCCS
Clock to Clock Skew
5.2
6.0
6.0
8.0
ns
Master Reset Timing
tRS
tRS
tRSR
tRSF
Master Reset Pulse Width
Master Reset Set-up Time
Master Reset Recovery Time
Master Reset to Outputs Inactive
7.0
6.0
6.0
7.5
6.0
7.5
7.5
6.0
7.5
10
8.5
10
ns
ns
ns
ns
ns
10.0
10.0
10.0
10.0
10.0
NA
10.0
NA
tRSCNTINT
Master Reset to Counter Interrupt
Flag Reset Time
Notes:
27. This parameter is guaranteed by design, but it is not production tested.
28. Test conditions used are Load 2.
Document #: 38-06059 Rev. *Q
Page 14 of 28
[+] Feedback
CY7C0837AV
CY7C0830AV/CY7C0831AV
CY7C0832AV/CY7C0833AV
JTAG Timing and Switching Waveforms
CY7C0837AV/CY7C0830AV
CY7C0831AV/CY7C0832AV
CY7C0833AV
Parameter
fJTAG
tTCYC
tTH
Description
Maximum JTAG TAP Controller Frequency
Min.
Max.
10
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
TCK Clock Cycle Time
TCK Clock HIGH Time
TCK Clock LOW Time
100
40
40
10
10
10
10
tTL
tTMSS
tTMSH
tTDIS
tTDIH
tTDOV
tTDOX
TMS Set-up to TCK Clock Rise
TMS Hold After TCK Clock Rise
TDI Set-up to TCK Clock Rise
TDI Hold After TCK Clock Rise
TCK Clock LOW to TDO Valid
TCK Clock LOW to TDO Invalid
30
ns
ns
0
tTH
tTL
Test Clock
TCK
tTCYC
tTMSS
tTMSH
Test Mode Select
TMS
tTDIS
tTDIH
Test Data-In
TDI
Test Data-Out
TDO
tTDOX
tTDOV
Document #: 38-06059 Rev. *Q
Page 15 of 28
[+] Feedback
CY7C0837AV
CY7C0830AV/CY7C0831AV
CY7C0832AV/CY7C0833AV
Switching Waveforms
Master Reset
MRST
tRS
tRSF
ALL
ADDRESS/
DATA
tRSS
INACTIVE
LINES
tRSR
ALL
OTHER
INPUTS
ACTIVE
TMS
CNTINT
INT
TDO
Read Cycle[11, 29, 30, 31, 32]
tCYC2
tCH2
tCL2
CLK
CE
tSC
tHC
tSC
tHC
tSB
tHB
BE0–BE1
R/W
tSW
tSA
tHW
tHA
ADDRESS
An
An+1
An+2
An+3
tDC
1 Latency
tCD2
DATAOUT
Qn
Qn+1
Qn+2
tOHZ
tCKLZ
tOLZ
OE
t
OE
Notes:
29. OE is asynchronously controlled; all other inputs (excluding MRST and JTAG) are synchronous to the rising clock edge.
30. ADS = CNTEN = LOW, and MRST = CNTRST = CNT/MSK = HIGH.
31. The output is disabled (high-impedance state) by CE = V following the next rising edge of the clock.
IH
32. Addresses do not have to be accessed sequentially since ADS = CNTEN = V with CNT/MSK = V constantly loads the address on the rising edge of the CLK.
IL
IH
Numbers are for reference only.
Document #: 38-06059 Rev. *Q
Page 16 of 28
[+] Feedback
CY7C0837AV
CY7C0830AV/CY7C0831AV
CY7C0832AV/CY7C0833AV
Switching Waveforms (continued)
Bank Select Read[33, 34]
tCYC2
tCH2
tCL2
CLK
tHA
tSA
A3
A4
ADDRESS(B1)
A5
A0
A1
A2
tHC
tSC
CE(B1)
tCD2
tCD2
tCD2
tCKHZ
tHC
tCKHZ
tSC
Q0
Q3
Q1
DATAOUT(B1)
ADDRESS(B2)
tHA
tSA
tDC
A2
tDC
A3
tCKLZ
A4
A5
A0
A1
tHC
tSC
CE(B2)
tCD2
tCKHZ
tCD2
tSC
tHC
DATAOUT(B2)
Q4
Q2
tCKLZ
tCKLZ
Read-to-Write-to-Read (OE = LOW)[32, 35, 36, 37, 38]
tCYC2
tCH2
tCL2
CLK
CE
tSC
tHC
tSW
tHW
R/W
tSW
tHW
An
An+1
An+2
An+2
tSD tHD
Dn+2
An+3
An+4
ADDRESS
DATAIN
tSA
tHA
tCD2
tCD2
tCKHZ
Qn
Qn+3
DATAOUT
tCKLZ
READ
READ
NO OPERATION
WRITE
Notes:
33. In this depth-expansion example, B1 represents Bank #1 and B2 is Bank #2; each bank consists of one Cypress FLEx18 device from this data sheet. ADDRESS
(B1)
= ADDRESS
.
(B2)
34. ADS = CNTEN= BE0 – BE1 = OE = LOW; MRST = CNTRST = CNT/MSK = HIGH.
35. Output state (HIGH, LOW, or high-impedance) is determined by the previous cycle control signals.
36. During “No Operation,” data in memory at the selected address may be corrupted and should be rewritten to ensure data integrity.
37. CE = OE = BE0 – BE1 = LOW; CE = R/W = CNTRST = MRST = HIGH.
0
0
1
1
38. CE = BE0 – BE1 = R/W = LOW; CE = CNTRST = MRST = CNT/MSK = HIGH. When R/W first switches low, since OE = LOW, the Write operation cannot be
completed (labelled as no operation). One clock cycle is required to three-state the I/O for the Write operation on the next rising edge of CLK.
Document #: 38-06059 Rev. *Q
Page 17 of 28
[+] Feedback
CY7C0837AV
CY7C0830AV/CY7C0831AV
CY7C0832AV/CY7C0833AV
Switching Waveforms (continued)
Read-to-Write-to-Read (OE Controlled)[32, 35, 37, 38]
tCYC2
tCH2
tCL2
CLK
CE
tSC
tHC
tHW
tSW
R/W tSW
tHW
An
An+1
An+2
An+3
An+4
An+5
ADDRESS
tSA
tHA
tSD tHD
Dn+2
DATAIN
Dn+3
tCD2
tCD2
DATAOUT
Qn
Qn+4
tOHZ
OE
READ
WRITE
READ
Read with Address Counter Advance[37]
tCYC2
tCH2
tCL2
CLK
tSA
tHA
ADDRESS
An
tSAD
tHAD
ADS
tSAD
tHAD
CNTEN
tSCN
tHCN
tSCN
tHCN
tCD2
Qx–1
Qx
tDC
Qn
Qn+1
COUNTER HOLD
Qn+2
DATAOUT
Qn+3
READ
READ WITH COUNTER
READ WITH COUNTER
EXTERNAL
ADDRESS
Document #: 38-06059 Rev. *Q
Page 18 of 28
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CY7C0837AV
CY7C0830AV/CY7C0831AV
CY7C0832AV/CY7C0833AV
Switching Waveforms (continued)
Write with Address Counter Advance[38]
tCYC2
tCH2
tCL2
CLK
tSA
tHA
An
ADDRESS
INTERNAL
ADDRESS
An
An+1
An+2
An+3
An+4
tSAD
tHAD
ADS
CNTEN
DATAIN
tSCN
tHCN
Dn
Dn+1
Dn+1
Dn+2
Dn+3
Dn+4
tSD
tHD
WRITE EXTERNAL
WRITE WITH WRITE COUNTER
COUNTER HOLD
WRITE WITH COUNTER
ADDRESS
Document #: 38-06059 Rev. *Q
Page 19 of 28
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CY7C0837AV
CY7C0830AV/CY7C0831AV
CY7C0832AV/CY7C0833AV
Switching Waveforms (continued)
Counter Reset[39, 40]
tCYC2
tCH2 tCL2
CLK
tHA
Am
tSA
Ap
An
ADDRESS
INTERNAL
Ax
Ap
An
1
0
Am
ADDRESS
tHW
tSW
R/W
ADS
CNTEN
CNTRST
tHRST
tSRST
tHD
D0
tSD
DATAIN
tCD2
tCD2
[41]
DATAOUT
Q0
Qn
Q1
tCKLZ
READ
ADDRESS 0
READ
ADDRESS 1
READ
COUNTER
RESET
WRITE
ADDRESS 0
READ
ADDRESS Am
ADDRESS An
Notes:
39. CE = BE0 – BE1 = LOW; CE = MRST = CNT/MSK = HIGH.
0
1
40. No dead cycle exists during counter reset. A Read or Write cycle may be coincidental with the counter reset.
41. Retransmit happens if the counter remains in increment mode after it wraps to initially loaded value.
Document #: 38-06059 Rev. *Q
Page 20 of 28
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CY7C0837AV
CY7C0830AV/CY7C0831AV
CY7C0832AV/CY7C0833AV
Switching Waveforms (continued)
Readback State of Address Counter or Mask Register[42, 43, 44, 45]
tCYC2
tCH2 tCL2
CLK
tCA2 or tCM2
tSA
tHA
EXTERNAL
An*
An
ADDRESS
A0–A16
INTERNAL
ADDRESS
An+4
An+1
An+2
An+3
An
tSAD
tHAD
ADS
CNTEN
tSCN
tHCN
tCD2
tCKHZ
Qn
tCKLZ
DATAOUT
Qn+1
Qx-1
Qn+2
Qx-2
Q
n+3
LOAD
READBACK
COUNTER
INTERNAL
ADDRESS
INCREMENT
EXTERNAL
ADDRESS
Notes:
42. CE = OE = BE0 – BE1 = LOW; CE = R/W = CNTRST = MRST = HIGH.
0
1
43. Address in output mode. Host must not be driving address bus after t
in next clock cycle.
CKLZ
44. Address in input mode. Host can drive address bus after t
.
CKHZ
45. An * is the internal value of the address counter (or the mask register depending on the CNT/MSK level) being Read out on the address lines.
Document #: 38-06059 Rev. *Q
Page 21 of 28
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CY7C0837AV
CY7C0830AV/CY7C0831AV
CY7C0832AV/CY7C0833AV
Switching Waveforms (continued)
Left_Port (L_Port) Write to Right_Port (R_Port) Read[46, 47, 48]
tCYC2
tCH2
tCL2
CLKL
tHA
tSA
L_PORT
An
ADDRESS
tSW
tHW
R/WL
tCKHZ
tSD
tHD
tCKLZ
L_PORT
DATAIN
Dn
tCCS
tCYC2
tCL2
CLKR
tCH2
tSA
tHA
R_PORT
An
ADDRESS
R/WR
tCD2
R_PORT
DATAOUT
Qn
tDC
Notes:
46. CE = OE = ADS = CNTEN = BE0 – BE1 = LOW; CE = CNTRST = MRST = CNT/MSK = HIGH.
0
1
47. This timing is valid when one port is writing, and other port is reading the same location at the same time. If t
is violated, indeterminate data will be Read out.
CCS
CYC2
48. If t
< minimum specified value, then R_Port will Read the most recent data (written by L_Port) only (2 * t
+ t
) after the rising edge of R_Port's clock. If
CCS
CD2
t
> minimum specified value, then R_Port will Read the most recent data (written by L_Port) (t
+ t
) after the rising edge of R_Port's clock.
CCS
CYC2
CD2
Document #: 38-06059 Rev. *Q
Page 22 of 28
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CY7C0837AV
CY7C0830AV/CY7C0831AV
CY7C0832AV/CY7C0833AV
Switching Waveforms (continued)
Counter Interrupt and Retransmit[14, 41, 49, 50, 51, 52]
tCYC2
tCH2
tCL2
CLK
tSCM
tHCM
CNT/MSK
ADS
CNTEN
COUNTER
INTERNAL
ADDRESS
3FFFE
tSCINT
3FFFC
Last_Loaded
3FFFD
3FFFF
tRCINT
Last_Loaded +1
CNTINT
Notes:
49. CE = OE = BE0 – BE1 = LOW; CE = R/W = CNTRST = MRST = HIGH.
0
1
50. CNTINT is always driven.
51. CNTINT goes LOW when the unmasked portion of the address counter is incremented to the maximum value.
52. The mask register assumed to have the value of 3FFFFh.
Document #: 38-06059 Rev. *Q
Page 23 of 28
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CY7C0837AV
CY7C0830AV/CY7C0831AV
CY7C0832AV/CY7C0833AV
Switching Waveforms (continued)
MailBox Interrupt Timing[53, 54, 55, 56, 57]
tCYC2
tCH2
tCL2
CLKL
tSA tHA
7FFFF
L_PORT
An+1
An
An+2
ADDRESS
An+3
tSINT
tRINT
INTR
tCYC2
tCL2
tCH2
CLKR
tSA tHA
Am
R_PORT
Am+1
7FFFF
Am+3
Am+4
ADDRESS
Table 7. Read/Write and Enable Operation (Any Port)[1, 16, 58, 59, 60]
Inputs
Outputs
OE
CLK
CE0
CE1
R/W
DQ0 – DQ17
Operation
X
H
X
X
High-Z
Deselected
Deselected
Write
X
X
L
X
L
L
L
L
H
H
H
X
L
High-Z
DIN
H
X
DOUT
High-Z
Read
H
X
Outputs Disabled
Notes:
53. CE = OE = ADS = CNTEN = LOW; CE = CNTRST = MRST = CNT/MSK = HIGH.
0
1
54. Address “7FFFF” is the mailbox location for R_Port of the 9Mb device.
55. L_Port is configured for Write operation, and R_Port is configured for Read operation.
56. At least one byte enable (BE0 – BE1) is required to be active during interrupt operations.
57. Interrupt flag is set with respect to the rising edge of the Write clock, and is reset with respect to the rising edge of the Read clock.
58. OE is an asynchronous input signal.
59. When CE changes state, deselection and Read happen after one cycle of latency.
60. CE = OE = LOW; CE = R/W = HIGH.
0
1
Document #: 38-06059 Rev. *Q
Page 24 of 28
[+] Feedback
CY7C0837AV
CY7C0830AV/CY7C0831AV
CY7C0832AV/CY7C0833AV
Ordering Information
512K
×
18 (9-Mbit) 3.3V Synchronous CY7C0833AV Dual-Port SRAM
Speed
Package
Operating
(MHz)
Ordering Code
CY7C0833AV-133BBC
CY7C0833AV-133BBI
CY7C0833AV-100BBC
CY7C0833AV-100BBI
Name
BB144
BB144
BB144
BB144
Package Type
Range
144-ball Leaded Ball Grid Array 13 mm × 13 mm with 1.0-mm pitch Commercial
144-ball Leaded Ball Grid Array 13 mm × 13 mm with 1.0-mm pitch Industrial
144-ball Leaded Ball Grid Array 13 mm × 13 mm with 1.0-mm pitch Commercial
144-ball Leaded Ball Grid Array 13 mm × 13 mm with 1.0-mm pitch Industrial
133
100
256K
×
18 (4-Mbit) 3.3V Synchronous CY7C0832AV Dual-Port SRAM
Package
Speed
Operating
Range
(MHz)
Ordering Code
CY7C0832AV-167BBC
CY7C0832AV-167AC
CY7C0832AV-133BBC
CY7C0832AV-133BBI
CY7C0832AV-133AC
CY7C0832AV-133AI
Name
BB144
A120
Package Type
167
167
133
144-ball Leaded Ball Grid Array 13 mm × 13 mm with 1.0-mm pitch Commercial
120-pin Leaded Thin Quad Flat Pack 14 mm x 14 mm Commercial
144-ball Leaded Ball Grid Array 13 mm × 13 mm with 1.0-mm pitch Commercial
144-ball Leaded Ball Grid Array 13 mm × 13 mm with 1.0-mm pitch Industrial
120-pin Leaded Thin Quad Flat Pack 14 mm x 14 mm
120-pin Leaded Thin Quad Flat Pack 14 mm x 14 mm
BB144
BB144
A120
133
Commercial
Industrial
A120
128K
×
18 (2-Mbit) 3.3V Synchronous CY7C0831AV Dual-Port SRAM
Package
Speed
Operating
Range
(MHz)
Ordering Code
Name
BB144
A120
Package Type
167
167
133
CY7C0831AV-167BBC
CY7C0831AV-167AC
CY7C0831AV-133BBC
CY7C0831AV-133BBXC
144-ball Leaded Ball Grid Array 13 mm × 13 mm with 1.0-mm pitch Commercial
120-pin Leaded Thin Quad Flat Pack 14 mm x 14 mm Commercial
144-ball Leaded Ball Grid Array 13 mm × 13 mm with 1.0-mm pitch Commercial
BB144
BW144
144-ball Lead(Pb)-Free Ball Grid Array 13 mm × 13 mm with
Commercial
1.0-mm pitch
CY7C0831AV-133BBI
CY7C0831AV-133BBXI
BB144
BW144
144-ball Leaded Ball Grid Array 13 mm × 13 mm with 1.0-mm pitch Industrial
144-ball Lead(Pb)-Free Ball Grid Array 13 mm × 13 mm with
Industrial
1.0-mm pitch
133
CY7C0831AV-133AC
CY7C0831AV-133AXC
CY7C0831AV-133AI
A120
AZ0AE
A120
120-pin Leaded Thin Quad Flat Pack 14 mm x 14 mm
120-pin Lead(Pb)-Free Thin Quad Flat Pack 14 mm x 14 mm
120-pin Leaded Thin Quad Flat Pack 14 mm x 14 mm
Commercial
Commercial
Industrial
64K
×
18 (1-Mbit) 3.3V Synchronous CY7C0830AV Dual-Port SRAM
Package
Speed
Operating
Range
(MHz)
Ordering Code
CY7C0830AV-167BBC
CY7C0830AV-167AC
CY7C0830AV-133BBC
CY7C0830AV-133BBI
CY7C0830AV-133AC
CY7C0830AV-133AI
Name
BB144
A120
Package Type
167
167
133
144-ball Leaded Ball Grid Array 13 mm × 13 mm with 1.0-mm pitch Commercial
120-pin Leaded Thin Quad Flat Pack 14 mm x 14 mm Commercial
144-ball Leaded Ball Grid Array 13 mm × 13 mm with 1.0-mm pitch Commercial
144-ball Leaded Ball Grid Array 13 mm × 13 mm with 1.0-mm pitch Industrial
120-pin Leaded Thin Quad Flat Pack 14 mm x 14 mm
120-pin Leaded Thin Quad Flat Pack 14 mm x 14 mm
BB144
BB144
A120
133
Commercial
Industrial
A120
32K
×
18 (512-Kbit) 3.3V Synchronous CY7C0837AV Dual-Port SRAM
Package
Speed
Operating
Range
(MHz)
Ordering Code
CY7C0837AV-167BBC
CY7C0837AV-133BBC
CY7C0837AV-133BBI
Name
BB144
BB144
BB144
Package Type
167
133
144-ball Leaded Ball Grid Array 13 mm × 13 mm with 1.0-mm pitch Commercial
144-ball Leaded Ball Grid Array 13 mm × 13 mm with 1.0-mm pitch Commercial
144-ball Leaded Ball Grid Array 13 mm × 13 mm with 1.0-mm pitch Industrial
Document #: 38-06059 Rev. *Q
Page 25 of 28
[+] Feedback
CY7C0837AV
CY7C0830AV/CY7C0831AV
CY7C0832AV/CY7C0833AV
Package Diagrams
144 Leaded FBGA (13 x 13 x 1.6 mm) BB144
144 Lead(Pb)-free FBGA (13 x 13 x 1.6 mm) BW144
TOP VIEW
BOTTOM VIEW
Ø0.05 M C
Ø0.25 M C A B
A1 CORNER
+0.10
Ø0.50 (144X)
-0.05
1
2
3
4
5
6
7
8
9
10
11 12
12 11 10
9
8
7
6
5
3
2
1
4
A
B
A
B
C
D
E
C
D
E
F
G
F
G
H
J
H
J
K
K
L
L
M
M
5.50
A
A
1.00
13.00 0.10
B
11.00
13.00 0.10
B
0.15(4X)
DIMENSIONS IN MILLIMETERS
REFERENCE JEDEC: PUBLICATION 95
DESIGN GUIDE 4.14D
PKG. WEIGHT: 0.53 gms
SEATING PLANE
C
51-85141-*B
Document #: 38-06059 Rev. *Q
Page 26 of 28
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CY7C0837AV
CY7C0830AV/CY7C0831AV
CY7C0832AV/CY7C0833AV
Package Diagrams (continued)
120-Pin Leaded Thin Quad Flatpack (14 x 14 x 1.4 mm) A120
120-Pin Lead(Pb)-Free Thin Quad Flatpack (14 x 14 x 1.4 mm) AZ0AE
51-85100-**
FLEx18 is a trademark of Cypress Semiconductor Corporation. All product and company names mentioned in this document may
be the trademarks of their respective holders.
Document #: 38-06059 Rev. *Q
Page 27 of 28
© Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
[+] Feedback
CY7C0837AV
CY7C0830AV/CY7C0831AV
CY7C0832AV/CY7C0833AV
Document History Page
Document Title: FLEx18™ 3.3V 32K/64K/128K/256K/512K x 18 Synchronous Dual-Port RAM
Document Number: 38-06059
Issue
Date
11/27/01
Orig. of
REV.
**
ECN NO.
111473
Change Description of Change
DSG
Change from Spec number: 38-01056 to 38-06059
*A
111942
12/21/01
JFU
Updated capacitance values
Updated switching parameters and ISB3
Updated “Read-to-Write-to-Read (OE Controlled)” waveform
Revised static discharge voltage
Revised footnote regarding ISB3
*B
113741
04/02/02
KRE
Updated Isb values
Updated ESD voltage
Corrected 0853 pins L3 and L12
*C
*D
*E
*F
*G
114704
115336
122307
123636
126053
04/24/02
07/01/02
12/27/02
1/27/03
KRE
KRE
RBI
KRE
SPN
Added discussion of Pause/Restart for JTAG boundary scan
Revised speed offerings for all densities
Power up requirements added to Maximum Ratings Information
Revise tcd2, tOE, tOHZ, tCKHZ, tCKLZ for the CY7C0853V to 4.7 ns
08/11/03
Separated out 4M and 9M data sheets
Updated Isb and ICC values
*H
*I
129443
231993
11/03/03
See ECN
RAZ
YDT
Updated Isb and ICC values
Removed “A particular port can write to a certain location while another port
is reading that location.” from Functional Description.
*J
231813
See ECN
WWZ
Removed x36 devices (CY7C0852/CY7C0851) from this datasheet. Added
0.5M, 1M and 9M x18 devices to it. Changed title to FLEx18 3.3V
32K/64K/128K/256K/512K x18 Synchronous Dual-Port RAM. Changed
datasheet to accommodate the removals and additions. Removed general
JTAG description. Updated JTAG ID codes for all devices. Added 144FBGA
package for all devices. Updated selection guide table and moved to the
front page. Updated block diagram to reflect x18 configuration. Added
preliminary status back due to the addition of the new devices.
*K
*L
311054
329111
See ECN
See ECN
RYQ
SPN
Minor Change: Correct the revision indicated on the footer.
Updated Marketing part numbers
Updated tRSF
*M
*N
330561
375198
See ECN
See ECN
RUY
YDT
Added Byte Select Operation Table
Removed Preliminary status
Added ISB5
Changed tRSCNTINT to 10ns
*O
*P
*Q
391525
414109
461113
See ECN
See ECN
SEE ECN
SPN
LIJ
Updated Counter reset section to reflect what is loaded into the mirror
register
Corrected Ordering Codes for 0831 devices in the 133 Mhz speed bin.
Added CY7C0833AV-133BBI.
Changed VDDIO to VDD (typo)
Added lead(Pb)-free parts
Corrected typo in DC table
YDT
Document #: 38-06059 Rev. *Q
Page 28 of 28
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相关型号：
CY7C0832AV-133BBC
256KX18 DUAL-PORT SRAM, 4ns, PBGA144, 13 X 13 MM, 1.60 MM HEIGHT, 1 MM PITCH, FBGA-144
ROCHESTER
CY7C0832AV-167BBC
256KX18 DUAL-PORT SRAM, 4ns, PBGA144, 13 X 13 MM, 1.60 MM HEIGHT, 1 MM PITCH, FBGA-144
ROCHESTER
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