CY7C038V-15AXC [CYPRESS]
3.3V 32K/64K x 16/18 Dual-Port Static RAM; 3.3V 32K / 64K X 16/18双端口静态RAM
| 型号： | CY7C038V-15AXC |
| 厂家： | 
CYPRESS |
| 描述： | 3.3V 32K/64K x 16/18 Dual-Port Static RAM |
| 文件： | 总18页 (文件大小：237K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Pb
CY7C027V/028V
CY7C037V/038V
LEAD-FREE
3.3V 32K/64K x 16/18 Dual-Port Static RAM
• Fully asynchronous operation
• Automatic power-down
• Expandable data bus to 32/36 bits or more using Mas-
ter/Slave chip select when using more than one device
Features
• True Dual-Ported memory cells which allow
simultaneous access of the same memory location
• 32K x 16 organization (CY7C027V)
• 64K x 16 organization (CY7C028V)
• 32K x 18 organization (CY7C037V)
• 64K x 18 organization (CY7C038V)
• 0.35-micron CMOS for optimum speed/power
• High-speed access: 15/20/25 ns
• Low operating power
• On-chip arbitration logic
• Semaphores included to permit software handshaking
between ports
• INT flag for port-to-port communication
• Separate upper-byte and lower-byte control
• Dual Chip Enables
• Pin select for Master or Slave
— Active: ICC = 115 mA (typical)
• Commercial and Industrial temperature ranges
• 100-pin Lead(Pb)-free TQFP and 100-pin TQFP
—Standby: ISB3 = 10 µA (typical)
Logic Block Diagram
R/W
R/W
UB
L
R
R
UB
L
CE
CE
CE
CE
0L
1L
0R
1R
CE
CE
R
L
LB
LB
R
L
OE
OE
R
L
8/9
8/9
[1]
[1]
I/O
–I/O
[2]
I/O
–I/O
8/9L
15/17L
8/9L
15/17R
[2]
8/9
8/9
I/O
Control
I/O
Control
I/O –I/O
I/O –I/O
0L
7/8L
0L
7/8R
15/16
15/16
[3]
–A
A
A
–A[3]
A
A
Address
Decode
Address
Decode
True Dual-Ported
0L 14/15L
0R
14/15R
RAM Array
15/16
15/16
–A[3]
[3]
–A
0L 14/15L
0R
14/15R
CE
CE
Interrupt
Semaphore
Arbitration
L
R
OE
OE
L
R
R/W
R/W
L
R
SEM
SEM
L
R
[4]
[4]
BUSY
BUSY
INT
UB
L
R
R
R
R
INT
L
UB
L
LB
M/S
LB
L
Notes:
1. I/O –I/O for x16 devices; I/O –I/O for x18 devices.
8
15
9
17
2. I/O –I/O for x16 devices; I/O –I/O for x18 devices.
0
7
0
8
3. A –A for 32K; A –A for 64K devices.
0
14
0
15
4. BUSY is an output in master mode and an input in slave mode.
Cypress Semiconductor Corporation
Document #: 38-06078 Rev. *A
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Revised September 20, 2004
CY7C027V/028V
CY7C037V/038V
Pin Configurations
100-Pin TQFP (Top View)
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
A9L
A10L
A11L
A12L
A13L
A14L
1
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A9R
2
A10R
A11R
A12R
A13R
A14R
A15R [5]
NC
3
4
5
6
[5]
A15L
NC
7
8
NC
9
NC
LBL
10
11
12
13
14
15
16
17
18
19
20
21
22
23
LBR
UBL
UBR
CE0L
CE1L
SEML
VCC
CE0R
CE1R
SEMR
GND
CY7C028V (64K x 16)
CY7C027V (32K x 16)
R/WL
OEL
R/WR
OER
GND
GND
I/O15L
I/O14L
I/O13L
I/O12L
GND
GND
I/O15R
I/O14R
I/O13R
I/O12R
I/O11R
I/O10R
I/O11L
I/O10L
24
25
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Note:
5. This pin is NC for CY7C027V.
Document #: 38-06078 Rev. *A
Page 2 of 18
CY7C027V/028V
CY7C037V/038V
Pin Configurations (continued)
100-Pin TQFP (Top View)
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
A9L
A10L
1
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A8R
2
A9R
A11L
3
A10R
A11R
A12R
A13R
A14R
A15R
LBR
A12L
4
A13L
5
A14L
6
[6] A15L
LBL
7
[6]
8
UBL
9
CE0L
CE1L
SEML
R/WL
OEL
10
11
12
13
14
15
16
17
18
19
20
21
22
23
UBR
CE0R
CE1R
SEMR
R/WR
GND
OER
GND
CY7C038V (64K x 18)
CY7C037V (32K x 18)
VCC
GND
I/O17L
I/O16L
GND
I/O17R
GND
I/O15L
I/O14L
I/O13L
I/O12L
I/O16R
I/O15R
I/O14R
I/O13R
I/O12R
I/O11R
I/O11L
I/O10L
24
25
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Selection Guide
CY7C037V/038V CY7C037V/038V CY7C037V/038V
-15
-20
-25
Unit
ns
Maximum Access Time
15
20
25
Typical Operating Current
125
35
120
35
115
30
mA
mA
µA
Typical Standby Current for ISB1 (Both ports TTL level)
Typical Standby Current for ISB3 (Both ports CMOS level)
10 µA
10 µA
10 µA
Note:
6. This pin is NC for CY7C037V.
Document #: 38-06078 Rev. *A
Page 3 of 18
CY7C027V/028V
CY7C037V/038V
Pin Definitions
Left Port
CE0L, CE1L
R/WL
Right Port
CE0R, CE1R
Description
Chip Enable (CE is LOW when CE0 ≤ VIL and CE1 ≥ VIH)
R/WR
Read/Write Enable
OEL
OER
Output Enable
A
0L–A15L
A0R–A15R
I/O0R–I/O17R
SEMR
UBR
Address (A0–A14 for 32K; A0–A15 for 64K devices)
I/O0L–I/O17L
SEML
UBL
Data Bus Input/Output (I/O0–I/O15 for x16 devices; I/O0–I/O17 for x18)
Semaphore Enable
Upper Byte Select (I/O8–I/O15 for x16 devices; I/O9–I/O17 for x18 devices)
LBL
LBR
Lower Byte Select (I/O0–I/O7 for x16 devices; I/O0–I/O8 for x18 devices)
INTL
INTR
Interrupt Flag
Busy Flag
BUSYL
M/S
BUSYR
Master or Slave Select
Power
VCC
GND
NC
Ground
No Connect
shared latches. Only one side can control the latch (semaphore) at
any time. Control of a semaphore indicates that a shared resource is
in use. An automatic power-down feature is controlled independently
Architecture
The CY7C027V/028V and CY7037V/038V consist of an array
of 32K and 64K words of 16 and 18 bits each of dual-port RAM
cells, I/O and address lines, and control signals (CE, OE, R/W).
These control pins permit independent access for reads or writes to
any location in memory. To handle simultaneous writes/reads to the
same location, a BUSY pin is provided on each port. Two interrupt
(INT) pins can be utilized for port-to-port communication. Two sema-
phore (SEM) control pins are used for allocating shared resources.
With the M/S pin, the devices can function as a master (BUSY pins
are outputs) or as a slave (BUSY pins are inputs). The devices also
have an automatic power-down feature controlled by CE. Each port
is provided with its own output enable control (OE), which allows data
to be read from the device.
on each port by a chip select (CE) pin.
The CY7C027V/028V and CY7037V/038V are available in
100-pin Thin Quad Plastic Flatpacks (TQFP).
Write Operation
Data must be set up for a duration of tSD before the rising edge
of R/W in order to guarantee a valid write. A write operation is con-
trolled by either the R/W pin (see Write Cycle No. 1 waveform) or the
CE pin (see Write Cycle No. 2 waveform). Required inputs for
non-contention operations are summarized in Table 1.
If a location is being written to by one port and the opposite
port attempts to read that location, a port-to-port flowthrough
delay must occur before the data is read on the output; other-
wise the data read is not deterministic. Data will be valid on the
port tDDD after the data is presented on the other port.
Functional Description
The CY7C027V/028V and CY7037V/038V are low-power
CMOS 32K, 64K x 16/18 dual-port static RAMs. Various arbi-
tration schemes are included on the devices to handle situa-
tions when multiple processors access the same piece of data.
Two ports are provided, permitting independent, asynchro-
nous access for reads and writes to any location in memory.
The devices can be utilized as stand-alone 16/18-bit dual-port
static RAMs or multiple devices can be combined in order to
function as a 32/36-bit or wider master/slave dual-port static
RAM. An M/S pin is provided for implementing 32/36-bit or
wider memory applications without the need for separate mas-
ter and slave devices or additional discrete logic. Application
areas include interprocessor/multiprocessor designs, commu-
nications status buffering, and dual-port video/graphics mem-
ory.
Read Operation
When reading the device, the user must assert both the OE
and CE pins. Data will be available tACE after CE or tDOE after OE is
asserted. If the user wishes to access a semaphore flag, then the
SEM pin must be asserted instead of the CE pin, and OE must also
be asserted.
Interrupts
The upper two memory locations may be used for message
passing. The highest memory location (7FFF for the
CY7C027V/37V, FFFF for the CY7C028V/38V) is the mailbox
for the right port and the second-highest memory location
(7FFE for the CY7C027V/37V, FFFE for the CY7C028V/38V)
is the mailbox for the left port. When one port writes to the
other port’s mailbox, an interrupt is generated to the owner.
The interrupt is reset when the owner reads the contents of the
mailbox. The message is user defined.
Each port has independent control pins: chip enable (CE),
read or write enable (R/W), and output enable (OE). Two flags are
provided on each port (BUSY and INT). BUSY signals that the port is
trying to access the same location currently being accessed by the
other port. The interrupt flag (INT) permits communication between
ports or systems by means of a mail box. The semaphores are used
to pass a flag, or token, from one port to the other to indicate that a
shared resource is in use. The semaphore logic is comprised of eight
Each port can read the other port’s mailbox without resetting
the interrupt. The active state of the busy signal (to a port)
prevents the port from setting the interrupt to the winning port.
Document #: 38-06078 Rev. *A
Page 4 of 18
CY7C027V/028V
CY7C037V/038V
Also, an active busy to a port prevents that port from reading
its own mailbox and, thus, resetting the interrupt to it.
left port wants to request a given resource, it sets a latch by
writing a zero to a semaphore location. The left port then ver-
ifies its success in setting the latch by reading it. After writing
to the semaphore, SEMor OE must be deasserted for tSOP before
attempting to read the semaphore. The semaphore value will be
available tSWRD + tDOE after the rising edge of the semaphore write.
If the left port was successful (reads a zero), it assumes control of the
shared resource, otherwise (reads a one) it assumes the right port
has control and continues to poll the semaphore. When the right side
has relinquished control of the semaphore (by writing a one), the left
side will succeed in gaining control of the semaphore. If the left side
no longer requires the semaphore, a one is written to cancel its re-
quest.
If an application does not require message passing, do not
connect the interrupt pin to the processor’s interrupt request
input pin.
The operation of the interrupts and their interaction with Busy
are summarized in Table 2.
Busy
The CY7C027V/028V and CY7037V/038V provide on-chip ar-
bitration to resolve simultaneous memory location access
(contention). If both ports’ CEs are asserted and an address
match occurs within tPS of each other, the busy logic will determine
which port has access. If tPS is violated, one port will definitely gain
permission to the location, but it is not predictable which port will get
that permission. BUSY will be asserted tBLA after an address match
or tBLC after CE is taken LOW.
Semaphores are accessed by asserting SEM LOW. The SEM
pin functions as a chip select for the semaphore latches (CE must
remain HIGH during SEM LOW). A0–2 represents the semaphore
address. OE and R/W are used in the same manner as a normal
memory access. When writing or reading a semaphore, the other
address pins have no effect.
Master/Slave
When writing to the semaphore, only I/O0 is used. If a zero is
written to the left port of an available semaphore, a one will appear at
the same semaphore address on the right port. That semaphore can
now only be modified by the side showing zero (the left port in this
case). If the left port now relinquishes control by writing a one to the
semaphore, the semaphore will be set to one for both sides. Howev-
er, if the right port had requested the semaphore (written a zero) while
the left port had control, the right port would immediately own the
semaphore as soon as the left port released it. Table 3 shows sam-
ple semaphore operations.
A M/S pin is provided in order to expand the word width by configur-
ing the device as either a master or a slave. The BUSY output of the
master is connected to the BUSY input of the slave. This will allow the
device to interface to a master device with no external components.
Writing to slave devices must be delayed until after the BUSY input
has settled (tBLC or tBLA), otherwise, the slave chip may begin a write
cycle during a contention situation. When tied HIGH, the M/S pin al-
lows the device to be used as a master and, therefore, the BUSY line
is an output. BUSY can then be used to send the arbitration outcome
to a slave.
When reading a semaphore, all sixteen/eighteen data lines
output the semaphore value. The read value is latched in an
output register to prevent the semaphore from changing state
during a write from the other port. If both ports attempt to
access the semaphore within tSPS of each other, the semaphore
will definitely be obtained by one side or the other, but there is no
guarantee which side will control the semaphore.
Semaphore Operation
The CY7C027V/028V and CY7037V/038V provide eight
semaphore latches, which are separate from the dual-port
memory locations. Semaphores are used to reserve resources
that are shared between the two ports.The state of the sema-
phore indicates that a resource is in use. For example, if the
Document #: 38-06078 Rev. *A
Page 5 of 18
CY7C027V/028V
CY7C037V/038V
DC Input Voltage[7] .................................. –0.5V to VCC+0.5V
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage.......................................... > 1100V
Latch-up Current.................................................... > 200 mA
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Operating Range
Ambient
Supply Voltage to Ground Potential............... –0.5V to +4.6V
Range
Commercial
Industrial[8]
Temperature
0°C to +70°C
–40°C to +85°C
VCC
DC Voltage Applied to
Outputs in High-Z State............................–0.5V to VCC+0.5V
3.3V ± 300 mV
3.3V ± 300 mV
Electrical Characteristics Over the Operating Range
CY7C037V/038V
-20
-15
-25
Parameter
Description
Output HIGH Voltage
Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit
VOH
2.4
2.4
2.4
V
(VCC=Min., IOH= –4.0 mA)
VOL
VIH
VIL
IIX
Output LOW Voltage (VCC=Min., IOH= +4.0 mA)
Input HIGH Voltage
0.4
0.4
0.4
V
2.2
2.2
2.2
V
Input LOW Voltage
0.8
5
0.8
5
0.8
V
Input Leakage Current
−5
−5
−5
5
10
µA
µA
mA
mA
mA
mA
mA
mA
µA
µA
mA
mA
IOZ
ICC
Output Leakage Current
–10
10 –10
125 185
10
–10
Operating Current (VCC=Max. IOUT=0 Com’l.
mA) Outputs Disabled
Ind.[8]
120 175
140 195
115 165
ISB1
ISB2
ISB3
ISB4
Standby Current (Both Ports TTL
Level) CEL & CER ≥ VIH, f=fMAX
Com’l.
Ind.[8]
35
50
35
45
75
85
10
10
70
80
45
55
30
65
10
60
40
95
Standby Current (One Port TTL Level) Com’l.
80 120
10 250
75 105
110
120
250
250
95
CEL | CER ≥ VIH, f=fMAX
Ind.[8]
Com’l.
Ind.[8]
Standby Current (Both Ports CMOS
Level) CEL & CER ≥ VCC−0.2V, f=0
250
80
Standby Current (One Port CMOS Lev- Com’l.
[9]
el) CEL | CER ≥ VIH, f=fMAX
Ind.[8]
105
Capacitance[10]
Parameter
Description
Input Capacitance
Output Capacitance
Test Conditions
Max.
Unit
CIN
TA = 25°C, f = 1 MHz,
CC = 3.3V
10
10
pF
pF
V
COUT
Notes:
7. Pulse width < 20 ns.
8. Industrial parts are available in CY7C028V and CY7C038V only.
9.
f
= 1/t = All inputs cycling at f = 1/t (except output enable). f = 0 means no address or control lines change. This applies only to inputs at CMOS level standby I
.
MAX
RC
RC
SB3
10. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-06078 Rev. *A
Page 6 of 18
CY7C027V/028V
CY7C037V/038V
AC Test Loads and Waveforms
3.3V
3.3V
R
TH
= 250Ω
R1 = 590Ω
OUTPUT
C = 30 pF
OUTPUT
R1 = 590Ω
OUTPUT
C = 5 pF
C = 30 pF
R2 = 435Ω
R2 = 435Ω
V
TH
= 1.4V
(a) Normal Load (Load 1)
(c) Three-State Delay(Load 2)
(b) Thévenin Equivalent (Load 1)
(Used for tLZ, tHZ, tHZWE, & tLZWE
including scope and jig)
ALL INPUTPULSES
3.0V
GND
90%
90%
10%
3 ns
10%
3 ns
≤
≤
Switching Characteristics Over the Operating Range[11]
CY7C037V/038V
-20
-15
-25
Parameter
Description
Read Cycle Time
Min.
15
Max.
Min.
Max.
Min.
25
3
Max.
Unit
Read Cycle
tRC
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
Address to Data Valid
Output Hold From Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
15
20
25
tOHA
3
3
[12]
tACE
tDOE
tLZOE
15
10
20
12
25
13
[13, 14, 15]
[13, 14, 15]
3
3
0
3
3
0
3
3
0
tHZOE
OE HIGH to High Z
10
10
12
12
15
15
[13, 14, 15]
tLZCE
CE LOW to Low Z
[13, 14, 15]
tHZCE
CE HIGH to High Z
[15]
[15]
tPU
tPD
CE LOW to Power-Up
CE HIGH to Power-Down
Byte Enable Access Time
15
15
20
20
25
25
[12]
tABE
Write Cycle
tWC
Write Cycle Time
15
12
12
0
20
16
16
0
25
20
20
0
ns
ns
ns
ns
ns
ns
ns
[12]
tSCE
tAW
tHA
CE LOW to Write End
Address Valid to Write End
Address Hold From Write End
Address Set-Up to Write Start
Write Pulse Width
[12]
tSA
0
0
0
tPWE
12
10
17
12
22
15
tSD
Data Set-Up to Write End
Notes:
11. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
/I and 30-pF load capacitance.
I
OI OH
12. To access RAM, CE=L, UB=L, SEM=H. To access semaphore, CE=H and SEM=L. Either condition must be valid for the entire t
time.
SCE
13. At any given temperature and voltage condition for any given device, t
14. Test conditions used are Load 2.
is less than t
and t
is less than t
.
HZCE
LZCE
HZOE
LZOE
15. This parameter is guaranteed by design, but it is not production tested. For information on port-to-port delay through RAM cells from writing port to reading
port, refer to Read Timing with Busy waveform.
Document #: 38-06078 Rev. *A
Page 7 of 18
CY7C027V/028V
CY7C037V/038V
Switching Characteristics Over the Operating Range[11](continued)
CY7C037V/038V
-20
-15
-25
Parameter
tHD
tHZWE
Description
Data Hold From Write End
R/W LOW to High Z
Min.
Max.
Min.
Max.
Min.
Max.
Unit
ns
0
0
0
[14, 15]
[14 ,15]
10
12
15
ns
tLZWE
R/W HIGH to Low Z
3
3
3
ns
[41]
tWDD
Write Pulse to Data Delay
Write Data Valid to Read Data Valid
30
25
40
30
50
35
ns
[41]
tDDD
Busy Timing[16]
tBLA
ns
BUSY LOW from Address Match
BUSY HIGH from Address Mismatch
BUSY LOW from CE LOW
BUSY HIGH from CE HIGH
Port Set-Up for Priority
15
15
15
15
20
20
20
16
20
20
20
17
ns
ns
ns
ns
ns
ns
ns
ns
tBHA
tBLC
tBHC
tPS
5
0
5
0
5
0
tWB
R/W HIGH after BUSY (Slave)
R/W HIGH after BUSY HIGH (Slave)
BUSY HIGH to Data Valid
tWH
13
15
17
[18]
tBDD
Interrupt Timing[16]
15
20
25
tINS
INT Set Time
15
15
20
20
20
20
ns
ns
tINR
INT Reset Time
Semaphore Timing
tSOP
tSWRD
tSPS
SEM Flag Update Pulse (OE or SEM)
SEM Flag Write to Read Time
SEM Flag Contention Window
SEM Address Access Time
10
5
10
5
12
5
ns
ns
ns
ns
5
5
5
tSAA
15
20
25
Data Retention Mode
Timing
The CY7C027V/028V and CY7037V/038V are designed with
battery backup in mind. Data retention voltage and supply cur-
rent are guaranteed over temperature. The following rules en-
sure data retention:
Data Retention Mode
3.0V
V
CC
3.0V
V
CC
> 2.0V
t
RC
1. Chip enable (CE) must be held HIGH during data retention, with-
in VCC to VCC – 0.2V.
V
CC
to V – 0.2V
CC
V
IH
CE
2. CE must be kept between VCC – 0.2V and 70% of VCC
during the power-up and power-down transitions.
3. The RAM can begin operation >tRC after VCC reaches the min-
imum operating voltage (3.0 volts).
Parameter
Test Conditions[19]
Max.
Unit
ICCDR1
@ VCCDR = 2V
50
µA
16. For information on port-to-port delay through RAM cells from writing port
to reading port, refer to Read Timing with Busy waveform.
17. Test conditions used are Load 1.
18.
t
isacalculatedparameterandisthegreateroft
–t
(actual)ort –t
BDD
WDD PWE
DDD SD
(actual).
19. CE = V , V = GND to V , T = 25° C. This parameter is guaranteed
CC
in
CC
A
but not tested.
Document #: 38-06078 Rev. *A
Page 8 of 18
CY7C027V/028V
CY7C037V/038V
Switching Waveforms
Read Cycle No. 1 (Either Port Address Access)[20, 21, 22]
t
RC
ADDRESS
DATA OUT
t
AA
t
t
OHA
OHA
PREVIOUS DATAVALID
DATA VALID
Read Cycle No. 2 (Either Port CE/OE Access)[20, 23, 24]
t
ACE
CE and
LB or UB
t
HZCE
t
DOE
OE
t
HZOE
t
LZOE
DATA VALID
DATA OUT
t
LZCE
t
PU
t
PD
I
CC
CURRENT
I
SB
Read Cycle No. 3 (Either Port)[20, 22, 23, 24]
t
RC
ADDRESS
t
AA
t
OHA
UB or LB
t
t
HZCE
t
t
LZCE
LZCE
t
ABE
CE
HZCE
t
ACE
DATA OUT
Notes:
20. R/W is HIGH for read cycles.
21. Device is continuously selected CE = V and UB or LB = V . This waveform cannot be used for semaphore reads.
IL
IL
22. OE = V .
IL
23. Address valid prior to or coincident with CE transition LOW.
24. To access RAM, CE = V , UB or LB = V , SEM = V . To access semaphore, CE = V , SEM = V .
IL
IL
IH
IH
IL
Document #: 38-06078 Rev. *A
Page 9 of 18
CY7C027V/028V
CY7C037V/038V
Switching Waveforms(continued)
Write Cycle No. 1: R/W Controlled Timing[25, 26, 27, 28]
t
WC
ADDRESS
OE
[31]
t
HZOE
t
AW
[29,30]
CE
[28]
PWE
t
t
t
HA
SA
R/W
DATAOUT
DATA IN
[31]
HZWE
t
t
LZWE
NOTE 32
NOTE 32
t
t
HD
SD
Write Cycle No. 2: CE Controlled Timing[25, 26, 27, 33]
t
WC
ADDRESS
t
AW
[29,30]
CE
t
t
t
HA
SA
SCE
R/W
t
t
HD
SD
DATA IN
Notes:
25. R/W must be HIGH during all address transitions.
26. A write occurs during the overlap (t or t
) of a LOW CE or SEM and a LOW UB or LB.
PWE
SCE
27.
t
is measured from the earlier of CE or R/W or (SEM or R/W) going HIGH at the end of write cycle.
HA
28. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of t
or (t
+ t ) to allow the I/O drivers to turn off and data to be placed on
PWE
HZWE SD
the bus for the required t . If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified t
.
SD
PWE
29. To access RAM, CE = V , SEM = V
.
IL
IH
30. To access upper byte, CE = V , UB = V , SEM = V .
IL
IL
IH
To access lower byte, CE = V , LB = V , SEM = V .
IL
IL
IH
31. Transition is measured ±500 mV from steady state with a 5-pF load (including scope and jig). This parameter is sampled and not 100% tested.
32. During this period, the I/O pins are in the output state, and input signals must not be applied.
33. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high-impedance state.
Document #: 38-06078 Rev. *A
Page 10 of 18
CY7C027V/028V
CY7C037V/038V
Switching Waveforms(continued)
Semaphore Read After Write Timing, Either Side[34]
t
t
OHA
SAA
A0–A
VALID ADRESS
VALID ADRESS
2
t
AW
t
ACE
t
HA
SEM
t
t
SOP
SCE
t
SD
I/O
0
DATA VALID
DATA
VALID
IN
OUT
t
HD
t
t
PWE
SA
R/W
OE
t
t
DOE
SWRD
t
SOP
WRITE CYCLE
READ CYCLE
Timing Diagram of Semaphore Contention[35, 36, 37]
A
0L
–A
2L
MATCH
R/W
L
SEM
–A
L
t
SPS
A
MATCH
0R
2R
R/W
R
SEM
R
Notes:
34. CE = HIGH for the duration of the above timing (both write and read cycle).
35. I/O = I/O = LOW (request semaphore); CE = CE = HIGH.
0R
0L
R
L
36. Semaphores are reset (available to both ports) at cycle start.
37. If t is violated, the semaphore will definitely be obtained by one side or the other, but which side will get the semaphore is unpredictable.
SPS
Document #: 38-06078 Rev. *A
Page 11 of 18
CY7C027V/028V
CY7C037V/038V
Switching Waveforms(continued)
Timing Diagram of Read with BUSY (M/S=HIGH)[38]
t
WC
ADDRESS
R
MATCH
t
PWE
R/W
R
t
t
HD
SD
DATA IN
VALID
R
t
PS
ADDRESS
L
MATCH
t
BLA
t
BHA
BUSY
L
t
BDD
t
DDD
DATA
VALID
OUTL
t
WDD
Write Timing with Busy Input (M/S=LOW)
t
PWE
R/W
t
t
WH
WB
BUSY
Note:
38. CE = CE = LOW.
L
R
Document #: 38-06078 Rev. *A
Page 12 of 18
CY7C027V/028V
CY7C037V/038V
Switching Waveforms(continued)
Busy Timing Diagram No. 1 (CE Arbitration)[39]
CELValid First:
ADDRESS
L,R
ADDRESS MATCH
CE
L
t
PS
CE
R
t
t
BHC
BLC
BUSY
R
CER ValidFirst:
ADDRESS
ADDRESS MATCH
L,R
CE
R
t
PS
CE
L
L
t
t
BHC
BLC
BUSY
Busy Timing Diagram No. 2 (Address Arbitration)[39]
Left Address Valid First:
t
or t
WC
RC
ADDRESS
L
ADDRESS MATCH
ADDRESS MISMATCH
t
PS
ADDRESS
R
t
t
BHA
BLA
BUSY
R
Right AddressValid First:
t
or t
WC
RC
ADDRESS
R
ADDRESS MATCH
ADDRESS MISMATCH
t
PS
ADDRESS
L
t
t
BHA
BLA
BUSY
L
Note:
39. If t is violated, the busy signal will be asserted on one side or the other, but there is no guarantee to which side BUSY will be asserted.
PS
Document #: 38-06078 Rev. *A
Page 13 of 18
CY7C027V/028V
CY7C037V/038V
Switching Waveforms(continued)
Interrupt Timing Diagrams
Left Side Sets INT :
R
t
WC
ADDRESS
WRITE 7FFF (FFFF for CY7C028V/38V)
[40]
L
t
HA
CE
L
R/W
INT
L
R
[41]
t
INS
Right Side Clears INT :
R
t
RC
READ 7FFF
(FFFF for CY7C028V/38V)
ADDRESS
R
CE
R
[41]
t
INR
R/W
R
OE
R
INT
R
:
Right Side Sets INTL
t
WC
ADDRESS
WRITE 7FFE (FFFE for CY7C028V/38V)
[40]
R
t
HA
CE
R
R
R/W
INT
L
[41]
INS
t
Left Side Clears INT :
L
t
RC
READ 7FFE
(FFFF for CY7C028V/38V)
ADDRESS
CE
R
L
[41]
t
INR
R/W
L
OE
INT
L
L
Notes:
40.
41.
t
depends on which enable pin (CE or R/W ) is deasserted first.
HA L L
t
or t depends on which enable pin (CE or R/W ) is asserted last.
INS
INR
L
L
Document #: 38-06078 Rev. *A
Page 14 of 18
CY7C027V/028V
CY7C037V/038V
Table 1. Non-Contending Read/Write
Inputs
Outputs
CE
H
X
L
R/W
X
OE
X
X
X
X
X
L
UB
X
H
L
LB
X
H
H
L
SEM
H
H
H
H
H
H
H
H
X
I/O9–I/O17
High Z
I/O0–I/O8
High Z
Operation
Deselected: Power-Down
Deselected: Power-Down
Write to Upper Byte Only
Write to Lower Byte Only
Write to Both Bytes
X
High Z
High Z
L
Data In
High Z
High Z
L
L
H
L
Data In
Data In
High Z
L
L
L
Data In
Data Out
High Z
L
H
H
H
X
L
H
L
Read Upper Byte Only
Read Lower Byte Only
Read Both Bytes
L
L
H
L
Data Out
Data Out
High Z
L
L
L
Data Out
High Z
X
H
X
H
H
L
X
X
H
X
X
X
H
X
Outputs Disabled
H
H
L
Data Out
Data Out
Data In
Data Out
Data Out
Data In
Read Data in Semaphore Flag
Read Data in Semaphore Flag
Write DIN0 into Semaphore Flag
L
L
X
L
X
X
H
H
L
Data In
Data In
Write DIN0 into Semaphore Flag
L
L
X
X
X
X
L
X
L
L
L
Not Allowed
Not Allowed
X
Table 2. Interrupt Operation Example (assumes BUSYL=BUSYR=HIGH)[42]
Left Port
Right Port
Function
R/WL CEL
OEL
X
A0L–14L
7FFF
X
INTL R/WR CER
OER
X
A0R–14R
X
INTR
L[44]
H[43]
X
Set Right INTR Flag
Reset Right INTR Flag
Set Left INTL Flag
Reset Left INTL Flag
L
X
X
X
L
X
X
L
X
X
X
L
X
L
L
X
X
X
L
7FFF
7FFE
X
X
X
L[43]
H[44]
X
L
7FFE
X
X
X
Table 3. Semaphore Operation Example
Function I/O0–I/O17 Left I/O0–I/O17 Right
Status
No action
1
0
0
1
1
0
1
1
1
0
1
1
1
1
0
0
1
1
0
1
1
1
Semaphore free
Left Port has semaphore token
Left port writes 0 to semaphore
Right port writes 0 to semaphore
Left port writes 1 to semaphore
Left port writes 0 to semaphore
Right port writes 1 to semaphore
Left port writes 1 to semaphore
Right port writes 0 to semaphore
Right port writes 1 to semaphore
Left port writes 0 to semaphore
No change. Right side has no write access to semaphore
Right port obtains semaphore token
No change. Left port has no write access to semaphore
Left port obtains semaphore token
Semaphore free
Right port has semaphore token
Semaphore free
Left port has semaphore token
Semaphore free
Left port writes 1 to semaphore
Notes:
42.
A
and A
,FFFF/FFFE for the CY7C028V/038V.
0L–15L
0R–15R
43. If BUSY =L, then no change.
R
44. If BUSY =L, then no change.
L
Document #: 38-06078 Rev. *A
Page 15 of 18
CY7C027V/028V
CY7C037V/038V
Ordering Information
32K x16 3.3V Asynchronous Dual-Port SRAM
Speed
(ns)
Package
Operating
Range
Ordering Code
CY7C027V-15AC
Name
A100
A100
A100
A100
A100
A100
Package Type
15
20
25
100-Pin Thin Quad Flat Pack
Commercial
CY7C027V-15AXC
CY7C027V-20AC
CY7C027V-20AXC
CY7C027V-25AC
CY7C027V-25AXC
100-Pin Lead Free Thin Quad Flat Pack
100-Pin Thin Quad Flat Pack
Commercial
Commercial
Commercial
Commercial
Commercial
100-Pin Lead Free Thin Quad Flat Pack
100-Pin Thin Quad Flat Pack
100-Pin Lead Free Thin Quad Flat Pack
64K x16 3.3V Asynchronous Dual-Port SRAM
Speed
(ns)
Package
Name
Operating
Range
Ordering Code
CY7C028V-15AC
Package Type
15
A100
A100
A100
A100
A100
A100
A100
A100
100-Pin Thin Quad Flat Pack
Commercial
Commercial
Commercial
Commercial
Industrial
CY7C028V-15AXC
CY7C028V-20AC
CY7C028V-20AXC
CY7C028V-20AI
CY7C028V-20AXI
CY7C028V-25AC
CY7C028V-25AXC
100-Pin Lead Free Thin Quad Flat Pack
100-Pin Thin Quad Flat Pack
20
100-Pin Lead Free Thin Quad Flat Pack
100-Pin Thin Quad Flat Pack
100-Pin Lead Free Thin Quad Flat Pack
100-Pin Thin Quad Flat Pack
Industrial
25
Commercial
Commercial
100-Pin Lead Free Thin Quad Flat Pack
32K x18 3.3V Asynchronous Dual-Port SRAM
Speed
(ns)
Package
Operating
Range
Ordering Code
CY7C037V-15AC
Name
A100
A100
A100
A100
A100
A100
Package Type
100-Pin Thin Quad Flat Pack
15
20
25
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
CY7C037V-15AXC
CY7C037V-20AC
CY7C037V-20AXC
CY7C037V-25AC
CY7C037V-25AXC
100-Pin Lead Free Thin Quad Flat Pack
100-Pin Thin Quad Flat Pack
100-Pin Lead Free Thin Quad Flat Pack
100-Pin Thin Quad Flat Pack
100-Pin Lead Free Thin Quad Flat Pack
64K x18 3.3V Asynchronous Dual-Port SRAM
Speed
(ns)
Package
Name
Operating
Range
Ordering Code
CY7C038V-15AC
Package Type
15
A100
A100
A100
A100
A100
A100
A100
A100
100-Pin Thin Quad Flat Pack
Commercial
Commercial
Commercial
Commercial
Industrial
CY7C038V-15AXC
CY7C038V-20AC
CY7C038V-20AXC
CY7C038V-20AI
CY7C038V-20AXI
CY7C038V-25AC
CY7C038V-25AXC
100-Pin Lead Free Thin Quad Flat Pack
100-Pin Thin Quad Flat Pack
20
100-Pin Lead Free Thin Quad Flat Pack
100-Pin Thin Quad Flat Pack
100-Pin Lead Free Thin Quad Flat Pack
100-Pin Thin Quad Flat Pack
Industrial
25
Commercial
Commercial
100-Pin Lead Free Thin Quad Flat Pack
Document #: 38-06078 Rev. *A
Page 16 of 18
CY7C027V/028V
CY7C037V/038V
Package Diagram
100-Pin Thin Plastic Quad Flat Pack (TQFP) A100
100-Pin Lead(Pb)-Free Thin Plastic Quad Flat Pack (TQFP) A100
51-85048-*B
All product and company information mentioned in this document are trademarks of their respective holders.
Document #: 38-06078 Rev. *A
Page 17 of 18
© Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY7C027V/028V
CY7C037V/038V
Document History Page
Document Title: CY7C027V/CY7C028V/CY7C037V/CY7C038V 3.3V 32K/64K x 16/18 Dual Port Static RAM
Document Number: 38-06078
Orig. of
REV.
ECN NO. Issue Date Change
Description of Change
**
237626
6/30/04
YDT
JHX
Converted data sheet from old spec 38-00670 to conform with new data
sheet. Removed cross information from features section
*A
259110
See ECN
Added Lead(Pb)-Free packaging information.
Document #: 38-06078 Rev. *A
Page 18 of 18
相关型号：
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