CY7B992 [CYPRESS]
Programmable Skew Clock Buffer; 可编程偏移时钟缓冲器
| 型号： | CY7B992 |
| 厂家： | 
CYPRESS |
| 描述： | Programmable Skew Clock Buffer |
| 文件： | 总15页 (文件大小：290K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
92
CY7B991
CY7B992
Programmable Skew Clock Buffer
functions. These multiple-output clock drivers provide the sys-
tem integrator with functions necessary to optimize the timing
of high-performance computer systems. Eight individual driv-
ers, arranged as four pairs of user-controllable outputs, can
each drive terminated transmission lines with impedances as
low as 50Ω while delivering minimal and specified output skews
and full-swing logic levels (CY7B991 TTL or CY7B992 CMOS).
Features
• All output pair skew <100 ps typical (250 max.)
• 3.75- to 80-MHz output operation
• User-selectable output functions
— Selectable skew to 18 ns
— Inverted and non-inverted
— Operation at 1⁄2 and 1⁄4 input frequency
Each output can be hardwired to one of nine delay or function
configurations. Delay increments of 0.7 to 1.5 ns are deter-
mined by the operating frequency with outputs able to skew up
to ±6 time units from their nominal “zero” skew position. The com-
pletely integrated PLL allows external load and transmission line
delay effects to be canceled. When this “zero delay”capability of the
PSCB is combined with the selectable output skew functions, the
user can create output-to-output delays of up to ±12 time units.
— Operation at 2x and 4x input frequency (input as low
as 3.75 MHz)
• Zero input to output delay
• 50% duty-cycle outputs
• Outputs drive 50Ω terminated lines
• Low operating current
• 32-pin PLCC/LCC package
Divide-by-two and divide-by-four output functions are provided
for additional flexibility in designing complex clock systems.
When combined with the internal PLL, these divide functions
allow distribution of a low-frequency clock that can be multi-
plied by two or four at the clock destination. This facility mini-
mizes clock distribution difficulty while allowing maximum sys-
tem clock speed and flexibility.
• Jitter < 200 ps peak-to-peak (< 25 ps RMS)
• Compatible with a Pentium™-based processor
Functional Description
The CY7B991 and CY7B992 Programmable Skew Clock Buff-
ers (PSCB) offer user-selectable control over system clock
Logic Block Diagram
Pin Configuration
TEST
PLCC/LCC
PHASE
FREQ
DET
FB
VCO AND
TIME UNIT
GENERATOR
FILTER
REF
4
3
2
1
32 31 30
29
FS
2F0
GND
1F1
1F0
5
6
3F1
4F0
28
27
4Q0
4Q1
4F0
4F1
4F1
7
8
9
SELECT
INPUTS
(THREE
LEVEL)
V
26
25
24
23
CCQ
CY7B991
CY7B992
V
CCN
SKEW
SELECT
MATRIX
V
CCN
3Q0
3Q1
3F0
3F1
4Q1
10
1Q0
1Q1
GND
GND
4Q0
GND
GND
11
12
22
21
2Q0
2Q1
2F0
2F1
13
14 15 16 17 18 19 20
1Q0
1Q1
1F0
1F1
7B991–2
7B991–1
Pentium is a trademark of Intel Corporation.
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Document #: 38-07138 Rev. **
Revised September 26, 2001
CY7B991
CY7B992
Pin Definitions
Signal
Name
I/O
Description
REF
I
Reference frequency input. This inputsupplies the frequency and timingagainst whichallfunctional
variation is measured.
FB
I
PLL feedback input (typically connected to one of the eight outputs).
Three-level frequency range select. See Table 1.
Three-level function select inputs for output pair 1 (1Q0, 1Q1). See Table 2.
Three-level function select inputs for output pair 2 (2Q0, 2Q1). See Table 2.
Three-level function select inputs for output pair 3 (3Q0, 3Q1). See Table 2.
Three-level function select inputs for output pair 4 (4Q0, 4Q1). See Table 2.
Three-level select. See test mode section under the block diagram descriptions.
Output pair 1. See Table 2.
FS
I
1F0, 1F1
2F0, 2F1
3F0, 3F1
4F0, 4F1
TEST
I
I
I
I
I
1Q0, 1Q1
2Q0, 2Q1
3Q0, 3Q1
4Q0, 4Q1
VCCN
O
O
Output pair 2. See Table 2.
O
Output pair 3. See Table 2.
O
Output pair 4. See Table 2.
PWR
PWR
PWR
Power supply for output drivers.
VCCQ
Power supply for internal circuitry.
GND
Ground.
(xF0, xF1) inputs. Table 2 below shows the nine possible out-
Block Diagram Description
put functions for each section as determined by the function
select inputs. All times are measured with respect to the REF
input assuming that the output connected to the FB input has
0tU selected.
Phase Frequency Detector and Filter
These two blocks accept inputs from the reference frequency
(REF) input and the feedback (FB) input and generate correc-
tion information to control the frequency of the Voltage-Con-
trolled Oscillator (VCO). These blocks, along with the VCO,
form a Phase-Locked Loop (PLL) that tracks the incoming
REF signal.
Table 2. Programmable Skew Configurations[1]
Function Selects
Output Functions
1F1, 2F1, 1F0, 2F0, 1Q0,1Q1,
3F1, 4F1 3F0, 4F0 2Q0, 2Q1 3Q0, 3Q1 4Q0, 4Q1
VCO and Time Unit Generator
LOW
LOW
LOW
MID
LOW
MID
–4tU
–3tU
–2tU
–1tU
0tU
Divide by 2 Divide by 2
The VCO accepts analog control inputs from the PLL filter
block and generates a frequency that is used by the time unit
generator to create discrete time units that are selected in the
skew select matrix. The operational range of the VCO is de-
termined by the FS control pin. The time unit (tU) is determined
by the operating frequency of the device and the level of the
FS pin as shown in Table 1.
–6tU
–4tU
–2tU
0tU
–6tU
–4tU
–2tU
0tU
HIGH
LOW
MID
MID
MID
HIGH
LOW
MID
+1tU
+2tU
+3tU
+4tU
+2tU
+4tU
+6tU
+2tU
+4tU
+6tU
Table 1. Frequency Range Select and tU Calculation[1]
HIGH
HIGH
fNOM (MHz)
1
tU = -----------------------
Approximate
Frequency(MHz)At
Which tU = 1.0 ns
HIGH
HIGH
Divide by 4 Inverted
f
NOM × N
FS[2, 3] Min. Max.
where N =
Notes:
1. For all three-state inputs, HIGH indicates a connection to VCC, LOW
indicates a connection to GND, and MID indicates an open connection.
Internal termination circuitry holds an unconnected input to VCC/2.
2. The level to be set on FS is determined by the “normal” operating fre-
quency (fNOM) of the VCO and Time Unit Generator (see Logic Block
Diagram). Nominal frequency (fNOM) always appears at 1Q0 and the
other outputs when they are operated in their undivided modes (see
Table 2). The frequency appearing at the REF and FB inputs will be fNOM
when the output connected to FB is undivided. The frequency of the REF
and FB inputs will be fNOM/2 or fNOM/4 when the part is configured for a
frequency multiplication by using a divided output as the FB input.
3. When the FS pin is selected HIGH, the REF input must not transition
upon power-up until VCC has reached 4.3V.
LOW
MID
15
25
40
30
50
80
44
26
16
22.7
38.5
62.5
HIGH
Skew Select Matrix
The skew select matrix is comprised of four independent sec-
tions. Each section has two low-skew, high-fanout drivers
(xQ0, xQ1), and two corresponding three-level function select
Document #: 38-07138 Rev. **
Page 2 of 15
CY7B991
CY7B992
FBInput
REFInput
1Fx
2Fx
3Fx
4Fx
(N/A)
LM
– 6t
– 4t
– 3t
U
U
U
LL
LH
LM
(N/A)
LH
ML
ML
– 2t
– 1t
U
U
(N/A)
MM
MH
HL
MM
(N/A)
MH
0t
U
U
U
U
+1t
+2t
+3t
HM
(N/A)
HH
HL
HM
+4t
+6t
U
U
(N/A)
(N/A)
(N/A)
LL/HH
HH
DIVIDED
INVERT
7B991–3
Figure 1. Typical Outputs with FB Connected to a Zero-Skew Output[4]
Ambient Temperature with
Test Mode
Power Applied ............................................ –55°C to +125°C
Supply Voltage to Ground Potential ...............–0.5V to +7.0V
DC Input Voltage ............................................–0.5V to +7.0V
Output Current into Outputs (LOW)............................. 64 mA
The TEST input is a three-level input. In normal system oper-
ation, this pin is connected to ground, allowing the
CY7B991/CY7B992 to operate as explained briefly above (for
testing purposes, any of the three-level inputs can have a re-
movable jumper to ground, or be tied LOW through a 100Ω
resistor. This will allow an external tester to change the state
of these pins.)
Static Discharge Voltage ........................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current..................................................... >200 mA
If the TEST input is forced to its MID or HIGH state, the device
will operate with its internal phase locked loop disconnected,
and input levels supplied to REF will directly control all outputs.
Relative output to output functions are the same as in normal
mode.
Operating Range
Ambient
Range
Commercial
Industrial
Temperature
VCC
In contrast with normal operation (TEST tied LOW). All outputs
will function based only on the connection of their own function
select inputs (xF0 and xF1) and the waveform characteristics
of the REF input.
0°C to +70°C
5V ± 10%
5V ± 10%
5V ± 10%
–40°C to +85°C
–55°C to +125°C
Military[5]
Maximum Ratings
Notes:
4. FB connected to an output selected for “zero” skew (i.e., xF1 = xF0 =
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
MID).
5. Indicates case temperature.
Storage Temperature .................................–65°C to +150°C
Document #: 38-07138 Rev. **
Page 3 of 15
CY7B991
CY7B992
Electrical Characteristics Over the Operating Range[6]
CY7B991
CY7B992
Parameter
Description
Test Conditions
VCC = Min., IOH = –16 mA
VCC = Min., IOH =–40 mA
VCC = Min., IOL = 46 mA
VCC = Min., IOL = 46 mA
Min.
Max.
Min.
Max.
Unit
VOH
Output HIGH Voltage
2.4
V
VCC–0.75
VOL
Output LOW Voltage
0.45
V
0.45
VCC
VIH
VIL
Input HIGH Voltage
(REF and FB inputs only)
2.0
–0.5
VCC
0.8
VCC
–
V
V
1.35
Input LOW Voltage
(REF and FB inputs only)
–0.5
1.35
VCC
VIHH
VIMM
VILL
IIH
Three-Level Input HIGH
Voltage (Test, FS, xFn)[7]
Min. ≤ VCC ≤ Max.
Min. ≤ VCC ≤ Max.
Min. ≤ VCC ≤ Max.
VCC – 0.85
VCC
VCC – 0.85
V
Three-Level Input MID
VCC/2 –
500 mV
VCC/2 +
500 mV
VCC/2 –
500 mV
VCC/2 +
500 mV
V
Voltage (Test, FS, xFn)[7]
Three-Level Input LOW
Voltage (Test, FS, xFn)[7]
0.0
–500
–50
0.85
0.0
–500
–50
0.85
V
InputHIGHLeakageCurrent VCC = Max., VIN = Max.
(REF and FB inputs only)
10
10
µA
µA
µA
µA
µA
mA
mA
IIL
Input LOW Leakage Current VCC = Max., VIN = 0.4V
(REF and FB inputs only)
IIHH
IIMM
IILL
Input HIGH Current
(Test, FS, xFn)
VIN = VCC
VIN = VCC/2
VIN = GND
200
50
200
50
Input MID Current
(Test, FS, xFn)
Input LOW Current
(Test, FS, xFn)
–200
–250
–200
N/A
IOS
Output Short Circuit
Current[8]
VCC = Max., VOUT
= GND (25°C only)
ICCQ
Operating Current Used by VCCN = VCCQ
Internal Circuitry
=
Com’l
85
90
85
90
Max., All Input
Selects Open
Mil/Ind
ICCN
Output Buffer Current per
Output Pair[9]
VCCN = VCCQ = Max.,
IOUT = 0 mA
14
19
mA
Input Selects Open, fMAX
PD
Power Dissipation per
Output Pair[10]
VCCN = VCCQ = Max.,
IOUT = 0 mA
78
104[11]
mW
Input Selects Open, fMAX
Notes:
6. See the last page of this specification for Group A subgroup testing information.
7. These inputs are normally wired to VCC, GND, or left unconnected (actual threshold voltages vary as a percentage of VCC). Internal termination resistors hold
unconnected inputs at VCC/2. If these inputs are switched, the function and timing of the outputs may glitch and the PLL may require an additional tLOCK time
before all datasheet limits are achieved.
8. CY7B991 should be tested one output at a time, output shorted for less than one second, less than 10% duty cycle. Room temperature only. CY7B992 outputs
should not be shorted to GND. Doing so may cause permanent damage.
9. Total output current per output pair can be approximated by the following expression that includes device current plus load current:
CY7B991: ICCN = [(4 + 0.11F) + [((835 – 3F)/Z) + (.0022FC)]N] x 1.1
CY7B992: ICCN = [(3.5+ 0.17F) + [((1160 – 2.8F)/Z) + (.0025FC)]N] x 1.1
Where
F = frequency in MHz
C = capacitive load in pF
Z = line impedance in ohms
N = number of loaded outputs; 0, 1, or 2
FC = F < C
10. Total power dissipation per output pair can be approximated by the following expression that includes device power dissipation plus power dissipation due to
the load circuit:
CY7B991: PD = [(22 + 0.61F) + [((1550 – 2.7F)/Z) + (.0125FC)]N] x 1.1
CY7B992: PD = [(19.25+ 0.94F) + [((700 + 6F)/Z) + (.017FC)]N] x 1.1
See note 9 for variable definition.
11. CMOS output buffer current and power dissipation specified at 50-MHz reference frequency.
Document #: 38-07138 Rev. **
Page 4 of 15
CY7B991
CY7B992
Capacitance[12]
Parameter
Description
Test Conditions
Max.
Unit
CIN
Input Capacitance
TA = 25°C, f = 1 MHz, VCC = 5.0V
10
pF
Note:
12. Applies to REF and FB inputs only. Tested initially and after any design or process changes that may affect these parameters.
AC Test Loads and Waveforms
5V
3.0V
2.0V
=1.5V
0.8V
2.0V
=1.5V
0.8V
R1=130
R2=91
R1
R2
V
th
V
th
C = 50 pF (C =30 pF for –2 and –5 devices)
L
L
0.0V
C
(Includes fixture and probe capacitance)
L
≤1ns
≤1ns
7B991–4
7B991–5
TTL ACTest Load (CY7B991)
TTL Input Test Waveform (CY7B991)
V
CC
V
CC
R1=100
R2=100
80%
80%
= V /2
20%
R1
C = 50 pF (C =30 pF for –2 and –5 devices)
L
L
V
= V /2
V
th
CC
th
CC
(Includes fixture and probe capacitance)
20%
0.0V
C
L
R2
≤3ns
≤3ns
7B991–6
7B991–7
CMOS AC Test Load (CY7B992)
CMOS Input Test Waveform (CY7B992)
Document #: 38-07138 Rev. **
Page 5 of 15
CY7B991
CY7B992
Switching Characteristics Over the Operating Range[2, 13]
CY7B991–2[14]
CY7B992–2[14]
Parameter
Description
Min.
Typ.
Max.
Min.
Typ.
Max.
Unit
fNOM
Operating Clock
Frequency in MHz
FS = LOW[1, 2]
FS = MID[1, 2]
FS = HIGH[1, 2 , 3]
15
25
30
50
80
15
30
MHz
25
40
50
80[15]
40
tRPWH
tRPWL
tU
REF Pulse Width HIGH
REF Pulse Width LOW
Programmable Skew Unit
5.0
5.0
5.0
ns
ns
5.0
See Table 1
tSKEWPR
Zero Output Matched-Pair Skew
(XQ0, XQ1)[16, 17]
0.05
0.20
0.05
0.20
ns
tSKEW0
tSKEW1
Zero Output Skew (All Outputs)[16, 18,19]
0.1
0.25
0.5
0.1
0.25
0.5
ns
ns
Output Skew (Rise-Rise, Fall-Fall, Same
Class Outputs)[16, 20]
0.25
0.25
tSKEW2
tSKEW3
tSKEW4
Output Skew (Rise-Fall, Nominal-Inverted,
Divided-Divided)[16, 20]
0.3
0.25
0.5
0.5
0.5
0.9
0.3
0.25
0.5
0.5
0.5
0.7
ns
ns
ns
Output Skew (Rise-Rise, Fall-Fall, Different
Class Outputs)[16, 20]
Output Skew (Rise-Fall, Nominal-Divided,
Divided-Inverted)[16, 20]
tDEV
Device-to-Device Skew[14, 21]
Propagation Delay, REF Rise to FB Rise
Output Duty Cycle Variation[22]
Output HIGH Time Deviation from 50%[23, 24]
Output LOW Time Deviation from 50%[23, 24]
Output Rise Time[23, 25]
0.75
+0.25
+0.65
2.0
0.75
+0.25
+0.5
3.0
ns
ns
ns
ns
ns
ns
ns
ms
ps
ps
tPD
–0.25
–0.65
0.0
0.0
–0.25
–0.5
0.0
0.0
tODCV
tPWH
tPWL
tORISE
tOFALL
tLOCK
tJR
1.5
3.0
0.15
0.15
1.0
1.0
1.2
0.5
0.5
2.0
2.0
2.5
Output Fall Time[23, 25]
PLL Lock Time[26]
1.2
2.5
0.5
0.5
Cycle-to-Cycle Output
Jitter
RMS[14]
Peak-to-Peak[14]
25
25
200
200
Note:
13. Test measurement levels for the CY7B991 are TTL levels (1.5V to 1.5V). Test measurement levels for the CY7B992 are CMOS levels (VCC/2 to VCC/2). Test
conditions assume signal transition times of 2 ns or less and output loading as shown in the AC Test Loads and Waveforms unless otherwise specified.
14. Guaranteed by statistical correlation. Tested initially and after any design or process changes that may affect these parameters.
15. Except as noted, all CY7B992–2 and –5 timing parameters are specified to 80-MHz with a 30-pF load.
16. SKEW is defined as the time between the earliest and the latest output transition among all outputs for which the same tU delay has been selected when all are
loaded with 50 pF and terminated with 50Ω to 2.06V (CY7B991) or VCC/2 (CY7B992).
17. tSKEWPR is defined as the skew between a pair of outputs (XQ0 and XQ1) when all eight outputs are selected for 0tU.
18.
tSKEW0 is defined as the skew between outputs when they are selected for 0tU. Other outputs are divided or inverted but not shifted.
19. CL=0 pF. For CL=30 pF, tSKEW0=0.35 ns.
20. There are three classes of outputs: Nominal (multiple of tU delay), Inverted (4Q0 and 4Q1 only with 4F0 = 4F1 = HIGH), and Divided (3Qx and 4Qx only in Divide-by-2
or Divide-by-4 mode).
21. tDEV is the output-to-output skew between any two devices operating under the same conditions (VCC ambient temperature, air flow, etc.)
22. tODCV is the deviation of the output from a 50% duty cycle. Output pulse width variations are included in tSKEW2 and tSKEW4 specifications.
23. Specified with outputs loaded with 30 pF for the CY7B99X–2 and –5 devices and 50 pF for the CY7B99X–7 devices. Devices are terminated through 50Ω to
2.06V (CY7B991) or VCC/2 (CY7B992).
24. tPWH is measured at 2.0V for the CY7B991 and 0.8 VCC for the CY7B992. tPWL is measured at 0.8V for the CY7B991 and 0.2 VCC for the CY7B992.
25.
tORISE and tOFALL measured between 0.8V and 2.0V for the CY7B991 or 0.8VCC and 0.2VCC for the CY7B992.
26. tLOCK is the time that is required before synchronization is achieved. This specification is valid only after VCC is stable and within normal operating limits. This parameter
is measured from the application of a new signal or frequency at REF or FB until tPD is within specified limits.
Document #: 38-07138 Rev. **
Page 6 of 15
CY7B991
CY7B992
Switching Characteristics Over the Operating Range[2, 13] (continued)
CY7B991–5
CY7B992–5
Parameter
Description
Min.
15
Typ.
Max.
30
Min.
15
Typ.
Max.
30
Unit
fNOM
Operating Clock
FS = LOW[1, 2]
FS = MID[1, 2]
MHz
Frequency in MHz
25
50
25
50
FS = HIGH[1, 2 , 3]
40
80
40
80[15]
tRPWH
tRPWL
tU
REF Pulse Width HIGH
REF Pulse Width LOW
Programmable Skew Unit
5.0
5.0
5.0
5.0
ns
ns
See Table 1
tSKEWPR
Zero Output Matched-Pair Skew
(XQ0, XQ1)[16, 17]
0.1
0.25
0.1
0.25
ns
tSKEW0
tSKEW1
Zero Output Skew (All Outputs)[16, 18]
0.25
0.6
0.5
0.7
0.25
0.6
0.5
0.7
ns
ns
Output Skew (Rise-Rise, Fall-Fall, Same
Class Outputs)[16, 20]
tSKEW2
tSKEW3
tSKEW4
Output Skew (Rise-Fall, Nominal-Inverted,
Divided-Divided)[16, 20]
0.5
0.5
0.5
1.0
0.7
1.0
0.6
0.5
0.6
1.5
0.7
1.7
ns
ns
ns
Output Skew (Rise-Rise, Fall-Fall, Different
Class Outputs)[16, 20]
Output Skew (Rise-Fall, Nominal-Divided,
Divided-Inverted)[16, 20]
tDEV
Device-to-Device Skew[14, 21]
Propagation Delay, REF Rise to FB Rise
Output Duty Cycle Variation[22]
Output HIGH Time Deviation from 50%[23, 24]
Output LOW Time Deviation from 50%[23, 24]
Output Rise Time[23, 25]
1.25
+0.5
+1.0
2.5
3
1.25
+0.5
+1.2
4.0
ns
ns
ns
ns
ns
ns
ns
ms
ps
ps
tPD
–0.5
–1.0
0.0
0.0
–0.5
–1.2
0.0
0.0
tODCV
tPWH
tPWL
tORISE
tOFALL
tLOCK
tJR
4.0
0.15
0.15
1.0
1.0
1.5
1.5
0.5
25
0.5
0.5
2.0
2.0
3.5
Output Fall Time[23, 25]
3.5
PLL Lock Time[26]
0.5
Cycle-to-Cycle Output
Jitter
RMS[14]
25
Peak-to-Peak[14]
200
200
Document #: 38-07138 Rev. **
Page 7 of 15
CY7B991
CY7B992
Switching Characteristics Over the Operating Range[2, 13] (continued)
CY7B991–7
CY7B992–7
Parameter
Description
Min.
15
Typ.
Max.
30
Min.
15
Typ.
Max.
Unit
fNOM
Operating Clock
FS = LOW[1, 2]
FS = MID[1, 2]
FS = HIGH[1, 2]
30
MHz
Frequency in MHz
25
50
25
50
80[15]
40
80
40
tRPWH
tRPWL
tU
REF Pulse Width HIGH
REF Pulse Width LOW
Programmable Skew Unit
5.0
5.0
5.0
5.0
ns
ns
See Table 1
tSKEWPR
Zero Output Matched-Pair Skew
(XQ0, XQ1)[16, 17]
0.1
0.25
0.1
0.25
ns
tSKEW0
tSKEW1
Zero Output Skew (All Outputs)[16, 18]
0.3
0.6
0.75
1.0
0.3
0.6
0.75
1.0
ns
ns
Output Skew (Rise-Rise, Fall-Fall, Same
Class Outputs)[16, 20]
tSKEW2
tSKEW3
tSKEW4
Output Skew (Rise-Fall, Nominal-Inverted,
Divided-Divided)[16, 20]
1.0
0.7
1.2
1.5
1.2
1.7
1.0
0.7
1.2
1.5
1.2
1.7
ns
ns
ns
Output Skew (Rise-Rise, Fall-Fall, Different
Class Outputs)[16, 20]
Output Skew (Rise-Fall, Nominal-Divided,
Divided-Inverted)[16, 20]
tDEV
Device-to-Device Skew[14, 21]
Propagation Delay, REF Rise to FB Rise
Output Duty Cycle Variation[22]
Output HIGH Time Deviation from 50%[23, 24]
Output LOW Time Deviation from 50%[23, 24]
Output Rise Time[23, 25]
1.65
+0.7
+1.2
3
1.65
+0.7
+1.5
5.5
ns
ns
ns
ns
ns
ns
ns
ms
ps
ps
tPD
–0.7
–1.2
0.0
0.0
–0.7
–1.5
0.0
0.0
tODCV
tPWH
tPWL
tORISE
tOFALL
tLOCK
tJR
3.5
2.5
2.5
0.5
25
5.5
0.15
0.15
1.5
1.5
0.5
0.5
3.0
3.0
5.0
Output Fall Time[23, 25]
PLL Lock Time[26]
5.0
0.5
Cycle-to-Cycle Output
Jitter
RMS[14]
Peak-to-Peak[14]
25
200
200
Document #: 38-07138 Rev. **
Page 8 of 15
CY7B991
CY7B992
AC Timing Diagrams
t
t
RPWL
REF
t
RPWH
REF
t
t
ODCV
PD
t
ODCV
FB
Q
t
JR
t
t
t
t
SKEWPR,
SKEW0,1
SKEWPR,
SKEW0,1
OTHERQ
t
SKEW2
t
SKEW2
INVERTED Q
t
SKEW3,4
t
t
SKEW3,4
t
SKEW3,4
REF DIVIDED BY 2
REF DIVIDED BY 4
t
SKEW1,3, 4
SKEW2,4
7B991–8
Document #: 38-07138 Rev. **
Page 9 of 15
CY7B991
CY7B992
Operational Mode Descriptions
REF
LOAD
Z
Z
0
L1
L2
FB
SYSTEM
CLOCK
REF
FS
LOAD
LOAD
4Q0
4Q1
4F0
4F1
0
3Q0
3Q1
3F0
3F1
L3
L4
2F0
2F1
2Q0
2Q1
Z
0
1F0
1F1
1Q0
1Q1
LOAD
TEST
Z
0
LENGTH L1 = L2 = L3 = L4
7B991–9
Figure 2. Zero-Skew and/or Zero-Delay Clock Driver
Figure 2 shows the PSCB configured as a zero-skew clock
buffer. In this mode the 7B991/992 can be used as the basis
for a low-skew clock distribution tree. When all of the function
select inputs (xF0, xF1) are left open, the outputs are aligned
and may each drive a terminated transmission line to an inde-
pendent load. The FB input can be tied to any output in this
configuration and the operating frequency range is selected
with the FS pin. The low-skew specification, coupled with the
ability to drive terminated transmission lines (with impedances
as low as 50 ohms), allows efficient printed circuit board de-
sign.
REF
LOAD
Z
0
L1
L2
FB
REF
FS
SYS–
TEM
CLOCK
LOAD
LOAD
4Q0
4Q1
4F0
4F1
Z
0
3Q0
3Q1
3F0
3F1
L3
L4
2F0
2F1
2Q0
2Q1
Z
0
1F0
1F1
1Q0
1Q1
LOAD
TEST
Z
0
LENGTH L1 = L2
L3 < L2 by 6 inches
L4 > L2 by 6 inches
7B991–10
Figure 3. Programmable-Skew Clock Driver
Figure 3 shows a configuration to equalize skew between met-
al traces of different lengths. In addition to low skew between
outputs, the PSCB can be programmed to stagger the timing
of its outputs. The four groups of output pairs can each be
programmed to different output timing. Skew timing can be
adjusted over a wide range in small increments with the appro-
priate strapping of the function select pins. In this configuration
the 4Q0 output is fed back to FB and configured for zero skew.
The other three pairs of outputs are programmed to yield dif-
ferent skews relative to the feedback. By advancing the clock
signal on the longer traces or retarding the clock signal on
shorter traces, all loads can receive the clock pulse at the
same time.
In this illustration the FB input is connected to an output with
0-ns skew (xF1, xF0 = MID) selected. The internal PLL syn-
chronizes the FB and REF inputs and aligns their rising edges
to insure that all outputs have precise phase alignment.
Clock skews can be advanced by ±6 time units (tU) when using
an output selected for zero skew as the feedback. A wider range of
delays is possible if the output connected to FB is also skewed.
Since “Zero Skew”, +tU, and –tU are defined relative to output
groups, and since the PLL aligns the rising edges of REF and FB,
it is possible to create wider output skews by proper selection of the
xFn inputs. For example a +10 tU between REF and 3Qx can be
achieved by connecting 1Q0 to FB and setting 1F0 = 1F1 = GND,
Document #: 38-07138 Rev. **
Page 10 of 15
CY7B991
CY7B992
3F0 = MID, and 3F1 = High. (Since FB aligns at –4 tU and 3Qx
skews to +6 tU, a total of +10 tU skew is realized.) Many other con-
figurations can be realized by skewing both the output used as the
FB input and skewing the other outputs.
form at these outputs. Note that the 20- and 40-MHz clocks fall
simultaneously and are out of phase on their rising edge. This
will allow the designer to use the rising edges of the 1⁄2 fre-
1
quency and
⁄ frequency outputs without concern for ris-
4
ing-edge skew. The 2Q0, 2Q1, 1Q0, and 1Q1 outputs run at
80 MHz and are skewed by programming their select inputs
accordingly. Note that the FS pin is wired for 80-MHz operation
because that is the frequency of the fastest output.
REF
FB
REF
REF
FS
4Q0
4F0
4F1
FB
REF
20 MHz
4Q1
FS
3Q0
3Q1
3F0
3F1
10 MHz
4Q0
4F0
4Q1
4F1
2Q0
2Q1
2F0
2F1
5 MHz
3Q0
3Q1
3F0
3F1
1Q0
1Q1
1F0
1F1
20 MHz
2Q0
2Q1
2F0
2F1
TEST
1F0
1F1
1Q0
1Q1
7B991–11
Figure 4. Inverted Output Connections
TEST
7B991–13
Figure 4 shows an example of the invert function of the PSCB.
In this example the 4Q0 output used as the FB input is pro-
grammed for invert (4F0 = 4F1 = HIGH) while the other three
pairs of outputs are programmed for zero skew. When 4F0 and
4F1 are tied high, 4Q0 and 4Q1 become inverted zero phase
outputs. The PLL aligns the rising edge of the FB input with the
rising edge of the REF. This causes the 1Q, 2Q, and 3Q out-
puts to become the “inverted” outputs with respect to the REF
input. By selecting which output is connect to FB, it is possible
to have 2 inverted and 6 non-inverted outputs or 6 inverted and
2 non-inverted outputs. The correct configuration would be de-
termined by the need for more (or fewer) inverted outputs. 1Q,
2Q, and 3Q outputs can also be skewed to compensate for
varying trace delays independent of inversion on 4Q.
Figure 6. Frequency Divider Connections
Figure 6 demonstrates the PSCB in a clock divider application.
2Q0 is fed back to the FB input and programmed for zero skew.
3Qx is programmed to divide by four. 4Qx is programmed to
divide by two. Note that the falling edges of the 4Qx and 3Qx
outputs are aligned. This allows use of the rising edges of the
1
1
⁄
frequency and ⁄ frequency without concern for skew
2
4
mismatch. The 1Qx outputs are programmed to zero skew and
are aligned with the 2Qx outputs. In this example, the FS input
is grounded to configure the device in the 15- to 30-MHz range
since the highest frequency output is running at 20 MHz.
Figure 7 shows some of the functions that are selectable on
the 3Qx and 4Qx outputs. These include inverted outputs and
outputs that offer divide-by-2 and divide-by-4 timing. An invert-
ed output allows the system designer to clock different sub-
systems on opposite edges, without suffering from the pulse
asymmetry typical of non-ideal loading. This function allows
the two subsystems to each be clocked 180 degrees out of
phase, but still to be aligned within the skew spec.
REF
FB
20 MHz
REF
FS
40 MHz
4Q0
4Q1
The divided outputs offer a zero-delay divider for portions of
the system that need the clock to be divided by either two or
four, and still remain within a narrow skew of the “1X” clock.
Without this feature, an external divider would need to be add-
ed, and the propagation delay of the divider would add to the
skew between the different clock signals.
4F0
4F1
20 MHz
80 MHz
3Q0
3Q1
3F0
3F1
2F0
2F1
2Q0
2Q1
1Q0
1Q1
1F0
1F1
TEST
These divided outputs, coupled with the Phase Locked Loop,
allow the PSCB to multiply the clock rate at the REF input by
either two or four. This mode will enable the designer to dis-
tribute a low-frequency clock between various portions of the
system, and then locally multiply the clock rate to a more suit-
able frequency, while still maintaining the low-skew character-
istics of the clock driver. The PSCB can perform all of the func-
tions described above at the same time. It can multiply by two
and four or divide by two (and four) at the same time that it is
shifting its outputs over a wide range or maintaining zero skew
between selected outputs.
7B991–12
Figure 5. Frequency Multiplier with Skew Connections
Figure 5 illustrates the PSCB configured as a clock multiplier.
The 3Q0 output is programmed to divide by four and is fed
back to FB. This causes the PLL to increase its frequency until
the 3Q0 and 3Q1 outputs are locked at 20 MHz while the 1Qx
and 2Qx outputs run at 80 MHz. The 4Q0 and 4Q1 outputs are
programmed to divide by two, which results in a 40-MHz wave-
Document #: 38-07138 Rev. **
Page 11 of 15
CY7B991
CY7B992
REF
LOAD
Z
0
80-MHz
INVERTED
FB
REF
FS
20–MHz
DISTRIBUTION
CLOCK
LOAD
LOAD
4Q0
4Q1
4F0
4F1
20-MHz
Z
0
3Q0
3Q1
2Q0
2Q1
3F0
3F1
2F0
2F1
80-MHz
ZERO SKEW
Z
0
1Q0
1Q1
1F0
LOAD
80-MHz
SKEWED –3.125 ns (–4t )
1F1
TEST
U
Z
0
7B991–14
Figure 7. Multi-Function Clock Driver
LOAD
LOAD
REF
Z
0
L1
FB
SYSTEM
CLOCK
REF
FS
4F0
4F1
L2
Z
0
4Q0
4Q1
3Q0
3Q1
3F0
3F1
LOAD
L3
2F0
2F1
2Q0
2Q1
Z
0
1F0
1F1
1Q0
1Q1
L4
FB
REF
TEST
FS
LOAD
4Q0
4Q1
4F0
4F1
3F0
3F1
2F0
2F1
1F0
1F1
Z
0
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1
LOAD
TEST
7B991–15
Figure 8. Board-to-Board Clock Distribution
Figure 8 shows the CY7B991/992 connected in series to con-
struct a zero-skew clock distribution tree between boards. De-
lays of the downstream clock buffers can be programmed to
compensate for the wire length (i.e., select negative skew
equal to the wire delay) necessary to connect them to the mas-
ter clock source, approximating a zero-delay clock tree. Cas-
caded clock buffers will accumulate low-frequency jitter be-
cause of the non-ideal filtering characteristics of the PLL filter.
It is recommended that not more than two clock buffers be
connected in series.
Document #: 38-07138 Rev. **
Page 12 of 15
CY7B991
CY7B992
Ordering Information
Accuracy
Package
Name
Operating
Range
(ps)
250
500
Ordering Code
Package Type
CY7B991–2JC
CY7B991–5JC
CY7B991–5JI
CY7B991–7JC
CY7B991–7JI
CY7B991–7LMB
CY7B992–2JC
CY7B992–5JC
CY7B992–5JI
CY7B992–7JC
CY7B992–7JI
CY7B992–7LMB
J65
J65
J65
J65
J65
L55
J65
J65
J65
J65
J65
L55
32-Lead Plastic Leaded Chip Carrier
32-Lead Plastic Leaded Chip Carrier
32-Lead Plastic Leaded Chip Carrier
32-Lead Plastic Leaded Chip Carrier
32-Lead Plastic Leaded Chip Carrier
Commercial
Commercial
Industrial
750
Commercial
Industrial
32-Pin Rectangular Leadless Chip Carrier Military
250
500
32-Lead Plastic Leaded Chip Carrier
32-Lead Plastic Leaded Chip Carrier
32-Lead Plastic Leaded Chip Carrier
32-Lead Plastic Leaded Chip Carrier
32-Lead Plastic Leaded Chip Carrier
Commercial
Commercial
Industrial
750
Commercial
Industrial
32-Pin Rectangular Leadless Chip Carrier Military
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Parameter
VOH
VOL
VIH
Subgroups
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
VIL
VIHH
VIMM
VILL
IIH
IIL
IIHH
IIMM
IILL
ICCQ
ICCN
Document #: 38-07138 Rev. **
Page 13 of 15
CY7B991
CY7B992
Package Diagrams
32-Lead Plastic Leaded Chip Carrier
32-Pin Rectangular Leadless Chip Carrier
MIL-STD-1835 C-12
Document #: 38-07138 Rev. **
Page 14 of 15
© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7B991
CY7B992
Document Title: CY7B991/CY7B992 Programmable Skew Clock Buffer (PSCB)
Document Number: 38-07138
Issue
Date
Orig. of
Change
REV.
ECN NO.
Description of Change
**
110247
12/19/01
SZV
Change from Spec number: 38-00513 to 38-07138
Document #: 38-07138 Rev. **
Page 15 of 15
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