CY7B9911_08 [CYPRESS]
Programmable Skew Clock Buffer; 可编程偏移时钟缓冲器
| 型号： | CY7B9911_08 |
| 厂家： | 
CYPRESS |
| 描述： | Programmable Skew Clock Buffer |
| 文件： | 总13页 (文件大小：491K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7B9911
RoboClock+™
Programmable Skew Clock Buffer
Features
Functional Description
■ All output pair skew <100 ps typical (250 max)
■ 3.75 to 100 MHz output operation
The CY7B9911 High Speed Programmable Skew Clock Buffer
(PSCB) offers user selectable control over system clock
functions. This multiple output clock driver provides the system
integrator with functions necessary to optimize the timing of high
performance computer systems. Each of the eight individual TTL
drivers, arranged in four pairs of user controllable outputs, can
drive terminated transmission lines with impedances as low as
50Ω. They deliver minimal and specified output skews and full
swing logic levels.
■ User selectable output functions
❐ Selectable skew to 18 ns
❐ Inverted and non-inverted
❐ Operation at ½ and ¼ input frequency
❐ Operation at 2x and 4x input frequency (input as low as 3.75
MHz)
Each output is hardwired to one of nine delay or function config-
urations. Delay increments of 0.6 to 1.5 ns are determined by the
operating frequency with outputs able to skew up to ±6 time units
from their nominal “zero” skew position. The completely
integrated PLL allows cancellation of external load and trans-
mission line delay effects. When this “zero delay” capability of the
PSCB is combined with the selectable output skew functions,
you can create output-to-output delays of up to ±12 time units.
■ Zero input to output delay
■ 50% duty cycle outputs
■ Outputs drive 50Ω terminated lines
■ Low operating current
■ 32-pin PLCC/LCC package
■ Jitter < 200 ps peak-to-peak (< 25 ps RMS)
Divide-by-two and divide-by-four output functions are provided
for additional flexibility in designing complex clock systems.
When combined with the internal PLL, these divide functions
enable distribution of a low frequency clock that is multiplied by
two or four at the clock destination. This facility minimizes clock
distribution difficulty enabling maximum system clock speed and
flexibility.
Logic Block Diagram
TEST
PHASE
FB
VCO AND
TIME UNIT
GENERATOR
FREQ
DET
FILTER
REF
FS
4Q0
4Q1
4F0
4F1
SELECT
INPUTS
(THREE
LEVEL)
SKEW
3Q0
3F0
3F1
3Q1
SELECT
2Q0
2F0
2F1
MATRIX
2Q1
1Q0
1Q1
1F0
1F1
Cypress Semiconductor Corporation
Document Number: 38-07209 Rev. *C
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised October 20, 2008
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CY7B9911
RoboClock+™
Pin Configuration
PLCC/LCC
4
3
2
1
32 31 30
29
2F0
GND
1F1
1F0
5
6
3F1
4F0
28
27
4F1
7
8
9
V
26
25
24
23
CCQ
CY7B9911
V
CCN
V
CCN
4Q1
10
11
12
13
1Q0
1Q1
GND
GND
4Q0
GND
GND
22
21
14 15 16 17 18 19 20
Pin Definitions
Signal Name
IO
Description
REF
I
Reference frequency input. This input supplies the frequency and timing against which all functional
variation is measured.
FB
I
PLL feedback input (typically connected to one of the eight outputs).
Three level frequency range select. See Table 1.
Three level function select inputs for output pair 1 (1Q0, 1Q1). See Table 2.
Three level function select inputs for output pair 2 (2Q0, 2Q1). See Table 2
Three level function select inputs for output pair 3 (3Q0, 3Q1). See Table 2
Three level function select inputs for output pair 4 (4Q0, 4Q1). See Table 2
Three level select. See test mode section under the block diagram descriptions.
Output pair 1. See Table 2.
FS
I
1F0, 1F1
2F0, 2F1
3F0, 3F1
4F0, 4F1
TEST
I
I
I
I
I
1Q0, 1Q1
2Q0, 2Q1
3Q0, 3Q1
4Q0, 4Q1
VCCN
O
O
Output pair 2. See Table 2.
O
Output pair 3. See Table 2.
O
Output pair 4. See Table 2.
PWR
PWR
PWR
Power supply for output drivers.
VCCQ
Power supply for internal circuitry.
GND
Ground.
Document Number: 38-07209 Rev. *C
Page 2 of 13
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RoboClock+™
Skew Select Matrix
Block Diagram Description
The skew select matrix contains four independent sections. Each
section has two low skew, high fanout drivers (xQ0, xQ1), and
two corresponding three level function select (xF0, xF1) inputs.
Table 2 shows the nine possible output functions for each section
as determined by the function select inputs. All times are
measured with respect to the REF input assuming that the output
connected to the FB input has 0tU selected.
Phase Frequency Detector and Filter
The Phase Frequency Detector and Filter blocks accept inputs
from the reference frequency (REF) input and the feedback (FB)
input. They generate correction information to control the
frequency of the Voltage controlled Oscillator (VCO). These
blocks, along with the VCO, form a Phase Locked Loop (PLL)
that tracks the incoming REF signal.
Table 2. Programmable Skew Configurations[1]
VCO and Time Unit Generator
Function Selects
Output Functions
The VCO accepts analog control inputs from the PLL filter block
and generates a frequency that is used by the time unit generator
to create discrete time units that are selected in the skew select
matrix. The operational range of the VCO is determined by the
FS control pin. The time unit (tU) is determined by the operating
frequency of the device and the level of the FS pin as shown in
Table 1.
1F1,2F1, 1F0,2F0, 1Q0,1Q1,
3F1, 4F1 3F0, 4F0 2Q0, 2Q1
3Q0, 3Q1 4Q0, 4Q1
LOW
LOW
LOW
MID
LOW
MID
–4tU
–3tU
–2tU
–1tU
0tU
Divide by 2 Divide by 2
–6tU
–4tU
–2tU
0tU
–6tU
–4tU
–2tU
0tU
HIGH
LOW
MID
Table 1. Frequency Range Select and tU Calculation[1]
fNOM (MHz)
MID
MID
HIGH
LOW
MID
+1tU
+2tU
+3tU
+4tU
+2tU
+4tU
+6tU
+2tU
+4tU
+6tU
1
Approximate
Frequency(MHz)At
Which tU = 1.0 ns
-----------------------
tU
=
FS[2,3]
fNOM × N
HIGH
HIGH
HIGH
Min Max
where N =
LOW
MID
15
25
40
30
50
44
26
16
22.7
38.5
62.5
HIGH
Divide by 4 Inverted
HIGH
100
Notes
1. For all three state inputs, HIGH indicates a connection to VCC, LOW indicates a connection to GND, and MID indicates an open connection. Internal termination
circuitry holds an unconnected input to VCC/2.
2. The level to be set on FS is determined by the “normal” operating frequency (fNOM) of the VCO and Time Unit Generator (see Logic Block Diagram). Nominal
frequency (fNOM) always appears at 1Q0 and the other outputs when they are operated in their undivided modes (see Table 2). The frequency appearing at the REF
and FB inputs will be fNOM when the output connected to FB is undivided. The frequency of the REF and FB inputs will be fNOM/2 or fNOM/4 when the part is
configured for a frequency multiplication by using a divided output as the FB input.
3. When the FS pin is selected HIGH, the REF input must not transition upon power-up until VCC has reached 4.3V.
Document Number: 38-07209 Rev. *C
Page 3 of 13
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Figure 1. Typical Outputs with FB Connected to a Zero-Skew Output[4]
FB Input
REF Input
1Fx
2Fx
3Fx
4Fx
(N/A)
LM
– 6t
– 4t
– 3t
U
U
U
LL
LH
LM
(N/A)
LH
ML
ML
– 2t
– 1t
U
U
(N/A)
MM
MH
HL
MM
(N/A)
MH
0t
U
U
U
U
+1t
+2t
+3t
HM
(N/A)
HH
HL
HM
+4t
+6t
U
U
(N/A)
(N/A)
(N/A)
LL/HH
HH
DIVIDED
INVERT
Test Mode
The TEST input is a three level input. In normal system
operation, this pin is connected to ground, enabling the
CY7B9911 to operate as explained in the previous section (for
testing purposes). Any of the three level inputs can have a
removable jumper to ground or be tied LOW through a 100Ω
resistor. This enables an external tester to change the state of
these pins.
Maximum Ratings
Operating outside these boundaries may affect the performance
and life of the device. These user guidelines are not tested.
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied ............................................–55°C to +125°C
Supply Voltage to Ground Potential................–0.5V to +7.0V
DC Input Voltage ............................................–0.5V to +7.0V
Output Current into Outputs (LOW)............................. 64 mA
If the TEST input is forced to its MID or HIGH state, the device
operates with its internal phase locked loop disconnected, and
input levels supplied to REF directly control all outputs. Relative
output to output functions are the same as in normal mode.
In contrast with normal operation (TEST tied LOW), all outputs
function based only on the connection of their own function
select inputs (xF0 and xF1) and the waveform characteristics of
the REF input.
Static Discharge Voltage............................................>2001V
(per MIL-STD-883, Method 3015)
Latch Up Current .....................................................>200 mA
Note
4. FB connected to an output selected for “zero” skew (i.e., xF1 = xF0 = MID).
Document Number: 38-07209 Rev. *C
Page 4 of 13
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RoboClock+™
Operating Range
Ambient
Temperature
Range
VCC
Commercial
0°C to +70°C
5V ± 10%
Electrical Characteristics Over the Operating Range
CY7B9911
Parameter
Description
Output HIGH Voltage
Test Conditions
VCC = Min, IOH = –16 mA
VCC = Min, IOH =–40 mA
VCC = Min, IOL = 46 mA
VCC = Min, IOL = 46 mA
Min
Max
Unit
VOH
2.4
V
VOL
Output LOW Voltage
0.45
V
VIH
VIL
Input HIGH Voltage
(REF and FB inputs only)
2.0
VCC
0.8
V
Input LOW Voltage
(REF and FB inputs only)
–0.5
V
VIHH
VIMM
VILL
IIH
Three Level Input HIGH
Voltage (Test, FS, xFn)[5]
Min £ VCC £ Max
Min £ VCC £ Max
Min £ VCC £ Max
VCC – 0.85
VCC
V
Three Level Input MID
VCC/2 – 500 mV VCC/2 + 500 mV
V
Voltage (Test, FS, xFn)[5]
Three Level Input LOW
Voltage (Test, FS, xFn)[5]
0.0
0.85
10
V
Input HIGH Leakage Current (REF and VCC = Max, VIN = Max.
FB inputs only)
µA
µA
µA
µA
µA
mA
mA
IIL
Input LOW Leakage Current (REF and VCC = Max, VIN = 0.4V
FB inputs only)
–500
–50
IIHH
IIMM
IILL
Input HIGH Current
(Test, FS, xFn)
VIN = VCC
VIN = VCC/2
VIN = GND
200
50
Input MID Current
(Test, FS, xFn)
Input LOW Current
(Test, FS, xFn)
–200
–250
85
IOS
Output Short Circuit
Current[5]
VCC = Max, VOUT
= GND (25×C only)
ICCQ
Operating Current Used by
Internal Circuitry
VCCN =VCCQ =Max, Com’l
All Input
Selects Open
ICCN
Output Buffer Current per
Output Pair[6]
VCCN = VCCQ = Max,
IOUT = 0 mA
Input Selects Open, fMAX
14
78
mA
PD
Power Dissipation per
Output Pair[8]
VCCN = VCCQ = Max,
mW
IOUT = 0 mA
Input Selects Open, fMAX
Notes
5. These inputs are normally wired to VCC, GND, or left unconnected (actual threshold voltages vary as a percentage of VCC). Internal termination resistors
hold unconnected inputs at VCC/2. If these inputs are switched, the function and timing of the outputs glitch and the PLL requires an additional tLOCK time
before all datasheet limits are achieved.
6. CY7B9911 must be tested one output at a time, output shorted for less than one second, less than 10% duty cycle. Room temperature only.
7. Total output current per output pair is approximated by the following expression that includes device current plus load current:
CY7B9911:ICCN = [(4 + 0.11F) + [((835 – 3F)/Z) + (.0022FC)]N] x 1.1
Where F = frequency in MHz; C = capacitive load in pF; Z = line impedance in ohms; N = number of loaded outputs; 0, 1, or 2; FC = F * C.
8. Total power dissipation per output pair is approximated by the following expression that includes device power dissipation plus power dissipation due to the
load circuit: CY7B9911:PD = [(22 + 0.61F) + [((1550 – 2.7F)/Z) + (.0125FC)]N] x 1.1.
Document Number: 38-07209 Rev. *C
Page 5 of 13
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RoboClock+™
Capacitance
Test conditions assume signal transition times unless otherwise specified.
Parameter
CIN
Description
Test Conditions
Max
Unit
Input Capacitance
TA = 25°C, f = 1 MHz, VCC = 5.0V
10
pF
AC Test Loads and Waveforms
5V
3.0V
2.0V
=1.5V
0.8V
2.0V
th
0.8V
R1=130
R2=91
R1
R2
V
th
V =1.5V
C = 30 pF
L
0.0V
C
L
(Includes fixture and probe capacitance)
≤1ns
≤1ns
TTL ACTest Load (CY7B9911)
TTL Input Test Waveform (CY7B9911)
Document Number: 38-07209 Rev. *C
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Switching Characteristics
Over the Operating Range[2, 10]
CY7B9911–5
Typ
CY7B9911–7
Parameter
Description
Min
15
Max
30
Min
15
Typ
Max
30
Unit
fNOM
Operating Clock
FS = LOW[1, 2]
FS = MID[1, 2]
MHz
Frequency in MHz
25
50
25
50
FS = HIGH[1, 2 , 3]
40
100
40
100
tRPWH
tRPWL
tU
REF Pulse Width HIGH
REF Pulse Width LOW
Programmable Skew Unit
4.0
4.0
See
4.0
4.0
See
ns
ns
Table 1
Table 1
tSKEWPR
Zero Output Matched Pair Skew
(XQ0, XQ1)[11, 12]
0.1
0.25
0.1
0.25
ns
tSKEW0
tSKEW1
Zero Output Skew (All Outputs)[11, 13]
0.25
0.6
0.5
0.7
0.3
0.6
0.75
1.0
ns
ns
Output Skew (Rise-Rise, Fall-Fall, Same
Class Outputs)[11, 14]
tSKEW2
tSKEW3
tSKEW4
Output Skew (Rise-Fall, Nominal-Inverted,
Divided-Divided)[11, 14]
0.5
0.5
0.5
1.2
0.9
1.2
1.0
0.7
1.2
1.7
1.4
1.9
ns
ns
ns
Output Skew (Rise-Rise, Fall-Fall, Different
Class Outputs)[11, 14]
Output Skew (Rise-Fall, Nominal-Divided,
Divided-Inverted)[11, 14]
tDEV
Device-to-Device Skew[10, 15]
Propagation Delay, REF Rise to FB Rise
Output Duty Cycle Variation[18]
Output HIGH Time Deviation from 50%[17, 18]
Output LOW Time Deviation from 50%[17, 18]
Output Rise Time[17, 19]
1.25
+0.5
+1.0
2.0
1.65
+0.7
+1.2
2.5
3
ns
ns
ns
ns
ns
ns
ns
ms
ps
ps
tPD
–0.5
–1.0
0.0
0.0
–0.7
–1.2
0.0
0.0
tODCV
tPWH
tPWL
tORISE
tOFALL
tLOCK
tJR
2.5
0.15
0.15
1.0
1.0
1.5
0.15
0.15
1.5
1.5
2.5
2.5
0.5
25
Output Fall Time[17, 19]
1.5
PLL Lock Time[20]
0.5
Cycle-to-Cycle Output
Jitter
RMS[10]
25
Peak-to-Peak[10]
200
200
Notes
9. Test conditions assume signal transition times of 2 ns or less and output loading as shown in the AC Test Loads and Waveforms unless otherwise specified.
10. Guaranteed by statistical correlation. Tested initially and after any design or process changes that affect these parameters.
11. SKEW is defined as the time between the earliest and the latest output transition among all outputs for which the same t delay is selected when all are loaded with
U
30 pF and terminated with 50Ω to 2.06V.
12. t
13. t
is defined as the skew between a pair of outputs (XQ0 and XQ1) when all eight outputs are selected for 0t .
SKEWPR
U
is defined as the skew between outputs when they are selected for 0t . Other outputs are divided or inverted but not shifted.
SKEW0
U
14. There are three classes of outputs: Nominal (multiple of t delay), Inverted (4Q0 and 4Q1 only with 4F0 = 4F1 = HIGH), and Divided (3Qx and 4Qx only in Divide-by-2
U
or Divide-by-4 mode).
15. t
16. t
is the output-to-output skew between any two devices operating under the same conditions (V ambient temperature, air flow, and so on).
DEV
CC
is the deviation of the output from a 50% duty cycle. Output pulse width variations are included in t
and t
specifications.
ODCV
SKEW2
SKEW4
17. Specified with outputs loaded with 30 pF. Devices are terminated through 50Ω to 2.06V.
18. t
19. t
20. t
is measured at 2.0V. t
is measured at 0.8V.
PWH
PWL
and t
measured between 0.8V and 2.0V.
ORISE
LOCK
OFALL
is the time that is required before synchronization is achieved. This specification is valid only after V is stable and within normal operating limits. This
CC
parameter is measured from the application of a new signal or frequency at REF or FB until t is within specified limits.
PD
Document Number: 38-07209 Rev. *C
Page 7 of 13
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AC Timing Diagrams
Figure 2. AC Timing Diagrams
t
t
RPWL
REF
t
RPWH
REF
t
t
ODCV
PD
t
ODCV
FB
Q
t
JR
t
t
t
t
SKEWPR,
SKEW0,1
SKEWPR,
SKEW0,1
OTHERQ
t
SKEW2
t
SKEW2
INVERTED Q
t
SKEW3,4
t
t
SKEW3,4
t
SKEW3,4
REF DIVIDED BY 2
REF DIVIDED BY 4
t
SKEW1,3, 4
SKEW2,4
Document Number: 38-07209 Rev. *C
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Figure 3. Zero Skew and Zero Delay Clock Driver
REF
LOAD
Z
0
L1
L2
FB
SYSTEM
CLOCK
REF
FS
LOAD
LOAD
4Q0
4Q1
4F0
4F1
Z
0
3Q0
3Q1
3F0
3F1
L3
L4
2F0
2F1
2Q0
2Q1
Z
0
1F0
1F1
1Q0
1Q1
LOAD
TEST
Z
0
LENGTH L1 = L2 = L3 = L4
Operational Mode Descriptions
Figure 2 shows the PSCB configured as a zero skew clock buffer. In this mode the 7B9911 is used as the basis for a low skew clock
distribution tree. When all of the function select inputs (xF0, xF1) are left open, the outputs are aligned and each drive a terminated
transmission line to an independent load. The FB input is tied to any output in this configuration and the operating frequency range
is selected with the FS pin. The low skew specification, coupled with the ability to drive terminated transmission lines (with impedances
as low as 50 ohms), enables efficient printed circuit board design.
Figure 4. Programmable Skew Clock Driver
REF
LOAD
Z
0
L1
L2
FB
REF
FS
SYSTEM
CLOCK
LOAD
LOAD
4Q0
4Q1
4F0
4F1
Z
0
3Q0
3Q1
3F0
3F1
L3
L4
2F0
2F1
2Q0
2Q1
Z
0
1F0
1F1
1Q0
1Q1
LOAD
TEST
Z
0
LENGTH L1 = L2
L3 < L2 by 6 inches
L4 > L2 by 6 inches
Figure 3 shows a configuration to equalize skew between metal
traces of different lengths. In addition to low skew between
outputs, the PSCB is programmed to stagger the timing of its
outputs. The four groups of output pairs are each programmed
to different output timing. Skew timing is adjusted over a wide
range in small increments with the appropriate strapping of the
function select pins. In this configuration the 4Q0 output is sent
to FB and configured for zero skew. The other three pairs of
outputs are programmed to yield different skews relative to the
feedback. By advancing the clock signal on the longer traces or
retarding the clock signal on shorter traces, all loads receive the
clock pulse at the same time.
In this illustration the FB input is connected to an output with 0
ns skew (xF1, xF0 = MID) selected. The internal PLL synchro-
nizes the FB and REF inputs and aligns their rising edges to
make certain that all outputs have precise phase alignment.
Clock skews is advanced by ±6 time units (tU) when using an
output selected for zero skew as the feedback. There is a wider
Document Number: 38-07209 Rev. *C
Page 9 of 13
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range of delays, if the output connected to FB is also skewed. As
“Zero Skew”, +tU, and –tU are defined relative to output groups
and the PLL aligns the rising edges of REF and FB, wider output
skews are created by proper selection of the xFn inputs. For
example, a +10 tU between REF and 3Qx is achieved by
connecting 1Q0 to FB and setting 1F0 = 1F1 = GND, 3F0 = MID,
and 3F1 = High. (Since FB aligns at –4 tU and 3Qx skews to +6
tU, a total of +10 tU skew is realized.) Many other configurations
are realized by skewing both the output used as the FB input and
skewing the other outputs.
Figure 6. Frequency Multiplier with Skew Connections
REF
FB
20 MHz
REF
FS
40 MHz
4Q0
4Q1
4F0
4F1
20 MHz
80 MHz
3Q0
3Q1
3F0
3F1
2F0
2F1
Figure 5. Inverted Output Connections
2Q0
2Q1
REF
1Q0
1Q1
1F0
1F1
FB
TEST
REF
FS
Figure 5 illustrates the PSCB configured as a clock multiplier.
The 3Q0 output is programmed to divide by four and is sent back
to FB. This causes the PLL to increase its frequency until the 3Q0
and 3Q1 outputs are locked at 20 MHz while the 1Qx and 2Qx
outputs run at 80 MHz. The 4Q0 and 4Q1 outputs are
programmed to divide by two, that results in a 40 MHz waveform
at these outputs. Note that the 20 and 40 MHz clocks fall simul-
taneously and are out of phase on their rising edge. This enables
the designer to use the rising edges of the 1⁄2 frequency and 1⁄4
frequency outputs without concern for rising edge skew. The
2Q0, 2Q1, 1Q0, and 1Q1 outputs run at 80 MHz and are skewed
by programming their select inputs accordingly. Note that the FS
pin is wired for 80 MHz operation because that is the frequency
of the fastest output.
4Q0
4F0
4Q1
4F1
3Q0
3Q1
3F0
3F1
2Q0
2Q1
2F0
2F1
1Q0
1Q1
1F0
1F1
TEST
Figure 4 shows an example of the invert function of the PSCB.
In this example the 4Q0 output used as the FB input is
programmed for invert (4F0 = 4F1 = HIGH) while the other three
pairs of outputs are programmed for zero skew. When 4F0 and
4F1 are tied high, 4Q0 and 4Q1 become inverted zero phase
outputs. The PLL aligns the rising edge of the FB input with the
rising edge of the REF. This causes the 1Q, 2Q, and 3Q outputs
to become the “inverted” outputs with respect to the REF input.
By selecting the output to connect to FB, you can have two
inverted and six non-inverted outputs or six inverted and two
non-inverted outputs. The correct configuration is determined by
the need for more (or fewer) inverted outputs. 1Q, 2Q, and 3Q
outputs is also skewed to compensate for varying trace delays
independent of inversion on 4Q.
Figure 7. Frequency Divider Connections
REF
FB
REF
20 MHz
FS
10 MHz
4Q0
4F0
4Q1
4F1
5 MHz
3Q0
3Q1
3F0
3F1
20 MHz
2Q0
2Q1
2F0
2F1
1F0
1F1
1Q0
1Q1
TEST
Figure 6 demonstrates the PSCB in a clock divider application.
2Q0 is fed back to the FB input and programmed for zero skew.
3Qx is programmed to divide by four. 4Qx is programmed to
divide by two. Note that the falling edges of the 4Qx and 3Qx
outputs are aligned. This enables use of the rising edges of the
1⁄2 frequency and 1⁄4 frequency without concern for skew
mismatch. The 1Qx outputs are programmed to zero skew and
are aligned with the 2Qx outputs. In this example, the FS input
is grounded to configure the device in the 15 to 30 MHz range
since the highest frequency output is running at 20 MHz.
Document Number: 38-07209 Rev. *C
Page 10 of 13
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CY7B9911
RoboClock+™
Figure 7 shows some of the functions that are selectable on the
3Qx and 4Qx outputs. These include inverted outputs and
outputs that offer divide-by-2 and divide-by-4 timing. An inverted
output allows the system designer to clock different subsystems
on opposite edges, without suffering from the pulse asymmetry
typical of non-ideal loading. This function enables each of the
two subsystems to clock 180 degrees out of phase, but still stay
aligned within the skew specification.
delay of the divider adds to the skew between the different clock
signals.
These divided outputs, coupled with the Phase Locked Loop,
enable the PSCB to multiply the clock rate at the REF input by
either two or four. This mode enables the designer to distribute
a low frequency clock between various portions of the system. It
also locally multiplies the clock rate to a more suitable frequency,
maintaining the low skew characteristics of the clock driver. The
PSCB performs all of the functions described in this section at
the same time. It can multiply by two and four or divide by two
(and four) at the same time that it is shifting its outputs over a
wide range or maintaining zero skew between selected outputs.
The divided outputs offer a zero delay divider for portions of the
system that divides the clock by either two or four, and still remain
within a narrow skew of the “1X” clock. Without this feature,
addition of an external divider is required and the propagation
Figure 8. Multi-Function Clock Driver
REF
LOAD
Z
0
80 MHz
INVERTED
FB
REF
FS
20 MHz
DISTRIBUTION
CLOCK
LOAD
LOAD
4Q0
4Q1
4F0
4F1
20 MHz
Z
0
3Q0
3Q1
2Q0
2Q1
3F0
3F1
2F0
2F1
80 MHz
ZEROSKEW
Z
0
1Q0
1Q1
1F0
LOAD
80 MHz
SKEWED4ns
1F1
TEST
Z
0
Figure 9. Board-to-Board Clock Distribution
LOAD
REF
Z
0
L1
FB
LOAD
LOAD
SYSTEM
CLOCK
REF
FS
4F0
4F1
L2
Z
0
4Q0
4Q1
3Q0
3Q1
3F0
3F1
L3
2F0
2F1
2Q0
2Q1
Z
0
1F0
1F1
1Q0
1Q1
L4
FB
REF
TEST
FS
LOAD
4Q0
4Q1
4F0
4F1
3F0
3F1
2F0
2F1
1F0
1F1
TEST
Z
0
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1
LOAD
Document Number: 38-07209 Rev. *C
Page 11 of 13
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CY7B9911
RoboClock+™
Figure 8 shows the CY7B9911 connected in series to construct
a zero-skew clock distribution tree between boards. Delays of
the downstream clock buffers are programmed to compensate
for the wire length (that is, select negative skew equal to the wire
delay) necessary to connect them to the master clock source,
approximating a zero delay clock tree. Cascaded clock buffers
accumulate low frequency jitter because of the non-ideal filtering
characteristics of the PLL filter. Do not connect more than two
clock buffers in series.
Ordering Information
Accuracy
Ordering Code
(ps)
Operating
Package Type
Range
500
500
750
CY7B9911–5JC
CY7B9911–5JCT
CY7B9911–7JC[21]
32-Pb Plastic Leaded Chip Carrier
Commercial
Commercial
Commercial
32-Pb Plastic Leaded Chip Carrier - Tape and Reel
32-Pb Plastic Leaded Chip Carrier
Package Diagrams
Figure 10. 32-Pin Plastic Leaded Chip Carrier J65 (51-85002)
51-85002-*B
Note
21. Not recommended for the new design.
Document Number: 38-07209 Rev. *C
Page 12 of 13
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CY7B9911
RoboClock+™
Document History Page
Document Title: CY7B9911 RoboClock+™ Programmable Skew Clock Buffer
Document Number: 38-07209
Orig. of
Change
Submission
Date
REV.
ECN NO.
Description of Change
**
110342
SZV
12/21/01 Change from Specification number: 38-00623 to 38-07209
*A
1199925
KVM/AESA
See ECN Added Tape and Reel part in Ordering Information
Added note: Not recommended for the new design
*B
*C
1286064
2593494
AESA
See ECN Change status to final
CXQ/PYRS
10/20/08 Changed unit of measurement in the Electrical Characteristics table for pa-
rameters IIH, IIL, IIHH, IIMM, and IILL
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Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 38-07209 Rev. *C
Revised October 20, 2008
Page 13 of 13
PSoC Designer™, Programmable System-on-Chip™, and PSoC Express™ are trademarks and PSoC® is a registered trademark of Cypress Semiconductor Corp. All other trademarks or registered
2
trademarks referenced herein are property of the respective corporations. Purchase of I C components from Cypress or one of its sublicensed Associated Companies conveys a license under the
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Philips I C Patent Rights to use these components in an I C system, provided that the system conforms to the I C Standard Specification as defined by Philips. RoboClock+ is a trademark of Cypress
Semiconductor Corporation. All products and company names mentioned in this document may be the trademarks of their respective holders.
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