CY6264-55SNCT [CYPRESS]
Standard SRAM, 8KX8, 55ns, CMOS, PDSO28, 0.300 INCH, SOIC-28;
| 型号： | CY6264-55SNCT |
| 厂家： | 
CYPRESS |
| 描述： | Standard SRAM, 8KX8, 55ns, CMOS, PDSO28, 0.300 INCH, SOIC-28 |
| 文件： | 总8页 (文件大小：256K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
1CY6264
PRELIMINARY
CY6264
8K x 8 Static RAM
over 70% when deselected. The CY6264 is packaged in a
450-mil (300-mil body) SOIC.
Features
• 55, 70 ns access times
• CMOS for optimum speed/power
An active LOW write enable signal (WE) controls the writ-
ing/reading operation of the memory. When CE and WE in-
1
• Easy memory expansion with CE , CE , and OE fea-
puts are both LOW and CE is HIGH, data on the eight data
1
2
2
tures
input/output pins (I/O through I/O ) is written into the memory
0
7
location addressed by the address present on the address
pins (A through A ). Reading the device is accomplished by
• TTL-compatible inputs and outputs
• Automatic power-down when deselected
0
12
selecting the device and enabling the outputs, CE and OE
1
active LOW, CE active HIGH, while WE remains inactive or
Functional Description
2
HIGH. Under these conditions, the contents of the location ad-
dressed by the information on address pins is present on the
eight data input/output pins.
The CY6264 is a high-performance CMOS static RAM orga-
nized as 8192 words by 8 bits. Easy memory expansion is
provided by an active LOW chip enable (CE ), an active HIGH
1
The input/output pins remain in a high-impedance state unless
the chip is selected, outputs are enabled, and write enable
(WE) is HIGH. A die coat is used to insure alpha immunity.
chip enable (CE ), and active LOW output enable (OE) and
2
three-state drivers. Both devices have an automatic pow-
er-down feature (CE ), reducing the power consumption by
1
Logic Block Diagram
Pin Configuration
SOIC
Top View
NC
V
CC
1
2
3
4
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A
WE
CE
4
A
5
2
A
A
3
6
I/O
0
A
A
2
A
1
7
5
6
7
8
INPUT BUFFER
A
8
I/O
1
A
9
OE
A
A
A
A
0
10
11
12
CE
1
9
A
1
I/O
2
I/O
I/O
I/O
I/O
I/O
7
6
5
4
3
10
11
12
13
14
A
2
I/O
I/O
I/O
0
1
2
A
I/O
3
3
A
256 x 32 x 8
ARRAY
4
GND
A
5
I/O
4
A
6
CY6264-2
A
A
8
7
I/O
5
I/O
6
POWER
DOWN
CE
1
I/O
7
COLUMN DECODER
CE
2
WE
OE
CY6264-1
Selection Guide
CY6264-55
CY6264-70
Maximum Access Time (ns)
55
70
Maximum Operating Current (mA)
100
100
Maximum Standby Current (mA)
20/15
20/15
Shaded area contains advanced information.
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
October 1994 – Revised June 1996
•
408-943-2600
PRELIMINARY
CY6264
Output Current into Outputs (LOW)............................. 20 mA
Maximum Ratings
Static Discharge Voltage .......................................... >2001V
(per MIL-STD-883, Method 3015)
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Latch-Up Current.................................................... >200 mA
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Operating Range
Ambient
Supply Voltage to Ground Potential............... –0.5V to +7.0V
Range
Temperature
V
CC
DC Voltage Applied to Outputs
[1]
Commercial
0°C to +70°C
5V ± 10%
in High Z State ............................................ –0.5V to +7.0V
[1]
DC Input Voltage ......................................... –0.5V to +7.0V
Electrical Characteristics Over the Operating Range
6264-55
6264-70
Min. Max.
Parameter
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Test Conditions
= Min., I = –4.0 mA
Min.
Max.
Unit
V
V
V
V
2.4
2.4
OH
OL
IH
CC
CC
OH
V
V
V
= Min., I = 8.0 mA
0.4
0.4
V
OL
2.2
–0.5
–5
V
2.2
–0.5
–5
V
V
CC
CC
[1]
Input LOW Voltage
0.8
+5
+5
0.8
V
IL
I
I
Input Load Current
GND < V < V
CC
+5
+5
µA
µA
IX
I
Output Leakage
Current
GND < V < V ,
CC
–5
–5
OZ
I
Output Disabled
I
I
I
I
Output Short
Circuit Current
V
V
= Max.,
–300
100
20
–300
100
20
mA
mA
mA
mA
OS
CC
[2]
= GND
OUT
V
Operating
V
= Max.,
= 0 mA
CC
CC
CC
Supply Current
I
OUT
Automatic CE
Power–Down Current
Max. V , CE > V
IH,
Min. Duty Cycle=100%
SB1
SB2
1
CC
1
Automatic CE
Power–Down Current
Max. V , CE > V – 0.3V,
V
15
15
1
CC
1
CC
> V – 0.3V or V < 0.3V
IN CC IN
Shaded area contains advanced information.
Capacitance[3]
Parameter
Description
Input Capacitance
Output Capacitance
Test Conditions
T = 25°C, f = 1 MHz,
Max.
Unit
C
C
7
7
pF
pF
IN
A
V
= 5.0V
CC
OUT
Notes:
1. Minimum voltage is equal to -3.0V for pulse durations less than 30 ns.
2. Not more than 1 output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
3. Tested initially and after any design or process changes that may affect these parameters.
AC Test Loads and Waveforms
R1 481Ω
R1 481Ω
5V
5V
ALL INPUT PULSES
90%
OUTPUT
OUTPUT
3.0V
GND
90%
10%
30 pF
5 pF
R2
255Ω
R2
255Ω
10%
< 5 ns
INCLUDING
JIG AND
SCOPE
INCLUDING
JIG AND
SCOPE
< 5 ns
CY6264-3
CY6264-4
(a)
(b)
Equivalent to:
THÉVENIN EQUIVALENT
167Ω
OUTPUT
1.73V
2
PRELIMINARY
CY6264
[4]
Switching Characteristics Over the Operating Range
6264-55
Max.
6264-70
Max.
Parameter
Description
Min.
55
5
Min.
70
Unit
READ CYCLE
t
t
t
t
t
t
t
t
t
t
t
Read Cycle Time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RC
Address to Data Valid
55
70
AA
Data Hold from Address Change
5
OHA
CE LOW to Data Valid
55
40
25
70
70
35
ACE1
ACE2
DOE
1
CE HIGH to Data Valid
2
OE LOW to Data Valid
OE LOW to Low Z
3
5
LZOE
HZOE
LZCE1
LZCE2
HZCE
[5]
OE HIGH to High Z
20
30
[6]
CE LOW to Low Z
5
3
5
5
1
CE HIGH to Low Z
2
[5, 6]
CE HIGH to High Z
20
25
30
30
1
CE LOW to High Z
2
t
t
CE LOW to Power-Up
0
0
ns
ns
PU
PD
1
CE HIGH to Power-Down
1
[7]
WRITE CYCLE
t
t
t
t
t
t
t
t
t
t
t
Write Cycle Time
50
40
30
40
0
70
60
50
55
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
WC
CE LOW to Write End
SCE1
SCE2
AW
1
CE HIGH to Write End
2
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
HA
0
0
SA
25
25
0
40
35
0
PWE
SD
Data Set-Up to Write End
Data Hold from Write End
HD
[5]
WE LOW to High Z
20
30
HZWE
WE HIGH to Low Z
5
5
LZWE
Shaded area contains advanced information.
Notes:
4. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
OL/IOH and 30-pF load capacitance.
I
5. tHZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
6. At any given temperature and voltage condition, tHZCE is less than tLZCE for any given device.
7. The internal write time of the memory is defined by the overlap of CE1 LOW, CE2 HIGH, and WE LOW. Both signals must be LOW to initiate a write and either
signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
3
PRELIMINARY
CY6264
Switching Waveforms
[8, 9]
Read Cycle No.1
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
CY6264-5
[10, 11]
Read Cycle No. 2
t
RC
CE
1
CE
2
t
ACE
OE
t
HZOE
t
DOE
t
HZCE
t
LZOE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA OUT
DATA VALID
t
LZCE
t
PD
t
PU
ICC
V
CC
SUPPLY
CURRENT
50%
50%
ISB
CY6264-6
[9, 11]
Write Cycle No.1 (WE Controlled)
t
WC
ADDRESS
t
SCE1
CE
1
CE
2
t
SCE2
OE
t
t
HA
AW
t
SA
t
PWE
WE
t
t
HD
SD
DATA VALID
DATA IN
DATA I/O
IN
t
t
LZWE
HZWE
HIGH IMPEDANCE
DATA UNDEFINED
CY6264-7
Notes:
8. Device is continuously selected. OE, CE = VIL. CE2 = VIH.
9. Address valid prior to or coincident with CE transition LOW.
10. WE is HIGH for read cycle.
11. Data I/O is High Z if OE = VIH, CE1 = VIH, or WE = VIL
.
4
PRELIMINARY
CY6264
Switching Waveforms (continued)
[9, 11, 12]
Write Cycle No. 2 (CE Controlled)
t
WC
ADDRESS
CE
1
t
SCE1
t
SA
t
SCE2
CE
2
t
t
HA
AW
t
PWE
WE
t
t
HD
SD
DATA VALID
DATA IN
IN
t
HZWE
HIGH IMPEDANCE
DATA I/O
DATA UNDEFINED
CY6264-8
Note:
12. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
Typical DC and AC Characteristics
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
OUTPUT SOURCE CURRENT
vs. OUTPUT VOLTAGE
120
100
80
1.4
1.2
1.0
1.2
1.0
0.8
I
I
CC
CC
0.8
0.6
0.4
V
=5.0V
CC
0.6
0.4
60
T =25°C
A
40
V
V
IN
=5.0V
=5.0V
CC
0.2
0.0
20
0
I
SB
0.2
0.0
I
SB
−55
25
125
0.0
1.0
2.0
3.0
4.0
4.0
4.5
5.0
5.5
6.0
AMBIENT TEMPERATURE (°C)
OUTPUT VOLTAGE (V)
SUPPLY VOLTAGE (V)
NORMALIZED ACCESS TIME
vs. AMBIENT TEMPERATURE
OUTPUT SINK CURRENT
vs.OUTPUT VOLTAGE
NORMALIZED ACCESS TIME
vs. SUPPLY VOLTAGE
140
120
1.6
1.4
1.4
1.3
1.2
100
80
V
CC
=5.0V
1.2
1.0
T =25°C
A
1.1
1.0
60
T =25°C
A
V
CC
=5.0V
40
0.8
20
0
0.9
0.8
0.6
−55
0.0
1.0
2.0
3.0
4.0
25
125
4.0
4.5
5.0
5.5
6.0
AMBIENT TEMPERATURE (°C)
OUTPUT VOLTAGE (V)
SUPPLY VOLTAGE (V)
5
PRELIMINARY
CY6264
Typical DC and AC Characteristics (continued)
TYPICAL POWER-ON CURRENT
vs. SUPPLY VOLTAGE
TYPICAL ACCESS TIME CHANGE
vs. OUTPUT LOADING
NORMALIZED I vs. CYCLE TIME
CC
3.0
2.5
2.0
1.5
30.0
25.0
20.0
15.0
1.25
1.00
0.75
0.50
V
=5.0V
CC
T =25°C
A
V
CC
=0.5V
1.0
0.5
0.0
10.0
5.0
V
=4.5V
CC
T =25°C
A
0.0
0.0
1.0
2.0
3.0
4.0
5.0
0
200 400
600 800 1000
10
20
30
40
SUPPLY VOLTAGE(V)
CAPACITANCE(pF)
CYCLE FREQUENCY (MHz)
Truth Table
CE
H
X
CE
X
WE
X
OE
X
Input/Output
High Z
Mode
1
2
Deselect/Power-Down
Deselect
L
X
X
High Z
L
H
H
L
Data Out
Data In
Read
L
H
L
X
Write
L
H
H
H
High Z
Deselect
Address Designators
Address
Name
Address
Function
Pin
Number
A4
A5
X3
X4
X5
X6
X7
Y1
Y4
Y3
Y0
Y2
X0
X1
X2
2
3
A6
4
A7
5
A8
6
A9
7
A10
A11
A12
A0
8
9
10
21
23
24
25
A1
A2
A3
6
PRELIMINARY
CY6264
Ordering Information
Speed
Package
Operating
Range
(ns)
Ordering Code
CY6264-55SC
Name
Package Type
[13]
55
S23
28-Lead 330-Mil SOIC
28-Lead 330-Mil SOIC
28-Lead 300-Mil SOIC
28-Lead 300-Mil SOIC
Commercial
Commercial
Commercial
Commercial
[13]
70
CY6264-70SC
S23
55
CY6264-55SNC
CY6264-70SNC
S22
70
S22
Shaded area contains advanced information.
Note:
13. Not recommended for new designs.
Document #: 38-00425-A
Package Diagrams
28-Lead 450-Mil (300-Mil Body Width) SOIC S22
7
PRELIMINARY
CY6264
Package Diagrams (continued)
28-Lead (330-Mil) SOIC S23
© Cypress Semiconductor Corporation, 1996. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of anycircuitry other than circuitry embodied in a CypressSemiconductor product. Nor does it conveyor imply any license under patent or other rights. CypressSemiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
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