CY62256 [CYPRESS]
256K (32K x 8) Static RAM; 256K （ 32K ×8 ）静态RAM
| 型号： | CY62256 |
| 厂家： | 
CYPRESS |
| 描述： | 256K (32K x 8) Static RAM |
| 文件： | 总12页 (文件大小：395K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY62256
256K (32K x 8) Static RAM
Features
Functional Description[1]
• Temperature Ranges
—Commercial: 0°C to 70°C
— Industrial: –40°C to 85°C
— Automotive: –40°C to 125°C
• High speed: 55 ns and 70 ns
The CY62256 is a high-performance CMOS static RAM
organized as 32K words by 8 bits. Easy memory expansion is
provided by an active LOW chip enable (CE) and active LOW
output enable (OE) and three-state drivers. This device has an
automatic power-down feature, reducing the power
consumption by 99.9% when deselected.
An active LOW write enable signal (WE) controls the
writing/reading operation of the memory. When CE and WE
inputs are both LOW, data on the eight data input/output pins
(I/O0 through I/O7) is written into the memory location
addressed by the address present on the address pins (A0
through A14). Reading the device is accomplished by selecting
the device and enabling the outputs, CE and OE active LOW,
while WE remains inactive or HIGH. Under these conditions,
the contents of the location addressed by the information on
address pins are present on the eight data input/output pins.
• Voltage range: 4.5V–5.5V operation
• Low active power (70 ns, LL version, Com’l and Ind’l)
— 275 mW (max.)
• Low standby power (70 ns, LL version, Com’l and Ind’l)
— 28 µW (max.)
• Easy memory expansion with CE and OE features
• TTL-compatible inputs and outputs
• Automatic power-down when deselected
• CMOS for optimum speed/power
• Package available in a standard 450-mil-wide (300-mil
body width) 28-lead narrow SOIC, 28-lead TSOP-1,
28-lead reverse TSOP-1, and 600-mil 28-lead PDIP
packages
The input/output pins remain in a high-impedance state unless
the chip is selected, outputs are enabled, and write enable
(WE) is HIGH.
Logic Block Diagram
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0
1
2
3
4
5
6
INPUTBUFFER
A
10
A
9
A
8
A
7
A
6
512 x 512
ARRAY
A
5
A
4
3
2
A
A
CE
POWER
DOWN
COLUMN
WE
DECODER
I/O
7
OE
Note:
1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Document #: 38-05248 Rev. *C
Revised June 25, 2004
CY62256
Product Portfolio
Power Dissipation
Operating, ICC
Standby, ISB2
VCC Range (V)
Typ.[2]
(mA)
(µA)
Speed
(ns)
70
55/70
70
55/70
55
Product
Min.
Max.
5.5
Typ.[2]
28
Max.
55
Typ.[2]
1
Max.
5
CY62256
Commercial
4.5
5.0
CY62256L
CY62256LL
CY62256LL
CY62256LL
Com’l / Ind’l
Commercial
Industrial
25
50
2
50
5
10
15
25
50
0.1
0.1
0.1
25
50
Automotive
25
50
Pin Configurations
21
20
A
OE
22
23
24
25
26
27
28
1
2
3
4
5
0
A
1
CE
19
18
17
16
15
14
13
12
11
10
9
8
I/O
A
2
Narrow SOIC
Top View
7
DIP
I/O
I/O
I/O
I/O
A
3
6
Top View
A
4
5
4
3
WE
TSOP I
Top View
A
28
V
CC
V
1
A
5
28
V
CC
1
5
CC
GND
A
5
27 WE
A
2
27 WE
A
6
2
I/O
2
6
A
6
(not to scale)
A
I/O
1
26
A
A7
3
4
5
6
A
7
A
26
A
3
4
5
6
7
4
4
I/O
0
8
A
A
A
25
3
A
8
25
3
8
A
A
14
9
24
A
24
A
A
A
A
9
A
13
6
7
9
2
10
2
A
A
12
11
A
A
23
22
A
A
23
22
A
10
1
10
1
OE
A
OE
11
12
13
7
A11
A10
11
7
8
9
A12
A13
A14
I/O0
I/O1
I/O2
7
6
5
4
3
A
0
21
20
19
18
17
16 I/O
15
A
0
A
21
20
19
18
17
16 I/O
15
A
8
8
12
10
11
12
13
14
15
16
17
18
19
20
21
A9
A
CE
I/O
9
A
CE
I/O
9
13
A8
TSOP I
Reverse Pinout
Top View
A
10
11
12
13
14
A
10
11
12
13
14
14
I/O
A67
A
14
7
7
2
I/O
I/O
6
I/O
6
0
0
GND
A5
1
I/O
I/O
I/O
5
I/O
1
5
1
28
I/O3
VCC
(not to scale)
I/O
I/O
2
27
26
25
24
23
I/O4
I/O5
I/O6
I/O7
CE
2
4
4
WE
A4
I/O
GND
I/O
3
GND
3
A3
A2
A1
22
A0
OE
Pin Definitions
Pin Number
1-10, 21, 23-26
11-13, 15-19,
27
Type
Input
Input/Output I/O0-I/O7. Data lines. Used as input or output lines depending on operation
Description
A0-A14. Address Inputs
Input/Control WE. When selected LOW, a WRITE is conducted. When selected HIGH, a READ is
conducted
20
22
Input/Control CE. When LOW, selects the chip. When HIGH, deselects the chip
Input/Control OE. Output Enable. Controls the direction of the I/O pins. When LOW, the I/O pins
behave as outputs. When deasserted HIGH, I/O pins are three-stated, and act as
input data pins
14
Ground
GND. Ground for the device
28
Power Supply Vcc. Power supply for the device
Notes:
2. Typical specifications are the mean values measured over a large sample size across normal production process variations and are taken at nominal conditions
(T = 25°C, V ). Parameters are guaranteed by design and characterization, and not 100% tested.
A
CC
Document #: 38-05248 Rev. *C
Page 2 of 12
CY62256
Output Current into Outputs (LOW)............................. 20 mA
Maximum Ratings
Static Discharge Voltage.......................................... > 2001V
(Above which the useful life may be impaired. For user guide-
(per MIL-STD-883, Method 3015)
lines, not tested.)
Latch-up Current.................................................... > 200 mA
Storage Temperature .................................–65°C to +150°C
Operating Range
Range
Commercial
Industrial
Ambient Temperature with
Power Applied..............................................-55°C to +125°C
Ambient Temperature (TA)[4]
0°C to +70°C
VCC
Supply Voltage to Ground Potential
5V ± 10%
5V ± 10%
5V ± 10%
(Pin 28 to Pin 14) ........................................... –0.5V to +7.0V
–40°C to +85°C
–40°C to +125°C
DC Voltage Applied to Outputs
in High-Z State[3] ....................................–0.5V to VCC + 0.5V
Automotive
DC Input Voltage[3].................................–0.5V to VCC + 0.5V
Electrical Characteristics Over the Operating Range
CY62256−55
CY62256−70
Parameter
VOH
VOL
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Test Conditions
VCC = Min., IOH = −1.0 mA
VCC = Min., IOL = 2.1 mA
Min. Typ.[2] Max. Min. Typ.[2] Max. Unit
2.4
2.2
2.4
V
V
V
0.4
0.4
VIH
VCC
2.2
VCC
+0.5V
+0.5V
VIL
IIX
IOZ
ICC
Input LOW Voltage
Input Leakage Current GND < VI < VCC
–0.5
–0.5
0.8
–0.5
0.8
+0.5
+0.5
55
V
+0.5 –0.5
+0.5 –0.5
55
µA
µA
mA
Output Leakage Current GND < VO < VCC, Output Disabled –0.5
VCC Operating Supply VCC = Max., IOUT = 0 mA,
28
28
Current
f = fMAX = 1/tRC
L
LL
25
25
0.5
0.4
0.3
1
50
50
2
0.6
0.5
5
50
5
10
15
25
25
0.5
0.4
0.3
1
2
0.1
0.1
50
50
2
0.6
0.5
5
50
5
10
mA
mA
mA
mA
mA
mA
µA
µA
µA
µA
ISB1
Automatic CE
Max. VCC, CE > VIH,
Power-down Current—
TTL Inputs
VIN > VIH or VIN < VIL, f =
L
LL
fMAX
ISB2
Automatic CE
Max. VCC, CE> VCC − 0.3V
Power-down Current—
CMOS Inputs
VIN > VCC − 0.3V, or VIN <
L
LL
LL - Ind’l
2
0.3V, f = 0
0.1
0.1
0.1
LL -
Auto
Capacitance[5]
Parameter
Description
Input Capacitance
Output Capacitance
Test Conditions
Max.
6
8
Unit
pF
pF
CIN
COUT
TA = 25°C, f = 1 MHz,
V
CC = 5.0V
Notes:
3.
V
A
(min.) = −2.0V for pulse durations of less than 20 ns.
IL
4.
T
is the “Instant-On” case temperature.
5. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05248 Rev. *C
Page 3 of 12
CY62256
Thermal Resistance
Description
Test Conditions
Symbol
DIP
SOIC TSOP RTSOP
Unit
Thermal Resistance
Still Air, soldered on a 4.25 x 1.125
ΘJA
75.61 76.56 93.89
93.89
°C/W
(Junction to Ambient)[5]
inch, 4-layer printed circuit board
Thermal Resistance
ΘJC
43.12 36.07 24.64
24.64
°C/W
(Junction to Case)[5]
AC Test Loads and Waveforms
R1 1800 Ω
R1 1800Ω
5V
OUTPUT
5V
OUTPUT
ALL INPUT PULSES
90%
3.0V
GND
90%
10%
10%
R2
R2
100 pF
5 pF
990Ω
990Ω
< 5 ns
< 5 ns
INCLUDING
JIG AND
SCOPE
INCLUDING
JIG AND
SCOPE
(a)
(b)
Equivalent to:
THÉVENIN EQUIVALENT
639Ω
OUTPUT
1.77V
Data Retention Characteristics
Parameter
VDR
ICCDR
Description
VCC for Data Retention
Data Retention Current
Conditions[6]
Min.
2.0
Typ.[2]
Max.
50
5
10
10
Unit
V
L
LL
LL - Ind’l
LL - Auto
VCC = 3.0V, CE > VCC − 0.3V,
IN > VCC − 0.3V, or VIN < 0.3V
2
µA
µA
µA
µA
ns
V
0.1
0.1
0.1
[5]
tCD[5R]
tR
Chip Deselect to Data Retention Time
Operation Recovery Time
0
tRC
ns
Data Retention Waveform
DATA RETENTION MODE
> 2V
3.0V
3.0V
V
V
CC
DR
t
t
R
CDR
CE
Notes:
6. No input may exceed V + 0.5V.
CC
Document #: 38-05248 Rev. *C
Page 4 of 12
CY62256
Switching Characteristics Over the Operating Range[7]
CY62256−55
CY62256−70
Parameter
Description
Min.
Max.
Min.
Max.
Unit
Read Cycle
tRC
tAA
tOHA
tACE
tDOE
tLZOE
tHZOE
tLZCE
Read Cycle Time
55
5
70
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low-Z[8]
55
70
5
55
25
70
35
5
5
0
5
5
0
OE HIGH to High-Z[8, 9]
CE LOW to Low-Z[8]
20
20
55
25
25
70
tHZCE
tPU
tPD
CE HIGH to High-Z[8, 9]
CE LOW to Power-up
CE HIGH to Power-down
Write Cycle[10, 11]
tWC
tSCE
tAW
tHA
tSA
tPWE
tSD
tHD
tHZWE
tLZWE
Write Cycle Time
55
45
45
0
70
60
60
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CE LOW to Write End
Address Set-up to Write End
Address Hold from Write End
Address Set-up to Write Start
WE Pulse Width
Data Set-up to Write End
Data Hold from Write End
WE LOW to High-Z[8, 9]
WE HIGH to Low-Z[8]
0
0
40
25
0
50
30
0
20
25
5
5
Switching Waveforms
Read Cycle No. 1[12, 13]
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Notes:
7. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
/I and 100-pF load capacitance.
I
OL OH
8. At any given temperature and voltage condition, t
is less than t
, t
is less than t
, and t
is less than t
for any given device.
HZCE
LZCE HZOE
LZOE
HZWE
LZWE
9.
t
, t
, and t
are specified with C = 5 pF as in (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
HZOE HZCE
HZWE L
10. The internal Write time of the memory is defined by the overlap of CELOW and WE LOW. Both signals must be LOW to initiate a Write and either signal can terminate
a Write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the Write.
11. The minimum Write cycle time for Write cycle #3 (WE controlled, OE LOW) is the sum of t
and t
SD
HZWE
12. Device is continuously selected. OE, CE = V .
IL
13. WE is HIGH for Read cycle.
Document #: 38-05248 Rev. *C
Page 5 of 12
CY62256
Switching Waveforms (continued)
Read Cycle No. 2 [13, 14]
t
RC
CE
t
ACE
OE
t
HZOE
HZCE
t
DOE
t
t
LZOE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA OUT
DATA VALID
t
LZCE
t
PD
t
PU
V
ICC
ISB
CC
SUPPLY
50%
50%
CURRENT
[10, 15, 16]
Write Cycle No. 1 (WE Controlled)
t
WC
ADDRESS
CE
t
t
HA
AW
t
SA
t
PWE
WE
OE
t
SD
t
HD
DATA VALID
DATA I/O
NOTE17
IN
t
HZOE
[10, 15, 16]
Write Cycle No. 2 (CE Controlled)
t
WC
ADDRESS
CE
t
SCE
t
SA
t
t
HA
AW
WE
t
t
HD
SD
DATA I/O
DATA VALID
IN
Notes:
14. Address valid prior to or coincident with CE transition LOW.
15. Data I/O is high impedance if OE = V
.
IH
16. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
17. During this period, the I/Os are in output state and input signals should not be applied.
Document #: 38-05248 Rev. *C
Page 6 of 12
CY62256
Switching Waveforms (continued)
[11, 16]
Write Cycle No. 3 (WE Controlled, OE LOW)
t
WC
ADDRESS
CE
t
t
HA
AW
t
SA
WE
t
t
HD
SD
DATA I/O
DATA VALID
NOTE 17
IN
t
t
LZWE
HZWE
Document #: 38-05248 Rev. *C
Page 7 of 12
CY62256
Typical DC and AC Characteristics
CURRENT
STANDBY
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
vs. SUPPLY VOLTAGE
1.4
3.0
2.5
2.0
1.5
1.0
1.4
I
CC
1.2
1.0
0.8
0.6
1.2
1.0
0.8
0.6
I
CC
I
SB
V
=5.0V
IN
T =25°C
A
V
=5.0V
=5.0V
0.5
0.4
CC
0.4
V
IN
V
=5.0V
=5.0V
CC
0.2
0.0
0.0
0.2
0.0
V
I
SB
IN
-0.5
−55
25
105
−55
25
125
4.0
4.5
5.0
5.5
6.0
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
NORMALIZED ACCESS TIME
vs. AMBIENT TEMPERATURE
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
NORMALIZED ACCESS TIME
vs. SUPPLY VOLTAGE
140
120
1.6
1.4
1.4
1.3
1.2
100
80
1.2
1.0
1.1
1.0
60
T =25°C
A
V
=5.0V
CC
T =25°C
V
CC
=5.0V
A
40
0.8
20
0
0.9
0.8
0.6
0.0
1.0
2.0
3.0
4.0
−55
25
125
4.0
4.5
5.0
5.5
6.0
AMBIENT TEMPERATURE (°C)
OUTPUT VOLTAGE (V)
SUPPLY VOLTAGE (V)
OUTPUT SOURCE CURRENT
vs. OUTPUT VOLTAGE
120
100
80
V
=5.0V
CC
60
T =25°C
A
40
20
0
0.0
1.0
2.0
3.0
4.0
OUTPUT VOLTAGE (V)
Document #: 38-05248 Rev. *C
Page 8 of 12
CY62256
Typical DC and AC Characteristics (continued)
TYPICAL POWER-ON CURRENT
TYPICAL ACCESS TIME CHANGE
NORMALIZED I vs.CYCLETIME
CC
vs. SUPPLY VOLTAGE
vs. OUTPUT LOADING
3.0
2.5
2.0
1.5
30.0
25.0
20.0
15.0
1.25
1.00
0.75
0.50
V
=5.0V
CC
T =25°C
A
V
IN
=0.5V
V
=4.5V
1.0
0.5
10.0
5.0
CC
T =25°C
A
0.0
0.0
0.0
1.0
2.0
3.0
4.0
5.0
0
200 400
600 800 1000
10
20
30
40
SUPPLY VOLTAGE (V)
CAPACITANCE (pF)
CYCLE FREQUENCY (MHz)
Truth Table
CE
H
L
L
L
WE
X
H
L
OE
X
L
X
H
Inputs/Outputs
High-Z
Data Out
Data In
High-Z
Mode
Deselect/Power-down
Power
Standby (ISB
Active (ICC
Active (ICC
Active (ICC
)
Read
Write
Output Disabled
)
)
)
H
Ordering Information
Speed
Package
Name
SN28
Operating
Range
Industrial
(ns)
Ordering Code
CY62256LL−55SNI
Package Type
28-lead (300-Mil Narrow Body) Narrow SOIC
55
CY62256LL−55ZI
CY62256LL−55SNE
CY62256LL−55ZE
CY62256LL−55ZRE
CY62256−70SNC
CY62256L−70SNC
CY62256LL−70SNC
CY62256L–70SNI
CY62256LL−70SNI
CY62256LL−70ZC
CY62256LL−70ZI
CY62256−70PC
Z28
SN28
Z28
ZR28
SN28
28-lead Thin Small Outline Package
28-lead (300-Mil Narrow Body) Narrow SOIC
28-lead Thin Small Outline Package
28-lead Reverse Thin Small Outline Package
28-lead (300-Mil Narrow Body) Narrow SOIC
Automotive
70
Commercial
Industrial
Z28
Z28
P15
P15
P15
ZR28
28-lead Thin Small Outline Package
28-lead (600-Mil) Molded DIP
Commercial
Industrial
Commercial
CY62256L−70PC
CY62256LL−70PC
CY62256LL−70ZRI
28-lead Reverse Thin Small Outline Package
Industrial
Document #: 38-05248 Rev. *C
Page 9 of 12
CY62256
Package Diagrams
28-lead (600-mil) Molded DIP P15
51-85017-A
28-lead (300-mil) SNC (Narrow Body) SN28
51-85092-*B
Document #: 38-05248 Rev. *C
Page 10 of 12
CY62256
Package Diagrams (continued)
28-lead Thin Small Outline Package Type 1 (8 x 13.4 mm) Z28
51-85071-*G
28-lead Reverse Type 1 Thin Small Outline Package (8 x 13.4 mm) ZR28
51-85074-*F
All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-05248 Rev. *C
Page 11 of 12
© Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY62256
Document Title: CY62256 256K (32K x 8) Static RAM
Document Number: 38-05248
Issue
Orig. of
REV.
ECN NO.
Date
Change
Description of Change
**
113454
03/06/02
MGN
Change from Spec number: 38-00455 to 38-05248
Remove obsolete parts from ordering info, standardize format
Changed SN Package Diagram
*A
*B
115227
116506
05/23/02
09/04/02
GBI
GBI
Added footnote 1.
Corrected package description in Ordering Information table
*C
238448
See ECN
AJU
Added Automotive product information
Document #: 38-05248 Rev. *C
Page 12 of 12
相关型号：
SI9130DB
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