CY62148CV30LL-55BAI [CYPRESS]
512K x 8 MoBL Static RAM; 512K ×8的MoBL静态RAM
| 型号： | CY62148CV30LL-55BAI |
| 厂家： | 
CYPRESS |
| 描述： | 512K x 8 MoBL Static RAM |
| 文件： | 总13页 (文件大小：274K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY62148CV25/30/33
MoBL™
512K x 8 MoBL Static RAM
advanced circuit design to provide ultra-low active current.
This is ideal for providing More Battery Life™ (MoBL™) in por-
table applications such as cellular telephones. The device also
has an automatic power-down feature that significantly reduc-
es power consumption by 80% when addresses are not tog-
gling. The device can be put into standby mode when dese-
lected (CE HIGH).
Features
• High Speed
— 55 ns and 70 ns availability
• Low voltage range:
— CY62148CV25: 2.2V–2.7V
— CY62148CV30: 2.7V–3.3V
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. Data on the eight I/O
pins (I/O0 through I/O7) is then written into the location speci-
fied on the address pins (A0 through A18).
— CY62148CV33: 3.0V–3.6V
• Pin compatible with CY62148V
• Ultra low active power
Reading from the device is accomplished by taking Chip En-
able (CE) and Output Enable (OE) LOW while forcing Write
Enable (WE) HIGH. Under these conditions, the contents of
the memory location specified by the address pins will appear
on the I/O pins.
— Typical active current: 1.5 mA @ f = 1MHz
— Typicalactivecurrent:5.5mA@f=fmax (70nsspeed)
• Low standby power
• Easy memory expansion with CE and OE features
• Automatic power-down when deselected
• CMOS for optimum speed/power
The eight input/output pins (I/O0 through I/O7) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a write
operation (CE LOW and WE LOW).
Functional Description
The CY62148CV25/30/33 are available in a 36-ball FBGA
package.
The CY62148CV25/30/33 are high-performance CMOS static
RAMs organized as 512K words by 8 bits. This device features
Logic Block Diagram
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0
1
2
Data in Drivers
A
0
A
1
A
2
A
3
A
4
A
3
4
5
6
512K x 8
ARRAY
5
A
6
A
A
A
7
8
9
POWER
DOWN
COLUMN
DECODER
CE
I/O
WE
7
OE
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Document #: 38-05035 Rev. *A
Revised September 7, 2001
CY62148CV25/30/33
MoBL™
[1,2]
FBGA (Top View)
Pin
Configurations
1
2
4
3
5
6
A
A
A
A
NC
A
6
A
B
C
3
8
1
0
A
I/O
WE
A
I/O
0
A
4
4
7
2
A
DNU
I/O
1
I/O
5
5
V
V
CC
D
E
F
SS
V
CC
V
SS
A
A
17
I/O
I/O
2
18
6
CE
A
G
H
I/O
OE
A
A
I/O
3
16
7
15
A
A
A
13
A
A
14
12
11
10
9
DC Voltage Applied to Outputs
Maximum Ratings
in High Z State[3] ...................................–0.5V to VCC + 0.3V
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
DC Input Voltage[3] ................................–0.5V to VCC + 0.3V
Output Current into Outputs (LOW).. ...........................20 mA
Static Discharge Voltage..........................................>2001V
MIL-STD-883, Method 3015)
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Latch-Up Current >...................................................>200 mA
Supply Voltage to Ground Potential.....–0.5V to Vccmax + 0.5V
Operating Range
Product
CY62148CV25
Range
Ambient Temperature
VCC
Industrial
–40°C to +85°C
2.2V to 2.7V
2.7V to 3.3V
3.0V to 3.6V
CY62148CV30
CY62148CV33
Product Portfolio
Power Dissipation (Industrial)
Operating (ICC
)
Standby (ISB2)
VCC Range
f = 1 MHz
Typ.[4]
Max.
1.5 mA 3 mA
f = fmax
Product
Min.
Typ.[4]
Max.
Speed
55 ns
70 ns
55 ns
70 ns
55 ns
70 ns
Typ.[4]
Max. Typ.[4]
Max.
CY62148CV25
2.2V
2.5V
2.7V
7 mA
15 mA 5 µA
15 µA
15 µA
20 µA
1.5 mA 3 mA 5.5 mA 12 mA
1.5 mA 3 mA 7 mA 15 mA 7 µA
1.5 mA 3 mA 5.5 mA 12 mA
1.5 mA 3 mA 7 mA 15 mA 8 µA
1.5 mA 3 mA 5.5 mA 12 mA
CY62148CV30
2.7V
3.0V
3.0V
3.3V
3.3V
3.6V
CY62148CV33
Notes:
1. NC pins are not connected to the die.
2. C3 (DNU) can be left as NC or Vss to ensure proper application.
3. VIL(min.) = –2.0V for pulse durations less than 20 ns.
4. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25°C.
Document #: 38-05035 Rev. *A
Page 2 of 13
CY62148CV25/30/33
MoBL™
Electrical Characteristics Over the Operating Range
CY62148CV25-55
CY62148CV25-70
Parameter
VOH
Description
Test Conditions
Min. Typ.[4] Max. Min. Typ.[4] Max. Unit
Output HIGH Voltage IOH = –0.1 mA
Output LOW Voltage IOL = 0.1 mA
Input HIGH Voltage
VCC = Min.
VCC = MinV
2.0
2.0
V
V
V
VOL
0.4
0.4
VIH
1.8
VCC+
1.8
VCC
+
0.3V
0.3V
VIL
IIX
Input LOW Voltage
–0.3
–1
0.6 –0.3
0.6
+1
+1
V
Input Load Current
GND < VI < VCC
+1
+1
–1
–1
µA
µA
IOZ
Output Leakage
Current
GND < VO < VCC, Output
Disabled
–1
ICC
VCC Operating Supply
Current
f = fMAX = 1/tRC
f = 1 MHz
VCC = 3.6V
IOUT = 0 mA
CMOS Levels
7
15
3
5.5
1.5
12
3
mA
mA
1.5
ISB1
Automatic CE
Power-Down Current VIN > VCC – 0.2V or VIN < 0.2V,
CE > VCC – 0.2V
5
15
5
15
µA
— CMOS Inputs
f = fmax (Address and Data Only),
f = 0 (OE,WE)
ISB2
Automatic CE
Power-Down Current VIN > VCC – 0.2V or VIN < 0.2V,
CE > VCC – 0.2V
— CMOS Inputs
f = 0, VCC = 3.6V
CY62148CV30-55
CY62148CV30-70
Parameter
VOH
Description
Test Conditions
Min. Typ.[4] Max. Min. Typ.[4] Max. Unit
Output HIGH Voltage IOH = –1.0 mA
Output LOW Voltage IOL = 2.1 mA
Input HIGH Voltage
VCC = Min.
VCC = MinV
2.4
2.2
2.4
2.2
V
V
V
VOL
0.4
0.4
VIH
VCC
+
VCC
+
0.5V
0.5V
VIL
IIX
Input LOW Voltage
–0.3
–1
0.8 –0.3
0.8
+1
+1
V
Input Load Current
GND < VI < VCC
+1
+1
–1
–1
µA
µA
IOZ
Output Leakage
Current
GND < VO < VCC, Output
Disabled
–1
ICC
VCC Operating Supply
Current
f = fMAX = 1/tRC
f = 1 MHz
VCC = 3.6V
IOUT = 0 mA
CMOS Levels
12
25
3
7
15
3
mA
mA
1.5
1.5
ISB1
Automatic CE
Power-Down Current VIN > VCC – 0.2V or VIN < 0.2V,
CE > VCC – 0.2V
7
15
7
15
µA
— CMOS Inputs
f = fmax (Address and Data Only),
f = 0 (OE,WE)
ISB2
Automatic CE
Power-Down Current VIN > VCC – 0.2V or VIN < 0.2V,
CE > VCC – 0.2V
— CMOS Inputs f = 0, VCC = 3.6V
Document #: 38-05035 Rev. *A
Page 3 of 13
CY62148CV25/30/33
MoBL™
CY62148CV33-55
CY62148CV33-70
Parameter
VOH
Description
Test Conditions
Min. Typ.[4] Max. Min. Typ.[4] Max. Unit
Output HIGH Voltage IOH = –1.0 mA
Output LOW Voltage IOL = 2.1 mA
Input HIGH Voltage
VCC = 3.0V
VCC = 3.0V
2.4
2.4
V
V
V
VOL
0.4
0.4
VIH
2.2
VCC
+
2.2
VCC
+
0.5V
0.5V
VIL
IIX
Input LOW Voltage
–0.3
–1
0.8 –0.3
0.8
+1
+1
V
Input Load Current
GND < VI < VCC
+1
+1
–1
–1
µA
µA
IOZ
Output Leakage
Current
GND < VO < VCC, Output
Disabled
–1
ICC
VCC Operating Supply
Current
f = fMAX = 1/tRC
f = 1 MHz
VCC = 3.6V
IOUT = 0 mA
CMOS Levels
7
15
3
5.5
1.5
12
3
mA
mA
1.5
ISB1
Automatic CE
Power-Down Current VIN > VCC – 0.2V or VIN < 0.2V,
CE > VCC – 0.2V
8
20
8
20
µA
— CMOS Inputs
f = fmax (Address and Data Only),
f = 0 (OE,WE)
ISB2
Automatic CE
Power-Down Current VIN > VCC – 0.2V or VIN < 0.2V,
CE > VCC – 0.2V
— CMOS Inputs
f = 0, VCC = 3.6V
Capacitance[5
Parameter
Description
Test Conditions
Max.
Unit
CIN
Input Capacitance
Output Capacitance
TA = 25°C, f = 1 MHz,
VCC = VCC(typ.)
6
8
pF
pF
COUT
Thermal Resistance
Description
Test Conditions
Symbol
BGA
Unit
Thermal Resistance[5]
(Junction to Ambient)
Still Air, soldered on a 3 x 4.5 inch, two-layer printed
circuit board
ΘJA
55
°C/W
Thermal Resistance[5]
(Junction to Case)
ΘJC
16
°C/W
Note:
5. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05035 Rev. *A
Page 4 of 13
CY62148CV25/30/33
MoBL™
AC Test Loads and Waveforms
R1
V
CC
ALL INPUT PULSES
90%
OUTPUT
V
Typ
CC
90%
10%
10%
R2
30 pF
GND
Fall time: 1 V/ns
Rise Time: 1 V/ns
INCLUDING
JIG AND
SCOPE
Equivalent to:
THÉVENIN EQUIVALENT
R
TH
OUTPUT
V
TH
Parameters
2.5V
16.6
15.4
8.0
3.0V
3.3V
Unit
R1
R2
1.105
1.550
0.645
1.75
1.216
1.374
0.645
1.75
K Ohms
K Ohms
K Ohms
Volts
RTH
VTH
1.20
Data Retention Characteristics (Over the Operating Range)
Parameter
VDR
Description
Conditions
Min.
Typ.[4]
Max.
Unit
VCC for Data Retention
1.5
Vccmax
V
VCC = 1.5V
CE > VCC − 0.2V,
VIN > VCC − 0.2V or VIN < 0.2V
ICCDR
Data Retention Current
3
10
µA
ns
ns
[5]
tCDR
Chip Deselect to Data
Retention Time
0
[6]
tR
Operation Recovery
Time
tRC
Data Retention Waveform
DATA RETENTION MODE
> 1.5V
V
V
V
V
CC
CC(min.)
CC(min.)
DR
t
t
R
CDR
CE
Note:
6. Full Device AC operation requires linear VCC ramp from VDR to VCC(min.) > 50 µs or stable at VCC(min.) > 50 µs.
Document #: 38-05035 Rev. *A
Page 5 of 13
CY62148CV25/30/33
MoBL™
Switching Characteristics Over the Operating Range[7]
55 ns
70 ns
Parameter
READ CYCLE
Description
Min.
55
Max.
Min.
70
Max.
Unit
tRC
Read Cycle Time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z[8]
OE HIGH to High Z[9]
CE LOW to Low Z[8]
CE HIGH to High Z[8, 9]
CE LOW to Power-Up
CE HIGH to Power-Down
55
70
tOHA
10
10
tACE
55
25
70
35
tDOE
tLZOE
5
10
0
5
10
0
tHZOE
20
20
55
25
25
70
tLZCE
tHZCE
tPU
tPD
WRITE CYCLE[10, 11]
tWC
tSCE
tAW
Write Cycle Time
55
45
45
0
70
60
60
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
tHA
tSA
0
0
tPWE
tSD
45
30
0
50
30
0
Data Set-Up to Write End
Data Hold from Write End
WE LOW to High Z[8, 9]
WE HIGH to Low Z[8]
tHD
tHZWE
20
25
tLZWE
5
10
Notes:
7. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to VCC(typ.), and output loading of the
specified IOL/IOH and 30 pF load capacitance.
8. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
9.
tHZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in part (b) of AC Test Loads. Transition is measured ±200 mV from steady-state voltage.
10. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can
terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
11. The minimum write cycle time for Write Cycle #3 (WE controlled, OE LOW) is the sum of tHZWE and tSD
.
Document #: 38-05035 Rev. *A
Page 6 of 13
CY62148CV25/30/33
MoBL™
Switching Waveforms
Read Cycle No. 1[12, 13]
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Read Cycle No. 2 [13, 14]
t
RC
CE
t
ACE
OE
t
t
HZOE
t
DOE
HZCE
t
LZOE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA OUT
DATA VALID
t
LZCE
t
PD
t
PU
V
I
CC
CC
SUPPLY
CURRENT
50%
50%
I
SB
Write Cycle No. 1 (WE Controlled)[10, 15, 16]
t
WC
ADDRESS
CE
t
t
HA
AW
t
SA
t
PWE
WE
OE
t
SD
t
HD
DATA I/O
DATA VALID
IN
NOTE17
t
HZOE
Notes:
12. Device is continuously selected. OE, CE = VIL
13. WE is HIGH for read cycle.
.
14. Address valid prior to or coincident with CE transition LOW.
15. Data I/O is high impedance if OE = VIH
.
16. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
17. During this period, the I/Os are in output state and input signals should not be applied.
Document #: 38-05035 Rev. *A
Page 7 of 13
CY62148CV25/30/33
MoBL™
Switching Waveforms (continued)
[10, 15, 16]
Write Cycle No. 2 (CE Controlled)
t
WC
ADDRESS
CE
t
SCE
t
SA
t
t
HA
AW
WE
t
t
HD
SD
DATA I/O
DATA VALID
IN
Write Cycle No. 3 (WE Controlled, OE LOW)[11, 16]
t
WC
ADDRESS
CE
t
t
HA
AW
t
SA
WE
t
t
HD
SD
DATA I/O
DATA VALID
NOTE 17
IN
t
t
LZWE
HZWE
Document #: 38-05035 Rev. *A
Page 8 of 13
CY62148CV25/30/33
MoBL™
Typical DC and AC Parameters
(Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25°C.)
Operating Current vs. Supply Voltage
14.0
12.0
10.0
14.0
14.0
12.0
10.0
MoBL
MoBL
MoBL
12.0
10.0
(f = f
(f = f
, 55ns)
, 70ns)
(f = f
, 55ns)
max
max
(f = f
(f = f
, 55ns)
, 70ns)
8.0
6.0
4.0
8.0
6.0
4.0
max
8.0
6.0
4.0
(f = f
, 70ns)
max
max
max
2.0
0.0
2.0
0.0
2.0
0.0
(f = 1 MHz)
3.6
(f = 1 MHz)
(f = 1 MHz)
3.0
2.7
3.3
2.7
2.2
2.5
3.3
3.0
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
Standby Current vs. Supply Voltage
12.0
12.0
10.0
12.0
10.0
MoBL
10.0
8.0
MoBL
MoBL
8.0
8.0
6.0
4.0
2.0
0
6.0
4.0
2.0
0
6.0
4.0
2.0
0
3.3
3.6
3.0
2.2
3.3
2.5 2.7
3.0
2.7
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
Access Time vs. Supply Voltage
MoBL
60
MoBL
60
MoBL
60
50
40
30
50
40
30
50
40
30
20
20
20
10
0
10
0
10
0
3.6
3.0
3.3
2.2
2.5
2.7
3.0
2.7
3.3
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
Truth Table
CE
H
L
WE
OE
X
Inputs/Outputs
Mode
Deselect/Power-Down
Power
Standby (ISB
Active (ICC
Active (ICC
Active (ICC
X
H
L
High Z
)
L
Data Out
Data In
High Z
Read
)
L
X
Write
)
L
H
H
Output Disabled
)
Document #: 38-05035 Rev. *A
Page 9 of 13
CY62148CV25/30/33
MoBL™
Ordering Information
Speed
(ns)
Package
Name
Operating
Range
Ordering Code
Package Type
70
CY62148CV25LL-70BAI
CY62148CV25LL-70BVI
CY62148CV30LL-70BAI
CY62148CV30LL-70BVI
CY62148CV33LL-70BAI
CY62148CV33LL-70BVI
CY62148CV25LL-55BAI
CY62148CV25LL-55BVI
CY62148CV30LL-55BAI
CY62148CV30LL-55BVI
CY62148CV33LL-55BAI
CY62148CV33LL-55BVI
BA36B
BV36A
BA36B
BV36A
BA36B
BV36A
BA36B
BV36A
BA36B
BV36A
BA36B
BV36A
36-Ball Fine Pitch BGA (7 mm x 8.5 mm x 1.2 mm)
36-Ball Fine Pitch BGA (6 mm x 8 mm x 1 mm)
36-Ball Fine Pitch BGA (7 mm x 8.5 mm x 1.2 mm)
36-Ball Fine Pitch BGA (6 mm x 8 mm x 1 mm)
36-Ball Fine Pitch BGA (7 mm x 8.5 mm x 1.2 mm)
36-Ball Fine Pitch BGA (6 mm x 8 mm x 1 mm)
36-Ball Fine Pitch BGA (7 mm x 8.5 mm x 1.2 mm)
36-Ball Fine Pitch BGA (6 mm x 8 mm x 1 mm)
36-Ball Fine Pitch BGA (7 mm x 8.5 mm x 1.2 mm)
36-Ball Fine Pitch BGA (6 mm x 8 mm x 1 mm)
36-Ball Fine Pitch BGA (7 mm x 8.5 mm x 1.2 mm)
36-Ball Fine Pitch BGA (6 mm x 8 mm x 1 mm)
Industrial
55
Document #: 38-05035 Rev. *A
Page 10 of 13
CY62148CV25/30/33
MoBL™
Package Diagrams
36-Ball (7.00 mm x 8.5 mm x 1.2 mm) Thin BGA BA36B
51-85105-*C
Document #: 38-05035 Rev. *A
Page 11 of 13
CY62148CV25/30/33
MoBL™
Package Diagrams (continued)
36-Lead VFBGA (6 x 8 x 1 mm) BV36A
51-85149-**
MoBL, MoBL2, and More Battery Life are trademarks of Cypress Semiconductor Corporation. All product and company names
mentioned in this document may be the trademarks of their respective holders.
Document #: 38-05035 Rev. *A
Page 12 of 13
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY62148CV25/30/33
MoBL™
Document Title: CY62148CV25/30/33 MoBL™ 512K x 8 MoBL Static RAM
Document Number: 38-05035
Issue
Date
Orig. of
Change
REV.
**
ECN NO.
109951
110643
Description of Change
12/02/01
05/01/02
SZV
Change from Spec number: 38-01126 to 38-05035
*A
MGN
Advance to Final, Improved Typical and Max Icc values, added BV package
Document #: 38-05035 Rev. *A
Page 13 of 13
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Standard SRAM, 512KX8, 55ns, CMOS, PBGA36, 6 X 8 MM, 1 MM HEIGHT, VFBGA-36
CYPRESS
CY62148CV33LL-70BAIT
Standard SRAM, 512KX8, 70ns, CMOS, PBGA36, 7 X 8.50 MM, 1.20 MM HEIGHT, FPBGA-36
CYPRESS
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