CY62147CV25LL-70BVIT [CYPRESS]
Standard SRAM, 256KX16, 70ns, CMOS, PBGA48, 6 X 8 MM, 1 MM HEIGHT, VFBGA-48;
| 型号： | CY62147CV25LL-70BVIT |
| 厂家： | 
CYPRESS |
| 描述： | Standard SRAM, 256KX16, 70ns, CMOS, PBGA48, 6 X 8 MM, 1 MM HEIGHT, VFBGA-48 静态存储器 内存集成电路 |
| 文件： | 总14页 (文件大小：303K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
47V
CY62147CV25/30/33
MoBL™
256K x 16 Static RAM
cantly reduces power consumption by 80% when addresses
are not toggling. The device can also be put into standby mode
reducing power consumption by more than 99% when dese-
lected (CE HIGH or both BLE and BHE are HIGH). The in-
put/output pins (I/O0 through I/O15) are placed in a high-im-
pedance state when: deselected (CE HIGH), outputs are
disabled (OE HIGH), both Byte High Enable and Byte Low
Enable are disabled (BHE, BLE HIGH), or during a write oper-
ation (CE LOW and WE LOW).
Features
• High Speed
— 55 ns and 70 ns availability
• Voltage range:
— CY62147CV25: 2.2V–2.7V
— CY62147CV30: 2.7V–3.3V
— CY62147CV33: 3.0V–3.6V
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is
written into the location specified on the address pins (A0
through A17). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O8 through I/O15) is written into the location
specified on the address pins (A0 through A17).
• Pin Compatible with CY62147V
• Ultra-low active power
— Typical active current: 1.5 mA @ f = 1 MHz
— Typicalactivecurrent:5.5mA@f=fmax (70nsspeed)
• Low standby power
• Easy memory expansion with CE and OE features
• Automatic power-down when deselected
• CMOS for optimum speed/power
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is
LOW, then data from memory will appear on I/O8 to I/O15. See
the truth table at the back of this data sheet for a complete
description of read and write modes.
Functional Description
The CY62147CV25/30/33 are high-performance CMOS static
RAMs organized as 256K words by 16 bits. These devices
feature advanced circuit design to provide ultra-low active cur-
rent. This is ideal for providing More Battery Life™ (MoBL™)
in portable applications such as cellular telephones. The de-
vices also have an automatic power-down feature that signifi-
The CY62147CV25/30/33 are available in a 48-ball FBGA
package.
Logic Block Diagram
DATA IN DRIVERS
A
10
9
A
A
8
7
6
A
A
A
A
A
256K x 16
5
4
RAM Array
I/O – I/O
0
7
2048 x 2048
3
I/O – I/O
A
8
15
2
A
A
1
0
COLUMN DECODER
BHE
WE
CE
OE
BLE
CE
Power -Down
Circuit
BHE
BLE
Cypress Semiconductor Corporation
Document #: 38-05202 Rev. *A
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Revised April 24, 2002
CY62147CV25/30/33
MoBL™
Pin Configuration[1, 2]
FBGA (Top View)
1
2
4
3
5
6
NC
I/O
A
A
2
A
OE
BLE
0
1
A
B
C
A
A
I/O BHE
8
CE
I/O
4
3
0
A
A
6
I/O I/O
I/O
2
5
9
10
1
V
A
V
I/O
I/O
3
A
cc
D
E
F
SS
7
11
17
V
DNU
A
16
V
CC
ss
I/O
I/O
12
4
A
A
15
I/O
I/O
5
I/O
I/O
6
14
13
14
A
A
G
H
I/O
NC
WE
I/O
7
13
12
15
A
A
9
A
A
NC
NC
10
11
8
Static Discharge Voltage .......................................... >2001V
(per MIL-STD-883, Method 3015)
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Latch-Up Current.................................................... >200 mA
Operating Range
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Ambient
Temperature
Device
Range
VCC
Supply Voltage to Ground Potential...–0.5V to Vccmax + 0.5V
CY62147CV25 Industrial –40°Cto+85°C 2.2V to 2.7V
DC Voltage Applied to Outputs
CY62147CV30
CY62147CV33
2.7V to 3.3V
3.0V to 3.6V
in High Z State[3]....................................–0.5V to VCC + 0.3V
DC Input Voltage[3] .................................-0.5V to VCC + 0.3V
Output Current into Outputs (LOW) .............................20 mA
Product Portfolio
Power Dissipation (Industrial)
Operating, ICC
f = 1 MHz f = fmax
VCC(max.) Speed Typ.[4] Max. Typ.[4] Max. Typ.[4]
V
CC Range
Standby (ISB2
)
[4]
Product
VCC(min.) VCC(typ.)
Max.
CY62147CV25
2.2V
2.7V
3.0V
2.5V
3.0V
3.3V
2.7V
3.3V
3.6V
55 ns
70 ns
55 ns
70 ns
55 ns
70 ns
1.5 mA 3 mA 7 mA 15 mA 5 µA
1.5 mA 3 mA 5.5 mA 12 mA
15 µA
15 µA
20 µA
CY62147CV30
1.5 mA 3 mA 7 mA 15 mA 7 µA
1.5 mA 3 mA 5.5 mA 12 mA
CY62147CV33
1.5 mA 3 mA 7 mA 15 mA 8 µA
1.5 mA 3 mA 5.5 mA 12 mA
Notes:
1. NC pins are not connected to the die.
2. E3 (DNU) can be left as NC or VSS to ensure proper application.
3. IL(min.) = –2.0V for pulse durations less than 20 ns.
V
4. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25°C.
Document #: 38-05202 Rev. *A
Page 2 of 14
CY62147CV25/30/33
MoBL™
Electrical Characteristics Over the Operating Range
CY62147CV25-55
CY62147CV25-70
Parameter
VOH
Description
Test Conditions
Min. Typ.[4] Max. Min. Typ.[4] Max. Unit
Output HIGH Voltage IOH = –0.1 mA
Output LOW Voltage IOL = 0.1 mA
Input HIGH Voltage
VCC = 2.2V
VCC = 2.2V
2.0
2.0
V
V
V
VOL
0.4
0.4
VIH
1.8
VCC
+
1.8
VCC
+
0.3V
0.3V
VIL
IIX
Input LOW Voltage
–0.3
–1
0.6
+1
+1
–0.3
–1
0.6
+1
+1
V
Input Leakage Current GND < VI < VCC
µA
µA
IOZ
Output Leakage
Current
GND < VO < VCC, Output Disabled –1
–1
VCC Operating Supply
Current
f = fMAX = 1/tRC
f = 1 MHz
VCC = 2.7V
IOUT = 0 mA
CMOS Levels
7
15
3
5.5
1.5
12
3
mA
ICC
1.5
Automatic CE
CE > VCC – 0.2V
5
15
5
15
µA
Power-Down Cur-
rent— CMOS Inputs
VIN > VCC – 0.2V or VIN < 0.2V,
f = fmax (Address and Data Only),
f=0 (OE,WE,BHE and BLE)
ISB1
Automatic CE
CE > VCC – 0.2V
ISB2
Power-Down Cur-
rent— CMOS Inputs
VIN > VCC – 0.2V or VIN < 0.2V,
f = 0, VCC = 2.7V
CY62147CV30-55
CY62147CV30-70
Parameter
VOH
Description
Test Conditions
Min. Typ.[4] Max. Min. Typ.[4] Max. Unit
Output HIGH Voltage IOH = –1.0 mA
Output LOW Voltage IOL = 2.1 mA
Input HIGH Voltage
VCC = 2.7V
VCC = 2.7V
2.4
2.2
2.4
2.2
V
V
V
VOL
0.4
0.4
VIH
VCC
+
VCC
+
0.3V
0.3V
VIL
IIX
Input LOW Voltage
–0.3
–1
0.8
+1
+1
–0.3
–1
0.8
+1
+1
V
Input Leakage Current GND < VI < VCC
µA
µA
IOZ
Output Leakage
Current
GND < VO < VCC, Output Disabled –1
–1
VCC Operating Supply
Current
f = fMAX = 1/tRC
f = 1 MHz
VCC = 3.3V
IOUT = 0 mA
CMOS Levels
7
15
3
5.5
1.5
12
3
mA
ICC
1.5
Automatic CE
Power-Down Cur-
rent— CMOS Inputs
CE > VCC – 0.2V
7
15
7
15
µA
VIN > VCC – 0.2V or VIN < 0.2V,
f = fmax (Address and Data Only),
f=0 (OE,WE,BHE and BLE)
ISB1
Automatic CE
Power-Down Cur-
rent— CMOS Inputs
CE > VCC – 0.2V
VIN > VCC – 0.2V or VIN < 0.2V,
f = 0, VCC = 3.3V
ISB2
Document #: 38-05202 Rev. *A
Page 3 of 14
CY62147CV25/30/33
MoBL™
Electrical Characteristics Over the Operating Range (continued)
CY62147CV33-55
CY62147CV33-70
Parameter
VOH
Description
Test Conditions
Min. Typ.[4] Max. Min. Typ.[4] Max. Unit
Output HIGH Voltage IOH = –1.0 mA
Output LOW Voltage IOL = 2.1 mA
Input HIGH Voltage
VCC = 3.0V
VCC = 3.0V
2.4
2.4
V
V
V
VOL
0.4
0.4
VIH
2.2
VCC
+
2.2
VCC +
0.3V
0.3V
0.8
+1
VIL
IIX
Input LOW Voltage
–0.3
–1
0.8
+1
+1
–0.3
–1
V
Input Leakage Current GND < VI < VCC
µA
µA
IOZ
Output Leakage Cur- GND < VO < VCC, Output Disabled
rent
–1
–1
+1
VCC Operating Supply
Current
f = fMAX = 1/tRC
f = 1 MHz
VCC = 3.6V
IOUT = 0 mA
CMOS Levels
7
15
3
5.5
1.5
12
3
mA
ICC
1.5
Automatic CE
Power-Down Cur-
rent— CMOS Inputs
CE > VCC – 0.2V
8
20
8
20
µA
VIN > VCC – 0.2V or VIN < 0.2V,
f = fmax (Address and Data Only),
f=0 (OE,WE,BHE and BLE)
ISB1
Automatic CE
Power-Down Cur-
rent— CMOS Inputs
CE > VCC – 0.2V
VIN > VCC – 0.2V or VIN < 0.2V,
f = 0, VCC = 3.6V
ISB2
.
Capacitance[5]
Parameter
Description
Input Capacitance
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
VCC = VCC(typ.)
Max.
Unit
CIN
6
8
pF
pF
COUT
Thermal Resistance
Description
Test Conditions
Symbol
BGA
Unit
Thermal Resistance
Still Air, soldered on a 3 x 4.5 inch, two-layer printed
circuit board
ΘJA
55
°C/W
(Junction to Ambient)[5]
Thermal Resistance
(Junction to Case)[5]
ΘJC
16
°C/W
Note:
5. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05202 Rev. *A
Page 4 of 14
CY62147CV25/30/33
MoBL™
AC Test Loads and Waveforms
R1
V
ALL INPUT PULSES
90%
CC
VCC Typ
OUTPUT
90%
10%
10%
GND
Rise TIme: 1 V/ns
R2
30 pF
Fall Time: 1 V/ns
INCLUDING
JIG AND
SCOPE
Equivalent to:
THÉVENIN EQUIVALENT
R
TH
OUTPUT
V
TH
Parameters
2.5V
16.6
15.4
8
3.0V
1.105
1.550
0.645
1.75
3.3V
1.216
1.374
0.645
1.75
Unit
KΩ
R1
R2
KΩ
RTH
VTH
KΩ
1.20
Volts
Data Retention Characteristics (Over the Operating Range)
Parameter
VDR
Description
VCC for Data Retention
Data Retention Current
Conditions
Min.
Typ.[4]
Max.
Vccmax
10
Unit
V
1.5
VCC= 1.5V
CE > VCC – 0.2V,
VIN > VCC – 0.2V or VIN < 0.2V
3
µA
ICCDR
[5]
tCDR
Chip Deselect to Data
Retention Time
0
ns
ns
[6]
tR
Operation Recovery Time
tRC
Data Retention Waveform[7]
DATA RETENTION MODE
> 1.5 V
VCC(min)
VCC(min)
V
V
CC
DR
t
t
R
CDR
CE or
BHE.BLE
Note:
6. Full Device AC operation requires linear VCC ramp from VDR to VCC(min.) > 100µs or stable at VCC(min.) >100 µs.
7. BHE.BLE is the AND of both BHE and BLE. Chip can be deselected by either disabling the chip enable signals or by disabling both BHE and BLE.
Document #: 38-05202 Rev. *A
Page 5 of 14
CY62147CV25/30/33
MoBL™
Switching Characteristics Over the Operating Range[8]
55 ns
70 ns
Parameter
READ CYCLE
Description
Min
55
Max
Min
70
Max
Unit
tRC
Read Cycle Time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
Address to Data Valid
55
70
tOHA
tACE
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
tPU
Data Hold from Address Change
CE LOW to Data Valid
10
10
55
25
70
35
OE LOW to Data Valid
OE LOW to Low Z[9]
OE HIGH to High Z[9, 11]
CE LOW to Low Z[9]
CE HIGH to High Z[9, 11]
5
10
0
5
10
0
20
20
25
25
CE LOW to Power-Up
tPD
CE HIGH to Power-Down
BHE / BLE LOW to Data Valid
BHE / BLE LOW to Low Z[9]
BHE / BLE HIGH to High Z[9, 11]
55
55
70
70
tDBE
[10]
tLZBE
5
5
tHZBE
20
25
WRITE CYCLE[12]
tWC
tSCE
tAW
tHA
Write Cycle Time
55
45
45
0
70
60
60
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
tSA
0
0
tPWE
tBW
tSD
45
50
25
0
50
60
30
0
BHE / BLE Pulse Width
Data Set-Up to Write End
Data Hold from Write End
WE LOW to High Z[9, 11]
WE HIGH to Low Z[9]
tHD
tHZWE
20
25
tLZWE
5
5
Notes:
8. Test conditions assume signal transition time of 5 ns or less, timing reference levels of VCC(typ.)/2, input pulse levels of 0 to VCC(typ.), and output loading of the
specified IOL/IOH and 30-pF load capacitance.
9. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for
any given device.
10. If both byte enables are toggled together this value is 10 ns.
11.
tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high impedance state.
12. The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE and/or BLE = VIL. All signals must be ACTIVE to initiate a write and any
of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates
the write.
Document #: 38-05202 Rev. *A
Page 6 of 14
CY62147CV25/30/33
MoBL™
Switching Waveforms
Read Cycle No. 1 (Address Transition Controlled)[13, 14]
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Read Cycle No. 2 (OE Controlled)[14, 15]
ADDRESS
CE
t
RC
t
PD
HZCE
t
t
ACE
OE
t
HZOE
tDOE
BHE/BLE
t
LZOE
t
HZBE
tDBE
t
LZBE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA OUT
DATA VALID
t
LZCE
t
PU
V
ICC
ISB
CC
SUPPLY
CURRENT
50%
50%
Notes:
13. Device is continuously selected. OE, CE = VIL, BHE and/or BLE = VIL
.
14. WE is HIGH for read cycle.
15. Address valid prior to or coincident with CE, BHE, BLE transition LOW.
Document #: 38-05202 Rev. *A
Page 7 of 14
CY62147CV25/30/33
MoBL™
Switching Waveforms (continued)
Write Cycle No. 1 (WE Controlled)[12, 16, 17]
t
WC
ADDRESS
CE
t
SCE
t
t
HA
AW
t
SA
t
PWE
WE
t
BW
BHE/BLE
OE
t
SD
t
HD
DATA VALID
DATA I/O
18
NOTE
IN
t
HZOE
Write Cycle No. 2 (CE Controlled)[12, 16, 17]
t
WC
ADDRESS
t
SCE
CE
tSA
t
t
HA
AW
t
PWE
WE
t
BW
BHE/BLE
OE
t
t
SD
HD
VALID
DATA
DATA I/O
IN
NOTE
18
t
HZOE
Notes:
16. Data I/O is high-impedance if OE = VIH
.
17. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
18. During this period, the I/Os are in output state and input signals should not be applied.
Document #: 38-05202 Rev. *A
Page 8 of 14
CY62147CV25/30/33
MoBL™
Switching Waveforms (continued)
Write Cycle No. 3 (WE Controlled, OE LOW)[17]
t
WC
ADDRESS
CE
t
SCE
t
BW
BHE/BLE
t
t
HA
AW
t
SA
t
PWE
WE
t
t
HD
SD
NOTE 18
DATAI/O
DATA VALID
IN
t
LZWE
t
HZWE
[17]
Write Cycle No. 4 (BHE/BLE Controlled, OE LOW)
t
WC
ADDRESS
CE
t
SCE
tAW
tHA
tBW
BHE/BLE
tSA
tPWE
WE
tSD
tHD
DATA I/O
NOTE 18
VALID
DATAIN
Document #: 38-05202 Rev. *A
Page 9 of 14
CY62147CV25/30/33
MoBL™
Typical DC and AC Parameters
(Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25°C.)
Operating Current vs. Supply Voltage
14.0
12.0
10.0
14.0
12.0
10.0
14.0
12.0
10.0
MoBL
MoBL
MoBL
(f = f
, 55 ns)
, 70 ns)
max
(f = f
, 55 ns)
, 70n s)
(f = f
, 55 ns)
max
max
8.0
6.0
8.0
6.0
4.0
8.0
6.0
4.0
(f = f
(f = f
max
max
(f = f
, 70 ns)
max
4.0
2.0
0.0
2.0
0.0
2.0
0.0
(f = 1 MHz)
3.6
(f = 1 MHz)
(f = 1 MHz)
3.0
2.7
3.3
2.7
2.2
2.5
3.3
3.0
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
Standby Current vs. Supply Voltage
12.0
12.0
10.0
12.0
10.0
MoBL
10.0
8.0
MoBL
MoBL
8.0
8.0
6.0
4.0
2.0
0
6.0
4.0
2.0
0
6.0
4.0
2.0
0
3.3
3.6
3.0
2.2
3.3
2.5 2.7
3.0
2.7
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
Access Time vs. Supply Voltage
MoBL
60
MoBL
60
MoBL
60
50
40
30
50
40
30
50
40
30
20
20
20
10
0
10
0
10
0
3.6
3.0
3.3
2.2
2.5
2.7
3.0
2.7
3.3
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
Document #: 38-05202 Rev. *A
Page 10 of 14
CY62147CV25/30/33
MoBL™
Truth Table
CE
H
X
WE
X
OE
X
BHE
X
BLE
X
Inputs/Outputs
High Z
High Z
Mode
Power
Deselect/Power-Down
Deselect/Power-Down
Read
Standby (ISB
Standby (ISB
Active (ICC
Active (ICC
)
X
X
H
H
)
L
H
L
L
L
Data Out (I/OO–I/O15
)
)
L
H
L
H
L
Data Out (I/OO–I/O7);
I/O8–I/O15 in High Z
Read
)
L
H
L
L
H
Data Out (I/O8–I/O15);
I/O0–I/O7 in High Z
Read
Active (ICC)
L
L
L
L
L
H
H
H
L
H
H
H
X
X
L
H
L
L
L
H
L
L
High Z
High Z
High Z
Output Disabled
Output Disabled
Output Disabled
Write
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
)
)
)
L
Data In (I/OO–I/O15
)
)
L
H
Data In (I/OO–I/O7);
I/O8–I/O15 in High Z
Write
)
L
L
X
L
H
Data In (I/O8–I/O15);
I/O0–I/O7 in High Z
Write
Active (ICC)
Ordering Information
Speed
Package
Operating
Range
(ns)
Ordering Code
Name
BA48B
BV48A
BA48B
BV48A
BA48B
BV48A
BA48B
BV48A
BA48B
BV48A
BA48B
BV48A
Package Type
70
CY62147CV25LL-70BAI
CY62147CV25LL-70BVI
CY62147CV30LL-70BAI
CY62147CV30LL-70BVI
CY62147CV33LL-70BAI
CY62147CV33LL-70BVI
CY62147CV25LL-55BAI
CY62147CV25LL-55BVI
CY62147CV30LL-55BAI
CY62147CV30LL-55BVI
CY62147CV33LL-55BAI
CY62147CV33LL-55BVI
48-Ball Fine Pitch BGA (7 mm x 8.5 mm x 1.2 mm)
48-Ball Fine Pitch BGA (6 mm x 8 mm x 1 mm)
48-Ball Fine Pitch BGA (7 mm x 8.5 mm x 1.2 mm)
48-Ball Fine Pitch BGA (6 mm x 8 mm x 1 mm)
48-Ball Fine Pitch BGA (7 mm x 8.5 mm x 1.2 mm)
48-Ball Fine Pitch BGA (6 mm x 8 mm x 1 mm)
48-Ball Fine Pitch BGA (7 mm x 8.5 mm x 1.2 mm)
48-Ball Fine Pitch BGA (6 mm x 8 mm x 1 mm)
48-Ball Fine Pitch BGA (7 mm x 8.5 mm x 1.2 mm)
48-Ball Fine Pitch BGA (6 mm x 8 mm x 1 mm)
48-Ball Fine Pitch BGA (7 mm x 8.5 mm x 1.2 mm)
48-Ball Fine Pitch BGA (6 mm x 8 mm x 1 mm)
Industrial
55
Document #: 38-05202 Rev. *A
Page 11 of 14
CY62147CV25/30/33
MoBL™
Package Diagrams
48-Ball (7.00 mm x 8.5 mm x 1.2 mm) Thin BGA BA48B
51-85106-*C
Document #: 38-05202 Rev. *A
Page 12 of 14
CY62147CV25/30/33
MoBL™
Package Diagrams (continued)
48-Lead VFBGA (6 mm x 8 mm x 1 mm) BV48A
51-85150-**
MoBL, MoBL2 and More Battery Life are trademarks of Cypress Semiconductor Corporation. All product and company names
mentioned in this document may be the trademarks of their respective holders.
Document #: 38-05202 Rev. *A
Page 13 of 14
© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY62147CV25/30/33
MoBL™
Document Title: CY62147CV25/30/33 MoBL™ 256K x 16 Static RAM
Document Number: 38-05202
REV.
ECN NO.
Issue
Date
Orig. of
Change
Description of Change
**
112394
114216
01/31/02
GAV
Converted from Spec# 38-01123 to 38-05202. Advance Information to Final
*A
05/01/02 MGN/GUG Improved Typical & Max Icc values
Document #: 38-05202 Rev. *A
Page 14 of 14
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