CY62137VSL-55ZI [CYPRESS]
2-Mbit (128K x 16) Static RAM; 2兆位（ 128K ×16 ）静态RAM
| 型号： | CY62137VSL-55ZI |
| 厂家： | 
CYPRESS |
| 描述： | 2-Mbit (128K x 16) Static RAM |
| 文件： | 总11页 (文件大小：215K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY62137V MoBL
2-Mbit (128K x 16) Static RAM
also has an automatic power-down feature that reduces power
consumption by 99% when addresses are not toggling. The
device can also be put into standby mode when deselected
(CE HIGH) or when CE is LOW and both BLE and BHE are
HIGH. The input/output pins (I/O0 through I/O15) are placed in
a high-impedance state when: deselected (CE HIGH), outputs
are disabled (OE HIGH), BHE and BLE are disabled (BHE,
BLE HIGH), or during a write operation (CE LOW, and WE
LOW).
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is
written into the location specified on the address pins (A0
through A16). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O8 through I/O15) is written into the location
specified on the address pins (A0 through A16).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is
LOW, then data from memory will appear on I/O8 to I/O15. See
the truth table at the back of this data sheet for a complete
description of read and write modes.
Features
• Temperature Ranges
—Commercial: 0°C to 70°C
— Industrial: –40°C to 85°C
— Automotive: –40°C to 125°C
• High Speed: 55 ns and 70 ns
• Wide voltage range: 2.7V–3.6V
• Ultra-low active, standby power
• Easy memory expansion with CE and OE features
• TTL-compatible inputs and outputs
• Automatic power-down when deselected
• CMOS for optimum speed/power
• Package Available in a standard 44-pin TSOP Type II
(forward pinout) package
Functional Description[1]
The CY62137V is a high-performance CMOS static RAM
organized as 128K words by 16 bits. This device features
advanced circuit design to provide ultra-low active current.
This is ideal for providing More Battery Life® (MoBL®) in
portable applications such as cellular telephones. The device
Logic Block Diagram
DATA IN DRIVERS
10
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
128K x 16
RAM Array
2048 x 1024
I/O0 – I/O7
I/O8 – I/O15
COLUMN DECODER
BHE
WE
CE
OE
BLE
CE
Power-down
Circuit
BHE
BLE
Note:
1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Document #: 38-05051 Rev. *B
Revised June 21, 2004
CY62137V MoBL
Product Portfolio
Power Dissipation
Operating, ICC
Standby, ISB2
VCC Range (V)
Typ.[3]
(mA)
(µA)
Speed
(ns)
Product
CY62137VLL Industrial
CY62137VSL
Min.
2.7
Max.
3.6
Typ.[3]
Max.
20
Typ.[3]
Max.
15
5
3.0
55
55
70
70
70
7
7
7
7
7
1
1
1
1
1
20
15
CY62137VLL
CY62137VSL
CY62137VLL Automotive
15
5
15
15
20
Pin Configurations
TSOP II (Forward)
Top View
44
1
A
A
5
4
43
42
41
40
39
38
37
36
35
34
33
A
A
6
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
3
A
A
2
7
OE
A
1
BHE
BLE
A
0
CE
I/O
I/O
0
15
I/O
I/O
I/O
1
14
13
12
I/O
2
I/O
V
I/O
3
V
SS
CC
V
V
SS
CC
32
I/O
I/O
I/O
4
5
6
7
11
10
9
8
31
30
29
28
27
26
25
I/O
I/O
I/O
I/O
I/O
WE 17
NC
18
A
A
8
16
19
A
A
15
9
A
20
21
22
A
14
10
A
11
A
24
23
13
NC
A12
Pin Definitions
Pin Number
Type
Description
1-5, 18-22, 24-27, 42-45 Input
A0-A16. Address Inputs
7-10, 13-16, 29-32, 35-38 Input/Output
I/O0-I/O15. Data lines. Used as input or output lines depending on operation
NC. This pin is not connected to the die
23
17
No Connect
Input/Control
WE. When selected LOW, a WRITE is conducted. When selected HIGH, a READ
is conducted
6
Input/Control
Input/Control
CE. When LOW, selects the chip. When HIGH, deselects the chip
39, 40
BHE, BLE. BHE = LOW selects higher order byte WRITEs or READs on the
SRAM.BLE = LOW selects lower order byte WRITEs or READs on the SRAM
41
Input/Control
OE. Output Enable. Controls the direction of the I/O pins. When LOW, the I/O pins
behave as outputs. When deasserted HIGH, I/O pins are three-stated, and act as
input data pins
12, 34
Ground
Vss. Ground for the device
11, 33
Power Supply
Vcc. Power supply for the device
Notes:
2. NC pins are not connected on the die.
3. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V = V
CC
., T = 25°C.
A
CC(TYP)
Document #: 38-05051 Rev. *B
Page 2 of 11
CY62137V MoBL
Output Current into Outputs (LOW)............................. 20 mA
Maximum Ratings
Static Discharge Voltage.......................................... > 2001V
(Above which the useful life may be impaired. For user guide-
(per MIL-STD-883, Method 3015)
lines, not tested.)
Latch-up Current.................................................... > 200 mA
Storage Temperature .................................–65°C to +150°C
Operating Range
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Ambient
Supply Voltage to Ground Potential............... –0.5V to +4.6V
Range
Industrial
Automotive
Temperature
–40°C to +85°C
–40°C to +125°C
VCC
2.7V to 3.6V
2.7V to 3.6V
DC Voltage Applied to Outputs
in High-Z State[4] ....................................–0.5V to VCC + 0.5V
DC Input Voltage[4].................................–0.5V to VCC + 0.5V
Electrical Characteristics Over the Operating Range
CY62137V-55
CY62137V-70
Parameter
VOH
VOL
Description
Test Conditions
Min. Typ.[3] Max. Min. Typ.[3] Max. Unit
Output HIGH Voltage IOH = –1.0 mA
Output LOW Voltage IOL = 2.1 mA
Input HIGH Voltage
VCC = 2.7V
VCC = 2.7V
2.4
2.2
2.4
2.2
V
V
V
0.4
0.4
VIH
VCC
+
VCC
+
0.5V
0.5V
VIL
IIX
IOZ
Input LOW Voltage
Input Load Current
–0.5
–1
–1
0.8 –0.5
0.8
+1
+1
V
µA
µA
GND < VI < VCC
+1
+1
–1
–1
Output Leakage
GND < VO < VCC
,
Current
Output Disabled
ICC
VCC Operating Supply IOUT = 0 mA,
VCC = 3.6V
7
1
20
7
1
15 mA
Current
f = fMAX = 1/tRC,
CMOS Levels
IOUT = 0 mA, f = 1
2
2
mA
MHz, CMOS Levels
ISB1
Automatic CE
Power-down
Current— CMOS
Inputs
CE > VCC – 0.3V,
VCC = 3.6V
100
100 µA
V
IN > VCC – 0.3V or
VIN < 0.3V, f = fMAX
ISB2
Automatic CE
Power-down
Current— CMOS
Inputs
CE > VCC – 0.3V
VCC
=
LL
1
1
15
5
1
1
1
15
20
5
V
IN > VCC – 0.3V
3.6V
Automotive
SL
or VIN < 0.3V, f = 0
9
Capacitance[5]
Parameter
Description
Input Capacitance
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
CC = VCC(typ)
Max.
6
8
Unit
pF
pF
CIN
COUT
V
Thermal Resistance
Description
Test Conditions
Symbol
TSOPII
Unit
Thermal Resistance
Still Air, soldered on a 4.25 x 1.125 inch, 4-layer
ΘJA
60
°C/W
(Junction to Ambient)[5]
printed circuit board
Thermal Resistance
ΘJC
22
°C/W
(Junction to Case)[5]
Notes:
4. V (min.) = –2.0V for pulse durations less than 20 ns.
IL
5. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05051 Rev. *B
Page 3 of 11
CY62137V MoBL
AC Test Loads and Waveforms
R1
R1
ALL INPUT PULSES
VCC
OUTPUT
VCC
OUTPUT
VCC Typ
GND
90%
10%
90%
10%
R2
5 pF
R2
30 pF
INCLUDING
Fall Time:
1 V/ns
Rise Time:
1 V/ns
INCLUDING
JIG AND
SCOPE
JIG AND
SCOPE
(a)
(b)
Equivalent to:
THÉVENIN EQUIVALENT
(c)
RTH
OUTPUT
V
Parameters
3.0V
1105
1550
645
Unit
Ohms
Ohms
Ohms
Volts
R1
R2
RTH
VTH
1.75
Data Retention Characteristics (Over the Operating Range)
Parameter
VDR
Description
Conditions
Min. Typ.[3] Max. Unit
VCC for Data Retention
Data Retention Current
1.0
V
ICCDR
VCC = 1.0V, CE > VCC – 0.3V, VIN > VCC – 0.3V LL
orVIN < 0.3V;No input may exceed; VCC+0.3V
0.5
0.5
7.5
10
5
µA
Automotive
SL
[5]
tCDR
Chip Deselect to Data
Retention Time
0
ns
ns
tR
Operation Recovery Time
70
Data Retention Waveform
DATA RETENTION MODE
> 1.0 V
VCC(min.)
VCC(min.)
V
VCC
CE
DR
t
t
R
CDR
Document #: 38-05051 Rev. *B
Page 4 of 11
CY62137V MoBL
[6]
Switching Characteristics Over the Operating Range
55 ns
70 ns
Parameter
Read Cycle
Description
Min.
55
Max.
Min.
70
Max.
Unit
tRC
Read Cycle Time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
Address to Data Valid
55
70
tOHA
tACE
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
tPU
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low-Z[7]
OE HIGH to High-Z[7, 8]
CE LOW to Low-Z[7]
10
10
55
25
70
35
5
10
0
5
10
0
25
25
25
25
CE HIGH to High-Z[7, 8]
CE LOW to Power-up
tPD
CE HIGH to Power-down
BHE / BLE LOW to Data Valid
BHE / BLE LOW to Low-Z
BHE / BLE HIGH to High-Z
55
55
70
70
tDBE
(9)
tLZBE
5
5
tHZBE
25
25
Write Cycle[10, 11]
tWC
tSCE
tAW
Write Cycle Time
55
45
45
0
70
60
60
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CE LOW to Write End
Address Set-up to Write End
Address Hold from Write End
Address Set-up to Write Start
WE Pulse Width
tHA
tSA
0
0
tPWE
tSD
40
25
0
50
30
0
Data Set-up to Write End
Data Hold from Write End
WE LOW to High-Z[7, 8]
WE HIGH to Low-Z[7]
tHD
tHZWE
tLZWE
20
25
5
10
60
tBW
BHE / BLE LOW to End of Write
50
Notes:
6. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input levels of 0 to V typ., and output loading of the specified
CC
I
/I and 30 pF load capacitance.
OL OH
7. At any given temperature and voltage condition, t
is less than t
, t
is less than t
, and t
is less than t
for any given device.
HZCE
LZCE HZOE
LZOE
HZWE
LZWE
8.
t
, t
, and t
are specified with C = 5 pF as in (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
HZOE HZCE
HZWE L
9. If both byte enables are toggled together this value is 10 ns.
10. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate
a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
11. The minimum write cycle time for write cycle #3 (WE controlled, OE LOW) is the sum of t
and t .
SD
HZWE
Document #: 38-05051 Rev. *B
Page 5 of 11
CY62137V MoBL
Switching Waveforms
Read Cycle No. 1[12, 13]
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Read Cycle No. 2 [13, 14]
t
RC
CE
t
PD
HZCE
t
t
ACE
OE
t
HZOE
t
DOE
BHE/BLE
t
LZOE
t
HZBE
t
DBE
t
LZBE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA OUT
DATA VALID
t
LZCE
t
PU
V
ICC
ISB
CC
SUPPLY
50%
50%
CURRENT
Notes:
12. Device is continuously selected. OE, CE = V
13. WE is HIGH for read cycle.
.
IL
14. Address valid prior to or coincident with CE transition LOW.
Document #: 38-05051 Rev. *B
Page 6 of 11
CY62137V MoBL
Switching Waveforms (continued)
Write Cycle No. 1 (WE Controlled)[10, 15, 16]
t
WC
ADDRESS
CE
t
t
AW
HA
t
SA
t
PWE
WE
t
BW
BHE/BLE
OE
t
SD
t
HD
DATA VALID
DATA I/O
NOTE17
IN
t
HZOE
Write Cycle No. 2 (CE Controlled)[10, 15, 16]
t
WC
ADDRESS
CE
t
SCE
t
SA
t
t
HA
AW
t
BW
BHE/BLE
t
PWE
WE
t
t
HD
SD
DATA I/O
DATA VALID
IN
Notes:
15. Data I/O is high-impedance if OE = V
.
IH
16. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
17. During this period, the I/Os are in output state and input signals should not be applied.
Document #: 38-05051 Rev. *B
Page 7 of 11
CY62137V MoBL
Switching Waveforms (continued)
Write Cycle No. 3 (WE Controlled, OE LOW)[11, 16]
t
WC
ADDRESS
CE
t
t
HA
AW
t
BW
BHE/BLE
WE
t
SA
t
t
HD
SD
DATA I/O
DATA VALID
NOTE 17
IN
t
t
LZWE
HZWE
Write Cycle No. 4 (BHE/BLE Controlled, OE LOW)[17]
t
WC
ADDRESS
CE
t
t
HA
AW
t
BW
BHE/BLE
WE
t
SA
t
t
HD
SD
DATA I/O
DATA VALID
NOTE 17
IN
t
t
LZWE
HZWE
Document #: 38-05051 Rev. *B
Page 8 of 11
CY62137V MoBL
Typical DC and AC Characteristics
Normalized Operating Current
vs. Supply Voltage
Standby Current vs. Supply Voltage
35
1.4
1.2
MoBL
30
MoBL
25
20
15
1.0
0.8
0.6
10
0.4
5
0
0.2
0.0
2.7
1.0
3.7
2.8
SUPPLY VOLTAGE (V)
1.9
1.7
2.2
2.7
3.2
3.7
SUPPLY VOLTAGE (V)
Access Time vs. Supply Voltage
80
70
MoBL
60
50
40
30
20
10
1.0
3.7
2.8
1.9
2.7
SUPPLY VOLTAGE (V)
Truth Table
CE
H
L
WE
X
OE
BHE
BLE
X
Inputs/Outputs
Mode
Power
Standby (ISB
Standby (ISB
Active (ICC
Active (ICC
X
X
L
L
X
H
L
High-Z
Deselect/Power-down
Deselect/Power-down
Read
)
X
H
High-Z
)
L
H
L
Data Out (I/OO–I/O15
)
)
L
H
H
L
Data Out (I/OO–I/O7);
I/O8–I/O15 in High-Z
Read
)
L
H
L
L
H
Data Out (I/O8–I/O15);
I/O0–I/O7 in High-Z
Read
Active (ICC)
L
L
L
L
L
H
H
H
L
H
H
H
X
X
L
H
L
L
L
H
L
L
High-Z
High-Z
High-Z
Deselect/Output Disabled
Deselect/Output Disabled
Deselect/Output Disabled
Write
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
)
)
)
L
Data In (I/OO–I/O15
)
)
L
H
Data In (I/OO–I/O7);
I/O8–I/O15 in High-Z
Write
)
L
L
X
L
H
Data In (I/O8–I/O15);
I/O0 –I/O7 in High-Z
Write
Active (ICC)
Document #: 38-05051 Rev. *B
Page 9 of 11
CY62137V MoBL
Ordering Information
Speed
Package
Name
Operating
Range
(ns)
Ordering Code
Package Type
55
CY62137VLL-55ZI
CY62137VSL-55ZI
CY62137VLL-70ZI
CY62137VSL-70ZI
CY62137VLL-70ZE
Z44
44-pin TSOP II
Industrial
70
Automotive
Package Diagrams
44-Pin TSOP II Z44
DIMENSION IN MM (INCH)
MAX
MIN.
PIN 1 I.D.
22
1
R
O
E
K
A
X
S G
EJECTOR PIN
23
44
TOP VIEW
BOTTOM VIEW
10.262 (0.404)
10.058 (0.396)
0.400(0.016)
0.300 (0.012)
0.800 BSC
(0.0315)
BASE PLANE
0.210 (0.0083)
0.120 (0.0047)
0°-5°
0.10 (.004)
18.517 (0.729)
18.313 (0.721)
0.597 (0.0235)
0.406 (0.0160)
SEATING
PLANE
51-85087-*A
MoBL is a registered trademark, and More Battery Life is a trademark, of Cypress Semiconductor. All product and company
names mentioned in this document are the trademarks of their respective holders.
Document #: 38-05051 Rev. *B
Page 10 of 11
© Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY62137V MoBL
Document Title: CY62137V MoBL® 2M (128K x 16) Static RAM
Document Number: 38-05051
Orig. of
REV. ECN NO. Issue Date Change
Description of Change
**
109960
10/03/01
SZV
Changed from Spec number: 38-00738 to 38-05051
*A
116788
09/04/02
GBI
Added footnote number one.
Added SL power bin.
Deleted fBGA package; replacement fBGA package is available in
CY62137CV30.
*B
237428
See ECN
AJU
Added Automotive product information
Document #: 38-05051 Rev. *B
Page 11 of 11
相关型号：
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Standard SRAM, 256KX8, 55ns, CMOS, PBGA36, 6 X 8 MM, 1 MM HEIGHT, VFBGA-36
CYPRESS
CY62138CV25LL-70BVIT
Standard SRAM, 256KX8, 70ns, CMOS, PBGA36, 6 X 8 MM, 1 MM HEIGHT, VFBGA-36
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