CY62128LL-70SC [CYPRESS]
128K x 8 Static RAM; 128K ×8静态RAM
| 型号： | CY62128LL-70SC |
| 厂家： | 
CYPRESS |
| 描述： | 128K x 8 Static RAM |
| 文件： | 总8页 (文件大小：254K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
1CY62128
fax id: 1072
PRELIMINARY
CY62128
128K x 8 Static RAM
feature that reduces power consumption by more than 75%
when deselected.
Features
• 4.5V − 5.5V operation
Writing to the device is accomplished by taking chip enable
• CMOS for optimum speed/power
• Low active power (70 ns, LL version)
— 330 mW (max.) (60 mA)
one (CE ) and write enable (WE) inputs LOW and chip enable
1
two (CE ) input HIGH. Data on the eight I/O pins (I/O through
2
0
I/O ) is then written into the location specified on the address
7
pins (A through A ).
0
16
• Low standby power (70 ns, LL version)
— 110 µW (max.) (20 µA)
Reading from the device is accomplished by taking chip en-
able one (CE ) and output enable (OE) LOW while forcing
1
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE , CE , and OE options
write enable (WE) and chip enable two (CE ) HIGH. Under
2
these conditions, the contents of the memory location speci-
fied by the address pins will appear on the I/O pins.
1
2
The eight input/output pins (I/O through I/O ) are placed in a
0
7
Functional Description
high-impedance state when the device is deselected (CE
1
HIGH or CE LOW), the outputs are disabled (OE HIGH), or
2
The CY62128 is a high-performance CMOS static RAM orga-
nized as 131,072 words by 8 bits. Easy memory expansion is
during a write operation (CE LOW, CE HIGH, and WE LOW).
1
2
The CY62128 is available in a standard 400-mil-wide SOJ,
525-mil wide (450-mil-wide body width) SOIC and 32-pin
TSOP type I.
provided by an active LOW chip enable (CE ), an active HIGH
1
chip enable (CE ), an active LOW output enable (OE), and
2
three-state drivers. This device has an automatic power-down
Logic Block Diagram
Pin
Configurations
Top View
SOJ / SOIC
V
NC
32
31
30
1
CC
A
A
A
16
14
12
A
15
2
3
4
CE
2
29
28
WE
5
A
A
A
A
A
7
13
8
27
26
6
6
I/O
A
5
7
0
9
INPUT BUFFER
25
24
23
22
21
A
A
3
8
9
10
11
12
13
A
11
4
OE
I/O
1
A
A
CE
I/O
I/O
2
A
10
0
A
1
1
A
1
A
2
A
7
6
0
0
I/O
2
I/O
I/O
I/O
20
19
A
3
4
I/O
1
2
5
4
3
14
15
16
A
I/O
I/O
I/O
18
17
3
512 x 256 x 8
ARRAY
A
5
6
GND
A
I/O
4
A
7
8
A
A
1
2
32
31
OE
11
I/O
5
A
A
A
A
9
8
10
3
4
5
6
7
8
30
29
28
CE
1
I/O
I/O
I/O
I/O
13
6
7
6
5
POWER
DOWN
COLUMN
DECODER
WE
CE
A
CE
2
WE
1
CE
27
26
25
24
23
22
21
20
19
18
2
I/O
TSOP I
7
15
I/O
I/O
4
3
Top View
V
CC
62128-1
(not to scale)
NC
A
9
GND
OE
I/O
10
11
12
13
14
15
16
16
2
I/O
1
I/O
0
A
0
A
1
A
A
A
7
14
12
A
6
A
2
A
5
A
A
3
17
4
62128-2
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
July 1996 - Revised November 1996
CY62128
PRELIMINARY
Selection Guide
CY62128–55
55
CY62128–70
70
Maximum Access Time (ns)
Maximum Operating Current
Commercial
Commercial
115 mA
70 mA
70 mA
10 mA
100 µA
20 µA
110 mA
60 mA
60 mA
10 mA
100 µA
20 µA
L
LL
Maximum CMOS Standby Current
L
LL
Current into Outputs (LOW) ........................................ 20 mA
Maximum Ratings
Static Discharge Voltage ........................................... >2001V
(per MIL-STD-883, Method 3015)
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Latch-Up Current..................................................... >200 mA
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Operating Range
Ambient
Temperature
[1]
[2]
Supply Voltage on V to Relative GND .... –0.5V to +7.0V
Range
V
CC
CC
DC Voltage Applied to Outputs
in High Z State .....................................–0.5V to V +0.5V
Commercial
0°C to +70°C
5V ± 10%
[1]
CC
[1]
DC Input Voltage ..................................–0.5V to V +0.5V
CC
[3]
Electrical Characteristics Over the Operating Range
62128–55
62128–70
Parameter
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Test Conditions
= Min., I = – 1.0 mA
Min. Max. Min. Max. Unit
V
V
V
V
V
2.4
2.4
V
V
V
OH
OL
IH
CC
CC
OH
= Min., I = 2.1mA
0.4
0.4
OL
2.2
V
+
2.2
V
+
CC
CC
0.3
0.3
[1]
V
Input LOW Voltage
–0.3
–1
0.8
+1
+5
–0.3
–1
0.8
+1
+5
V
IL
I
I
I
I
Input Load Current
GND ≤ V ≤ V
CC
µA
IX
I
Output Leakage Current
Output Short Circuit Current
GND ≤ V ≤ V , Output Disabled
–5
–5
µA
OZ
OS
CC
I
CC
[4]
V
= Max., V
= GND
OUT
–300
115
70
–300
110
60
mA
mA
mA
mA
mA
mA
mA
mA
µA
CC
V
Operating
V
= Max.
,
= 0 mA,
Com’l
Com’l
Com’l
CC
CC
Supply Current
I
OUT
L
f = f
= 1/t
RC
MAX
LL
70
60
I
I
Automatic CE
Max. V , CE ≥ V
25
25
SB1
SB2
CC
1
IH
Power-Down Current
—TTL Inputs
or CE < V ,
2 IL
≥ V or
IH
L
10
10
V
V
IN
IN
≤ V , f = f
LL
2
2
IL
MAX
Automatic CE
Max. V
,
10
10
CC
Power-Down Current
—CMOS Inputs
CE ≥ V – 0.3V,
1 CC
L
100
20
100
20
or CE ≤ 0.3V,
2
V
≥ V – 0.3V,
LL
µA
IN
CC
or V ≤ 0.3V, f=0
IN
Shaded areas contain advance information
Notes:
1.
VIL (min.) = –2.0V for pulse durations of less than 20 ns.
2. TA is the “instant on” case temperature.
3. See the last page of this specification for Group A subgroup testing information.
4. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
2
CY62128
PRELIMINARY
Capacitance[5]
Parameter
Description
Test Conditions
T = 25°C, f = 1 MHz,
Max.
Unit
pF
C
C
Input Capacitance
Output Capacitance
9
9
IN
A
V
= 5.0V
CC
pF
OUT
AC Test Loads and Waveforms
R1 1800 Ω
ALL INPUT PULSES
90%
Ω
R1 1800
5V
5V
3.0V
GND
90%
10%
OUTPUT
OUTPUT
10%
R2
990 Ω
R2
990Ω
100 pF
5 pF
≤ 5ns
≤ 5 ns
INCLUDING
JIG AND
SCOPE
INCLUDING
JIG AND
SCOPE
(b)
62128-3
(a)
62128-4
Equivalent to:
OUTPUT
THÉVENIN EQUIVALENT
639Ω
1.77V
Switching Characteristics[3,6] Over the Operating Range
62128–55
62128–70
Parameter
Description
Min.
Max.
Min.
Max.
Unit
READ CYCLE
t
t
t
t
t
t
t
t
t
t
t
Read Cycle Time
55
5
70
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RC
Address to Data Valid
55
70
AA
Data Hold from Address Change
OHA
ACE
DOE
LZOE
HZOE
LZCE
HZCE
PU
CE LOW to Data Valid, CE HIGH to Data Valid
55
20
70
35
1
2
OE LOW to Data Valid
OE LOW to Low Z
0
5
0
0
5
0
[7, 8]
OE HIGH to High Z
20
20
55
25
25
70
[8]
CE LOW to Low Z, CE HIGH to Low Z
1
2
[7, 8]
CE HIGH to High Z, CE LOW to High Z
1
2
CE LOW to Power-Up, CE HIGH to Power-Up
1
2
CE HIGH to Power-Down, CE LOW to Power-Down
PD
1
2
[9]
WRITE CYCLE
t
t
t
t
t
t
t
Write Cycle Time
CE LOW to Write End, CE HIGH to Write End
55
45
45
0
70
60
60
0
ns
ns
ns
ns
ns
ns
ns
WC
SCE
AW
HA
1
2
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
0
0
SA
45
45
50
55
PWE
SD
Data Set-Up to Write End
Shaded areas contain advance information
Notes:
5. Tested initially and after any design or process changes that may affect these parameters.
6. Test conditions assume signal transition time of 5ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and 100pF load capacitance.
7.
tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
8. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
9. The internal write time of the memory is defined by the overlap of CE1 LOW, CE2 HIGH, and WE LOW. CE1 and WE must be LOW and CE2 HIGH to initiate a write,
and the transition of any of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates
the write.
3
CY62128
PRELIMINARY
Switching Characteristics[3,6] Over the Operating Range (continued)
62128–55
62128–70
Parameter
Description
Data Hold from Write End
Min.
Max.
Min.
Max.
Unit
ns
t
t
t
0
5
0
5
HD
[8]
WE HIGH to Low Z
WE LOW to High Z
ns
LZWE
HZWE
[7,8]
20
25
ns
Shaded area contains advanced information.
Switching Waveforms
[10,11]
Read Cycle No.1
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
62128-5
[11,12]
Read Cycle No. 2 (OE Controlled)
ADDRESS
t
RC
CE
1
CE
2
t
ACE
OE
t
HZOE
t
DOE
t
HZCE
t
LZOE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA OUT
DATA VALID
t
LZCE
t
PD
ICC
ISB
t
PU
V
CC
50%
50%
SUPPLY
CURRENT
62128-6
Notes:
10. Device is continuously selected. OE, CE1 = VIL, CE2 = VIH
.
11. WE is HIGH for read cycle.
12. Address valid prior to or coincident with CE1 transition LOW and CE2 transition HIGH.
4
CY62128
PRELIMINARY
Switching Waveforms (continued)
[13,14]
Write Cycle No. 1 (CE or CE Controlled)
1
2
t
WC
ADDRESS
t
SCE
CE
1
t
SA
CE
2
t
SCE
t
t
HA
AW
t
PWE
WE
t
t
HD
SD
DATA I/O
DATA VALID
62128-7
[13,14]
WC
Write Cycle No. 2 (WE Controlled, OE HIGH During Write)
t
ADDRESS
t
SCE
CE
1
CE
2
t
SCE
t
t
HA
AW
t
SA
t
PWE
WE
OE
t
t
SD
HD
DATA VALID
DATA I/O
IN
NOTE 15
t
HZOE
62128-8
Notes:
13. Data I/O is high impedance if OE = VIH
.
14. If CE1 goes HIGH or CE2 goes LOW simultaneously with WE going HIGH, the output remains in a high-impedance state.
15. During this period the I/Os are in the output state and input signals should not be applied.
5
CY62128
PRELIMINARY
Switching Waveforms (continued)
[13,14]
Write Cycle No.3 (WE Controlled, OE LOW)
t
WC
ADDRESS
t
SCE
CE
1
CE
2
t
SCE
t
t
HA
AW
t
SA
t
PWE
WE
t
t
HD
SD
NOTE 15
DATAI/O
DATA VALID
t
t
LZWE
HZWE
62128-9
Truth Table
CE CE OE WE
I/O – I/O
Mode
Power-Down
Power
1
2
0
7
H
X
L
L
L
X
L
X
X
L
X
X
H
L
High Z
Standby (I
Standby (I
)
SB
High Z
Power-Down
Read
)
SB
H
H
H
Data Out
Data In
High Z
Active (I
Active (I
Active (I
)
CC
X
H
Write
)
CC
H
Selected, Outputs Disabled
)
CC
Ordering Information
Speed
Package
Operating
Range
(ns)
Ordering Code
CY62128–55VC
CY62128–55SC
CY62128−55ZC
CY62128–70VC
CY62128–70SC
CY62128−70ZC
CY62128L−70SC
CY62128L−70ZC
CY62128LL−70SC
CY62128LL−70ZC
Name
V33
S34
Z32
V33
S34
Z32
S34
Z32
S34
Z32
Package Type
55
32-Lead (400-Mil) Molded SOJ
32-Lead (450-Mil) Molded SOIC
32-Lead TSOP TypeI
Commercial
70
32-Lead (400-Mil) Molded SOJ
32-Lead (450-Mil) Molded SOIC
32-Lead TSOP Type I
Commercial
32-Lead (450-Mil) Molded SOIC
32-Lead TSOP Type I
32-Lead (450-Mil) Molded SOIC
32-Lead TSOP Type I
Shaded area contains advanced information.
Document #: 38–00524
6
CY62128
PRELIMINARY
Package Diagrams
32-Lead (450 Mil) Molded SOIC S34
32-Lead Thin Small Outline Package Z32
7
CY62128
PRELIMINARY
Package Diagrams (continued)
32-Lead (400-Mil) Molded SOJ V33
© Cypress Semiconductor Corporation, 1996. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of anycircuitry other than circuitry embodied in a CypressSemiconductor product. Nor does it conveyor imply any license under patent or other rights. CypressSemiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
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