CY62128BNLL-55ZIT [CYPRESS]
Standard SRAM, 128KX8, 55ns, CMOS, PDSO32, 8 X 20 MM, TSOP1-32;
| 型号： | CY62128BNLL-55ZIT |
| 厂家： | 
CYPRESS |
| 描述： | Standard SRAM, 128KX8, 55ns, CMOS, PDSO32, 8 X 20 MM, TSOP1-32 存储 内存集成电路 静态存储器 光电二极管 |
| 文件： | 总12页 (文件大小：594K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY62128BN
MoBL®
1-Mbit (128K x 8) Static RAM
Features
Functional Description[1]
• Temperature Ranges
The CY62128BN is a high-performance CMOS static RAM
organized as 128K words by 8 bits. Easy memory expansion
is provided by an active LOW Chip Enable (CE1), an active
HIGH Chip Enable (CE2), an active LOW Output Enable (OE),
and tri-state drivers. This device has an automatic
power-down feature that reduces power consumption by more
than 75% when deselected.
— Commercial: 0°C to 70°C
— Industrial: –40°C to 85°C
— Automotive-A: –40°C to 85°C
— Automotive-E: –40°C to 125°C
• 4.5V–5.5V operation
Writing to the device is accomplished by taking Chip Enable
One (CE1) and Write Enable (WE) inputs LOW and Chip
Enable Two (CE2) input HIGH. Data on the eight I/O pins (I/O0
through I/O7) is then written into the location specified on the
address pins (A0 through A16).
• CMOS for optimum speed/power
• Low active power
(70 ns Commercial, Industrial, Automotive-A)
— 82.5 mW (max.) (15 mA)
Reading from the device is accomplished by taking Chip
Enable One (CE1) and Output Enable (OE) LOW while forcing
Write Enable (WE) and Chip Enable Two (CE2) HIGH. Under
these conditions, the contents of the memory location
specified by the address pins will appear on the I/O pins.
• Low standby power
(55/70 ns Commercial, Industrial, Automotive-A)
— 110 µW (max.) (15 µA)
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE1, CE2, and OE options
The eight input/output pins (I/O0 through I/O7) are placed in a
high-impedance state when the device is deselected (CE1
HIGH or CE2 LOW), the outputs are disabled (OE HIGH), or
during a write operation (CE1 LOW, CE2 HIGH, and WE LOW).
• Available in Pb-free and non-Pb-free 32-pin (450
mil-wide) SOIC, 32-pin STSOP and 32-pin TSOP-I
Logic Block Diagram
Pin Configuration
Top View
SOIC
V
NC
A
16
32
1
2
3
4
5
CC
31
30
A
15
CE
A
14
2
A
12
29
28
27
26
I/O
WE
A
13
0
INPUT BUFFER
A
7
6
A
A
I/O
I/O
6
8
1
2
A
A
A
0
1
2
7
8
9
10
11
12
13
14
A
5
A
9
A
11
OE
25
24
23
22
21
20
19
A
4
A
3
A
A
A
A
A
A
3
4
5
6
7
8
A
A
I/O
I/O
I/O
2
128K x 8
ARRAY
10
3
4
5
A
CE
1
I/O
I/O
6
I/O
5
1
A
7
0
I/O
0
I/O
1
15
I/O
GN
G
GgNncD
18
17
I/O
I/O
3
2
4
16
I/O
I/O
6
7
POWER
DOWN
COLUMN
DECODER
CE
CE
WE
1
2
OE
Note:
1. For best-practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
Cypress Semiconductor Corporation
Document #: 001-06498 Rev. *A
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised August 3, 2006
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CY62128BN
MoBL®
Product Portfolio
Power Dissipation
Operating, ICC (mA) Standby, ISB2 (µA)
VCC Range (V)
Typ.[2]
Speed
(ns)
Product
Min.
Max.
Typ.[2]
Max.
20
Typ.[2]
Max.
15
CY62128BNLL Commercial
4.5
5.0
5.5
55
70
55
70
70
70
7.5
6
2.5
15
2.5
15
Industrial
7.5
6
20
2.5
15
15
2.5
15
Automotive-A
Automotive-E
6
15
2.5
15
6
25
2.5
25
Pin Configurations
A11
A9
25
26
A
11
1
2
24
23
OE
32
OE
10
31
30
29
28
27
26
25
24
A
A10
A
9
8
27
28
29
30
31
32
3
4
5
6
7
8
A8
A
22
21
20
19
18
17
16
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
GND
CE
1
A13
A
I/O
13
7
6
WE
CE2
A15
WE
I/O
I/O
CE
2
5
STSOP
A
TSOP I
Top View
(not to scale)
I/O
I/O
15
4
Top View
V
VCC
CC
3
(not to scale)
NC
9
GND
NC
1
2
3
4
5
6
7
8
A
23 I/O
A16
15 I/O2
14 I/O1
13 I/O0
12
11
10
9
10
11
12
13
14
15
16
16
2
1
0
22
21
20
19
18
17
I/O
A
A14
A12
A7
14
A
I/O
12
A
A
A0
A1
A2
A3
7
0
A
A
A6
A5
A4
1
6
A
A
2
5
A
A
3
4
Pin Definitions
Input
A0–A16. Address Inputs
Input/Output I/O0–I/O7. Data lines. Used as input or output lines depending on operation
Input/Control WE. Write Enable, Active LOW. When selected LOW, a WRITE is conducted. When selected HIGH, a READ is
conducted.
Input/Control CE1. Chip Enable 1, Active LOW.
Input/Control CE2. Chip Enable 2, Active HIGH.
Input/Control OE. Output Enable, Active LOW. Controls the direction of the I/O pins. When LOW, the I/O pins behave as
outputs. When deasserted HIGH, I/O pins are tri-stated, and act as input data pins
Ground
GND. Ground for the device
VCC. Power supply for the device
Power Supply
Note:
2. Typical values are included for reference only and are not tested or guaranteed. Typical values are an average of the distribution across normal production
variations as measured at V = 5.0V, T = 25°C, and t = 70 ns.
CC
A
AA
Document #: 001-06498 Rev. *A
Page 2 of 12
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CY62128BN
MoBL®
Static Discharge Voltage...........................................> 2001V
(per MIL-STD-883, Method 3015)
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Latch-up Current.....................................................> 200 mA
Operating Range
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Supply Voltage on VCC to Relative GND[3] .... –0.5V to +7.0V
Ambient
Range
Commercial
Industrial
Temperature (TA)[4]
0°C to +70°C
VCC
5V ± 10%
DC Voltage Applied to Outputs
–40°C to +85°C
–40°C to +85°C
–40°C to +125°C
in High-Z State[3] ....................................–0.5V to VCC + 0.5V
Automotive-A
Automotive-E
DC Input Voltage[3].................................–0.5V to VCC + 0.5V
Current into Outputs (LOW).........................................20 mA
Electrical Characteristics Over the Operating Range
-55
-70
Parameter
Description
Output HIGH
Voltage
Test Conditions
Min. Typ.[2] Max. Min. Typ.[2] Max. Unit
VOH
VCC = Min., IOH = –1.0 mA
2.4
2.4
V
VOL
VIH
Output LOW Voltage VCC = Min., IOL = 2.1 mA
Input HIGH Voltage
0.4
0.4
V
V
2.2
VCC
+ 0.3
2.2
VCC
+ 0.3
VIL
IIX
Input LOW Voltage[3]
–0.3
–1
0.8 –0.3
0.8
+1
V
Input Leakage
Current
GND ≤ VI ≤ VCC
Commercial/
Industrial
+1
+1
20
2
–1
µA
Automotive-A
Automotive-E
–1
–10
–1
+1
+10
+1
µA
µA
µA
IOZ
Output Leakage
Current
GND ≤ VI ≤ VCC
,
Commercial/
Industrial
–1
Output Disabled
Automotive-A
Automotive-E
–1
+1
+10
15
µA
µA
–10
ICC
VCC Operating
Supply Current
VCC = Max.,
Commercial/
Industrial
7.5
0.1
2.5
6
mA
I
OUT = 0 mA,
f = fMAX = 1/tRC
Automotive-A
Automotive-E
6
6
15
25
1
mA
mA
mA
ISB1
ISB2
Notes:
Automatic CE
Power-down Current or CE2 < VIL,
—TTL Inputs
Max. VCC, CE1 ≥ VIH Commercial/
0.1
Industrial
VIN ≥ VIH or
VIN ≤ VIL, f = fMAX
Automotive-A
Automotive-E
0.1
0.1
2.5
1
2
mA
mA
µA
Automatic CE
Power-down Current CE1 ≥ VCC – 0.3V,
—CMOS Inputs
Max. VCC
,
Commercial/
Industrial
15
15
or CE2 ≤ 0.3V,
VIN ≥ VCC – 0.3V,
or VIN ≤ 0.3V, f = 0
Automotive-A
Automotive-E
2.5
2.5
15
25
µA
µA
3. V (min.) = –2.0V for pulse durations of less than 20 ns.
IL
4. T is the “Instant On” case temperature.
A
Document #: 001-06498 Rev. *A
Page 3 of 12
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CY62128BN
MoBL®
Capacitance[5]
Parameter
Description
Input Capacitance
Output Capacitance
Test Conditions
Max.
Unit
pF
CIN
TA = 25°C, f = 1 MHz,
CC = 5.0V
9
9
V
COUT
pF
Thermal Resistance[5]
Parameter
Description
Test Conditions
32 SOIC 32 STSOP 32 TSOP
Unit
ΘJA
Thermal Resistance
(Junction to Ambient)
Test conditions follow standard test
methods and procedures for measuring
thermal impedance, per EIA / JESD51.
66.17
105.14
97.44
°C/W
ΘJC
Thermal Resistance
(Junction to Case)
30.87
14.09
26.05
°C/W
AC Test Loads and Waveforms
R1 1800Ω
ALL INPUT PULSES
90%
R1 1800Ω
5V
5V
OUTPUT
VCC
90%
OUTPUT
10%
10%
R2
990Ω
R2
990Ω
100 pF
GND
5 pF
INCLUDING
JIG AND
SCOPE
INCLUDING
JIG AND
SCOPE
Rise TIme:
1 V/ns
Fall TIme:
1 V/ns
(b)
(a)
Equivalent to:
THÉVENIN EQUIVALENT
639Ω
1.77V
OUTPUT
Data Retention Waveform
DATA RETENTION MODE
VCC, min.
tR
> 2V
VDR
VCC, min.
tCDR
VCC
CE
1
or
CE2
Data Retention Characteristics (Over the Operating Range)
Parameter
VDR
Description
Conditions[6]
Min.
Typ.
Max.
Unit
V
VCC for Data Retention
Data Retention Current
2.0
ICCDR
VCC = VDR = 2.0V,
CE1 ≥ VCC – 0.3V, or CE2 ≤ 0.3V, Industrial
VIN ≥ VCC – 0.3V or, VIN ≤ 0.3V Automotive-A
Commercial/
1.5
15
µA
Automotive-E
1.5
25
µA
tCDR
Chip Deselect to Data
Retention Time
0
ns
tR
Operation Recovery Time
70
ns
Note:
5. Tested initially and after any design or process changes that may affect these parameters.
6. No input may exceed V + 0.5V.
CC
Document #: 001-06498 Rev. *A
Page 4 of 12
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CY62128BN
MoBL®
Switching Characteristics[7] Over the Operating Range
CY62128BN-55
CY62128BN-70
Parameter
READ CYCLE
tRC
Description
Min.
55
5
Max.
Min.
Max.
Unit
Read Cycle Time
70
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
Address to Data Valid
55
70
tOHA
Data Hold from Address Change
5
tACE
CE1 LOW to Data Valid, CE2 HIGH to Data Valid
OE LOW to Data Valid
55
20
70
35
tDOE
tLZOE
tHZOE
tLZCE
OE LOW to Low Z
OE HIGH to High Z[7, 9]
0
5
0
0
5
0
20
20
55
25
25
70
CE1 LOW to Low Z, CE2 HIGH to Low Z[9]
CE1 HIGH to High Z, CE2 LOW to High Z[8, 9]
CE1 LOW to Power-up, CE2 HIGH to Power-up
CE1 HIGH to Power-down, CE2 LOW to Power-down
tHZCE
tPU
tPD
WRITE CYCLE[10]
tWC
Write Cycle Time
55
45
45
0
70
60
60
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSCE
tAW
CE1 LOW to Write End, CE2 HIGH to Write End
Address Set-up to Write End
Address Hold from Write End
Address Set-up to Write Start
WE Pulse Width
tHA
tSA
0
0
tPWE
tSD
45
25
0
50
30
0
Data Set-up to Write End
Data Hold from Write End
WE HIGH to Low Z[9]
tHD
tLZWE
tHZWE
5
5
WE LOW to High Z[8, 9]
20
25
Switching Waveforms
Read Cycle No.1[11, 12]
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Notes:
7. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
/I and 100-pF load capacitance.
OL OH
8. t
, t
, and t
are specified with a load capacitance of 5 pF as in (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
HZOE HZCE
HZWE
9. At any given temperature and voltage condition, t
is less than t
, t
is less than t
, and t
is less than t
for any given device.
HZCE
LZCE HZOE
LZOE
HZWE
LZWE
10. The internal write time of the memory is defined by the overlap of CE LOW, CE HIGH, and WE LOW. CE and WE must be LOW and CE HIGH to initiate a
1
2
1
2
write, and the transition of any of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the
signal that terminates the write.
11. Device is continuously selected. OE, CE = V , CE = V .
1
IL
2
IH
12. WE is HIGH for read cycle.
Document #: 001-06498 Rev. *A
Page 5 of 12
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CY62128BN
MoBL®
Switching Waveforms (continued)
Read Cycle No. 2 (OE Controlled)[12, 13]
ADDRESS
t
RC
CE
1
CE
2
t
ACE
OE
t
HZOE
t
DOE
t
HZCE
t
LZOE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA OUT
DATA VALID
t
LZCE
t
PD
ICC
ISB
t
PU
V
CC
50%
50%
SUPPLY
CURRENT
Write Cycle No. 1 (CE1 or CE2 Controlled)[14, 15]
t
WC
ADDRESS
t
SCE
CE
1
t
SA
CE
2
t
SCE
t
t
HA
AW
t
PWE
WE
t
t
HD
SD
DATA I/O
DATA VALID
Notes:
13. Address valid prior to or coincident with CE transition LOW and CE transition HIGH.
1
2
14. Data I/O is high impedance if OE = V
.
IH
15. If CE goes HIGH or CE goes LOW simultaneously with WE going HIGH, the output remains in a high-impedance state.
1
2
Document #: 001-06498 Rev. *A
Page 6 of 12
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CY62128BN
MoBL®
Switching Waveforms (continued)
Write Cycle No. 2 (WE Controlled, OE HIGH During Write)[14, 15]
t
WC
ADDRESS
t
SCE
CE
1
CE
2
t
SCE
t
t
HA
AW
t
t
PWE
SA
WE
OE
t
t
SD
HD
DATA VALID
DATA I/O
IN
16
NOTE
t
HZOE
Write Cycle No.3 (WE Controlled, OE LOW)[14, 15]
t
WC
ADDRESS
t
SCE
CE
1
CE
2
t
SCE
t
t
HA
AW
t
SA
t
PWE
WE
t
t
HD
SD
NOTE 16
DATAI/O
DATA VALID
t
t
LZWE
HZWE
Note:
16. During this period the I/Os are in the output state and input signals should not be applied.
Document #: 001-06498 Rev. *A
Page 7 of 12
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CY62128BN
MoBL®
Truth Table
CE1
H
CE2
OE
X
WE
X
I/O0–I/O7
High Z
Mode
Power
X
L
Power-down
Power-down
Read
Standby (ISB
)
)
X
X
X
High Z
Standby (ISB
L
H
H
H
L
H
Data Out
Data In
High Z
Active (ICC
Active (ICC
Active (ICC
)
)
)
L
X
L
Write
L
H
H
Selected, Outputs Disabled
Ordering Information
Package
Diagram
Operating
Range
Speed (ns)
Ordering Code
CY62128BNLL-55SC
CY62128BNLL-55SXC
CY62128BNLL-55SI
CY62128BNLL-55SXI
CY62128BNLL-55ZAI
CY62128BNLL-55ZAXI
CY62128BNLL-55ZI
CY62128BNLL-55ZXI
CY62128BNLL-70SC
CY62128BNLL-70SXC
CY62128BNLL-70ZC
CY62128BNLL-70ZXC
CY62128BNLL-70SI
CY62128BNLL-70SXI
CY62128BNLL-70ZAI
CY62128BNLL-70ZAXI
CY62128BNLL-70ZI
CY62128BNLL-70ZXI
CY62128BNLL-70ZXA
CY62128BNLL-70SXA
CY62128BNLL-70SXE
CY62128BNLL-70ZAXE
Package Type
55
51-85081 32-pin 450-Mil SOIC
32-pin 450-Mil SOIC (Pb-Free)
Commercial
32-pin 450-Mil SOIC
Industrial
32-pin 450-Mil SOIC (Pb-Free)
51-85094 32-pin STSOP
32-pin STSOP (Pb-Free)
51-85056 32-pin TSOP Type I
32-pin TSOP Type I (Pb-Free)
70
51-85081 32-pin 450-Mil SOIC
32-pin 450-Mil SOIC (Pb-Free)
51-85056 32-pin TSOP Type I
32-pin TSOP Type I (Pb-Free)
Commercial
Industrial
51-85081 32-pin 450-Mil SOIC
32-pin 450-Mil SOIC (Pb-Free)
51-85094 32-pin STSOP
32-pin STSOP (Pb-Free)
51-85056 32-pin TSOP Type I
32-pin TSOP Type I (Pb-Free)
51-85056 32-pin TSOP Type I (Pb-Free)
51-85081 32-pin 450-Mil SOIC (Pb-Free)
51-85081 32-pin 450-Mil SOIC (Pb-Free)
51-85094 32-pin STSOP (Pb-Free)
Automotive-A
Automotive-E
Please contact your local Cypress sales representative for availability of these parts
Document #: 001-06498 Rev. *A
Page 8 of 12
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CY62128BN
MoBL®
Package Diagrams
32-pin (450 Mil) Molded SOIC (51-85081)
16
1
0.546[13.868]
0.566[14.376]
0.440[11.176]
0.450[11.430]
17
32
0.793[20.142]
0.817[20.751]
0.006[0.152]
0.012[0.304]
0.101[2.565]
0.111[2.819]
0.118[2.997]
MAX.
0.004[0.102]
0.047[1.193]
0.063[1.600]
0.004[0.102]
MIN.
0.050[1.270]
BSC.
0.023[0.584]
0.039[0.990]
0.014[0.355]
0.020[0.508]
SEATING PLANE
51-85081-*B
Document #: 001-06498 Rev. *A
Page 9 of 12
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CY62128BN
MoBL®
Package Diagrams (continued)
32-pin STSOP (8 x 13.4 mm) (51-85094)
51-85094-*D
Document #: 001-06498 Rev. *A
Page 10 of 12
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CY62128BN
MoBL®
Package Diagrams (continued)
32-pin TSOP Type I (8 x 20 mm) (51-85056)
51-85056-*D
All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 001-06498 Rev. *A
Page 11 of 12
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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CY62128BN
MoBL®
Document History Page
Document Title: CY62128BN MoBL® 1-Mbit (128K x 8) Static RAM
Document Number: 001-06498
Orig. of
REV. ECN NO. Issue Date Change
Description of Change
**
426503
488954
See ECN
See ECN
NXR
NXR
New Data Sheet
*A
Added Automotive product
Removed RTSOP Package
Updated ordering Information table
Document #: 001-06498 Rev. *A
Page 12 of 12
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