CY62126EV30LL-55ZSXE [CYPRESS]
1-Mbit (64K x 16) Static RAM; 1兆位（ 64K ×16 ）静态RAM
| 型号： | CY62126EV30LL-55ZSXE |
| 厂家： | 
CYPRESS |
| 描述： | 1-Mbit (64K x 16) Static RAM |
| 文件： | 总12页 (文件大小：611K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY62126EV30 MoBL®
1-Mbit (64K x 16) Static RAM
portable applications such as cellular telephones. The device
also has an automatic power down feature that significantly
reduces power consumption when addresses are not toggling.
Placing the device into standby mode reduces power
consumption by more than 99% when deselected (CE HIGH).
The input and output pins (IO0 through IO15) are placed in a
high impedance state when:
Features
• High speed: 45 ns
• Temperature ranges
— Industrial: –40°C to +85°C
— Automotive: –40°C to +125°C
• Wide voltage range: 2.2V–3.6V
• Pin compatible with CY62126DV30
• Ultra low standby power
• Deselected (CE HIGH)
• Outputs are disabled (OE HIGH)
• Both Byte High Enable and Byte Low Enable are disabled
(BHE, BLE HIGH)
— Typical standby current: 1 µA
— Maximum standby current: 4 µA
• Ultra low active power
• Write operation is active (CE LOW and WE LOW)
To write to the device, take Chip Enable (CE) and Write Enable
(WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data
from IO pins (IO0 through IO7) is written into the location
specified on the address pins (A0 through A15). If Byte High
Enable (BHE) is LOW, then data from IO pins (IO8 through
IO15) is written into the location specified on the address pins
(A0 through A15).
— Typical active current: 1.3 mA @ f = 1 MHz
• Easy memory expansion with CE and OE features
• Automatic power down when deselected
• CMOS for optimum speed and power
• Offered in Pb-free 48-ball VFBGA and 44-pin TSOP II
packages
To read from the device, take Chip Enable (CE) and Output
Enable (OE) LOW while forcing the Write Enable (WE) HIGH.
If Byte Low Enable (BLE) is LOW, then data from the memory
location specified by the address pins appear on IO0 to IO7. If
Byte High Enable (BHE) is LOW, then data from memory
appears on IO8 to IO15. See the “Truth Table” on page 9 for a
complete description of read and write modes.
Functional Description[1]
The CY62126EV30 is a high performance CMOS static RAM
organized as 64K words by 16 bits. This device features
advanced circuit design to provide ultra low active current.
This is ideal for providing More Battery Life™ (MoBL®) in
Logic Block Diagram
DATA IN DRIVERS
A10
A9
A8
A7
A6
A5
A4
A3
64K x 16
IO0–IO7
RAM Array
IO8–IO15
A2
A1
A0
COLUMN DECODER
BHE
WE
CE
OE
BLE
Note
1. For best practice recommendations, refer to the Cypress application note AN1064, SRAM System Guidelines.
Cypress Semiconductor Corporation
Document #: 38-05486 Rev. *D
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised May 4, 2007
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CY62126EV30 MoBL®
Pin Configurations [2]
44-Pin TSOP II
Top View
48-Ball VFBGA
Top View
A
A
A
A
A
7
OE
BHE
BLE
IO
15
IO
IO
13
IO
1
2
3
4
5
6
1
2
3
4
5
6
7
8
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
4
3
5
6
A
A
A
2
1
A0
A1
A2
NC
A
B
C
OE
BLE
0
A4
A6
A3
A5
IO8 BHE
CE
IO1
IO3
IO0
IO2
CE
IO
0
IO10
IO11
IO
1
IO9
VSS
VCC
14
IO
9
2
IO
3
10
11
12
13
14
15
16
12
VCC
A7
NC
A15
D
E
F
NC
V
V
SS
CC
V
SS
V
CC
IO
IO
IO4 VSS
IO12 NC
IO
4
11
10
IO
5
IO
6
IO
7
IO
IO
A14
IO13
IO5
WE
IO6
IO7
NC
IO14
9
8
NC
WE 17
A12 A13
A9
IO15 NC
G
H
A
15
A
14
A
13
A
12
18
19
20
21
22
A
8
A
9
A
A
A10 A11
A8
NC
10
11
NC
NC
Product Portfolio
Power Dissipation
Operating, ICC (mA)
VCC Range (V)
Speed
(ns)
Product
Range
Standby, ISB2 (µA)
f = 1 MHz
f = fmax
Min
2.2
2.2
Typ[1]
3.0
Max
3.6
Typ[1] Max Typ[1] Max
Typ[1]
Max
4
CY62126EV30LL Industrial
45
55
1.3
1.3
2
4
11
11
16
35
1
1
CY62126EV30LL Automotive
3.0
3.6
30
Notes
2. NC pins are not connected on the die.
3. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V = V
, T = 25°C.
A
CC
CC(typ)
Document #: 38-05486 Rev. *D
Page 2 of 12
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CY62126EV30 MoBL®
DC Input Voltage[4, 5]...............−0.3V to 3.6V (VCCmax + 0.3V)
Maximum Ratings
Output Current into Outputs (LOW)............................. 20 mA
Exceeding maximum ratings may shorten the battery life of the
device. These user guidelines are not tested.
Static Discharge Voltage.......................................... > 2001V
(MIL-STD-883, Method 3015)
Storage Temperature .................................–65°C to +150°C
Latch up Current.................................................... > 200 mA
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Operating Range
Supply Voltage to Ground
Ambient
Potential.................................–0.3V to 3.6V (VCCmax + 0.3V)
[6]
Device
Range
VCC
Temperature
DC Voltage Applied to Outputs
in High-Z State[4, 5].................–0.3V to 3.6V (VCCmax + 0.3V)
CY62126EV30LL Industrial
–40°C to +85°C 2.2V to
3.6V
Automotive –40°C to +125°C
Electrical Characteristics (Over the Operating Range)
45 ns (Industrial)
55 ns (Automotive)
Unit
Parameter
Description
Test Conditions
Min Typ[1]
Max
Min Typ[1]
Max
VOH
Output HIGH Voltage IOH = –0.1 mA
IOH = –1.0 mA, VCC > 2.70V
Output LOW Voltage IOL = 0.1 mA
IOL = 2.1mA, VCC > 2.70V
2.0
2.4
2.0
2.4
V
V
VOL
VIH
VIL
0.4
0.4
0.4
0.4
V
V
Input HIGH Voltage
VCC = 2.2V to 2.7V
VCC = 2.7V to 3.6V
VCC = 2.2V to 2.7V
VCC = 2.7V to 3.6V
1.8
2.2
VCC + 0.3 1.8
VCC + 0.3 2.2
VCC + 0.3
VCC + 0.3
0.6
V
V
Input LOW
Voltage
–0.3
–0.3
–1
0.6
0.8
+1
–0.3
–0.3
–4
V
0.8
V
IIX
Input Leakage Current GND < VI < VCC
+4
µA
µA
IOZ
Output Leakage
Current
GND < VO < VCC, Output
Disabled
–1
+1
–4
+4
ICC
VCC Operating Supply f = fmax = 1/tRC VCC = VCCmax
11
16
11
35
mA
Current
IOUT = 0 mA
CMOS levels
f = 1 MHz
1.3
2.0
1.3
4.0
ISB1
Automatic CE Power CE > VCC − 0.2V,
1
4
4
1
35
30
µA
down Current
V
IN > VCC – 0.2V, VIN < 0.2V)
—CMOS Inputs
f = fmax (Address and Data Only),
f = 0 (OE, BHE, BLE and WE),
VCC = 3.60V
[7]
ISB2
Automatic CE Power CE > VCC – 0.2V,
1
1
µA
down Current
—CMOS Inputs
V
IN > VCC – 0.2V or VIN < 0.2V,
f = 0, VCC = 3.60V
Capacitance
For all packages. Tested initially and after any design or process changes that may affect these parameters.
Parameter
CIN
Description
Input Capacitance
Output Capacitance
Test Conditions
Max
10
Unit
pF
TA = 25°C, f = 1 MHz, VCC = VCC(typ)
COUT
10
pF
Notes
4.
5.
V
V
= –2.0V for pulse durations less than 20 ns.
IL(min)
= V +0.75V for pulse durations less than 20 ns.
IH(max)
CC
6. Full device AC operation assumes a 100 µs ramp time from 0 to V (min) and 200 µs wait time after V stabilization.
cc
cc
7. Only chip enable (CE) and byte enables (BHE and BLE) need to be tied to CMOS levels to meet the I
/ I
spec. Other inputs can be left floating.
SB2 CCDR
Document #: 38-05486 Rev. *D
Page 3 of 12
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CY62126EV30 MoBL®
Thermal Resistance
Tested initially and after any design or process changes that may affect these parameters.
VFBGA
TSOP II
Parameter
ΘJA
Description
Test Conditions
Unit
Package
Package
Thermal Resistance
(Junction to Ambient)
Still Air, soldered on a 4.25 x 1.125 inch,
two-layer printed circuit board
58.85
17.01
28.2
3.4
°C/W
ΘJC
Thermal Resistance
(Junction to Case)
°C/W
AC Test Loads and Waveforms
Figure 1. AC Test Loads and Waveforms
R1
ALL INPUT PULSES
90%
10%
VCC
OUTPUT
VCC
GND
90%
10%
R2
30 pF
Rise Time = 1 V/ns
Fall Time = 1 V/ns
INCLUDING
JIG AND
SCOPE
Equivalent to: THÉVENIN EQUIVALENT
RTH
OUTPUT
VTH
Parameters
2.2V - 2.7V
16600
15400
8000
2.7V - 3.6V
Unit
Ohms
Ohms
Ohms
Volts
R1
R2
1103
1554
645
RTH
VTH
1.2
1.75
Data Retention Characteristics
Over the Operating Range
Parameter
Description
Conditions
Min
Typ[1]
Max
Unit
V
VDR
VCC for Data Retention
1.5
[7]
ICCDR
Data Retention Current VCC= VDR, CE > VCC – 0.2V,
VIN > VCC – 0.2V or VIN < 0.2V
Industrial
3
µA
µA
ns
Automotive
30
[8]
tCDR
Chip Deselect to Data
Retention Time
0
[9]
tR
Operation Recovery Time
tRC
ns
Data Retention Waveform
Figure 2. Data Retention Waveform
DATA RETENTION MODE
VCC(min)
VCC(min)
V
> 1.5V
VCC
DR
t
t
R
CDR
CE
Notes
8. Tested initially and after any design or process changes that may affect these parameters.
9. Full device AC operation requires linear V ramp from V to V > 100 µs.
CC
DR
CC(min)
Document #: 38-05486 Rev. *D
Page 4 of 12
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CY62126EV30 MoBL®
Switching Characteristics
Over the Operating Range [10, 11]
45 ns (Industrial)
55 ns (Automotive)
Unit
Parameter
Description
Min
Max
Min
Max
Read Cycle
tRC
Read Cycle Time
45
55
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
Address to Data Valid
45
55
tOHA
Data Hold from Address Change
CE LOW to Data Valid
10
10
tACE
45
22
55
25
tDOE
OE LOW to Data Valid
OE LOW to Low Z [12]
OE HIGH to High Z [12, 13]
CE LOW to Low Z [12]
CE HIGH to High Z [12, 13]
tLZOE
tHZOE
tLZCE
tHZCE
tPU
5
10
0
5
10
0
18
18
20
20
CE LOW to Power Up
tPD
CE HIGH to Power Down
BHE / BLE LOW to Data Valid
BHE / BLE LOW to Low Z [12]
BHE / BLE HIGH to High Z [12, 13]
45
22
55
25
tDBE
tLZBE
tHZBE
Write Cycle [14]
tWC
5
5
18
20
Write Cycle Time
45
55
ns
tSCE
tAW
tHA
CE LOW to Write End
35
35
0
40
40
0
ns
ns
ns
ns
Address Setup to Write End
Address Hold from Write End
Address Setup to Write Start
tSA
0
0
tPWE
tBW
tSD
WE Pulse Width
35
35
25
0
40
40
25
0
ns
ns
ns
ns
BHE / BLE Pulse Width
Data Setup to Write End
Data Hold from Write End
tHD
tHZWE
tLZWE
WE LOW to High Z [12, 13]
WE HIGH to Low Z [12]
18
20
ns
ns
10
10
Notes
10. Test conditions assume signal transition time of 3 ns or less, timing reference levels of V
/2, input pulse levels of 0 to V
, and output loading of the
CC(typ)
CC(typ)
specified I /I and 30-pF load capacitance.
OL OH
11. AC timing parameters are subject to byte enable signals (BHE or BLE) not switching when chip is disabled. See application note AN13842 for further clarification.
12. At any temperature and voltage condition, t is less than t , t is less than t , t is less than t , and t is less than t for any device.
HZCE
LZCE HZBE
LZBE HZOE
LZOE
HZWE
LZWE
13. t
, t
, t
, and t
transitions are measured when the outputs enter a high impedance state.
HZOE HZCE HZBE
HZWE
14. The internal write time of the memory is defined by the overlap of WE, CE = V , BHE, BLE or both = V . All signals must be active to initiate a write and any of
IL
IL
these signals can terminate a write by going inactive. The data input setup and hold timing must refer to the edge of signal that terminates write.
Document #: 38-05486 Rev. *D
Page 5 of 12
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CY62126EV30 MoBL®
Switching Waveforms
Read Cycle No. 1 (Address transition controlled)[15, 16]
Figure 3. Read Cycle No. 1
tRC
ADDRESS
DATA OUT
tAA
tOHA
PREVIOUS DATA VALID
DATA VALID
Read Cycle No. 2 (OE controlled)[16, 17]
Figure 4. Read Cycle No. 2
ADDRESS
CE
t
RC
t
PD
HZCE
t
t
ACE
OE
t
HZOE
t
DOE
t
LZOE
BHE/BLE
t
HZBE
t
DBE
t
LZBE
HIGH
IMPEDANCE
HIGHIMPEDANCE
DATA VALID
DATA OUT
t
LZCE
t
PU
V
50%
50%
CC
I
SUPPLY
SB
CURRENT
Notes
15. The device is continuously selected. OE, CE = V , BHE, BLE, or both = V
.
IL
IL
16. WE is HIGH for read cycle.
17. Address valid before or similar to CE and BHE, BLE transition LOW.
Document #: 38-05486 Rev. *D
Page 6 of 12
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CY62126EV30 MoBL®
Switching Waveforms (continued)
Write Cycle No. 1 (WE controlled)[14, 18, 19]
Figure 5. Write Cycle No. 1
t
WC
ADDRESS
CE
tSCE
t
t
HA
AW
t
SA
t
PWE
WE
t
BW
BHE/BLE
OE
t
HD
t
SD
NOTE 20
DATAIN
DATA IO
t
HZOE
Write Cycle No. 2 (CE controlled)[14, 18, 19]
Figure 6. Write Cycle No. 2
t
WC
ADDRESS
CE
t
SCE
tSA
t
t
HA
AW
tPWE
WE
t
BW
BHE/BLE
OE
t
t
SD
HD
DATAIN
DATA IO
NOTE 20
t
HZOE
Notes
18. Data IO is high impedance if OE = V
.
IH
19. If CE goes HIGH simultaneously with WE = V , the output remains in a high impedance state.
IH
20. During this period, the IOs are in output state. Do not apply input signals.
Document #: 38-05486 Rev. *D
Page 7 of 12
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CY62126EV30 MoBL®
Switching Waveforms (continued)
Write Cycle No. 3 (WE controlled, OE LOW [19]
Figure 7. Write Cycle No. 3
t
WC
ADDRESS
CE
t
SCE
t
BW
BHE/BLE
t
t
HA
AW
t
SA
t
PWE
WE
t
HD
t
SD
DATA IO
NOTE 20
DATAIN
t
LZWE
t
HZWE
Write Cycle No. 4 (BHE/BLE controlled, OE LOW)[19]
Figure 8. Write Cycle No. 4
t
WC
ADDRESS
CE
t
SCE
t
t
HA
AW
tBW
BHE/BLE
WE
t
SA
tPWE
tHZWE
t
HD
t
SD
NOTE 20
DATAIN
DATA IO
tLZWE
Document #: 38-05486 Rev. *D
Page 8 of 12
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CY62126EV30 MoBL®
Truth Table
CE
H
X
WE
X
OE
X
BHE
X
BLE
X
Inputs/Outputs
High Z
Mode
Power
Standby (ISB
Deselect/Power Down
Output Disabled
Read
)
X
X
H
H
High Z
Active (ICC
Active (ICC
Active (ICC
)
)
)
L
H
L
L
L
Data Out (IO0–IO15)
L
H
L
H
L
Data Out (IO0–IO7);
IO8–IO15 in High Z
Read
L
H
L
L
H
Data Out (IO8–IO15);
IO0–IO7 in High Z
Read
Active (ICC
)
L
L
L
L
L
H
H
H
L
H
H
H
X
X
L
H
L
L
L
H
L
L
High Z
High Z
High Z
Output Disabled
Output Disabled
Output Disabled
Write
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
)
)
)
)
)
L
Data In (IO0–IO15)
L
H
Data In (IO0–IO7);
IO8–IO15 in High Z
Write
L
L
X
L
H
Data In (IO8–IO15);
IO0–IO7 in High Z
Write
Active (ICC
)
Ordering Information
Speed
(ns)
Package
Diagram
Operating
Range
Package Type
Ordering Code
45
CY62126EV30LL-45BVXI 51-85150 48-ball Very Fine Pitch Ball Grid Array (Pb-free)
CY62126EV30LL-45ZSXI 51-85087 44-pin Thin Small Outline Package II (Pb-free)
Industrial
55
CY62126EV30LL-55BVXE 51-85150 48-ball Very Fine Pitch Ball Grid Array (Pb-free)
CY62126EV30LL-55ZSXE 51-85087 44-pin Thin Small Outline Package II (Pb-free)
Automotive
Contact your local Cypress sales representative for availability of other parts.
Document #: 38-05486 Rev. *D
Page 9 of 12
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CY62126EV30 MoBL®
Package Diagrams
Figure 9. 48-Ball VFBGA (6 x 8 x 1 mm), 51-85150
BOTTOM VIEW
A1 CORNER
TOP VIEW
Ø0.05 M C
Ø0.25 M C A B
Ø0.30 0.05ꢀ(48X
A1 CORNER
1
2
3
(
5
6
6
5
(
3
2
1
A
A
B
C
D
B
C
D
E
E
F
F
G
G
H
H
1.475
A
A
0.75
B
6.00 0.10
3.75
B
6.00 0.10
0.15ꢀ(8X
SEATING PLANE
C
51-85150-*D
Document #: 38-05486 Rev. *D
Page 10 of 12
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CY62126EV30 MoBL®
Package Diagrams (continued)
Figure 10. 44-Pin TSOP II, 51-85087
51-85087-*A
MoBL is a registered trademark, and More Battery Life is a trademark of Cypress Semiconductor. All product and company names
mentioned in this document are the trademarks of their respective holders.
Document #: 38-05486 Rev. *D
Page 11 of 12
© Cypress Semiconductor Corporation, 2004-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the
use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to
be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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CY62126EV30 MoBL®
Document History Page
Document Title: CY62126EV30 MoBL®, 1-Mbit (64K x 16) Static RAM
Document Number: 38-05486
Orig. of
REV. ECN NO. IssueDate
Change
Description of Change
**
202760 See ECN
300835 See ECN
AJU
SYT
New data sheet
*A
Converted from Advance Information to Preliminary
Specified Typical standby power in the Features Section
Changed E3 ball from DNU to NC in the Pin Configuration for the FBGA Package
and removed the footnote associated with it on page #2
Changed tOHA from 6 ns to 10 ns for both 35- and 45-ns speed bins, respectively
Changed tDOE, tSD from 15 to 18 ns for 35-ns speed bin
Changed tHZOE, tHZBE, tHZWE from 12 and 15 ns to 15 and 18 ns for the 35- and
45-ns speed bins, respectively
Changed tHZCE from 12 and 15 ns to 18 and 22 ns for the 35- and 45-ns speed
bins, respectively
Changed tSCE,tBW from 25 and 40 ns to 30 and 35 ns for the 35- and 45-ns speed
bins, respectively
Changed tAW from 25 to 30 ns and 40 to 35 ns for 35 and 45-ns speed bins
respectively
Changed tDBE from 35 and 45 ns to 18 and 22 ns for the 35 and 45 ns speed bins
respectively
Removed footnote that read “BHE.BLE is the AND of both BHE and BLE. Chip can
be deselected by either disabling the chip enable signals or by disabling both BHE
and BLE” on page # 4
Removed footnote that read “If both BHE and BLE are toggled together, then tLZBE
is 10 ns” on page # 5
Added Pb-free package information
*B
461631 See ECN
NXR
Converted from Preliminary to Final
Removed 35 ns Speed Bin
Removed “L” version of CY62126EV30
Changed ICC (Typ) from 8 mA to 11 mA and ICC (max) from 12 mA to 16 mA for f = fmax
Changed ICC (max) from 1.5 mA to 2.0 mA for f = 1 MHz
Changed ISB1, ISB2 (max) from 1 µA to 4 µA
Changed ISB1, ISB2 (Typ) from 0.5 µA to 1 µA
Changed ICCDR (max) from 1.5 µA to 3 µA
Changed the AC Test load Capacitance value from 50 pF to 30 pF
Changed tLZOE from 3 to 5 ns
Changed tLZCE from 6 to 10 ns
Changed tHZCE from 22 to 18 ns
Changed tLZBE from 6 to 5 ns
Changed tPWE from 30 to 35 ns
Changed tSD from 22 to 25 ns
Changed tLZWE from 6 to 10 ns
Updated the Ordering Information table.
*C
*D
925501 See ECN
1045260 See ECN
VKN
VKN
Added footnote #7 related to ISB2 and ICCDR
Added footnote #11 related AC timing parameters
Added Automotive information
Updated Ordering Information table
Document #: 38-05486 Rev. *D
Page 12 of 12
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