CY62126DV30L-70ZXI [CYPRESS]
Standard SRAM, 64KX16, 70ns, CMOS, PDSO44, TSOP2-44;
| 型号： | CY62126DV30L-70ZXI |
| 厂家： | 
CYPRESS |
| 描述： | Standard SRAM, 64KX16, 70ns, CMOS, PDSO44, TSOP2-44 静态存储器 光电二极管 |
| 文件： | 总13页 (文件大小：250K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY62126DV30
MoBL®
1-Mbit (64K x 16) Static RAM
This is ideal for providing More Battery Life™ (MoBL®) in
portable applications such as cellular telephones. The device
also has an automatic power-down feature that significantly
reduces power consumption by 90% when addresses are not
toggling. The device can be put into standby mode reducing
power consumption by more than 99% when deselected (CE
HIGH). The input/output pins (I/O0 through I/O15) are placed
in a high-impedance state when: deselected (CE HIGH),
outputs are disabled (OE HIGH), both Byte High Enable and
Byte Low Enable are disabled (BHE, BLE HIGH) or during a
write operation (CE LOW and WE LOW).
Features
• Temperature Ranges
— Industrial: –40°C to 85°C
— Automotive: –40°C to 125°C
• Very high speed: 45 ns
• Wide voltage range: 2.2V to 3.6V
• Pin compatible with CY62126BV
• Ultra-low active power
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is
written into the location specified on the address pins (A0
through A15). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O8 through I/O15) is written into the location
specified on the address pins (A0 through A15).
— Typical active current: 0.85 mA @ f = 1 MHz
— Typical active current: 5 mA @ f = fMAX
• Ultra-low standby power
• Easy memory expansion with CE and OE features
• Automatic power-down when deselected
• Packages offered in a 48-ball FBGA, 56-lead QFN and
a 44-lead TSOP Type II
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is
LOW, then data from memory will appear on I/O8 to I/O15. See
the truth table at the back of this data sheet for a complete
description of read and write modes.
• Also available in Lead-free packages
Functional Description[1]
The CY62126DV30 is a high-performance CMOS static RAM
organized as 64K words by 16 bits. This device features
advanced circuit design to provide ultra-low active current.
Logic Block Diagram
DATA IN DRIVERS
A10
A9
A8
A7
A6
A5
A4
A3
A2
64K x 16
RAM Array
2048 x 512
I/O0–I/O7
I/O8–I/O15
A1
A0
COLUMN DECODER
BHE
WE
CE
OE
BLE
Note:
1. For best-practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
Cypress Semiconductor Corporation
Document #: 38-05230 Rev. *G
• 3901 North First Street
• San Jose, CA 95134
• 408-943-2600
Revised May 30, 2005
CY62126DV30
MoBL®
Product Portfolio
Power Dissipation
Operating, ICC (mA)
f = 1 MHz f = fMAX
Standby, ISB2
VCC Range (V)
Min. Typ. Max.
(µA)
Speed
(ns)
Product
Range
Industrial
Industrial
Industrial
Automotive
Industrial
Industrial
Industrial
Typ.[2]
Max.
1.5
1.5
1.5
1.5
1.5
1.5
1.5
Typ.[2]
Max.
13
Typ.[2]
Max.
CY62126DV30L
CY62126DV30LL
CY62126DV30L
CY62126DV30L
CY62126DV30LL
CY62126DV30L
CY62126DV30LL
2.2
3.0
3.6
45
45
55
55
55
70
70
0.85
0.85
0.85
0.85
0.85
0.85
0.85
6.5
6.5
5
1.5
5
4
13
1.5
2.2
3.0
3.6
10
1.5
5
5
10
1.5
15
4
5
10
1.5
2.2
3.0
3.6
5
10
1.5
5
5
10
1.5
4
Pin Configurations[3, 4]
FBGA (Top View)
TSOP II (Forward)
Top View
1
2
4
3
5
6
NC
I/O
44
1
A
4
A
5
A
A
2
A
OE
BLE
0
1
A
B
C
43
42
41
40
39
38
A
A
A
OE
BHE
BLE
2
3
4
5
6
3
6
A
2
7
A
A
A
4
I/O BHE
CE
I/O
1
3
0
8
A
0
CE
A
A
6
I/O I/O
I/O
2
5
I/O
9
10
1
I/O
7
0
15
37
36
35
34
33
I/O
I/O
8
I/O
I/O
1
2
14
13
12
9
VCC
VSS
NC
A
7
V
I/O
I/O
3
D
E
F
SS
11
10
11
12
13
I/O
V
SS
I/O
3
CC
V
SS
DNU NC
V
CC
I/O
I/O
V
V
12
4
CC
32
I/O
I/O
I/O
4
5
6
7
11
10
31
30
29
28
I/O
I/O
I/O
14
15
16
A
A
15
I/O
I/O
I/O
I/O
14
13
5
14
6
I/O
9
8
I/O
WE 17
NC
A
A
G
H
I/O
NC
WE
I/O
13
12
15
7
18
27
26
25
A
A
8
15
19
A
A
14
9
A
A
A
A
A
13
20
21
22
A
11
NC
NC
10
9
11
8
10
A
A
12
24
23
NC
NC
Notes:
2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V = V
, T = 25°C.
A
CC
CC(typ)
3. NC pins are not connected to the die.
4. E3 (DNU) can be left as NC or V to ensure proper operation. (Expansion Pins on FBGA Package: E4 - 2M, D3 - 4M, H1 - 8M, G2 - 16M, H6 - 32M).
SS
Document #: 38-05230 Rev. *G
Page 2 of 13
CY62126DV30
MoBL®
Pin Configurations (continued)
CE
1
2
42
41
40
39
38
37
36
35
34
33
32
31
30
29
BLE
I/O
I/O
I/O
I/O
I/O
V
0
1
2
3
15
14
13
12
I/O
I/O
I/O
V
3
4
5
6
CC
SS
V
7
V
SS
CC
56-pin QFN
I/O
8
I/O
I/O
I/O
I/O
4
5
6
7
11
10
9
I/O
I/O
I/O
9
10
11
12
13
14
8
WE
A
A
7
6
A
0
A
NC
1
Document #: 38-05230 Rev. *G
Page 3 of 13
CY62126DV30
MoBL®
DC Input Voltage[6] ................................ −0.3V to VCC + 0.3V
Maximum Ratings
Output Current into Outputs (LOW)............................. 20 mA
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
Storage Temperature .................................–65°C to +150°C
Latch-up Current ....................................................> 200 mA
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Operating Range
Supply Voltage to Ground
Potential..............................................................−0.3 to 3.9V
[7]
Range
Industrial
Automotive
Ambient Temperature (TA)
−40°C to +85°C
VCC
2.2V to 3.6V
2.2V to 3.6V
DC Voltage Applied to Outputs
in High-Z State[6] ....................................−0.3V to VCC + 0.3V
−40°C to +125°C
DC Electrical Characteristics (Over the Operating Range)
CY62126DV30-45 CY62126DV30-55 CY62126DV30-70
Parameter Description
Test Conditions
Min. Typ.[5] Max. Min. Typ.[5] Max. Min Typ.[5] Max. Unit
VOH
VOL
VIH
Output HIGH 2.2<VCC < IOH = −0.1 mA
2.0
2.0
2.0
V
V
V
V
Voltage
2.7
2.7<VCC < IOH = −1.0 mA
3.6
2.4
2.4
2.4
Output LOW
Voltage
2.2<VCC < IOL = 0.1 mA
2.7
0.4
0.4
0.4
0.4
0.4
0.4
2.7<VCC < IOL = 2.1 mA
3.6
Input HIGH
Voltage
2.2 < VCC < 2.7
1.8
2.2
VCC
+
1.8
2.2
VCC 1.8
+ 0.3
VCC
+ 0.3
0.3
2.7 < VCC < 3.6
VCC
+
VCC 2.2
+ 0.3
VCC
+ 0.3
0.3
VIL
Input LOW
Voltage
2.2 < VCC < 2.7
2.7 < VCC < 3.6
−0.3
−0.3
0.6 −0.3
0.8 −0.3
0.6 −0.3
0.8 −0.3
0.6
0.8
+1
IIX
Input Leakage GND < VI < VCC
Current
Ind’l −1
Auto
+1
−1
−4
−1
−4
+1
+4
+1
+4
−1
µA
µA
µA
µA
IOZ
Output
Leakage
Current
GND < VO < VCC
Output Disabled
,
Ind’l −1
Auto
+1
−1
+1
ICC
VCC Operating f = fMAX
Supply Current 1/tRC
=
VCC = 3.6V,
6.5
13
5
10
5
10 mA
I
OUT = 0 mA,
CMOS level
f = 1 MHz
0.85
1.5
1.5
5
0.85
1.5
1.5
1.5
1.5
5
0.85
1.5
1.5
ISB1
Automatic CE CE > VCC − 0.2V,
L
Ind’l
5
4
µA
µA
Power-down
Current—
V
IN > VCC − 0.2V,
Auto
15
4
VIN < 0.2V,
CMOS Inputs f = fMAX (Address LL
1.5
4
1.5
and Data Only),
f = 0 (OE, WE,
BHE and BLE)
ISB2
Automatic CE CE > VCC − 0.2V,
L
Ind’l
1.5
1.5
5
4
1.5
1.5
1.5
5
15
4
1.5
1.5
5
4
Power-down
Current—
V
or
IN > VCC − 0.2V
Auto
CMOS Inputs VIN < 0.2V,
LL
f = 0, VCC = 3.6V
Notes:
5. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V = V
, T = 25°C.
A
CC
CC(typ)
6. V
= −2.0V for pulse durations less than 20 ns., V
= V + 0.75V for pulse durations less than 20 ns.
IL(min.)
IH(max.) CC
7. Full device operation requires linear ramp of V from 0V to V
& V must be stable at V
for 500 µs.
CC(min)
CC
CC(min)
CC
Document #: 38-05230 Rev. *G
Page 4 of 13
CY62126DV30
MoBL®
Capacitance[8]
Parameter
Description
Input Capacitance
Output Capacitance
Test Conditions
Max.
Unit
pF
CIN
TA = 25°C, f = 1 MHz
CC = VCC(typ)
8
8
V
COUT
pF
Thermal Resistance
Parameter
Description
Test Conditions
QFN TSOP FBGA Unit
θJA
θJC
Thermal Resistance (Junction to Ambient)[8] StillAir, solderedona3x4.5inch, 22.08
two-layer printed circuit board
55
12
76
11
°C/W
°C/W
Thermal Resistance (Junction to Case)[8]
5.03
AC Test Loads and Waveforms[9]
R1
VCC
ALL INPUT PULSES
90%
VCC Typ
OUTPUT
90%
10%
10%
GND
Rise TIme: 1 V/ns
R2
50 pF
Fall Time: 1 V/ns
INCLUDING
JIG AND
SCOPE
Equivalent to:
THÉVENIN EQUIVALENT
RTH
OUTPUT
VTH
Parameters
2.5V
16600
15400
8000
1.2
3.0V
Unit
R1
R2
1103
1554
645
Ohms
Ohms
Ohms
Volts
RTH
VTH
1.75
Data Retention Characteristics
Parameter
VDR
Description
Conditions
Min.
Typ.[2]
Max.
Unit
V
VCC for Data Retention
Data Retention Current
1.5
ICCDR
VCC=1.5V, CE > VCC − 0.2V,
IN > VCC − 0.2V or VIN < 0.2V
L
L
Ind’l
4
10
3
µA
V
Auto
LL Ind’l
[8]
tCDR
Chip Deselect to Data
Retention Time
0
ns
[10]
tR
Operation Recovery Time
100
µs
Data Retention Waveform
DATA RETENTION MODE
> 1.5 V
VCC(min)
VCC(min)
V
V
CC
DR
t
t
R
CDR
CE
Notes:
8. Tested initially and after any design or proces changes that may affect these parameters.
9. Test condition for the 45-ns part is a load capacitance of 30 pF.
10. Full device operation requires linear V ramp from V to V >100 µs.
CC
DR
CC(min.)
Document #: 38-05230 Rev. *G
Page 5 of 13
CY62126DV30
MoBL®
Switching Characteristics (Over the Operating Range)[11]
CY62126DV30-45[9]
CY62126DV30-55 CY62126DV30-70
Parameter
Read Cycle
tRC
Description
Min.
45
Max.
Min.
Max.
Min.
Max.
Unit
Read Cycle Time
55
70
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
Address to Data Valid
45
55
70
tOHA
Data Hold from Address Change
CE LOW to Data Valid
10
10
10
tACE
45
25
55
25
70
35
tDOE
OE LOW to Data Valid
OE LOW to Low Z[12]
OE HIGH to High Z[12, 13]
CE LOW to Low Z[12]
CE HIGH to High Z[12, 13]
tLZOE
tHZOE
tLZCE
tHZCE
tPU
5
10
0
5
10
0
5
10
0
15
20
20
20
25
25
CE LOW to Power-up
tPD
CE HIGH to Power-down
BLE/BHE LOW to Data Valid
BLE/BHE LOW to Low Z[12]
BLE/BHE HIGH to High-Z[12, 13]
45
25
55
25
70
35
tDBE
tLZBE
tHZBE
Write Cycle[14]
tWC
5
5
5
15
20
25
Write Cycle Time
45
40
40
0
55
40
40
0
70
60
60
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSCE
CE LOW to Write End
tAW
Address Set-up to Write End
Address Hold from Write End
Address Set-up to Write Start
WE Pulse Width
tHA
tSA
0
0
0
tPWE
tBW
35
40
25
0
40
40
25
0
50
60
30
0
BLE/BHE LOW to Write End
Data Set-up to Write End
Data Hold from Write End
WE LOW to High Z[12, 13]
WE HIGH to Low Z[12]
tSD
tHD
tHZWE
15
20
25
tLZWE
10
10
5
Notes:
11. Test conditions assume signal transition time of 1V/ns or less, timing reference levels of V
/2, input pulse levels of 0 to V
, and output loading of the
CC(typ.)
CC(typ.)
specified I
.
OL
12. At any given temperature and voltage condition, t
is less than t
, t
is less than t
, t
is less than t
.
LZOE
HZCE
LZCE HZBE
LZBE HZOE
13. t
, t
, t
, and t
transitions are measured when the outputs enter a high-impedance state.
HZOE HZCE HZBE
HZWE
14. The internal Write time of the memory is defined by the overlap of WE, CE = V , BHE and/or BLE = V . All signals must be ACTIVE to initiate a write and any
IL
IL
of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates
the write.
Document #: 38-05230 Rev. *G
Page 6 of 13
CY62126DV30
MoBL®
Switching Waveforms
Read Cycle No. 1 (Address Transition Controlled)[15, 16]
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Read Cycle No. 2 (OE Controlled)[16, 17]
ADDRESS
CE
t
RC
t
PD
HZCE
t
t
ACE
OE
t
HZOE
tDOE
BHE/BLE
t
LZOE
t
HZBE
tDBE
LZBE
t
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA OUT
DATA VALID
t
LZCE
t
PU
V
I
CC
CC
SUPPLY
CURRENT
50%
50%
I
SB
Notes:
15. Device is continuously selected. OE, CE = V , BHE, BLE = V
.
IL
IL
16. WE is HIGH for Read cycle.
17. Address valid prior to or coincident with CE, BHE, BLE transition LOW.
Document #: 38-05230 Rev. *G
Page 7 of 13
CY62126DV30
MoBL®
Switching Waveforms(continued)
Write Cycle No. 1 (WE Controlled[13, 14, 17, 18, 19]
t
WC
ADDRESS
CE
tSCE
t
t
HA
AW
t
SA
t
PWE
WE
t
BW
BHE/BLE
OE
t
SD
t
HD
20
VALID
DATAIN
DATA I/O
NOTE
t
HZOE
Write Cycle No. 2 (CE Controlled)[13, 14, 17, 18, 19]
t
WC
ADDRESS
t
SCE
CE
tSA
t
t
HA
AW
tPWE
WE
t
BW
BHE/BLE
OE
t
t
SD
HD
VALID
DATAIN
DATA I/O
NOTE 20
t
HZOE
Notes:
18. Data I/O is high-impedance if OE = V
.
IH
19. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
20. During the DON'T CARE period in the DATA I/O waveform, the I/Os are in output state and input signals should not be applied.
Document #: 38-05230 Rev. *G
Page 8 of 13
CY62126DV30
MoBL®
Switching Waveforms(continued)
Write Cycle No. 3 (WE Controlled, OE LOW)[18, 19]
t
WC
ADDRESS
CE
t
SCE
t
BW
BHE/BLE
t
t
HA
AW
t
SA
t
PWE
WE
t
t
HD
SD
NOTE 20
DATAI/O
DATAIN VALID
t
LZWE
t
HZWE
Write Cycle No. 4 (BHE-/BLE-controlled, OE LOW)[17, 18]
t
WC
ADDRESS
CE
t
SCE
t
t
HA
AW
tBW
BHE/BLE
WE
t
SA
tPWE
t
t
HD
SD
DATA I/O
VALID
DATAIN
NOTE 20
Document #: 38-05230 Rev. *G
Page 9 of 13
CY62126DV30
MoBL®
Truth Table
CE
H
L
WE
X
OE
X
BHE
X
BLE
X
Inputs/Outputs
High Z
Mode
Deselect/Power-Down
Output Disabled
Read
Power
Standby (ISB
Active (ICC
Active (ICC
Active (ICC
)
X
X
H
H
High Z
)
L
H
L
L
L
Data Out (I/OO–I/O15
)
)
L
H
L
H
L
Data Out (I/OO–I/O7);
I/O8–I/O15 in High Z
Read
)
L
H
L
L
H
Data Out (I/O8–I/O15);
I/O0–I/O7 in High Z
Read
Active (ICC)
L
L
L
L
L
H
H
H
L
H
H
H
X
X
L
H
L
L
L
H
L
L
High Z
High Z
High Z
Output Disabled
Output Disabled
Output Disabled
Write
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
)
)
)
L
Data In (I/OO–I/O15
)
)
L
H
Data In (I/OO–I/O7);
I/O8–I/O15 in High Z
Write
)
L
L
X
L
H
Data In (I/O8–I/O15);
I/O0–I/O7 in High Z
Write
Active (ICC)
Ordering Information
Speed
Package
Operating
Range
(ns)
Ordering Code
Name
Package Type
48-ball Fine Pitch BGA (6 mm x 8 mm x 1 mm)
48-ball Fine Pitch BGA (6 mm x 8 mm x 1 mm) (Pb-free)
44-Lead TSOP Type II (Pb-free)
45
CY62126DV30LL-45BVI
BV48A
Industrial
CY62126DV30LL-45BVXI BV48A
CY62126DV30LL-45ZXI
CY62126DV30LL-45LFXI
CY62126DV30L-55BVI
CY62126DV30LL-55BVI
Z44
LF56
56-pin QFN (Pb-free)
55
BV48A
BV48A
48-ball Fine Pitch BGA (6 mm x 8 mm x 1 mm)
48-ball Fine Pitch BGA (6 mm x 8 mm x 1 mm)
48-ball Fine Pitch BGA (6 mm x 8 mm x 1 mm) (Pb-Free)
44-Lead TSOP Type II
Industrial
CY62126DV30LL-55BVXI BV48A
CY62126DV30L-55ZI
Z44
CY62126DV30LL-55ZI
CY62126DV30LL-55ZXI
CY62126DV30L-55ZSE
CY62126DV30L-55ZSXE
CY62126DV30L-55BVXE
CY62126DV30LL-55LFXI
CY62126DV30L-70BVI
CY62126DV30LL-70BVI
Z44
44-Lead TSOP Type II
Z44
44-Lead TSOP Type II (Pb-Free)
Z44
44-Lead TSOP Type II
Automotive
Z44
44-Lead TSOP Type II (Pb-Free)
BV48A
LF56
BV48A
BV48A
48-ball Fine Pitch BGA (6 mm x 8 mm x 1 mm) (Pb-Free)
56-pin QFN (Pb-free)
Industrial
Industrial
70
48-ball Fine Pitch BGA (6 mm x 8 mm x 1 mm)
48-ball Fine Pitch BGA (6 mm x 8 mm x 1 mm)
48-ball Fine Pitch BGA (6 mm x 8 mm x 1 mm) (Pb-Free)
44-Lead TSOP Type II
CY62126DV30LL-70BVXI BV48A
CY62126DV30L-70ZI
CY62126DV30LL-70ZI
CY62126DV30LL-70ZXI
CY62126DV30LL-70LFXI
Z44
Z44
Z44
LF56
44-Lead TSOP Type II
44-Lead TSOP Type II (Pb-Free)
56-pin QFN (Pb-free)
Document #: 38-05230 Rev. *G
Page 10 of 13
CY62126DV30
MoBL®
Package Diagrams
48-Lead VFBGA (6 x 8 x 1 mm) BV48A
51-85150-*B
44-pin TSOP II Z44
51-85087-*A
Document #: 38-05230 Rev. *G
Page 11 of 13
CY62126DV30
MoBL®
Package Diagrams (continued)
56-Lead QFN 8 x 8 MM LF56A
TOP VIEW
BOTTOM VIEW
SIDE VIEW
0.08[0.003]
C
1.00[0.039] MAX.
0.80[0.031] MAX.
7.90[0.311]
A
8.10[0.319]
0.05[0.002] MAX.
0.20[0.008] REF.
0.18[0.007]
0.28[0.011]
7.70[0.303]
7.80[0.307]
PIN1 ID
N
N
0.20[0.008] R.
1
1
2
2
0.45[0.018]
0.80[0.031]
DIA.
E-PAD
(PAD SIZE VARY
BY DEVICE TYPE)
0.30[0.012]
0.50[0.020]
0.24[0.009]
(4X)
0.60[0.024]
0°-12°
0.50[0.020]
6.45[0.254]
6.55[0.258]
C
SEATING
PLANE
51-85144-*D
MoBL is a registered trademark, and MoBL2 and More Battery Life are trademarks of Cypress Semiconductor. All product and
company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-05230 Rev. *G
Page 12 of 13
© Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY62126DV30
MoBL®
Document History Page
Document Title: CY62126DV30 MoBL® 1- Mbit (64K x 16) Static RAM
Document Number: 38-05230
Orig. of
REV. ECN NO. Issue Date Change Description of Change
**
117689
127313
08/27/02
06/13/03
JUI
New Data Sheet
*A
MPR Changed From Advanced Status to Preliminary.
Changed ISB2 to 5 µA (L), 4 µA (LL)
Changed ICCDR to 4 µA (L), 3 µA (LL)
Changed CIN from 6 pF to 8 pF
*B
128340
129002
07/22/03
08/29/03
JUI
Changed from Preliminary to Final
Add 70-ns speed, updated ordering information
*C
*D
*E
CDY Changed ICC 1 MHz typ from 0.5 mA to 0.85 mA
238050 See ECN
316039 See ECN
AJU
PCI
Fixed typo: Changed tDBE from 70 ns to 35 ns
Added 45-ns Speed Bin in AC, DC and Ordering Information tables
Added Footnote #8 on page #4
Added Pb-Free package ordering information on page # 9
Changed 44-pin TSOP-II package name from Z44 to ZS44
*F
335861 See ECN
357256 See ECN
SYT
PCI
Added Temperature Ranges in the Features Section on Page # 1
Added Automotive Product Information for CY62126DV30-L for 55 ns
Added ISB1 and ISB2 values for Automotive range of CY62126DV30-L for 55 ns
Added Automotive Information for ICCDR in the Data Retention Characteristics table
Added Pb-Free packages in the ordering information
Changed 44-pin TSOP-II package name from ZS44 to Z44
*G
Added Pin Configuration and Package Diagram for 56-Lead QFN Package
Updated Thermal Characteristics and Ordering Information Table
Added Automotive Specs for IIX and IOZ in the DC Electrical Characteristics table on
Page# 4
Document #: 38-05230 Rev. *G
Page 13 of 13
相关型号：
CY62126DV30LL-55BVIT
Standard SRAM, 64KX16, 55ns, CMOS, PBGA48, 6 X 8 MM, 1 MM HEIGHT, VFBGA-48
CYPRESS
CY62126DV30LL-55BVXI
64KX16 STANDARD SRAM, 55ns, PBGA48, 6 X 8 MM, 1 MM HEIGHT, LEAD FREE, VFBGA-48
ROCHESTER
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